Chip and design method thereof

Abstract

Embodiments of the present application provide a chip and a design method thereof. The method comprises: determining power consumptions of at least two different regions on a chip according to distribution parameters of a plurality of standard cells on the chip; adjusting distribution parameters of at least two through silicon vias on the chip according to the power consumptions of the at least two different regions; and adjusting distribution positions of the plurality of standard cells on the chip according to the adjusted distribution parameters of the through silicon vias.

Description

Technical Field

[0001] This application relates to the field of chip design, and includes, but is not limited to, a chip and its design method. Background Technology

[0002] In recent years, 3D integrated circuits (ICs) have been widely used. The initial form of 3D ICs involved stacking bare chips with identical functions from bottom to top to form a 3D stack, then connecting them with bonding wires on both sides, finally presenting a system-in-package (SiP) appearance. Stacking methods can include pyramidal, cantilever, or side-by-side stacking, among others.

[0003] In related technologies, 3D ICs generate a lot of heat during operation, especially in local areas with high power consumption where heat is prone to accumulate, which further leads to temperature rise, forming a negative cycle, affecting chip performance, and even causing chip overheating failure. Summary of the Invention

[0004] In view of this, embodiments of this application provide a chip and a design method thereof.

[0005] In a first aspect, embodiments of this application provide a chip design method, the method comprising:

[0006] Based on the distribution parameters of multiple standard cells on the chip, determine the power consumption of at least two different regions on the chip;

[0007] Based on the power consumption of the at least two different regions, adjust the distribution parameters of at least two through-silicon vias on the chip;

[0008] Based on the adjusted distribution parameters of the through-silicon vias, the distribution positions of multiple standard cells on the chip are adjusted.

[0009] In some embodiments, adjusting the distribution parameters of at least two through-silicon vias on the chip based on the power consumption of the at least two different regions includes:

[0010] Determine a first region on the chip where the power consumption is greater than a first threshold.

[0011] Adjust the distribution parameters of the through-silicon vias in the first region.

[0012] In some embodiments, adjusting the distribution parameters of the through-silicon vias in the first region includes:

[0013] Increase the cross-sectional area of ​​the through-silicon via in the first region; and / or

[0014] Add the through-silicon via in the first region.

[0015] In some embodiments, increasing the cross-sectional area of ​​the through-silicon via in the first region includes:

[0016] If the first region includes at least one of the through-silicon vias, increase the cross-sectional area of ​​at least one of the through-silicon vias in the first region.

[0017] In some embodiments, adding the through-silicon via in the first region includes:

[0018] If the first region does not include the through-silicon via (TSV), then at least one TSV is added to the first region.

[0019] In some embodiments, adding at least one through-silicon via (TSV) in the first region if the first region does not include the TSV includes:

[0020] Identify a first through-silicon via located outside the first region, with its x-coordinate within the x-coordinate range of the first region;

[0021] At least one second through-silicon via is added within the first region.

[0022] In some embodiments, adding at least one second through-silicon via in the first region includes:

[0023] Within the first region, at the same position as the first through-silicon via (TSV), add a second TSV with the same size as the first TSV.

[0024] In some embodiments, adjusting the distribution positions of multiple standard cells on the chip according to the adjusted distribution parameters of the through-silicon vias includes:

[0025] The distribution positions of multiple standard cells on the chip are adjusted so that the standard cells in the first region are distributed outside the coverage area of ​​the through-silicon vias in the first region.

[0026] In some embodiments, the method further includes:

[0027] A second region on the chip with power consumption greater than a second threshold is identified; wherein the second region is located within the first region; and the area of ​​the second region is less than or equal to the area of ​​the first region.

[0028] Adjust the distribution parameters of the through-silicon vias in the second region.

[0029] In some embodiments, the method further includes:

[0030] The distribution positions of multiple standard cells on the chip are adjusted so that the standard cells in the second region are distributed outside the coverage area of ​​the through-silicon vias in the second region.

[0031] In some embodiments, the method further includes:

[0032] The wiring of the chip is determined based on the adjusted distribution parameters of the through-silicon vias and the distribution positions of the standard cells.

[0033] On the other hand, embodiments of this application also provide a chip, which is designed using any of the above methods, including:

[0034] Substrate;

[0035] A device layer is located on the substrate; the device layer includes a plurality of standard cells;

[0036] Through-silicon vias penetrate the substrate and the device layer.

[0037] This application provides a chip and its design method. The method allows for the estimation of power consumption distribution on the chip during the chip design phase based on the distribution parameters of standard cells. Then, it adjusts the distribution parameters of through-silicon vias (TSVs) according to the power consumption distribution in different regions, and further adjusts the distribution positions of the standard cells. This reduces heat accumulation during actual use and decreases the current carried by the TSVs, thereby improving chip reliability. Attached Figure Description

[0038] Figure 1 A flowchart illustrating a chip design method provided in this application embodiment;

[0039] Figure 2 This is a schematic diagram of an optional structure for chip flip-chip packaging provided in an embodiment of this application;

[0040] Figure 3 A schematic diagram of a fixed-pattern through-silicon via (TSV) distribution provided in an embodiment of this application;

[0041] Figure 4 This is a schematic diagram of a structure for increasing the cross-sectional area of ​​through-silicon vias provided in an embodiment of this application;

[0042] Figure 5 This is a schematic diagram of a structure with added through-silicon vias provided in an embodiment of this application;

[0043] Figure 6 A schematic diagram of an automation script plugin provided in an embodiment of this application;

[0044] Figure 7 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0045] To facilitate understanding of the present invention, a more detailed and comprehensive description will be given below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0047] Firstly, embodiments of this application provide a chip design method, such as... Figure 1 As shown, the method includes:

[0048] Step S101: Determine the power consumption of at least two different regions on the chip based on the distribution parameters of multiple standard cells on the chip;

[0049] Step S102: Adjust the distribution parameters of at least two through-silicon vias on the chip according to the power consumption of the at least two different regions;

[0050] Step S103: Adjust the distribution positions of multiple standard cells on the chip according to the adjusted distribution parameters of the through silicon via.

[0051] The chips involved in this application are a general term for semiconductor component products, also known as integrated circuits, which can be manufactured on the surface of semiconductor wafers. The chip manufacturing process can include chip design, wafer fabrication, packaging, and testing. Chip design refers to generating a "pattern" according to the designer's needs. Wafer fabrication involves processes such as coating, photolithography, etching, doping, and wiring on the wafer to integrate transistors or other electronic components, forming individual wafers with electrical characteristics. The wafer is the raw material for chips, its main component being silicon, obtained by slicing silicon ingots. Packaging refers to cutting the wafer from the wafer, fixing the wafer onto a SiP substrate, binding pins, and fabricating it into various packaging forms according to requirements to form a finished chip. Packaging forms include, but are not limited to, DIP (Dual In-line Package), SOP (Small Out-line Package), QFP (Quad Flat Package), or PLCC (Plastic Leaded Chip Carrier) packaging. The demand here is mainly determined by external factors such as user application habits, application environment, and market conditions. Finally, after the above process, the finished chip is tested, screened, and packaged.

[0052] During the chip packaging process, such as Figure 2 As shown, two chips can be bonded together and then flip-chip packaged. The first chip 300 is connected to the SiP substrate 200 via first flip chip bumps 320 on the first substrate 310, and the SiP substrate 200 is connected to the printed circuit board (PCB) 100 via first flip chip bumps 210. Furthermore, the first chip 300 is connected to the second chip 500 via a bonding structure 400, which may include a metal layer 410 and a hybrid bonding layer 420. On the other hand, the first chip 300 also includes at least one backside through-silicon via (BTSV) 330, through which the second chip 500 can communicate with the SiP substrate 200. The first chip 300 and the second chip 500 also have a first electronic device layer 340 and a second electronic device layer 520, respectively.

[0053] During actual chip use, heat is generated on both the first and second chips. For the first chip, the presence of back-side through-silicon vias (TSVs) increases the thermal conductivity of the first electronic device layer and the first substrate, correspondingly reducing thermal resistance. This allows heat to diffuse from the second chip towards the first chip. It should be noted that the metal layers and hybrid bonding layers in the bonding structure are not composed of a single material; their thermal conductivity can be considered a weighted average of the thermal conductivity of multiple materials. Therefore, the chip's heat dissipation performance and the reliability of the 3D IC system primarily depend on the first chip. Figure 3 As shown, the distribution of the back-side vias 330 on the first chip is typically based on a fixed pattern according to the chip design layout. The standard cells 350 are arranged around the back-side vias 330 in the figure. It should be noted that the standard cells 350 involved in this embodiment may include multiple electronic components distributed in blocks on the substrate. For example, the thermal conductivity of the second chip may be 0.21 W / mK (watts per meter K), the thermal conductivity of the bonding structure may be 120 W / mK, and the thermal conductivity of the first chip may be 5 W / mK. Therefore, in areas with higher power consumption (i.e., more standard cells 350), the fixed-pattern distribution of the back-side vias 330 is more prone to heat accumulation. This heat accumulation further increases the temperature, causing the device to generate more heat during operation, leading to a further exacerbation of heat accumulation, thus forming a negative cycle and significantly affecting chip performance, even causing chip overheating failure. On the other hand, the higher the standard cell density in a region, the greater the average and peak current during normal operation. The required current is supplied by 1-2 flip-chip blocks in the local area through back silicon vias. This can cause individual back silicon vias to bear excessive current, causing them to fail due to electromigration and other reasons, thus leading to chip reliability issues.

[0054] In this embodiment, different regions can be determined based on the distribution parameters of multiple standard cells on the chip. These distribution parameters may include the size, coordinates, or density of each standard cell in different regions. For example, regions with higher standard cell density consume more power and are more prone to heat accumulation during subsequent use; conversely, regions with higher standard cell density consume less power and are less prone to heat accumulation. Therefore, at least two different power consumption regions can be determined on the chip: high-power regions and low-power regions.

[0055] Then, based on the power consumption information in the different regions mentioned above, the distribution parameters of the through-silicon vias (TSVs) on the chip can be adjusted. These distribution parameters may include size, coordinates, or cross-sectional area. In this embodiment, the TSV is also referred to as a back TSV, which can be a structure that penetrates the chip substrate and device layer and is electrically connected to a flip-chip block on the back of the chip. Furthermore, the TSV can be powered through at least one flip-chip block. For example, in a 3D IC, the chip at the top (away from the SiP substrate) can also communicate with the SiP substrate through TSVs on the bottom (closer to the SiP substrate) chip. It should be noted that the above-mentioned TSV is a vertical interconnect that penetrates the wafer or chip. Specifically, a TSV is formed by drilling a small hole in the chip and filling it with metal from the bottom. Then, the hole is drilled on the wafer or chip using dry etching or photolithography, and the hole is filled with a conductive material, such as copper, tungsten, or polysilicon.

[0056] In this embodiment, after adjusting the through-silicon vias (TSVs) on the chip, the distribution positions of the standard cells can be readjusted based on the new distribution parameters of the TSVs. In this embodiment, TSVs can be used not only for electrical connections but also for heat dissipation, i.e., to address heat accumulation in areas with high standard cell density. Therefore, standard cells in high-power regions need to be redistributed according to the TSV distribution parameters, while standard cells in low-power regions can be adjusted or not adjusted according to actual needs.

[0057] The chip design method used in this application embodiment can estimate the power consumption distribution on the chip based on the distribution parameters of the standard cells on the chip during the chip design stage. Then, the distribution parameters of the through-silicon vias are adjusted according to the power consumption distribution in different areas, and the distribution position of the standard cells is further adjusted. This can reduce heat accumulation during actual use and reduce the current carried by the through-silicon vias, thereby improving the reliability of the chip.

[0058] In some embodiments, adjusting the distribution parameters of at least two through-silicon vias on the chip based on the power consumption of the at least two different regions includes:

[0059] Determine a first region on the chip where the power consumption is greater than a first threshold.

[0060] Adjust the distribution parameters of the through-silicon vias in the first region.

[0061] In this embodiment, the power consumption of the chip can be set to a first threshold based on actual conditions. When the power consumption in a certain area of ​​the chip exceeds the first threshold, that area is considered a high-power area, i.e., the first area. Figure 4As shown, the chip may include at least one of the aforementioned first regions 1000, and the first region may be a square region of 50µm (micrometers) by 50µm. Multiple standard cells may be distributed within the first region, and the power consumption of the standard cells can be simulated using relevant software.

[0062] Then, in the embodiments of this application, the distribution parameters of the through-silicon vias in the first region can be adjusted under the power consumption conditions of more standard cells, so as to effectively reduce potential power consumption during the chip design stage.

[0063] In some embodiments, adjusting the distribution parameters of the through-silicon vias in the first region includes:

[0064] Increase the cross-sectional area of ​​the through-silicon via in the first region; and / or

[0065] Add the through-silicon via in the first region.

[0066] In this embodiment, the distribution parameters of through-silicon vias (TSVs) may include parameters such as the cross-sectional area of ​​the TSVs, the number of TSVs, their location, and their distribution density. Here, the cross-sectional area refers to the area of ​​the cross-section where the chip intersects with the TSV. For example, if the TSV is cylindrical and penetrates the chip substrate and device layer and is electrically connected to the flip-chip backing, then the cross-sectional area is the area of ​​each circular cross-section of the surface where the TSV axis intersects with the chip. An increase in cross-sectional area means an increase in the radius of the circular cross-section.

[0067] In this embodiment, within the aforementioned first region, distribution parameters can be adjusted by adding through-silicon vias (TSVs). "Adding" here refers to adding TSVs during the chip design phase to dissipate heat from standard cells with potentially high power consumption. For example, densely distributed standard cells within the first region have higher potential power consumption and are more prone to heat accumulation. In this case, adding TSVs allows for faster heat dissipation. Furthermore, adding TSVs can disperse the current in other TSVs surrounding the first region, preventing them from bearing excessive current and thus avoiding chip reliability issues.

[0068] Therefore, in this application embodiment, the distribution parameters can be adjusted by increasing the cross-sectional area of ​​the through-silicon via in the first region or by adding through-silicon vias in the first region. The former can make the through-silicon via have a larger heat-conducting area and can withstand a larger current; the latter can make the heat generated in the first region dissipate faster and reduce the current flowing through the surrounding through-silicon vias, thereby improving the reliability of the chip.

[0069] In some embodiments, increasing the cross-sectional area of ​​the through-silicon via in the first region includes:

[0070] If the first region includes at least one of the through-silicon vias, increase the cross-sectional area of ​​at least one of the through-silicon vias in the first region.

[0071] like Figure 4 As shown, if at least one through-silicon via (TSV) exists within the first region 1000, the cross-sectional area of ​​the TSV can be increased. Here, the increased cross-sectional area of ​​the TSV needs to be determined based on the actual situation. If the actual power consumption is high, a relatively larger cross-sectional area can be added; if the actual power consumption is low, a relatively smaller cross-sectional area can be added. Before adjusting the TSV, the standard cells in the first region are densely distributed around the TSV, resulting in low heat dissipation efficiency and the ability to withstand high current. However, after adjusting the TSV, the standard cells are redistributed due to the new TSV, thereby improving heat dissipation efficiency and allowing the TSV to withstand greater current.

[0072] In some embodiments, adding the through-silicon via in the first region includes:

[0073] If the first region does not include the through-silicon via (TSV), then at least one TSV is added to the first region.

[0074] like Figure 5 As shown, if the first region 1000 does not include through-silicon vias (TSVs), meaning it only contains densely distributed standard cells, heat will accumulate, hindering chip heat dissipation. Therefore, at least one TSV can be added to the first region, where the TSV's x and y coordinates are both within the x and y coordinate ranges of the first region. Before adjustment, the first region did not include TSVs, so heat dissipation and conductivity of the standard cells within the first region required TSVs in the surrounding area; however, after adding a TSV to the first region, heat dissipation and conductivity of the standard cells within this region can be achieved through the TSV.

[0075] In some embodiments, adding the through-silicon via in the first region includes:

[0076] If the first region includes at least one of the aforementioned through-silicon vias, then at least one of the aforementioned through-silicon vias is added to the first region.

[0077] In this embodiment, the number of through-silicon vias (TSVs) can be increased by adding at least one more TSV to the existing TSVs in the first region, thereby adjusting the distribution parameters. This makes the heat dissipation effect of the standard cells in the first region more significant, facilitating faster heat dissipation. On the other hand, the adjusted first region can include at least two of the aforementioned TSVs, which can withstand greater current and improve chip reliability.

[0078] In some embodiments, adjusting the distribution parameters of the through-silicon vias in the first region includes:

[0079] If the first region includes at least one of the through-silicon vias, increase the cross-sectional area of ​​at least one of the through-silicon vias in the first region, and add at least one of the through-silicon vias in the first region.

[0080] In this embodiment, the distribution parameters can be adjusted by increasing the cross-sectional area of ​​the through-silicon via (TSV) in the first region and simultaneously adding at least one TSV in the first region. This allows for faster heat dissipation even with high actual power consumption, improving the reliability of the chip's operation.

[0081] In the embodiments of this application, for the first region, one or more through-silicon vias can be flexibly adjusted according to actual needs or the needs of standard cells in the first region by increasing the number and adjusting the cross-sectional area of ​​the through-silicon vias, or a combination of two methods.

[0082] In some embodiments, adding at least one through-silicon via (TSV) in the first region if the first region does not include the TSV includes:

[0083] Identify a first through-silicon via located outside the first region, with its x-coordinate within the x-coordinate range of the first region;

[0084] At least one second through-silicon via is added within the first region.

[0085] Specifically, in this embodiment, adjusting the distribution parameters by adding through-silicon vias (TSVs) requires first determining a first TSV outside the first region, where the horizontal coordinate range of the first TSV lies within the horizontal coordinate range of the first region. Then, based on the distribution parameters of the first TSV, at least one second TSV is added within the first region. This maintains the consistency of the TSVs, ensures uniform heat distribution, and enhances chip reliability.

[0086] In some embodiments, adding at least one second through-silicon via in the first region includes:

[0087] Within the first region, at the same position as the first through-silicon via (TSV), add a second TSV with the same size as the first TSV.

[0088] In this embodiment, the added second via can have the same dimensions as the first via, including identical parameters such as cross-sectional area and height. For example, after determining the first via, the second via is added at the same horizontal coordinate as the first via within the first region. It should be noted that the effect after addition can be simulated using software during the chip design phase, and then implemented in subsequent manufacturing processes. In this way, the first region after adding the second via can reduce heat accumulation in the standard cell and decrease the current carried by the via per unit area, thereby enhancing chip reliability.

[0089] In some embodiments, adjusting the distribution positions of multiple standard cells on the chip according to the adjusted distribution parameters of the through-silicon vias includes:

[0090] The distribution positions of multiple standard cells on the chip are adjusted so that the standard cells in the first region are distributed outside the coverage area of ​​the through-silicon vias in the first region.

[0091] Furthermore, in this embodiment, after adjusting the distribution parameters of the through-silicon vias (TSVs), it is also necessary to adjust the distribution positions of multiple standard cells on the chip. The size of the standard cells can be determined according to actual needs, the coordinates of the standard cells need to be adjusted based on the coordinates of the TSVs, and the density of the standard cells needs to be adjusted based on the distribution parameters of the TSVs in the first region mentioned above.

[0092] For example, if the first region includes at least one through-silicon via (TSV), the cross-sectional area of ​​the TSV is increased. This will cause the positions of the standard cells originally distributed around the TSV to be occupied by the enlarged TSV. Therefore, the standard cells need to be rearranged around the new TSV size and coordinates. The standard cells located outside the TSV and unaffected can be arranged in their original distribution positions.

[0093] If the first region does not include through-silicon vias (TSVs), then TSVs are added. Since the standard cell density is high in the first region, the added TSVs will occupy more of the original standard cell positions. Therefore, the positions of the standard cells within the TSV coordinate range can be adjusted so that the standard cells are arranged around the added TSVs.

[0094] Therefore, the embodiments of this application can rearrange the distribution of standard cells with a smaller area consumption, which can improve heat dissipation efficiency and enhance chip reliability.

[0095] In some embodiments, the method further includes:

[0096] A second region on the chip with power consumption greater than a second threshold is identified; wherein the second region is located within the first region; and the area of ​​the second region is less than or equal to the area of ​​the first region.

[0097] Adjust the distribution parameters of the through-silicon vias in the second region.

[0098] In this embodiment, after adjusting the distribution position of the standard cells in the first region, the standard cells in the second region can also be adjusted. The second region can be located within the first region, and its power consumption should be greater than a second threshold, which can be set according to actual conditions. For example, the area of ​​the second region can be smaller than the area of ​​the first region, resulting in a higher density of standard cells distributed within the second region, making it easier for heat to accumulate. Therefore, the second threshold can be greater than the first threshold.

[0099] Therefore, embodiments of this application can determine a smaller second region, adjust the distribution parameters of through-silicon vias within the second region, and further adjust the distribution positions of standard cells. This allows for more precise identification of high-power regions, reduces potential heat accumulation within these regions, and further improves chip reliability.

[0100] In some embodiments, the method further includes:

[0101] The distribution positions of multiple standard cells on the chip are adjusted so that the standard cells in the second region are distributed outside the coverage area of ​​the through-silicon vias in the second region.

[0102] The standard cells involved in this embodiment can be distributed outside their coverage area according to the distribution parameters of the through-silicon vias (TSVs). This allows for adjustments within a small area of ​​the TSV region, minimizing changes to the distribution of standard cells in the chip, while simultaneously reducing heat accumulation, accelerating heat dissipation, and enhancing chip reliability.

[0103] In some embodiments, the method further includes:

[0104] The wiring of the chip is determined based on the adjusted distribution parameters of the through-silicon vias and the distribution positions of the standard cells.

[0105] In this embodiment, after the chip design is completed, i.e., after adjusting the distribution parameters of the through-silicon vias and the distribution positions of the standard cells, the wiring for the chip packaging stage must be determined. This layout and wiring needs to be determined based on the actual packaging process. For example, if a flip-chip packaging process is used, the connection wiring for flip-chip blocks or standard cells needs to be considered.

[0106] The embodiments of this application may also include:

[0107] An automation script plugin based on Redhawk software. For example... Figure 6 As shown, in the early stages of chip design, chip placement and routing (PR) can be achieved based on a fixed pattern of back through-silicon vias (i.e., the aforementioned through-silicon vias). Simulation of a first mode is performed based on the toggle rate data provided during the front-end design phase. This first mode can be the vectorless mode in Redhawk. In this embodiment, the region with higher power consumption, i.e., the aforementioned first region (50um*50um), can be obtained using the vectorless mode. This first region is also a region with concentrated current and a high density of standard cells, which easily leads to heat accumulation. It is a potential heat accumulation area during actual chip operation and needs to be avoided in advance. Therefore, this embodiment allows for adjustments to the distribution of standard cells within the first region during the design phase, thereby solving the aforementioned problem.

[0108] After adjusting the standard cell distribution in the first region using vectorless mode, further adjustments can be made using a VCD (Value Change Dump) file from the front-end design. This VCD file is an ASCII-based stimulus file defined by the IEEE 1364 standard (Verilog HDL language standard). It mainly contains header information, predefined variables, and variable value change information, used to record simulation information throughout the front-end design phase. Therefore, the VCD file can be used in the back-end design to reproduce the simulation, simulating the power consumption distribution under actual operating conditions; it can also be used to display waveforms and select a more precise region to adjust the standard cell distribution based on the complete signal change information, thereby reducing power consumption. For example, a VCD file is imported into Redhawk to determine the second region (30µm * 30µm). This second region can also be a region with higher power consumption, but because the VCD file can estimate power consumption more accurately, the area of ​​the second region can be smaller than the area of ​​the first region, allowing for more precise adjustment of the standard cell distribution and reducing the number of steps required.

[0109] It should be noted that the chip design method provided in this application embodiment can be used in any chip system with wafer-on-wafer or die-on-wafer, and can also be applied to chip systems using hybrid bonding technology.

[0110] On the other hand, embodiments of this application also provide a chip 100, which is designed using any of the methods described above. For example... Figure 7 As shown, the chip 100 includes:

[0111] Substrate 110;

[0112] Device layer 120 is located on substrate 110; device layer 120 includes a plurality of standard cells 121;

[0113] A through-silicon via 130 penetrates the substrate 110 and the device layer 120.

[0114] In this embodiment, chip 100 is a finished product after the chip design stage, and further packaging and testing are required. The through-silicon via (TSV) here, also known as a back-side TSV, is a vertical interconnect that penetrates the wafer or chip, used to connect the chip bonded to chip 100 to the system-in-package (SiP) substrate during subsequent packaging. For example, if flip chip packaging is used, flip chip bumps can also be electrically connected to the TSV to power the standard cells on the chip.

[0115] It should be noted that the features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0116] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip design method, characterized in that, The method includes: Based on the distribution parameters of multiple standard cells on the chip, the power consumption of at least two different regions on the chip is determined, including: in the early stage of chip design, the chip layout and routing are realized based on a fixed pattern of back silicon via layout, and simulation is performed based on the flip-flop rate data provided by the front-end design to determine the power consumption of at least two different regions on the chip. Based on the power consumption of the at least two different regions, adjust the distribution parameters of at least two through-silicon vias on the chip; Based on the adjusted distribution parameters of the through-silicon vias, the distribution positions of multiple standard cells on the chip are adjusted, including: rearranging the standard cells within the adjusted coordinate range of the through-silicon vias to outside the coverage area of ​​the through-silicon vias.

2. The method according to claim 1, characterized in that, The step of adjusting the distribution parameters of at least two through-silicon vias on the chip based on the power consumption of the at least two different regions includes: Determine a first region on the chip where the power consumption is greater than a first threshold. Adjust the distribution parameters of the through-silicon vias in the first region.

3. The method according to claim 2, characterized in that, Adjusting the distribution parameters of the through-silicon vias in the first region includes: Increase the cross-sectional area of ​​the through-silicon via in the first region; and / or Add the through-silicon via in the first region.

4. The method according to claim 3, characterized in that, Increasing the cross-sectional area of ​​the through-silicon via in the first region includes: If the first region includes at least one of the through-silicon vias, increase the cross-sectional area of ​​at least one of the through-silicon vias in the first region.

5. The method according to claim 3, characterized in that, Adding the through-silicon via in the first region includes: If the first region does not include the through-silicon via (TSV), then at least one TSV is added to the first region.

6. The method according to claim 5, characterized in that, If the first region does not include the through-silicon via (TSV), then adding at least one TSV to the first region includes: Identify a first through-silicon via located outside the first region, with its x-coordinate within the x-coordinate range of the first region; At least one second through-silicon via is added within the first region.

7. The method according to claim 6, characterized in that, Adding at least one second through-silicon via in the first region includes: Within the first region, at the same position as the first through-silicon via (TSV), add a second TSV with the same size as the first TSV.

8. The method according to claim 2, characterized in that, The method further includes: A second region on the chip with power consumption greater than a second threshold is identified; wherein the second region is located within the first region; and the area of ​​the second region is less than or equal to the area of ​​the first region. Adjust the distribution parameters of the through-silicon vias in the second region.

9. The method according to any one of claims 1 to 8, characterized in that, The method further includes: The wiring of the chip is determined based on the adjusted distribution parameters of the through-silicon vias and the distribution positions of the standard cells.

10. A chip, characterized in that, The chip is designed using any one of the methods of claims 1-8, and the chip comprises: Substrate; A device layer is located on the substrate; the device layer includes a plurality of standard cells; Through-silicon vias penetrate the substrate and the device layer.

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