A memory package including a memory chip and a memory controller

Abstract

A memory package including a memory chip and a memory controller. The memory package includes a package substrate that includes power wirings and ground wirings. The memory package further includes a memory controller disposed above the upper surface of the package substrate and electrically connected to the power wirings and the ground wirings. The memory package further includes a memory chip disposed above the memory controller and electrically connected to the power wirings and the ground wirings. The memory package additionally includes a band-pass filter that is disposed on one side of the memory controller above the upper surface of the package substrate and includes an inductor and a capacitor connected in series. The inductor and the capacitor connected in series are electrically connected between the power wiring and the ground wiring.

Description

Technical Field

[0001] This patent document relates to a memory package, and more particularly, to a memory package including a memory chip and a memory controller. Background Art

[0002] Electromagnetic interference refers to the phenomenon that high-frequency noise generated from an electronic circuit or system affects an adjacent circuit, system, or human body. One method of blocking or attenuating electromagnetic interference is to block or attenuate power supply noise. Summary of the Invention

[0003] In an embodiment, a memory package may include: a package substrate including a power supply wiring and a ground wiring; a memory controller disposed above an upper surface of the package substrate and electrically connected to the power supply wiring and the ground wiring; a memory chip disposed above the memory controller and electrically connected to the power supply wiring and the ground wiring; and a band-pass filter disposed above the upper surface of the package substrate on one side of the memory controller and including an inductor and a capacitor connected in series, wherein one of an electrode of the inductor and an electrode of the capacitor is electrically connected to the power supply wiring, and the other of the electrode of the inductor and the electrode of the capacitor is electrically connected to the ground wiring.

[0004] In another embodiment, a memory package may include: a package substrate including a power supply wiring and a ground wiring; a memory controller disposed on the upper surface of the package substrate and electrically connected to the power supply wiring and the ground wiring; a memory chip disposed above the memory controller and electrically connected to the power supply wiring and the ground wiring; and a band-pass filter disposed above the upper surface of the package substrate on one side of the memory controller and including an inductor and a capacitor connected in series. The inductor and the capacitor connected in series are electrically connected between the power supply wiring and the ground wiring. Brief Description of the Drawings

[0005] Figure 1 is a circuit diagram illustrating a circuit corresponding to a memory package according to an embodiment of the present disclosure.

[0006] Figure 2 is a plan view of a memory package according to an embodiment of the present disclosure.

[0007] Figure 3 is along Figure 2 a cross-sectional view taken along line A1 - A1'.

[0008] Figure 4 is along Figure 2 a cross-sectional view taken along line A2 - A2'.

[0009] Figure 5 is alongFigure 2 A sectional view taken along line A3 - A3'.

[0010] Figure 6 A diagram illustrating the effect of the memory package according to the present embodiment.

[0011] Figure 7A A diagram illustrating another effect of the memory package of the present embodiment.

[0012] Figure 7B For comparison with Figure 7A A diagram for comparison.

[0013] Figure 8 A block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment.

[0014] Figure 9 A block diagram illustrating another electronic system including a semiconductor package according to an embodiment. Detailed Description of the Embodiments

[0015] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0016] The drawings may not necessarily be drawn to scale, and in some cases, the scale of at least some of the structures shown in the drawings may have been exaggerated to clearly illustrate certain features of the described embodiments or implementations. When presenting a specific embodiment having two or more layers in a multi - layer structure in the drawings or the description, the relative positional relationship or the arrangement order of such layers shown reflects the specific implementation of the described or illustrated embodiment, and different relative positional relationships or arrangement orders of the layers are also possible. In addition, the described or illustrated embodiments of the multi - layer structure may not reflect all the layers present in the specific multi - layer structure (e.g., there may be one or more additional layers between two illustrated layers). As a specific example, when the first layer in the described or illustrated multi - layer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or the substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0017] Figure 1 A circuit diagram illustrating a circuit corresponding to the memory package according to an embodiment of the present disclosure.

[0018] Referring to Figure 1, the memory package may include a memory chip 120, a memory controller 110 electrically connected to the memory chip 120 and controlling the memory chip 120, and a band-pass filter 130 connected to an electrical connection path between the memory chip 120 and the memory controller 110.

[0019] The memory chip 120 may include a memory cell array 122 and a signal input / output circuit 124. The memory cell array 122 may store data. The signal input / output circuit 124 may transmit signals such as data between the memory controller 110 and the memory cell array 122.

[0020] The memory cell array 122 may function to store data corresponding to data signals transmitted from the signal input / output circuit 124. The memory cell array 122 may include a non-volatile memory. For example, the memory cell array 122 may include a NAND memory. However, the present disclosure is not limited thereto. The memory cell array 122 may include non-volatile memories such as phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), etc. The memory cell array 122 may include volatile memories such as dynamic random access memory (DRAM), static random access memory (SRAM), etc. The memory cell array 122 may also include a combination of a volatile memory and a non-volatile memory.

[0021] The signal input / output circuit 124 may be connected to a signal path 142 that electrically connects the memory controller 110 and the signal input / output circuit 124. The signal input / output circuit 124 may receive signals from the memory controller 110 or output signals to the memory controller 110. In addition, the signal input / output circuit 124 may be connected between a power path 144 and a ground path 146 to receive a power supply voltage such as VCCQ and a ground voltage such as VSSM. The signal input / output circuit 124 may operate using these voltages.

[0022] The memory controller 110 and the memory chip 120 may share a power supply voltage and a ground voltage. For this reason, the memory controller 110 may also be connected between the power path 144 and the ground path 146 and receive from the outside a power supply voltage and a ground voltage that are respectively equal to the power supply voltage and the ground voltage provided to the memory chip 120. The memory controller 110 may operate using these voltages.

[0023] The power supply provided during the operation of the memory controller 110 and the signal input / output circuit 124 may preferably be static. However, in actual operation, power supply noise may be generated, and such noise may create a high impedance in the operating band and harmonic band of the memory controller 110 and / or the signal input / output circuit 124. This high impedance may cause charge to accumulate in the wires, thereby emitting electromagnetic waves. This may cause problems such as electromagnetic interference. Therefore, the impedance can be reduced by blocking the power supply noise in a specific frequency band. In this embodiment, to meet this requirement, the band-pass filter 130 may be additionally connected between the power supply path 144 and the ground path 146.

[0024] The band-pass filter 130 may refer to a filter that selectively allows only the frequencies of a specific frequency band to pass through and blocks / attenuates the rest. The band-pass filter 130 may include an inductor 132 and a capacitor 134 connected in series. In other words, the band-pass filter 130 may be an LC filter. The inductor 132 may have the characteristic of suppressing high frequencies, and the capacitor 134 may have the characteristic of allowing high frequencies to pass through. Therefore, when the inductor 132 and the capacitor 134 are connected in series, frequencies can be selectively passed through or blocked. As a result, the power supply noise in a specific frequency band can be blocked / attenuated, thereby shielding EMI. In the present disclosure, one end of the inductor 132 is connected to the power supply path 144, and one end of the capacitor 134 is connected to the ground path 146. However, the positions of the inductor 132 and the capacitor 134 may be reversed.

[0025] In addition, in the band-pass filter 130 of this embodiment, the capacitor 134 may also function as a decoupling capacitor for preventing power shortage generated during the operation of the memory controller 110. Therefore, the capacitor 134 and the band-pass filter 130 including it may be placed adjacent to the memory controller 110. For example, the capacitor 134 and the band-pass filter 130 including it may be arranged to be closer to the memory controller 110 than the memory chip 120 in each of the power supply path 144 and the ground path 146.

[0026] According to the above circuit, the band-pass filter 130 may have the effect of shielding EMI by blocking / attenuating the noise of the power supply provided during the operation of the memory chip 120 and the memory controller 110.

[0027] In addition, the capacitor 134 included in the band-pass filter 130 can be used to prevent power shortage generated during the operation of the memory controller 110.

[0028] In addition, power supply noise may have an adverse effect on signal transmission between the memory chip 120 and the memory controller 110. When the power supply noise is blocked / attenuated as described above, the integrity of the signal transmitted between the memory chip 120 and the memory controller 110 can be ensured.

[0029] Hereinafter, reference will be made to Figures 2 to 5 describe the implementation of Figure 1 of the circuit of the memory package.

[0030] Figure 2 is a plan view illustrating a memory package according to an embodiment of the present disclosure, Figure 3 is a cross-sectional view taken along line A1-A1' of Figure 2 and is a cross-sectional view taken along line A2-A2' of Figure 4 is a cross-sectional view taken along line A3-A3' of Figure 2 and Figure 5 is a cross-sectional view taken along line A3-A3' of Figure 2 and is a cross-sectional view taken along line A3-A3'.

[0031] Referring to Figures 2 to 5 , the memory package may include a package substrate 100, a memory controller 110 and a band-pass filter 130 formed above the upper surface of the package substrate 100, a memory chip 120 formed above the memory controller 110, and external connection terminals 150 formed above the lower surface of the package substrate 100.

[0032] The package substrate 100 may have a multilayer wiring structure for transmitting electrical signals. As an example, the package substrate 100 may be a printed circuit board (PCB). After first describing the memory controller 110, the memory chip 120, and the band-pass filter 130, the multilayer wiring structure of the package substrate 100 will be described in detail.

[0033] The memory controller 110 may be disposed above the upper surface of the package substrate 100. The memory controller 110 may include a plurality of connection terminals 112, 114, and 116 for connecting to the package substrate 100 and receiving power or signals therefrom. Among the plurality of connection terminals 112, 114, and 116, the terminal to which a signal is applied will be referred to as the signal connection terminal 112, the terminal to which a power supply voltage is applied will be referred to as the power connection terminal 114, and the terminal to which a ground voltage is applied will be referred to as the ground connection terminal 116. In this embodiment, the connection terminals 112, 114, 116 may be conductive bumps formed above the lower surface of the memory controller 110 facing the package substrate 100. Additionally, in this embodiment, the signal connection terminal 112, the ground connection terminal 116, and the power connection terminal 114 may be arranged on each of the two side edges of the memory controller 110 in a first direction and arranged in a row along a second direction. However, the present disclosure is not limited thereto, and the shape, number, and arrangement of the connection terminals 112, 114, and 116 may be modified in various ways.

[0034] The memory chip 120 may be disposed above the memory controller 110. The memory chip 120 may be directly attached to the upper surface of the memory controller 110. Alternatively, an adhesive material (not shown) may be used to attach the memory chip 120 to the upper surface of the memory controller 110. In this embodiment, the memory chip 120 may have a larger planar area than the memory controller 110. Further, the memory chip 120 may be disposed such that the center of the memory chip 120 overlaps with the memory controller 110. However, the present disclosure is not limited thereto, and the planar area of the memory chip 120 or the overlapping portion with the memory controller 110 may be modified in various ways as long as the memory chip 120 is disposed above the memory controller 110 and overlaps with the memory controller 110.

[0035] A plurality of chip pads 122, 124, and 126 can be disposed above the upper surface of the memory chip 120. The chip pads 122, 124, and 126 can be electrically connected to the package substrate 100 and receive power or signals from the package substrate 100. Among the plurality of chip pads 122, 124, and 126, the chip pad to which a signal is applied will be referred to as the signal chip pad 122, the chip pad to which a power supply voltage is applied will be referred to as the power supply chip pad 124, and the chip pad to which a ground voltage is applied will be referred to as the ground chip pad 126. In this embodiment, the chip pads 122, 124, and 126 can be arranged in a row at one edge of the memory chip 120 in a first direction. As an example, two signal chip pads 122, one ground chip pad 126, and one power supply chip pad 124 are shown. However, the present disclosure is not limited thereto, and the number, arrangement, etc. of the chip pads 122, 124, and 126 can be modified in various ways.

[0036] The chip pads 122, 124, and 126 can be electrically connected to a part of the package substrate 100, such as a plurality of bonding pads 102, 104, and 106 disposed above the upper surface of the package substrate 100, through bonding wirings 128. Among the plurality of bonding pads 102, 104, and 106, the bonding pad to which a signal is applied will be referred to as the signal bonding pad 102, the bonding pad to which a power supply voltage is applied will be referred to as the power supply bonding pad 104, and the pad to which a ground voltage is applied will be referred to as the ground bonding pad 106. In this embodiment, the bonding pads 102, 104, and 106 can respectively correspond to the chip pads 122, 124, and 126. The bonding pads 102, 104, and 106 can be arranged in a row at one edge of the package substrate 100 in a first direction. As an example, two signal bonding pads 102, one ground bonding pad 106, and one power supply bonding pad 104 are shown. However, the present disclosure is not limited thereto, and the number, arrangement, etc. of the bonding pads 102, 104, and 106 can be modified in various ways.

[0037] Both ends of the bonding wiring 128 can be respectively connected to the signal chip pad 122 and the corresponding signal bonding pad 102 and electrically connect them. In addition, both ends of the bonding wiring 128 can be respectively connected to the power supply chip pad 124 and the corresponding power supply bonding pad 104 and electrically connect them. In addition, both ends of the bonding wiring 128 can be respectively connected to the ground chip pad 126 and the corresponding ground bonding pad 106 and electrically connect them.

[0038] In addition, in order to easily connect the chip pads 122, 124, and 126 to the bonding pads 102, 104, and 106 using the bonding wiring 128, the memory chip 120 may preferably be arranged to expose the bonding pads 102, 104, and 106 provided at one edge of the package substrate 100 in the first direction. As an example, the memory chip 120 may have a smaller planar area than the package substrate 100 and be arranged to overlap the center of the package substrate 100.

[0039] The band-pass filter 130 may include an inductor 132 and a capacitor 134. The inductor 132 and the capacitor 134 may be provided above the upper surface of the package substrate 100. One of the two electrodes of the inductor 132 and one of the two electrodes of the capacitor 134 may be connected to the package substrate 100 and receive power from the package substrate 100. In this embodiment, a power supply voltage is applied to one electrode of the inductor 132, and a ground voltage is applied to one electrode of the capacitor 134. However, the reverse may also be true. The other of the two electrodes of the inductor 132 and the other of the two electrodes of the capacitor 134 may be connected to the package substrate 100 and may be electrically connected to each other through the package substrate 100.

[0040] In this embodiment, the inductor 132 and the capacitor 134 may be provided on the other side of the memory controller 110 in the first direction. The inductor 132 and the capacitor 134 may be spaced apart from the memory controller by a certain distance. In this case, the power connection terminal 114 and the ground connection terminal 116 provided at the other edge of the memory controller 110 in the first direction may be connected to the inductor 132 and the capacitor 134, respectively. Thus, the distance between the power connection terminal 114 and the inductor 132 and / or between the ground connection terminal 116 and the capacitor 134 may be minimized as much as possible. As described above, when the electrical connection path between the capacitor 134 and the memory controller 110 is reduced, the power shortage generated during the operation of the memory controller 110 can be more easily resolved by the capacitor 134. However, the present disclosure is not limited thereto, and the arrangement and position of the inductor 132 and the capacitor 134 may be modified in various ways.

[0041] In addition, in this embodiment, the inductor 132 and the capacitor 134 may be provided at the other edge of the package substrate 100 in the first direction so as not to overlap with the memory chip 120. However, the present disclosure is not limited thereto, and at least a part of the inductor 132 and / or at least a part of the capacitor 134 may overlap with the memory chip 120. That is, at least a part of the inductor 132 and / or at least a part of the capacitor 134 may be provided in the space between the memory chip 120 and the package substrate 100.

[0042] The encapsulation substrate 100 may have a multi-layer wiring structure. In this embodiment, the encapsulation substrate 100 may include four layers L1, L2, L3, and L4 in which horizontal wirings are formed. For ease of description, the four layers L1, L2, L3, and L4 are respectively referred to as the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 according to the distance from the upper surface of the encapsulation substrate 100. In addition, the horizontal wirings respectively formed in the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 will be referred to as the first horizontal wiring W1, the second horizontal wiring W2, the third horizontal wiring W3, and the fourth horizontal wiring W4. The upper surface or the lower surface of the encapsulation substrate 100 and the horizontal wirings W1, W2, W3, and W4 may be connected to each other through vertical wirings. Hereinafter, the vertical wiring connecting the upper surface of the encapsulation substrate 100 and the first horizontal wiring W1 will be referred to as the first vertical wiring V1, the vertical wiring connecting the upper surface of the encapsulation substrate 100 and the second horizontal wiring W2 will be referred to as the second vertical wiring V2, the vertical wiring connecting the upper surface of the encapsulation substrate 100 and the third horizontal wiring W3 will be referred to as the third vertical wiring V3, and the vertical wiring connecting the upper surface of the encapsulation substrate 100 and the fourth horizontal wiring W4 will be referred to as the fourth vertical wiring V4. In this embodiment, the third horizontal wiring W3 and the fourth horizontal wiring W4 may be used as power supply wirings for receiving power from the outside. For this reason, the fifth vertical wiring V5 may be formed to connect the third horizontal wiring W3 and the lower surface of the encapsulation substrate 100 where the external connection terminal 150 is provided on the upper surface. In addition, the sixth vertical wiring V6 may be formed to connect the fourth horizontal wiring W4 and the lower surface of the encapsulation substrate 100 where the external connection terminal 150 is provided on the upper surface. The remaining part of the encapsulation substrate 100 other than the horizontal wirings W1, W2, W3, and W4 and the vertical wirings V1, V2, V3, V4, V5, and V6 may include an insulating material.

[0043] Hereinafter, with reference to Figure 2 and Figure 3 , the ground voltage transmission path in the encapsulation substrate 100 will be described. In the present embodiment, the wiring for transmitting the ground voltage may be the fourth horizontal wiring W4, and the fourth vertical wiring V4 and the sixth vertical wiring V6 connected thereto. However, the present disclosure is not limited thereto, and any one of the first horizontal wiring to the third horizontal wirings W1, W2, and W3 and the vertical wiring connected thereto may be used to transmit the ground voltage.

[0044] The fourth horizontal wiring W4 can be electrically connected to the ground connection terminal 116 of the memory controller 110, the ground bonding pad 106 above the upper surface of the package substrate 100, and one electrode of the inductor 132. As an example, the ground connection terminal 116 can be electrically connected to the fourth horizontal wiring W4 through the fourth vertical wiring V4 that overlaps and is directly connected to the ground connection terminal 116. The ground bonding pad 106 can also be electrically connected to the fourth horizontal wiring W4 through the fourth vertical wiring V4 that overlaps and is directly connected to the ground bonding pad 106. On the other hand, one electrode of the inductor 132 can be electrically connected to the fourth horizontal wiring W4 through the first vertical wiring V1 that overlaps and is directly connected to one electrode of the inductor 132, the first horizontal wiring W1 that connects the first vertical wiring V1 and extends to the fourth vertical wiring V4, and the fourth vertical wiring V4. However, the present disclosure is not limited thereto, and the ground connection terminal 116, the ground bonding pad 106, and one electrode of the inductor 132 can be electrically connected to the fourth vertical wiring V4 through an appropriate combination of the first vertical wiring to the third vertical wiring V1, V2, and V3 and the first horizontal wiring to the third horizontal wiring W1, W2, and W3.

[0045] In addition, in this cross-sectional view, the external connection terminals 150 should be invisible, but for ease of description, the ground external connection terminal 156 to which a ground voltage is applied among the external connection terminals 150 is illustrated together. The fourth horizontal wiring W4 can be electrically connected to the ground external connection terminal 156 through the sixth vertical wiring V6.

[0046] Therefore, a ground voltage supply path can be formed to transmit the ground voltage to the ground connection terminal 116 and the ground bonding pad 106 through the ground external connection terminal 156, the sixth vertical wiring V6, the fourth horizontal wiring W4, and the fourth vertical wiring V4. Additionally, a ground voltage supply path can be formed to transmit the ground voltage to one electrode of the inductor 132 through the ground external connection terminal 156, the sixth vertical wiring V6, the fourth horizontal wiring W4, the fourth vertical wiring V4, the first horizontal wiring W1, and the first vertical wiring V1.

[0047] In the plan view, the above-mentioned ground voltage supply path can have a wire shape that bends in various directions to interconnect the ground bonding pad 106, the ground connection terminal 116, the ground external connection terminal 156, and one electrode of the inductor 132.

[0048] Next, refer to Figure 2 and Figure 4, the power voltage transmission path in the package substrate 100 will be described. In the present embodiment, the wiring for transmitting the power voltage may be the third horizontal wiring W3 and the third vertical wiring V3 and the fifth vertical wiring V5 connected thereto. However, the present disclosure is not limited thereto, and any one of the first horizontal wiring W1, the second horizontal wiring W2, and the fourth horizontal wiring W4 and the vertical wiring connected thereto may be used to transmit the power voltage.

[0049] The third horizontal wiring W3 may be electrically connected to the power connection terminal 114 of the memory controller 110, the power bonding pad 104 above the upper surface of the package substrate 100, and one electrode of the capacitor 134. As an example, the power connection terminal 114 may be electrically connected to the third horizontal wiring W3 through the third vertical wiring V3 that overlaps and is directly connected to the power connection terminal 114. The power bonding pad 104 may also be electrically connected to the third horizontal wiring W3 through the third vertical wiring V3 that overlaps and is directly connected to the power bonding pad 104. On the other hand, one electrode of the capacitor 134 may be electrically connected to the third horizontal wiring W3 through the first vertical wiring V1 that overlaps and is directly connected to one electrode of the capacitor 134, the first horizontal wiring W1 connected to the first vertical wiring V1 and extending to the third vertical wiring V3, and the third vertical wiring V3. However, the present disclosure is not limited thereto, and the power connection terminal 114, the power bonding pad 104, and one electrode of the capacitor 134 may be electrically connected to the third vertical wiring V3 through an appropriate combination of the first vertical wiring V1 and the second vertical wiring V2, and the first horizontal wiring W1 and the second horizontal wiring W2.

[0050] In addition, in this cross-sectional view, the external connection terminals 150 should not be seen, but for ease of description, the power external connection terminal 154 to which the power voltage is applied among the external connection terminals 150 is illustrated together. The third horizontal wiring W3 may be electrically connected to the power external connection terminal 154 through the fifth vertical wiring V5.

[0051] Therefore, a power voltage supply path for transmitting the power voltage to the power connection terminal 114 and the power bonding pad 104 through the power external connection terminal 154, the fifth vertical wiring V5, the third horizontal wiring W3, and the third vertical wiring V3 can be formed. In addition, a power voltage supply path for transmitting the power voltage to one electrode of the capacitor 134 through the power external connection terminal 154, the fifth vertical wiring V5, the third horizontal wiring W3, the third vertical wiring V3, the first horizontal wiring W1, and the first vertical wiring V1 can be formed.

[0052] In summary, the inductor 132 and the capacitor 134 connected in series are electrically connected between the power wiring (see Figure 4 V5, W3, V3, W1, and V1) and the ground wiring (seeFigure 3 between V6, W4, V4, W1, and V1).

[0053] In a plan view, the above power supply voltage supply path may have a wire shape that bends in various directions to interconnect the power supply bonding pad 104, the power supply connection terminal 114, the power supply external connection terminal 154, and one electrode of the capacitor 134. Additionally, the power supply voltage supply path may be spaced apart and separated from the above ground voltage supply path.

[0054] Next, referring to Figure 2 , Figure 3 and Figure 4 , the connection path between the inductor 132 and the capacitor 134 in the package substrate 100 will be described. In the present embodiment, the wiring for connecting the inductor 132 and the capacitor 134 may be the first horizontal wiring W1 and the first vertical wiring V1 connected thereto. However, the present disclosure is not limited thereto, and any one of the second to fourth horizontal wirings W2, W3, and W4 and the vertical wiring connected thereto may be used to connect the inductor 132 and the capacitor 134.

[0055] The first horizontal wiring W1 may be electrically connected to the other electrode of the inductor 132 and the other electrode of the capacitor 134 through the first vertical wiring V1 that overlaps and is directly connected to each of the other electrode of the inductor 132 and the other electrode of the capacitor 134. Since the first vertical wiring V1 and the first horizontal wiring W1 are only used to connect the inductor 132 and the capacitor 134, there is no need to connect to the external connection terminal 150 or the like.

[0056] Next, referring to Figure 2 and Figure 5 , the signal transmission path in the package substrate 100 will be described. In this embodiment, the wiring for transmitting signals between the memory controller 110 and the memory chip 120 may be the second horizontal wiring W2 and the second vertical wiring V2 connected thereto. However, the present disclosure is not limited thereto, and any one of the first horizontal wiring W1, the third horizontal wiring W3, and the fourth horizontal wiring W4 and the vertical wiring connected thereto may be used to transmit signals.

[0057] The second horizontal wiring W2 can be electrically connected to the signal connection terminal 112 of the memory controller 110 and the signal bonding pad 102 above the upper surface of the package substrate 100. As an example, the signal connection terminal 112 can be electrically connected to the second horizontal wiring W2 through the second vertical wiring V2 that overlaps and is directly connected to the signal connection terminal 112. The signal bonding pad 102 can also be electrically connected to the second horizontal wiring W2 through the second vertical wiring V2 that overlaps and is directly connected to the signal bonding pad 102. However, the present disclosure is not limited thereto, and the signal connection terminal 112 and the signal bonding pad 102 can be electrically connected to the second vertical wiring V2 through an appropriate combination of the first vertical wiring V1 and the first horizontal wiring W1. Since the second vertical wiring V2 and the second horizontal wiring W2 are only used to connect the memory chip 120 and the memory controller 110, there is no need to connect to the external connection terminal 150 or the like.

[0058] According to the memory package described above, since a Figure 1 circuit is implemented, all the effects obtained by the Figure 1 circuit can be obtained.

[0059] In addition, since the paths connecting the connection inductor 132 and the capacitor 134 in the package substrate 100 are the shortest by using the first horizontal wiring W1 and the first vertical wiring V1, their electrical connection can be smoothly achieved.

[0060] In addition, since the path connecting the memory chip 120 and the memory controller 110 in the package substrate 100 is the second shortest by using the second horizontal wiring W2 and the second vertical wiring V2, signals can be smoothly exchanged between them.

[0061] Furthermore, instead of directly connecting one electrode of the inductor 132 and one electrode of the capacitor 134 to the third vertical wiring V3 and the fourth vertical wiring V4, one electrode of the inductor 132 and one electrode of the capacitor 134 can be connected to the third vertical wiring V3 and the fourth vertical wiring V4 via the first vertical wiring V1 and the first horizontal wiring W1. The first horizontal wiring W1 connected to one electrode of the inductor 132 can extend to the fourth vertical wiring V4 connected to the ground connection terminal 116 of the memory controller 110. The first horizontal wiring W1 connected to one electrode of the capacitor 134 can extend to the third vertical wiring V3 connected to the power connection terminal 114 of the memory controller 110. In this case, the distance between the memory controller 110 and the inductor 132 and the electrical connection path between the memory controller 110 and the capacitor 134 can be reduced. As a result, the decoupling capacitor function of the capacitor 134 can be improved.

[0062] Figure 6FIG. is a diagram illustrating the effects of a memory package according to the present embodiment. In Figure 6 the first case (Case 1) represents a case where only a capacitor is formed between the memory controller 110 and the memory chip 120, and the second case (Case 2) represents a case where a band-pass filter 130 including an inductor 132 and a capacitor 134 connected in series is formed between the memory controller 110 and the memory chip 120.

[0063] Referring to Figure 6 , it can be seen that, compared with the first case, the impedance in the second case is reduced by reducing the power supply noise in a specific frequency band (e.g., Wi-Fi frequency band).

[0064] Figure 7A FIG. is a diagram illustrating another effect of the memory package according to the present embodiment, and Figure 7B is a diagram for comparison with Figure 7A . Figure 7A shows the field strength representing the degree of electromagnetic wave generation when a band-pass filter 130 including an inductor 132 and a capacitor 134 connected in series is formed between the memory controller 110 and the memory chip 120. Figure 7B shows the field strength when only a capacitor is formed between the memory controller 110 and the memory chip 120.

[0065] Referring to Figure 7A , it can be seen that, compared with Figure 7B , the field strength is significantly reduced. As a result, it can be seen that, for the memory package according to this embodiment, the degree of electromagnetic wave generation is reduced.

[0066] According to an embodiment of the present disclosure, there is provided a memory package capable of shielding electromagnetic interference and ensuring signal integrity by blocking / attenuating power supply noise.

[0067] Figure 8 FIG. is a block diagram illustrating an electronic system including a memory card 7800 employing at least one semiconductor package according to an embodiment. The memory card 7800 includes a memory 7810 such as a non-volatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 can store data or read out the stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of the semiconductor packages according to the described embodiment.

[0068] The memory 7810 may include a non-volatile memory device applying the technology of the embodiment of the present disclosure. The memory controller 7820 may control the memory 7810 such that the stored data is read out or data is stored in response to a read / write request from the host 7830.

[0069] Figure 9 FIG. shows a block diagram of an electronic system 8710 including at least one semiconductor package according to the described embodiments. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be coupled to each other via a bus 8715 that provides a data movement path.

[0070] In an embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more semiconductor packages according to the embodiments of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 8713 is a device for storing data. The memory 8713 may store commands and / or data to be executed by the controller 8711, etc.

[0071] The memory 8713 may include a volatile memory device such as DRAM and / or a non-volatile memory device such as flash memory. For example, flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may form a solid state drive (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.

[0072] The electronic system 8710 may further include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be of a wired type or a wireless type. For example, the interface 8714 may include an antenna, or a wired or wireless transceiver.

[0073] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information sending / receiving system.

[0074] If the electronic system 8710 represents equipment capable of performing wireless communication, the electronic system 8710 may be used in a communication system using technologies such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0075] Although various embodiments have been described for exemplary purposes, it will be apparent to those skilled in the art that various variations and modifications can be made without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0076] Cross - reference to related applications

[0077] This application claims priority to Korean Patent Application No. 10 - 2020 - 0050620, filed on April 27, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A memory package, the memory package comprising: A package substrate, the package substrate including a power supply wiring and a ground wiring; A memory controller, the memory controller being disposed above the upper surface of the package substrate and electrically connected to the power supply wiring and the ground wiring; A memory chip, the memory chip being disposed above the memory controller and electrically connected to the power supply wiring and the ground wiring; And A band-pass filter, the band-pass filter being disposed on one side of the memory controller above the upper surface of the package substrate and including an inductor and a capacitor connected in series, Wherein, one of an electrode of the inductor and an electrode of the capacitor is electrically connected to the power supply wiring, and the other of an electrode of the inductor and an electrode of the capacitor is electrically connected to the ground wiring, Wherein, the package substrate further includes a connection wiring, the connection wiring connecting the other electrode of the inductor and the other electrode of the capacitor to each other, Wherein, the connection wiring, the power supply wiring and the ground wiring are located in different layers in a direction perpendicular to the upper surface of the package substrate, and Wherein, the connection wiring is closer to the upper surface of the package substrate than the power supply wiring and the ground wiring.

2. The memory package according to claim 1, wherein, The package substrate further includes a signal wiring for exchanging signals between the memory chip and the memory controller.

3. The memory package according to claim 2, wherein, The signal wiring, the power supply wiring and the ground wiring are located in different layers in a direction perpendicular to the upper surface of the package substrate; and The signal wiring is closer to the upper surface of the package substrate than the power supply wiring and the ground wiring.

4. The memory package according to claim 1, wherein, The memory controller includes a power supply connection terminal and a ground connection terminal formed on the lower surface of the memory controller; The power supply wiring includes a vertical power supply wiring extending vertically downward from the power supply connection terminal and a horizontal power supply wiring connected to the vertical power supply wiring; and The ground wiring includes a vertical ground wiring extending vertically downward from the ground connection terminal and a horizontal ground wiring connected to the vertical ground wiring.

5. The memory package according to claim 4, wherein, The horizontal power supply wiring and the horizontal ground wiring are located in different layers in the vertical direction.

6. The memory package according to claim 4, wherein, The connection wiring includes: a vertical connection wiring connecting to one of an electrode of the inductor and an electrode of the capacitor; and a horizontal connection wiring extending from the vertical connection wiring to the vertical power supply wiring; and The horizontal connection wiring is closer to the upper surface of the package substrate than the horizontal power supply wiring.

7. The memory package according to claim 4, wherein, The connection wiring includes: a vertical connection wiring that is connected to the other one of an electrode of the inductor and an electrode of the capacitor; and a horizontal connection wiring that extends from the vertical connection wiring to the vertical ground wiring; and the horizontal connection wiring is closer to the upper surface of the package substrate than the horizontal ground wiring.

8. The memory package according to claim 1, wherein, the package substrate further includes signal wiring for exchanging signals between the memory chip and the memory controller; and the connection wiring, the signal wiring, the power supply wiring, and the ground wiring are located in different layers in a direction perpendicular to the upper surface of the package substrate.

9. The memory package according to claim 8, wherein, the connection wiring is closer to the upper surface of the package substrate than the signal wiring; and the signal wiring is closer to the upper surface of the package substrate than the power supply wiring and the ground wiring.

10. The memory package according to claim 1, the memory package further comprising: External connection terminals are formed above the lower surface of the package substrate and are electrically connected to each of the power supply wiring and the ground wiring.

11. The memory package according to claim 1, wherein, the memory controller is connected to the package substrate through connection terminals formed on the lower surface of the memory controller; and the memory chip is connected to the package substrate through bonding wires.

12. The memory package according to claim 1, wherein, The band-pass filter is located outside the memory chip and the memory controller.

13. The memory package according to claim 1, wherein, The planar area of the memory chip is larger than the planar area of the memory controller.

14. The memory package according to claim 13, wherein, At least a part of the band-pass filter is located in the space between the memory chip and the package substrate.

15. The memory package according to claim 1, wherein, the connection path from the memory controller to the band-pass filter through the power supply wiring is shorter than the connection path from the memory chip to the band-pass filter through the power supply wiring; and the connection path from the memory controller to the band-pass filter through the ground wiring is shorter than the connection path from the memory chip to the band-pass filter through the ground wiring.

16. A memory package, the memory package includes: a package substrate that includes power supply wiring and ground wiring; a memory controller that is disposed above the upper surface of the package substrate and is electrically connected to the power supply wiring and the ground wiring; a memory chip that is disposed above the memory controller and is electrically connected to the power supply wiring and the ground wiring; and a band-pass filter that is disposed on one side of the memory controller above the upper surface of the package substrate and includes an inductor and a capacitor connected in series, wherein the inductor and the capacitor connected in series are electrically connected between the power supply wiring and the ground wiring. Among them, the encapsulation substrate further includes connection wirings, and the connection wirings are connected between the inductor and the capacitor. Among them, the connection wirings, the power supply wirings, and the ground wirings are located in different layers in a direction perpendicular to the upper surface of the encapsulation substrate, and among them, the connection wirings are closer to the upper surface of the encapsulation substrate than the power supply wirings and the ground wirings.

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