Semiconductor device and method of forming the same

Abstract

Semiconductor devices and methods of forming the same are disclosed. In one embodiment, a device includes a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along sidewalls of the first gate stack. The device also includes a first source / drain region in the first fin and adjacent the first gate spacer, the first source / drain region including a first epitaxial layer on the first fin, the first epitaxial layer including boron having a first dopant concentration. The device also includes a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including boron having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more specifically, to semiconductor devices and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] According to a first aspect of this disclosure, a semiconductor device is provided, comprising: a first fin extending from a substrate; a first gate stack located above and along the sidewalls of the first fin; a first gate spacer disposed along the sidewalls of the first gate stack; and a first source / drain region located in the first fin and adjacent to the first gate spacer, the first source / drain region comprising: a first epitaxial layer located on the first fin, the first epitaxial layer comprising boron having a first dopant concentration; and a second epitaxial layer located on the first epitaxial layer, the second epitaxial layer comprising boron having a second dopant concentration greater than the first dopant concentration.

[0005] According to a second aspect of this disclosure, a method for forming a semiconductor device is provided, comprising: depositing a first dummy gate on and along the sidewall of a first fin, the first fin extending from a substrate; forming a first gate spacer along the sidewall of the first dummy gate; forming a first recess in the first fin and adjacent to the first gate spacer; and forming a first source / drain region in the first recess, wherein forming the first source / drain region comprises: epitaxially growing a first layer in the first recess, the first layer extending above a top surface of the first fin, the first layer comprising a first dopant having a first dopant concentration; and epitaxially growing a second layer on the first layer, the second layer comprising the first dopant having a second dopant concentration greater than the first dopant concentration.

[0006] According to a third aspect of this disclosure, a method for forming a semiconductor device is provided, comprising: forming a first dummy gate on and along the sidewall of a first fin, the first fin extending upward from a substrate; forming a first gate spacer along the sidewall of the first dummy gate; etching a first recess in the first fin adjacent to the first gate spacer; forming a first source / drain region in the first recess, the first source / drain region including a first epitaxial layer and a second epitaxial layer, the first epitaxial layer growing from the first fin in the first recess, the second epitaxial layer growing from the first epitaxial layer, the second epitaxial layer having a larger boron concentration than the first epitaxial layer; and replacing the first dummy gate with a first functional gate stack disposed on and along the sidewall of the first fin. Attached Figure Description

[0007] The various aspects of the invention can be best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a FinFET is shown in a three-dimensional view according to some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 17A and Figure 17B This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] Figure 18 This is a perspective view of the source / drain regions according to some embodiments.

[0011] Figure 19 This is a graph showing the dopant concentration in the source / drain regions according to some embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0014] FinFETs and methods of forming them are provided according to various embodiments. Intermediate stages of forming a FinFET are illustrated. Some embodiments discussed herein are discussed in the context of FinFETs formed using a post-gate process (sometimes referred to as a replacement gate process). In other embodiments, a pre-gate process may be used. Some variations of the embodiments are discussed. Furthermore, some embodiments contemplate aspects used in planar devices (e.g., planar FETs). Other modifications that may be conceived within the scope of other embodiments will be readily understood by those skilled in the art. Although method embodiments are discussed in a particular order, various other method embodiments can be performed in any logical order and may include fewer or more steps than those described herein.

[0015] Before detailing the illustrated embodiments, certain advantageous features and aspects of embodiments of this disclosure will be set forth in general. Generally, this disclosure is a semiconductor device and a method of forming the same, used to improve the performance of a FinFET device by reducing the parasitic resistance of the source / drain regions of the semiconductor device. In the disclosed embodiments, the source / drain regions include a heavily doped layer located outside the source / drain regions, which can reduce the parasitic resistance of the source / drain regions. For example, for a p-type metal-oxide-semiconductor FET (MOSFET) such as a p-type FinFET, the source / drain regions include an outer layer heavily doped with boron to reduce parasitic resistance. By including a heavily doped layer, the Schottky barrier height at the interface between the conductive contacts and the source / drain regions is reduced, thus allowing charge carriers to tunnel through the interface more easily, thereby reducing parasitic resistance. This reduction in parasitic resistance can improve the performance of the semiconductor device. Specifically, the inventors discovered that for p-type metal-oxide-semiconductor FETs (MOSFETs), the p-type doping concentration in the source / drain regions significantly affects the total resistance of the semiconductor device, because parasitic resistance constitutes a large portion of the total resistance for p-type MOSFETs. The disclosed process and structure can improve the performance and reliability of FinFET devices.

[0016] Some embodiments envision fabricating both n-type devices (e.g., n-type FinFETs) and p-type devices (e.g., p-type FinFETs) during the manufacturing process. Therefore, some embodiments envision the formation of complementary devices. The following figures may illustrate a single device, but those skilled in the art will readily understand that multiple devices (some of which may have different device types) can be formed during processing. Some aspects of the formation of complementary devices are discussed below, but these aspects are not necessarily shown in the figures.

[0017] Figure 1 An example of a FinFET in a three-dimensional view according to some embodiments is shown. The FinFET includes fins 52 located on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in the substrate 50, and the fins 52 protrude above adjacent isolation regions 56. Although the isolation regions 56 are described / shown as separate from the substrate 50, as used herein, the term "substrate" can be used to refer only to the semiconductor substrate or to the semiconductor substrate including the isolation regions. Furthermore, although the fins 52 are shown as being of a single continuous material with the substrate 50, the fins 52 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 52 refers to the portion extending between adjacent isolation regions 56.

[0018] A gate dielectric layer 92 runs along the sidewall of fin 52 and is located above the top surface of fin 52, and a gate electrode 94 is located above the gate dielectric layer 92. Source / drain regions 82 are disposed on the opposite sides of fin 52 with respect to the gate dielectric layer 92 and the gate electrode 94. Figure 1 Reference cross sections used in the following figures are also shown. Cross section AA is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the current flow direction between the source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 52 and in the direction of current flow between the source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. These reference cross sections are referenced in subsequent figures for clarity.

[0019] Some embodiments discussed herein are described in the context of FinFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments are contemplated for use in planar devices (e.g., planar FETs), nanostructures (e.g., nanosheets, nanowires, gate-all-around structures, etc.), or field-effect transistors (NSFETs), etc.

[0020] Figures 2 to 17B This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figures 2 to 7 It shows Figure 1 The reference cross section AA shown is different in that it includes multiple fins / FinFETs. Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A It is along Figure 1 The reference section AA shown in the figure is illustrated, and Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 15C , Figure 16B and Figure 17B It is along Figure 1 The cross-section BB shown is illustrated, except that it includes multiple fins / FinFETs. Figure 10C , Figure 10D , Figure 11C and Figure 11D It is along Figure 1 The reference cross section CC shown is different in that it includes multiple fins / FinFETs.

[0021] exist Figure 2 A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., doped with p-type or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide; or combinations of the foregoing.

[0022] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, or an n-type FinFET. The p-type region 50P can be used to form a p-type device, such as a PMOS transistor, or a p-type FinFET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be formed between the n-type region 50N and the p-type region 50P.

[0023] exist Figure 3 In this embodiment, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic.

[0024] Fins can be patterned using any suitable method. For example, fin 52 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing patterns to be created with a pitch, for example, smaller than that achievable using a single direct photolithography process in other cases. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins. In some embodiments, a mask (or other layer) may be retained on fin 52.

[0025] exist Figure 4 An insulating material 54 is formed on the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to convert it into another material (e.g., oxide)), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown) can be formed first along the surfaces of the substrate 50 and the fins 52. A filler material as discussed above can then be formed on the liner.

[0026] exist Figure 5 In this process, a removal process is applied to the insulating material 54 to remove excess insulating material 54 over the fin 52. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back, or a combination thereof, may be used. The planarization process exposes the fin 52 such that, after the planarization process is completed, the top surface of the fin 52 is flush with the top surface of the insulating material 54. In embodiments where the mask remains on the fin 52, the planarization process may expose or remove the mask such that, after the planarization process is completed, the top surface of the mask or the top surface of the fin 52 is flush with the top surface of the insulating material 54, respectively.

[0027] exist Figure 6In this process, insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. The insulating material 54 is recessed such that the upper portions of the fins 52 in the n-type region 50N and p-type region 50P protrude between adjacent STI regions 56. Furthermore, the top surface of the STI region 56 may have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination of the foregoing. The top surface of the STI region 56 can be formed as flat, convex, and / or concave by appropriate etching. The STI region 56 can be recessed using an acceptable etching process, such as an etching process selective for the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than etching the material of the fins 52). For example, it can be removed using an oxide utilizing, for example, diluted hydrofluoric acid (dHF).

[0028] about Figures 2 to 6 The described process is merely one example of how fin 52 can be formed. In some embodiments, fins can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoethelic structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoethelic structure protrudes from the dielectric layer to form a fin. Furthermore, in some embodiments, heteroethelic structures can be used for fin 52. For example, Figure 5 The fin 52 can be recessed, and a different material can be epitaxially grown on the recessed fin 52. In such an embodiment, the fin 52 includes a recessed material and an epitaxial growth material disposed on the recessed material. In a further embodiment, a dielectric layer can be formed on the top surface of the substrate 50, and trenches can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trenches using a material different from that of the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, the epitaxial growth material can be doped in situ during growth, which avoids prior and subsequent implantation, but in-situ and implantation doping can be used together.

[0029] Furthermore, it may be advantageous to epitaxially grow a material different from that in the p-type region 50P (e.g., the PMOS region) in the n-type region 50N (e.g., the NMOS region). In various embodiments, the upper portion of the fin 52 may be made of silicon-germanium (Si... x Ge 1-xThe semiconductor can be formed from materials such as silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, or II-VI compound semiconductors, where x can be in the range of 0 to 1. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, aluminum indium arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, or gallium phosphide.

[0030] In addition, Figure 6 In this process, suitable wells (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a P-well may be formed in the n-type region 50N and an N-well may be formed in the p-type region 50P. In some embodiments, either a P-well or an N-well may be formed in both the n-type region 50N and the p-type region 50P.

[0031] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P can be achieved using photoresist and / or other masks (not shown). For example, photoresist can be formed over the fins 52 and STI regions 56 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, or antimony, etc., implanted in the region, with a concentration equal to or less than 10. 18 cm -3 (For example, in about 10) 16 cm -3 To about 10 18 cm -3 (between). After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0032] Following implantation into the p-type region 50P, a photoresist is formed over the fins 52 and STI regions 56 within the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, or indium, etc., implanted into the region, with a concentration equal to or less than 10. 18 cm -3 (For example, in about 10) 16cm -3 Peace Treaty 10 18 cm -3 (between). After injection, the photoresist is removed, for example, by an acceptable ashing process.

[0033] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation, but in-situ and implantation doping can be used together.

[0034] exist Figure 7 In this process, a dummy dielectric layer 60 is formed on fin 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, or a combination thereof, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60 and then planarized (e.g., by CMP). The mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, polycrystalline silicon germanium (polycrystalline SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 62 can be made of other materials that have high etch selectivity for etching isolation regions (e.g., STI region 56 and / or dummy dielectric layer 60). The mask layer 64 can comprise one or more layers of materials such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed on the n-type region 50N and the p-type region 50P. Note that, for illustrative purposes only, the dummy dielectric layer 60 is shown as covering only fin 52. In some embodiments, the dummy dielectric layer 60 can be deposited such that it covers the STI region 56, extending over the STI region and between the dummy gate layer 62 and the STI region 56.

[0035] Figures 8A to 17B Various additional steps in manufacturing the embodiment device are shown. Figures 8A to 17B The characteristics of either the n-type region 50N or the p-type region 50P are shown. For example, Figures 8A to 17B The structure shown is applicable to both n-type region 50N and p-type region 50P. The differences (if any) in the structure of n-type region 50N and p-type region 50P are described in the text accompanying each figure.

[0036] exist Figure 8A and Figure 8B In this process, acceptable photolithography and etching techniques can be used to process mask layer 64 (see...). Figure 7 The mask 74 is patterned to form a dummy gate layer 62. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 using an acceptable etching technique to form the dummy gate 72. The dummy gate 72 covers the corresponding channel region 58 of the fin 52. Each dummy gate 72 can be physically spaced from adjacent dummy gates using the pattern of the mask 74. The dummy gate 72 may also have a length direction substantially perpendicular to the length direction of the corresponding epitaxial fin 52.

[0037] In addition, Figure 8A and Figure 8B In this process, a gate sealing spacer 80 may be formed on the exposed surfaces of the dummy gate 72, mask 74, and / or fin 52. The gate sealing spacer 80 may be formed by thermal oxidation or deposition (followed by anisotropic etching). The gate sealing spacer 80 may be formed of silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0038] After the gate sealing spacer 80 is formed, implantation for the lightly doped source / drain (LDD) region (not explicitly shown) can be performed. In embodiments with different device types, the process is similar to that described above. Figure 6 The implantation discussed earlier can involve forming a mask (e.g., photoresist) over the n-type region 50N while exposing the p-type region 50P, and implanting an impurity of an appropriate type (e.g., p-type) into the exposed fins 52 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any n-type impurity discussed earlier, and the p-type impurity can be any p-type impurity discussed earlier. The lightly doped source / drain regions can have approximately 10... 15 cm -3 To about 10 19 cm -3 The concentration of impurities. Annealing can be used to repair injection damage and reactivate the injected impurities.

[0039] exist Figure 9A and Figure 9BIn this process, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination of the foregoing.

[0040] Note that the above disclosure generally describes the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, or different step sequences can be employed (e.g., gate seal spacer 80 may not be etched before forming gate spacer 86, creating an "L-shaped" gate seal spacer; the spacers may be formed and removed, etc.). Furthermore, n-type and p-type devices can be formed using different structures and steps. For example, the LDD region of an n-type device may be formed before forming gate seal spacer 80, while the LDD region of a p-type device may be formed after forming gate seal spacer 80.

[0041] exist Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C and Figure 11D In this process, source / drain regions 82 are formed in fin 52 to apply stress in the corresponding channel region 58, thereby improving performance. The source / drain regions 82 are formed in fin 52 such that each dummy gate 72 is disposed between adjacent pairs of corresponding source / drain regions 82. In some embodiments, the source / drain regions 82 may extend into fin 52 and may also penetrate fin 52. In some embodiments, gate spacers 86 are used to separate the source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance such that the source / drain regions 82 do not short-circuit the subsequently formed gate of the resulting FinFET.

[0042] The source / drain regions 82 can be formed using different processes, allowing each region to be made of a different material and formed using different processes. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0043] First refer to Figure 9A and Figure 9BA patterning process is performed on fin 52 to form recesses 85 in the source / drain regions of fin 52. The patterning process can be performed by forming recesses 85 between adjacent dummy gate stacks 72 / 74 (in the internal region of fin 52) or between isolation region 56 and adjacent dummy gate stacks 72 / 74 (in the end region of fin 52). In some embodiments, the patterning process may include a suitable anisotropic dry etching process, using dummy gate stacks 72 / 74, gate spacers 86, and / or isolation region 56 as a combined mask. Suitable anisotropic dry etching processes may include reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. For example, in some embodiments where RIE is used in the first patterning process, process parameters (e.g., process gas mixture, voltage bias, and RF power) can be selected such that etching is performed primarily using physical etching (e.g., ion bombardment) rather than chemical etching (e.g., radical etching via chemical reaction). In some embodiments, the voltage bias can be increased to increase the energy of the ions used in the ion bombardment process, and thus increase the rate of physical etching. Since physical etching is inherently anisotropic and chemical etching is inherently isotropic, this etching process has a higher etching rate in the vertical direction than in the lateral direction. In some embodiments, anisotropic etching processes can be performed using a mixture of process gases including fluoromethane, methane, hydrogen bromide, oxygen, argon, or combinations thereof. In some embodiments, a patterning process forms a recess 85 having a U-shaped bottom surface. The recess 85 may also be referred to as a U-shaped recess 85, an example of which is... Figure 9B As shown in the figure. In some embodiments, as measured from the top surface of the fin 52, the depth of the recess 85 is in the range of about 35 nm to about 60 nm.

[0044] exist Figures 10A to 10D as well as Figures 11A to 11D In the recess 85, a source / drain region 82 (including layers 82A and 82B) is formed. Figures 10A to 10D In the middle, an epitaxial layer 82A of the source / drain region 82 is grown in the recess 85.

[0045] The epitaxial source / drain region 82 in the n-type region 50N can be formed by masking the p-type region 50P and etching the source / drain region of the fin 52 in the n-type region 50N to form a recess in the fin 52. The epitaxial source / drain region 82 in the n-type region 50N is then epitaxially grown in the recess. The epitaxial source / drain layer 82 can include any acceptable material, such as materials suitable for n-type FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain layer 82A in the n-type region 50N can include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, or silicon phosphide. The epitaxial source / drain layer 82A in the n-type region 50N can have a surface protruding from the corresponding surface of the fin 52 and can have a facet.

[0046] The epitaxial source / drain region 82 in the p-type region 50P can be formed by masking the n-type region 50N and etching the source / drain region of the fin 52 in the p-type region 50P to form a recess in the fin 52. The epitaxial source / drain region 82 in the p-type region 50P is then epitaxially grown in the recess. The epitaxial source / drain layer 82 can include any acceptable material, such as materials suitable for p-type FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain layer 82A in the p-type region 50P can include a material that applies compressive stress in the channel region 58, such as silicon-germanium, boron-doped silicon-germanium, germanium, or germanium-tin. The epitaxial source / drain layer 82A in the p-type region 50P can have a surface protruding from the corresponding surface of the fin 52 and can have a facet.

[0047] In an embodiment with a boron-doped silicon-germanium source / drain layer 82A in the p-type region 50P, the source / drain layer 82A can be epitaxially grown under the following conditions: a temperature in the range of 580°C to 630°C; a pressure in the range of 17 Torr to 25 Torr; a flow rate of dichlorosilane (DCS) gas in the range of 30 sccm to 60 sccm; a flow rate of GeH4 gas in the range of 400 sccm to 800 sccm; and a flow rate of B2H6 gas in the range of 40 sccm to 150 sccm. The dopant concentration of the source / drain epitaxial layer 82A can be 10... 20 cm -3 Up to 10 21 cm -3 Within the range. In embodiments with boron-doped silicon-germanium source / drain layers 82A in the p-type region 50P, the boron concentration of the source / drain epitaxial layer 82A can be within 10. 20 cm -3 Up to 10 21 cm -3 between.

[0048] exist Figures 11A to 11D In this process, an external source / drain epitaxial layer 82B is formed on top of the epitaxial layer 82A. In some embodiments, the external source / drain epitaxial layer 82B is a heavily doped source / drain layer 82B and has a higher dopant concentration than layer 82A. The dopant concentration of the external source / drain epitaxial layer 82B can be 10... 21 cm -3 Up to 10 22 cm -3 Within the range. In embodiments with boron-doped silicon-germanium source / drain layers 82B in the p-type region 50P, the boron concentration of the external source / drain epitaxial layer 82B can be within 10. 21 cm -3 Up to 10 22 cm -3 In some embodiments, the boron concentration of the external source / drain epitaxial layer 82B is two to ten times that of the source / drain epitaxial layer 82A. In some embodiments, the source / drain region layers 82A and 82B can be in-situ doped during growth. In some embodiments, the source / drain region layers 82A and 82B can be doped by an implantation process. In both in-situ doping and implantation doping, an annealing process can be performed after the process.

[0049] In some embodiments, the heavily doped source / drain layer 82B can be grown to have a thickness T1. In some embodiments, the thickness T1 is in the range of 5 nm to 30 nm. If the thickness of the heavily doped source / drain layer 82B is greater than 30 nm, defects such as nodules may occur. These defects may affect the back-end loop and degrade wafer acceptance testing performance. If the thickness of the heavily doped source / drain layer 82B is less than 5 nm, the device performance will be limited because there will not be enough current transport space in the source / drain region 82. Figure 10B and Figure 11B As shown, layers 82A and 82B are both in physical contact with the gate spacer 86. In some embodiments, layer 82B is in contact with the gate spacer 86, while layer 82A is not in contact with the gate spacer 86.

[0050] In embodiments of a silicon-germanium source / drain layer 82A with heavily boron-doped silicon in the p-type region 50P, the heavily doped silicon-germanium source / drain layer 82B can be epitaxially grown under the following conditions: a temperature in the range of 580 °C to 630 °C; a pressure in the range of 17 Torr to 25 Torr; a flow rate of dichlorosilane (DCS) gas in the range of 30 sccm to 60 sccm; a flow rate of GeH4 gas in the range of 400 sccm to 800 sccm; and a flow rate of B2H6 gas in the range of 40 sccm to 150 sccm. In some embodiments, the growth conditions of layer 82B are the same as those of layer 82A, except that the growth process of the heavily doped silicon-germanium source / drain layer 82B is shorter than that of the highly doped silicon-germanium source / drain layer 82A. For example, a shorter process for the outer layer 82B may result in a larger ramp rate for the B2H6 gas, which could lead to more B2H6 gas flowing into the growth chamber and forming an over-doped silicon-germanium source / drain layer 82B.

[0051] In some embodiments, the source / drain region 82 in the p-type region 50P includes both layers 82A and 82B, while the source / drain region 82 in the n-type region does not include the heavily doped source / drain layer 82B. In some embodiments, both regions 50P and 50N include the same number of layers in the source / drain region 82.

[0052] The method described above for forming the source / drain region 82 can improve the performance of FinFET devices by reducing the parasitic resistance of the source / drain region 82 of the semiconductor device. In the disclosed embodiments, the source / drain region 82 includes a heavily doped layer 82B located outside the source / drain region 82, which can reduce the parasitic resistance of the source / drain region 82. For example, for a p-type MOSFET such as a p-type FinFET, the source / drain region 82 includes an outer layer heavily doped with boron to reduce parasitic resistance. By including the heavily doped layer, the Schottky barrier height at the interface between the subsequently formed conductive contact and the source / drain region 82 is reduced, thus allowing carriers to tunnel through the interface more easily, thereby reducing parasitic resistance. This reduction in parasitic resistance can improve the performance of the semiconductor device. Specifically, the inventors have found that for p-type MOSFETs, the p-type doping concentration in the source / drain region significantly affects the total resistance of the semiconductor device because, for p-type MOSFETs, parasitic resistance is a large part of the total resistance.

[0053] As a result of the epitaxial process used to form the epitaxial source / drain regions 82 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions has small planes that extend laterally outward beyond the sidewalls of the fin 52. In some embodiments, these small planes cause adjacent source / drain layers 82A of the same FinFET to merge, such as... Figure 10C and Figure 11C As shown. In some embodiments, these facets cause adjacent source / drain layers 82B of the same FinFET to merge, while layers 82A are not merged. In these embodiments, the outer layer 82B spans between adjacent layers 82A. In other embodiments, adjacent source / drain regions 82 remain separated after the epitaxial process is completed, as... Figure 10D and Figure 11D As shown. In Figures 10C to 10D as well as Figures 11C to 11D In the illustrated embodiment, the gate spacer 86 is formed such that the sidewalls of the covering fin 52 extend above a portion of the STI region 56, thereby preventing epitaxial growth. In some other embodiments, the spacer etching for forming the gate spacer 86 can be adjusted to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 56. In some embodiments, the source / drain region 82 has a flat top surface within process variations (see [link to documentation]). Figures 10C to 10D as well as Figures 11C to 11D In some embodiments, the source / drain region 82 includes a top surface with a small facet.

[0054] exist Figure 12A and Figure 12B In the middle, the first interlayer dielectric (ILD) 88 is deposited on Figure 11A and Figure 11B The structure shown is above the first ILD 88. The first ILD 88 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain region 82, mask 74, and gate spacer 86. The CESL 87 may include a dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, etc.) having an etch rate lower than that of the material of the overlying first ILD 88.

[0055] exist Figure 13A and Figure 13BIn this process, a planarization process such as CMP can be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process can also remove the mask 74 on the dummy gate 72, as well as portions of the gate sealing spacers 80 and 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacers 80, the gate spacers 86, and the first ILD 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 can be retained, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0056] exist Figure 14A and Figure 14B In one or more etching steps, the dummy gate 72 and mask 74 (if present) are removed to form a recess 90. A portion of the dummy dielectric layer 60 located in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, while the dummy dielectric layer 60 remains and is exposed through the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in a first region of the die (e.g., a core logic region) and remains in the recess 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 72 while little or no etching of the first ILD 88 or gate spacer 86. Each recess 90 exposes and / or covers the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 can be used as an etch stop layer when the dummy gate 72 is etched. The dummy dielectric layer 60 can then be optionally removed after the dummy gate 72 has been removed.

[0057] exist Figure 15A and Figure 15B In this process, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Figure 15C It shows Figure 15BA detailed view of region 89. The gate dielectric layer 92 includes one or more layers deposited in the recess 90, such as deposited on the top surface and sidewalls of the fin 52 and on the sidewalls of the gate sealing spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. In some embodiments, the gate dielectric layer 92 includes one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, the gate dielectric layer 92 includes an interface layer of silicon oxide formed by thermal oxidation or chemical oxidation and an overlying high-k dielectric material, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layer 92 may include a dielectric layer with a k value greater than about 7.0. Methods for forming the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where some portions of the dummy gate dielectric 60 remain in the recess 90, the gate dielectric layer 92 comprises the material of the dummy gate dielectric 60 (e.g., SiO2).

[0058] Gate electrodes 94 are deposited on the gate dielectric layer 92 and fill the remaining portion of the recess 90. Gate electrodes 94 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although... Figure 15B The diagram shows a single-layer gate electrode 94, but the gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and filler material 94C, such as... Figure 15C As shown. After filling the recess 90, a planarization process such as CMP can be performed to remove excess material from the gate dielectric layer 92 and gate electrode 94, which lie above the top surface of the ILD 88. Therefore, the remaining material of the gate electrode 94 and gate dielectric layer 92 forms the replacement gate of the resulting FinFET. The gate electrode 94 and gate dielectric layer 92 can be collectively referred to as the “gate stack”. The gate and gate stack can extend along the sidewalls of the channel region 58 of the fin 52.

[0059] The formation of the gate dielectric layer 92 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 92 in each region is formed of the same material, and the formation of the gate electrode 94 can occur simultaneously, such that the gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region can be formed using different processes, such that the gate dielectric layer 92 can be made of different materials, and / or the gate electrode 94 in each region can be formed using different processes, such that the gate electrode 94 can be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0060] exist Figure 16A and Figure 16B In this configuration, a gate mask 96 is formed on a gate stack (including a gate dielectric layer 92 and a corresponding gate electrode 94), and the gate mask may be disposed between opposing portions of the gate spacers 86. In some embodiments, forming the gate mask 96 includes recessing the gate stack, thereby forming recesses directly on the gate stack and between opposing portions of the gate spacers 86. The recesses are filled with the gate mask 96 comprising one or more layers of dielectric material (e.g., silicon nitride or silicon oxynitride, etc.), followed by a planarization process to remove excess dielectric material extending over the first ILD 88.

[0061] For example Figure 16A and Figure 16B As shown, the second ILD 108 is deposited on top of the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, and can be deposited by any suitable method such as CVD and PECVD. The gate contact 110 is subsequently formed ( Figure 17A and Figure 17B It penetrates the second ILD 108 and the gate mask 96 to contact the top surface of the recessed gate electrode 94.

[0062] exist Figure 17A and 17BIn some embodiments, gate contact 110 and source / drain contact 112 are shaped to pass through second ILD 108 and first ILD 88. An opening for source / drain contact 112 is formed to pass through first ILD 88 and second ILD 108, and an opening for gate contact 110 is formed to pass through second ILD 108 and gate mask 96. These openings can be formed using acceptable photolithography and etching techniques. A liner (not shown), such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of ILD 108. The remaining liner and conductive material form source / drain contact 112 and gate contact 110 in the openings. An annealing process can be performed to form silicide at the interface between the epitaxial source / drain region 82 and the source / drain contact 112. The source / drain contact 112 is physically and electrically coupled to the epitaxial source / drain region 82, and the gate contact 110 is physically and electrically coupled to the gate electrode 106. The source / drain contact 112 and the gate contact 110 can be formed using different processes or the same process. Although each source / drain contact 112 and the gate contact 110 is shown as being formed in the same cross-section, it should be understood that each source / drain contact 112 and the gate contact 110 can be formed in different cross-sections, which can prevent short circuits of the contacts.

[0063] In some embodiments, the source / drain contact 112 is in physical contact with the heavily doped source / drain layer 82B. In some embodiments, the source / drain contact 112 is in contact with the flat top surface of the heavily doped source / drain layer 82B (see [link]). Figures 11C to 11D Physical contact (see) Figure 18 ).

[0064] Figure 18 This is a perspective view of the source / drain region 82 according to some embodiments. As described above, by including a heavily doped source / drain layer 82B, the Schottky barrier height at the interface between the conductive contact 112 and the source / drain region 82 is reduced, thus allowing charge carriers to tunnel through the interface more easily, thereby reducing parasitic resistance. Figure 18 This idea is illustrated graphically by showing the current 120 flowing along all portions (upper, middle, and lower) of layer 82B. This current-carrying capacity reduces the parasitic resistance of the source / drain region 82 and improves the device performance.

[0065] Figure 19This is a graph showing the dopant concentration of the source / drain regions according to some embodiments. Specifically, line 130 shows the doping concentration of the superheavy external source / drain layer 82B, and line 132 shows the doping concentration of the source / drain layer 82A. Figure 19 The values ​​shown are examples, and other values ​​are also within the scope of this disclosure. For example... Figure 19 As shown, layer 82B has three dopant concentration peaks: a first peak at a depth between 0 nm and 5 nm, a second peak at a depth between 10 nm and 15 nm, and a third peak at a depth between 20 nm and 25 nm. In the illustrated embodiment, the first and third peaks are greater than the second peak, but other configurations are also within the scope of this disclosure.

[0066] The embodiments offer advantages. The disclosed semiconductor devices and their fabrication methods improve the performance of FinFET devices by reducing the parasitic resistance of the source / drain regions of the semiconductor device. In the disclosed embodiments, the source / drain regions include a heavily doped layer located outside the source / drain regions, which can reduce the parasitic resistance of the source / drain regions. For example, for a p-type MOSFET such as a p-type FinFET, the source / drain regions include an outer layer heavily doped with boron to reduce parasitic resistance. By including the heavily doped layer, the Schottky barrier height at the interface between the conductive contacts and the source / drain regions is reduced, thus allowing carriers to tunnel through the interface more easily, thereby reducing parasitic resistance. This reduction in parasitic resistance can improve the performance of the semiconductor device. Specifically, the inventors have found that for p-type MOSFETs, the p-type doping concentration in the source / drain regions significantly affects the total resistance of the semiconductor device because, for p-type MOSFETs, parasitic resistance is a large component of the total resistance. The disclosed processes and structures can improve the performance and reliability of FinFET devices.

[0067] The disclosed FinFET embodiments can also be applied to nanostructured devices, such as nanostructured (e.g., nanosheets, nanowires, gate-all-around structures, etc.) field-effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by patterning an alternating stack of channel and sacrificial layers. The dummy gate stack and source / drain regions are formed in a manner similar to those described in the embodiments above. After the dummy gate stack is removed, the sacrificial layer may be partially or completely removed in the channel region. The replacement gate structure is formed in a manner similar to those described in the embodiments above, and the replacement gate structure may partially or completely fill the opening left by removing the sacrificial layer, and the replacement gate structure may partially or completely surround the channel layer in the channel region of the NSFET device. The ILD and contacts with the replacement gate structure and source / drain regions can be formed in a manner similar to those described in the embodiments above. Nanostructured devices can be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0068] In one embodiment, a device includes a first fin extending from a substrate. The device also includes a first gate stack located above and along the sidewalls of the first fin. The device further includes a first gate spacer disposed along the sidewalls of the first gate stack. The device also includes a first source / drain region located in the first fin and adjacent to the first gate spacer, the first source / drain region including a first epitaxial layer on the first fin, the first epitaxial layer including boron having a first dopant concentration. The device also includes a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including boron having a second dopant concentration greater than the first dopant concentration.

[0069] The embodiment may include one or more of the following features. In this device, the thickness of the second epitaxial layer is in the range of 5 nm to 30 nm. The second epitaxial layer has a flat top surface. The device further includes: an etch stop layer located above the first source / drain region and on the sidewall of the first gate spacer; a first interlayer dielectric located above the etch stop layer; a second interlayer dielectric located above the first interlayer dielectric; and a first conductive contact extending through the first interlayer dielectric, the second interlayer dielectric, and the etch stop layer, the first conductive contact being electrically coupled to the first source / drain region. The second epitaxial layer is in contact with the first gate spacer. The first epitaxial layer is in contact with the first gate spacer. The device further includes: a second fin extending from a substrate; a second gate stack located above and along the sidewalls of the second fin; a second gate spacer disposed along the sidewalls of the second gate stack; and a second source / drain region located in the second fin and adjacent to the second gate spacer, the second source / drain region including a third epitaxial layer having a material composition different from the first and second epitaxial layers. The second dopant concentration is two to ten times that of the first dopant concentration.

[0070] In one embodiment, a method includes depositing a first dummy gate on and along the sidewalls of a first fin extending from a substrate. The method further includes forming a first gate spacer along the sidewalls of the first dummy gate. The method further includes forming a first recess in the first fin adjacent to the first gate spacer. The method further includes forming a first source / drain region in the first recess, wherein forming the first source / drain region includes epitaxially growing a first layer in the first recess, the first layer extending above a top surface of the first fin, the first layer including a first dopant having a first dopant concentration. The method further includes epitaxially growing a second layer on the first layer, the second layer including a second dopant concentration of the first dopant, the second dopant concentration being greater than the first dopant concentration.

[0071] The embodiment may include one or more of the following features. In this method, a first layer of a first source / drain region is physically contacted with a first gate spacer. The first layer is epitaxially grown for a first time period under a first set of growth conditions, and wherein a second layer is epitaxially grown for a second time period under the first set of growth conditions, the second time period being shorter than the first time period. The first dopant is boron. The thickness of the second layer is in the range of 5 nm to 30 nm. The method further includes replacing the first dummy gate with a stack of functional gates disposed on and along the sidewalls of the first fin. The concentration of the second dopant is two to ten times that of the first dopant. The concentration of the second dopant is 10 21 cm-3 Up to 10 22 cm -3 Within the range between.

[0072] In one embodiment, a method includes forming a first dummy gate on and along the sidewalls of a first fin, the first fin extending upward from a substrate. The method further includes forming a first gate spacer along the sidewalls of the first dummy gate. The method further includes etching a first recess in the first fin adjacent to the first gate spacer. The method further includes forming a first source / drain region in the first recess, the first source / drain region including a first epitaxial layer and a second epitaxial layer, the first epitaxial layer being grown from the first fin in the first recess, the second epitaxial layer being grown from the first epitaxial layer, the second epitaxial layer having a higher boron concentration than the first epitaxial layer. The method further includes replacing the first dummy gate with a first functional gate stack disposed on and along the sidewalls of the first fin.

[0073] The embodiment may include one or more of the following features. In this method, the second epitaxial layer is physically contacted with the first gate spacer. The method further includes: forming a second dummy gate on and along the sidewall of the second fin, the second fin extending upward from the substrate; forming a second gate spacer along the sidewall of the second dummy gate; etching a second recess in the second fin adjacent to the second gate spacer; forming a second source / drain region in the second recess, the second source / drain region including a third epitaxial layer, the material composition of the third epitaxial layer being different from that of the first and second epitaxial layers; and replacing the second dummy gate with a stack of second functional gates disposed on and along the sidewall of the first fin. The boron concentration of the second epitaxial layer is 10. 21 cm -3 Up to 10 22 cm -3 Within the range.

[0074] The foregoing has outlined features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0075] Example

[0076] Example 1. A semiconductor device comprising: a first fin extending from a substrate; a first gate stack located above and along the sidewalls of the first fin; a first gate spacer disposed along the sidewalls of the first gate stack; and a first source / drain region located in the first fin and adjacent to the first gate spacer, the first source / drain region comprising: a first epitaxial layer located on the first fin, the first epitaxial layer comprising boron having a first dopant concentration; and a second epitaxial layer located on the first epitaxial layer, the second epitaxial layer comprising boron having a second dopant concentration greater than the first dopant concentration.

[0077] Example 2. The semiconductor device according to Example 1, wherein the thickness of the second epitaxial layer is in the range of 5 nm to 30 nm.

[0078] Example 3. The semiconductor device according to Example 1, wherein the second epitaxial layer has a flat top surface.

[0079] Example 4. The semiconductor device according to Example 1 further includes: an etch stop layer located over the first source / drain region and on a sidewall of the first gate spacer; a first interlayer dielectric located over the etch stop layer; a second interlayer dielectric located over the first interlayer dielectric; and a first conductive contact extending through the first interlayer dielectric, the second interlayer dielectric, and the etch stop layer, the first conductive contact being electrically coupled to the first source / drain region.

[0080] Example 5. The semiconductor device according to Example 1, wherein the second epitaxial layer is in contact with the first gate spacer.

[0081] Example 6. The semiconductor device according to Example 5, wherein the first epitaxial layer is in contact with the first gate spacer.

[0082] Example 7. The semiconductor device according to Example 1 further includes: a second fin extending from a substrate; a second gate stack located above and along the sidewalls of the second fin; a second gate spacer disposed along the sidewalls of the second gate stack; and a second source / drain region located in the second fin and adjacent to the second gate spacer, the second source / drain region including a third epitaxial layer having a material composition different from the first epitaxial layer and the second epitaxial layer.

[0083] Example 8. The semiconductor device according to Example 1, wherein the concentration of the second dopant is two to ten times that of the concentration of the first dopant.

[0084] Example 9. A method for forming a semiconductor device, comprising: depositing a first dummy gate on and along the sidewall of a first fin, the first fin extending from a substrate; forming a first gate spacer along the sidewall of the first dummy gate; forming a first recess in the first fin and adjacent to the first gate spacer; and forming a first source / drain region in the first recess, wherein forming the first source / drain region comprises: epitaxially growing a first layer in the first recess, the first layer extending above a top surface of the first fin, the first layer comprising a first dopant having a first dopant concentration; and epitaxially growing a second layer on the first layer, the second layer comprising the first dopant having a second dopant concentration greater than the first dopant concentration.

[0085] Example 10. The method according to Example 9, wherein the first layer of the first source / drain region is in physical contact with the first gate spacer.

[0086] Example 11. The method according to Example 9, wherein the first layer extends and grows for a first time period under a first set of growth conditions, and wherein the second layer extends and grows for a second time period under the first set of growth conditions, the second time period being shorter than the first time period.

[0087] Example 12. The method according to Example 9, wherein the first dopant is boron.

[0088] Example 13. The method according to Example 9, wherein the thickness of the second layer is in the range of 5 nm to 30 nm.

[0089] Example 14. The method according to Example 9 further includes replacing the first dummy gate with a stack of functional gates disposed on and along the sidewall of the first fin.

[0090] Example 15. The method according to Example 9, wherein the concentration of the second dopant is two to ten times the concentration of the first dopant.

[0091] Example 16. The method according to Example 15, wherein the concentration of the second dopant is 10. 21 cm -3 Up to 10 22 cm -3 Within the range.

[0092] Example 17. A method for forming a semiconductor device, comprising: forming a first dummy gate on and along the sidewall of a first fin, the first fin extending upward from a substrate; forming a first gate spacer along the sidewall of the first dummy gate; etching a first recess in the first fin adjacent to the first gate spacer; forming a first source / drain region in the first recess, the first source / drain region including a first epitaxial layer and a second epitaxial layer, the first epitaxial layer growing from the first fin in the first recess, the second epitaxial layer growing from the first epitaxial layer, the second epitaxial layer having a larger boron concentration than the first epitaxial layer; and replacing the first dummy gate with a first functional gate stack disposed on and along the sidewall of the first fin.

[0093] Example 18. The method according to Example 17, wherein the second epitaxial layer is in physical contact with the first gate spacer.

[0094] Example 19. The method according to Example 17 further includes: forming a second dummy gate on and along the sidewall of a second fin, the second fin extending upward from a substrate; forming a second gate spacer along the sidewall of the second dummy gate; etching a second recess in the second fin adjacent to the second gate spacer; forming a second source / drain region in the second recess, the second source / drain region including a third epitaxial layer having a material composition different from the first epitaxial layer and the second epitaxial layer; and replacing the second dummy gate with a second functional gate stack disposed on and along the sidewall of the second fin.

[0095] Example 20. The method according to Example 19, wherein the boron concentration of the second epitaxial layer is 10. 21 cm -3 Up to 10 22 cm -3 Within the range.

Claims

1. A semiconductor device, comprising: A first fin, the first fin extending from the substrate; A first gate stack is located above and along the sidewall of the first fin; A first gate spacer is disposed along the sidewall of the first gate stack; A first source / drain region, located in the first fin and adjacent to the first gate spacer, includes: A first epitaxial layer, located on the first fin and being an inner layer of the first source / drain region, the first epitaxial layer comprising boron having a first dopant concentration; as well as A second epitaxial layer, located on the first epitaxial layer and being the outer layer of the first source / drain region, the second epitaxial layer comprising boron having a second dopant concentration greater than the first dopant concentration; and A first conductive contact is electrically coupled to the second epitaxial layer in the first source / drain region.

2. The semiconductor device according to claim 1, wherein, The thickness of the second epitaxial layer is in the range of 5 nm to 30 nm.

3. The semiconductor device according to claim 1, wherein, The second epitaxial layer has a flat top surface.

4. The semiconductor device according to claim 1, further comprising: An etch stop layer is located above the first source / drain region and on the sidewall of the first gate spacer. A first interlayer dielectric, which is located above the etch stop layer; The second interlayer dielectric is located on top of the first interlayer dielectric; and The first conductive contact extends through the first interlayer dielectric, the second interlayer dielectric, and the etch stop layer.

5. The semiconductor device according to claim 1, wherein, The second epitaxial layer is in contact with the first gate spacer.

6. The semiconductor device according to claim 5, wherein, The first epitaxial layer is in contact with the first gate spacer.

7. The semiconductor device according to claim 1, further comprising: A second fin, the second fin extending from the substrate; The second gate stack is located above and along the sidewall of the second fin; A second gate spacer is disposed along the sidewall of the second gate stack; as well as The second source / drain region is located in the second fin and adjacent to the second gate spacer. The second source / drain region includes a third epitaxial layer having a material composition different from that of the first epitaxial layer and the second epitaxial layer.

8. The semiconductor device according to claim 1, wherein, The concentration of the second dopant is two to ten times that of the concentration of the first dopant.

9. A method for forming a semiconductor device, comprising: A first dummy gate is deposited on and along the sidewall of the first fin, the first fin extending from the substrate; A first gate spacer is formed along the sidewall of the first dummy gate; A first recess is formed in the first fin and adjacent to the first gate spacer; A first source / drain region is formed in the first recess, wherein forming the first source / drain region includes: A first layer is epitaxially grown in the first recess, extending above the top surface of the first fin, the first layer being an inner layer of the first source / drain region and including a first dopant having a first dopant concentration; and A second layer is epitaxially grown on the first layer, the second layer being the outer layer of the first source / drain region and including the first dopant with a second dopant concentration greater than the first dopant concentration; and A source / drain contact is formed, which is electrically coupled to the second layer in the first source / drain region.

10. The method according to claim 9, wherein, The first layer of the first source / drain region is in physical contact with the first gate spacer.

11. The method according to claim 9, wherein, The first layer grows for a first time period under a first set of growth conditions, and the second layer grows for a second time period under the first set of growth conditions, the second time period being shorter than the first time period.

12. The method according to claim 9, wherein, The first dopant is boron.

13. The method according to claim 9, wherein, The thickness of the second layer is in the range of 5 nm to 30 nm.

14. The method of claim 9, further comprising: The first dummy gate is replaced by a stack of functional gates disposed on and along the sidewall of the first fin.

15. The method according to claim 9, wherein, The concentration of the second dopant is two to ten times that of the concentration of the first dopant.

16. The method according to claim 15, wherein, The concentration of the second dopant is 10 21 cm -3 Up to 10 22 cm -3 Within the range.

17. A method for forming a semiconductor device, comprising: A first dummy gate is formed on and along the sidewall of the first fin, the first fin extending upward from the substrate; A first gate spacer is formed along the sidewall of the first dummy gate; A first recess is etched in the first fin adjacent to the first gate spacer; A first source / drain region is formed in the first recess. The first source / drain region includes a first epitaxial layer and a second epitaxial layer. The first epitaxial layer grows from the first fin in the first recess, and the second epitaxial layer grows from the first epitaxial layer. The first epitaxial layer is the inner layer of the first source / drain region, and the second epitaxial layer is the outer layer of the first source / drain region. The second epitaxial layer has a higher boron concentration than the first epitaxial layer. The first dummy gate is replaced by a stack of first functional gates disposed on the sidewall of the first fin and disposed along the sidewall of the first fin. as well as A source / drain contact is formed, which is electrically coupled to the second epitaxial layer in the first source / drain region.

18. The method according to claim 17, wherein, The second epitaxial layer is in physical contact with the first gate spacer.

19. The method of claim 17, further comprising: A second dummy gate is formed on and along the sidewall of the second fin, the second fin extending upward from the substrate; A second gate spacer is formed along the sidewall of the second dummy gate; A second recess is etched in the second fin adjacent to the second gate spacer; A second source / drain region is formed in the second recess, the second source / drain region including a third epitaxial layer having a material composition different from the first epitaxial layer and the second epitaxial layer; as well as The second dummy gate is replaced by a stack of second functional gates disposed on and along the sidewall of the second fin.

20. The method according to claim 19, wherein, The boron concentration in the second epitaxial layer is 10 21 cm -3 Up to 10 22 cm -3 Within the range.

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