Preparation methods, semiconductor structures, memories and systems, electronic devices

Abstract

This application provides a three-dimensional memory and its fabrication method, semiconductor structure, memory system, and electronic device. The fabrication method of the three-dimensional memory includes: forming a stacked structure comprising multiple stacked layers on one side of a substrate; forming a first top cutout structure in the stacked structure, the first top cutout structure extending along a first direction parallel to the substrate and penetrating at least one of the stacked layers opposite to the substrate; forming multiple stepped sections in the stacked structure; forming a dielectric layer covering the stepped sections; and forming a virtual channel via and a top cutout, wherein the top cutout extends along the first direction, passes through the dielectric layer, and extends into the first top cutout structure within the stepped sections.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to three-dimensional memory and its fabrication methods, semiconductor structures, memory systems, and electronic devices. Background Technology

[0002] In 3D memory, top-notch structures can be used to divide block memory into smaller storage units, such as finger memory and slice memory. With increasing stacking layers and higher storage density per unit area, the fabrication precision of the top-notch structure is a crucial factor affecting the properties of 3D memory. Since the fabrication process of stepped regions in 3D memory is prone to wafer warping, the top-notch structure can be formed first in the stacked structure, followed by the step formation. This makes the top-notch structure formation process more controllable. However, this approach may allow the subsequent buffer layer covering the top surface of the step (which is later replaced by a conductive layer) to reconnect the areas separated by the top-notch structure.

[0003] It should be understood that this background section is intended to provide some useful context for understanding the art. However, this background section may also include ideas, concepts, or knowledge that were not part of what a person skilled in the art knew or understood prior to the relevant valid application date of the subject matter disclosed herein. Summary of the Invention

[0004] This application provides a method for fabricating a three-dimensional memory, which includes: forming a stacked structure comprising multiple stacked layers on one side of a substrate; forming a first top cut structure in the stacked structure, the first top cut structure extending along a first direction parallel to the substrate and penetrating at least one of the stacked layers opposite to the substrate; forming multiple stepped steps in the stacked structure; forming a dielectric layer covering the stepped steps; and forming a virtual channel hole and a top cut, wherein the top cut extends along the first direction, passes through the dielectric layer, and extends into the first top cut structure in the stepped steps.

[0005] In one embodiment, the virtual channel via extends through the stacked structure and into the substrate.

[0006] In one embodiment, at the surface of the stacked structure, the opening size of the virtual channel hole is larger than the width of the top cutout.

[0007] In one embodiment, forming a first top cutout structure in the stacked structure includes: forming a first top cutout in the stacked structure that penetrates at least one of the stacked layers; and filling the first top cutout with a first filler material to form the first top cutout structure.

[0008] In one embodiment, forming the virtual channel hole and the top cut includes: forming a patterned etch mask layer on the top surface of the stacked structure; and etching the stacked structure with the patterned etch mask layer as a mask to form the virtual channel hole and the top cut.

[0009] In one embodiment, forming a patterned etching mask layer on the top surface of the stacked structure includes: forming an etching mask layer on the top surface of the stacked structure; and forming a virtual channel hole pattern and a top notch pattern in the etching mask layer to form the patterned etching mask layer; and etching the stacked structure with the patterned etching mask layer as a mask includes: simultaneously etching the stacked structure via the virtual channel hole pattern and the top notch pattern, wherein the width of each top notch pattern is smaller than the opening size of each virtual channel hole pattern, such that etching via the top notch pattern automatically stops before etching via the virtual channel hole pattern stops.

[0010] In one embodiment, forming a plurality of stepped steps in the stacked structure includes: forming a patterned mask on the top surface of the stacked structure; and etching the stacked structure with the patterned mask as a mask to form the plurality of stepped steps.

[0011] In one embodiment, the dielectric layer includes a buffer layer and an insulating filler layer, wherein forming the dielectric layer covering the stepped steps includes: forming the buffer layer on the top surface of the plurality of stepped steps; and forming the insulating filler layer on the top surface of the buffer layer and the sidewalls of the stepped steps.

[0012] In one embodiment, the top cut penetrates the buffer layer.

[0013] In one embodiment, forming the buffer layer on the top surface of the plurality of steps includes: forming a buffer layer covering the steps; and removing a portion of the buffer layer that covers the sidewall of the steps.

[0014] In one embodiment, the first filler material comprises an oxide.

[0015] In one embodiment, the material of the buffer layer includes silicon nitride.

[0016] In one embodiment, before forming a first top cutout structure in the stacked structure, the method further includes forming a channel structure that extends through the stacked structure and extends to the substrate.

[0017] In one embodiment, the regions containing the channel structure, the virtual channel aperture, and the top notch do not overlap on a plane parallel to the substrate.

[0018] In one embodiment, the virtual channel hole and the top cut are filled with a second filling material to form a virtual channel structure and a second top cut structure.

[0019] Another embodiment of this application provides a semiconductor structure, including: a substrate; a stacked structure located on one side of the substrate and including a plurality of stacked layers; a first top cut structure extending along a first direction parallel to the substrate and penetrating at least one of the stacked layers opposite to the substrate; a plurality of stepped steps located in the stacked structure; a dielectric layer covering the stepped steps; and a second top cut structure extending along the first direction, passing through the dielectric layer and extending into the first top cut structure in the stepped steps.

[0020] In one embodiment, the semiconductor structure further includes a virtual channel structure extending through the stacked structure and to the substrate, wherein the opening size of the virtual channel structure is larger than the width of the second top cutout structure.

[0021] In one embodiment, the dielectric layer includes: a buffer layer located on the top surface of the plurality of stepped steps; and an insulating filler layer located on the top surface of the buffer layer and the sidewalls of the stepped steps.

[0022] In one embodiment, the material of the buffer layer includes silicon nitride.

[0023] In one embodiment, the second top cut structure penetrates the buffer layer formed on the top surface of the stepped step.

[0024] In one embodiment, the semiconductor structure further includes a channel structure extending through the stacked structure and to the substrate.

[0025] In one embodiment, the regions containing the channel structure, the virtual channel structure, and the second top cutout structure do not overlap on a plane parallel to the substrate.

[0026] In one embodiment, the width of the second top cut structure on the top surface of the dielectric layer is equal to the width of the first top cut structure.

[0027] Another embodiment of this application provides a three-dimensional memory. The three-dimensional memory includes: the semiconductor structure described above; and peripheral circuitry electrically connected to the semiconductor structure.

[0028] Another embodiment of this application provides a storage system. The storage system includes a controller and the aforementioned three-dimensional memory, the controller being coupled to the memory and used to control the three-dimensional memory to store data.

[0029] Another aspect of this application provides an electronic device including the above-described storage system.

[0030] In one embodiment, the electronic device includes at least one of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle-mounted device, wearable device, and power bank.

[0031] The three-dimensional memory and its fabrication method provided according to one or more embodiments of the present application may have at least one of the following advantages:

[0032] 1) Forming the first top cut structure before the formation of the stepped steps can avoid the impact of the height difference between the stepped steps and the stacked structure on the manufacturing process, making the manufacturing process of the first top cut structure more controllable; and

[0033] 2) Simultaneously forming virtual channel holes and top cuts can simplify process steps, improve manufacturing accuracy and efficiency, and help save costs. Attached Figure Description

[0034] Other features, objects, and advantages of the embodiments of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0035] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an embodiment of this application;

[0036] Figure 2A This is a schematic diagram of the structure formed after forming a stacked structure, a channel structure, and a first top cut on a substrate according to the fabrication method of the three-dimensional memory according to the embodiments of this application.

[0037] Figure 2B This is a schematic diagram of the structure formed after filling the first top cut with a first filler material according to the fabrication method of the three-dimensional memory according to the embodiments of this application;

[0038] Figure 3 This is a schematic diagram of the structure formed after forming the first top cut structure according to the method for fabricating a three-dimensional memory according to an embodiment of this application;

[0039] Figure 4 This is a schematic diagram of the structure formed after forming multiple stepped steps in a stacked structure according to the fabrication method of the three-dimensional memory according to the embodiments of this application.

[0040] Figure 5 This is a schematic diagram of the structure formed after forming a buffer layer on the top surface of multiple stepped steps according to the fabrication method of the three-dimensional memory according to the embodiments of this application.

[0041] Figure 6 This is a schematic diagram of the structure formed after forming an insulating filling layer on the top surface of the buffer layer and the sidewall of the stepped step according to the fabrication method of the three-dimensional memory according to the embodiments of this application.

[0042] Figure 7 This is a schematic diagram of the structure formed after forming a patterned etching mask layer on a stacked structure according to the fabrication method of the three-dimensional memory according to the embodiments of this application.

[0043] Figure 8 This is a schematic diagram of the structure formed after forming a virtual channel hole and a top cutout according to the fabrication method of the three-dimensional memory according to the embodiments of this application;

[0044] Figure 9 This is a schematic diagram of the structure formed after forming a virtual channel structure and a second top cutout structure according to the method for fabricating a three-dimensional memory according to an embodiment of this application.

[0045] Figure 10 yes Figure 9 The diagram shown is a cross-sectional view of the three-dimensional memory of this application embodiment taken along the AA direction;

[0046] Figure 11 This is a schematic diagram of the structure of a three-dimensional memory according to one embodiment of this application;

[0047] Figure 12 This is a schematic diagram of the structure of a storage system according to one embodiment of this application; and

[0048] Figure 13 This is a schematic diagram of the structure of an electronic device according to one embodiment of this application. Detailed Implementation

[0049] To better understand the embodiments of this application, various aspects of the embodiments of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely exemplary descriptions of the embodiments of this application and are not intended to limit the scope of the embodiments of this application in any way.

[0050] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of the embodiments of this application, the first filling material discussed in the embodiments of this application may also be referred to as the second filling material, and vice versa.

[0051] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0052] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, integrals, elements, components, and / or combinations thereof, but do not exclude the presence of one or more other features, integrals, elements, components, and / or combinations thereof.

[0053] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0054] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0055] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer can extend over the entire lower or upper layer structure, or can have a range smaller than that of the lower or upper layer structure. Furthermore, a layer can be a region of a homogeneous or non-homogeneous continuous structure whose height is less than the height of the continuous structure. For example, a layer can be located at the top and bottom surfaces of a continuous structure or between any set of horizontal planes. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can contain multiple layers.

[0056] Figure 1 This is a flowchart of a method for preparing a three-dimensional memory according to an embodiment of this application.

[0057] like Figure 1 As shown, the fabrication method 1000 of the three-dimensional memory provided in this application embodiment may include: S1, forming a stacked structure including multiple stacked layers on one side of a substrate; S2, forming a first top cut structure in the stacked structure, the first top cut structure extending along a first direction parallel to the substrate and penetrating at least the stacked layer opposite to the substrate side among the multiple stacked layers; S3, forming multiple stepped steps in the stacked structure; S4, forming a dielectric layer covering the stepped steps; and S5, forming a virtual channel hole and a top cut, wherein the top cut extends along the first direction, passes through the dielectric layer and extends into the first top cut structure in the stepped steps. Steps S1 to S5 will be described in detail below.

[0058] Step S1

[0059] like Figure 2A As shown, a stacked structure 200 comprising a plurality of stacked layers 210 can be formed on one side of the substrate 100, wherein each stacked layer 210 includes an interlayer insulating fill layer 211 and a sacrificial layer 212. Specifically, the interlayer insulating fill layer 211 and the sacrificial layer 212 are alternately stacked on the substrate 100 to form the stacked structure 200.

[0060] In exemplary embodiments of this application, the substrate 100 may be, for example, a polycrystalline silicon substrate, a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. In one embodiment, the substrate 100 may also be a stacked structure, such as Si / SiGe. In another embodiment, the substrate 100 may also be other epitaxial structures, such as silicon-germanium-on-insulator (SGOI).

[0061] In an exemplary embodiment of this application, forming a stacked structure 200 on the substrate 100 can be achieved through one or more deposition processes. The deposition processes for forming the stacked structure 200 include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. It should be understood that the number and thickness of the interlayer insulating filler layer 211 and the sacrificial layer 212 are not limited to... Figure 2A The quantities and thicknesses shown can be varied by those skilled in the art without departing from the concept of the embodiments of this application. Any number and thickness of interlayer insulating filler layers 211 and sacrificial layers 212 can be provided as needed. Furthermore, the materials of the interlayer insulating filler layers 211 and sacrificial layers 212 can be suitable materials known in the art. For example, the interlayer insulating filler layer 211 can be an oxide layer (such as silicon oxide), and the sacrificial layer 212 can be a nitride layer (such as silicon nitride).

[0062] Step S2

[0063] like Figure 3 As shown, a first top cutout structure 300 may be formed on the stacked structure 200, which may penetrate at least the stacked layer furthest from the substrate among the plurality of stacked layers 210. Exemplarily, the stacked layer furthest from the substrate may be a first stacked layer 220 located on the side facing away from the substrate. The first top cutout structure 300 may extend in a direction parallel to the substrate 100. Exemplarily, as... Figure 3 As shown, a first top cutout structure 300 can be formed on the stacked structure 200, penetrating at least the first stacked layer 220 furthest from the substrate among a plurality of stacked layers 210. The first top cutout structure 300 can be formed along a first direction X parallel to the substrate 100. Figure 3(Extended meaning). For example, a first top notch structure 300 can be formed on the stacked structure 200 using, for example, dry or wet etching processes, penetrating at least the first stacked layer 220 furthest from the substrate among a plurality of stacked layers. For the sake of brevity and clarity in this application, only one first top notch structure 300 is described below as an example. It should be understood that this application does not specifically limit the number of first top notch structures; the number of first top notch structures can be adjusted as needed, depending on the requirement for a number of smaller storage units in the three-dimensional memory.

[0064] In an exemplary embodiment of this application, forming a first top cutout structure 300 on the stacked structure 200 that penetrates at least the stacked layer 210 furthest from the substrate 100 may include: firstly, as Figure 2A As shown, a first top cutout 310 can be formed on the stacked structure 200, penetrating at least the first stacked layer 220 furthest from the substrate 100 among a plurality of stacked layers, and then, as Figure 2B As shown, the first top cutout 310 is filled with a first filling material 320 to form a first top cutout structure 300. Figure 3 For example, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof may be used to fill the first filler material 320 to the first top cutout 310 to form the first top cutout structure 300. The first filler material 320 may include any suitable insulating material such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide doped with fluorine, carbon, nitrogen, and / or hydrogen. It should be understood that in actual processes, during the filling of the first filler material 320 to the first top cutout 310, the first filler material 320 may also cover the top surface of the stacked structure 200.

[0065] For example, the first filler material 320 may be planarized using processes such as chemical mechanical polishing, so that the first filler material 320 provides a substantially flat upper surface for the top surface of the stacked structure 200. For example, the first filler material 320 covering the top surface of the stacked structure 200 may also be removed, leaving only the first filler material 320 filling the first top cutout 310 to form the first top cutout structure 300.

[0066] In an exemplary embodiment of this application, such as Figure 2AAs shown, a channel structure 400 can also be formed that penetrates the stacked structure 200 and extends to the substrate 100. Exemplarily, the channel structure 400 can be formed using, for example, a dry or wet etching process. Exemplarily, the first top notch structure 300 can extend in a first direction X parallel to the substrate 100 and pass through multiple channel structures 400. Of course, the first top notch structure 300 may not pass through the channel structures 400, that is, the first top notch structure 300 can also be disposed between multiple channel structures 400. It should be understood that in actual processes, the position of the first top notch structure 300 can be specifically set according to actual size requirements.

[0067] Step S3

[0068] like Figure 4 As shown, multiple stepped steps 500 can be formed in the stacked structure 200. Exemplarily, multiple stepped steps 500 can be formed on one side of the stacked structure 200, each stepped step 510 being formed by adjacent interlayer insulating filler layers 211 and sacrificial layers 212. Exemplarily, the region of the stacked structure 200 corresponding to the multiple stepped steps 500 is called a stepped region, which can be used to arrange word line connection structures. The region of the stacked structure 200 corresponding to the multiple channel structures 400 is called a core region, which can be used to form array memory cell strings.

[0069] Exemplarily, a plurality of stepped steps 500 are first formed in the stepped region by performing a repeated etch-trimming process on the stacked structure 200 using a patterned mask (not shown). The patterned mask may include a photoresist or a carbon-based polymer material and may be removed after the stepped steps are formed. Exemplarily, the top surface of each formed stepped step 510 exposes at least a portion of the sacrificial layer 212 located in the corresponding layer. That is, each stepped step 500 includes at least one level, each level including an interlayer insulating filler layer 211 and a sacrificial layer 212 from top to bottom. Exemplarily, after the plurality of stepped steps 500 are formed, a first top cutout structure 300 may extend along a first direction X parallel to the substrate 100 and penetrate at least the stepped step furthest from the substrate among the plurality of stepped steps 500. Although, Figure 4 The example illustrates three stepped steps and a first top cutout structure 300 penetrating three of the multiple stepped steps 500 that are far from the substrate. However, it should be understood that the embodiments of this application do not specifically limit the number of stepped steps or the number of stepped steps penetrated by the first top cutout structure. The number of stepped steps and the number of stepped steps penetrated by the first top cutout structure can be adjusted as needed, depending on the need for a number of smaller storage units in the three-dimensional memory.

[0070] Step S4

[0071] like Figure 6 As shown, a dielectric layer 600 can be formed to cover the stepped steps 500. Exemplarily, the dielectric layer 600 may include a buffer layer 610 formed on the top surface of the plurality of stepped steps 500. Figure 5 ) and an insulating filling layer 620 formed on the top surface of the buffer layer 610 and the sidewalls of the stepped step 500. Figure 6 ).

[0072] In an exemplary embodiment of this application, forming a buffer layer 610 on the top surface of a plurality of stepped steps 500 may include: first, forming a buffer layer 610 on the top surface and sidewall of each stepped step 500; then, removing the portion of the buffer layer 610 covering the sidewall of the stepped step 500 so that the buffer layers 610 on the top surfaces of adjacent steps are spaced apart from each other. Therefore, when the buffer layer 610 is subsequently replaced with a floating contact structure, this spacing effectively prevents word lines of adjacent gate layers from bridging each other and causing short circuits.

[0073] For example, the material forming the buffer layer 610 can be silicon nitride (TS SIN). For instance, when using phosphoric acid or similar etchants to wet-etch the silicon nitride on the sidewalls of the stepped step 500, the silicon nitride on the sidewalls of the stepped step 500, due to its lower density, can have an etching rate approximately two to three times that of normal SIN. This characteristic of silicon nitride material is beneficial for the subsequent formation of floating contact structures.

[0074] Exemplarily, the buffer layer 610 can be formed on the top surface and sidewalls of each step 500 by, for example, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. For example, the buffer layer 610 can be formed by an atomic layer deposition process. As an example, the buffer layer 610 formed on the sidewalls of the step can be removed by dry etching such as deep ion reactive etching (RIDE) or wet etching using phosphoric acid as an etchant, but the embodiments of this application are not limited thereto.

[0075] In an exemplary embodiment of this application, the insulating filler layer 620 can be formed on the top surface of the buffer layer 610 and the sidewalls of the stepped steps 500 by depositing oxide, which can be selected from, for example, a silicon oxide-based material. The insulating filler layer 620 can be formed by filling silicon oxide based on TEOS. Exemplarily, the insulating filler layer 620 can be a multilayer structure, first forming a first sub-film layer with good stepped step coverage, such as silicon oxide (SiO2) deposited by high-density plasma (HDP) or silicon oxide deposited by atomic layer deposition (ALD); then continuing to form a second sub-film layer with high filling efficiency, such as silicon oxide based on TEOS (TESO-based SiO2). In the exemplary embodiment, the density of the first sub-film layer is higher than the density of the second sub-film layer, thereby the first sub-film layer has good stepped step coverage, while the second sub-film layer has high filling efficiency.

[0076] As an example, processes such as chemical mechanical polishing can also be used to planarize the insulating filler layer 620, so that the insulating filler layer 620 provides a substantially flat upper surface for the stepped area of ​​the stacked structure 200.

[0077] Step S5

[0078] like Figure 8 As shown, a virtual channel hole 700 and a top notch 800 can be formed. The top notch 800 can extend along a first direction X, penetrate the dielectric layer 600, and extend at least into a first top notch structure 300 corresponding to the step furthest from the substrate 100 among a plurality of stepped steps 500. Exemplarily, the top notch 800 can extend along a first direction X parallel to the substrate 100 and penetrate the first stepped step 520 furthest from the substrate among a plurality of stepped steps 500, to extend into a first top notch structure 300 corresponding to the first stepped step 520. It should be understood that... Figure 8 The first step 520 is shown as an example only, comprising three steps. In actual manufacturing, the number of steps in the first step 520 can be determined according to actual needs.

[0079] Exemplarily, the top cutout 800 can penetrate the dielectric layer 600 and extend into the first top cutout structure 300 located within a plurality of stepped steps. Specifically, as Figure 7As shown, a patternable etchable mask layer 900 is used as a mask to etch the stacked structure 200 to form a virtual channel hole 700 that penetrates the stacked structure 200 and extends to the substrate 100, and a top cutout 800 extending along a first direction X parallel to the substrate 100 and penetrating the step 520 furthest from the substrate 100 among a plurality of stepped steps 500. Exemplarily, the top cutout 800 may extend along a direction parallel to the substrate 100 and penetrate a buffer layer 610 formed on the top surface of the plurality of stepped steps. In this case, the top cutout 800 partially overlaps with the first top cutout structure 300 because it penetrates the buffer layer 610.

[0080] For example, forming a patterned etching mask layer 900 on the top surface of the stacked structure 200 may include: forming an etching mask layer on the top surface of the stacked structure 200; and forming a plurality of virtual channel hole patterns 910 and a top notch pattern 920 in the etching mask layer to form the patterned etching mask layer 900. For example, masking the etching of the stacked structure with the patterned etching mask layer 900 may include: simultaneously etching the stacked structure 200 via the virtual channel hole patterns 910 and the top notch pattern 920, wherein the width of the top notch pattern 920 is smaller than the opening size of each virtual channel hole pattern 910, so that etching via the top notch pattern 920 automatically stops before etching via the virtual channel hole patterns 910 stops.

[0081] It should be understood that in the actual etching process, the virtual channel holes and top notches formed by etching should both be cone-shaped, that is, the opening size of the virtual channel hole near the top surface of the stacked structure is larger than its size near the substrate, and the width of the top notch near the top surface of the dielectric layer is larger than its width near the step. When the width of the top notch pattern 920 is small, the etching through the top notch pattern 920 will automatically stop after reaching a certain depth. Therefore, this application can control the width of the top notch pattern 920 to ensure that the etching through the top notch pattern 920 stops within the first top notch structure 300 in the step. The opening size of the virtual channel hole pattern 910 is larger than the width of the top notch pattern 920, so that the etching through the virtual channel hole pattern 910 has not stopped even after the etching through the top notch pattern 920 has automatically stopped.

[0082] In an exemplary embodiment of this application, a virtual channel hole 700 and a top notch 800 can be etched and formed by controlling the opening size of the virtual channel hole pattern 910 and the width of the top notch pattern 920. The virtual channel hole 700 can penetrate the stacked structure 200 and extend to the substrate 100, and the top notch 800 can penetrate the buffer layer 610 to partially overlap with the first top notch structure 300. Exemplarily, the opening size of the virtual channel hole can be controlled to be much larger than the width of the top notch 800. When the width of the top notch pattern 920 is small, the width of the top notch 800 formed by etching through the top notch pattern 920 is small. When the etching through the top notch pattern 920 automatically stops after reaching a certain depth, the top notch 800 can be made to only penetrate the buffer layer 610 or penetrate the buffer layer 610 and a portion of the first top notch structure 300 below the buffer layer 610, thereby ensuring that the top notch 800 does not penetrate the first top notch structure 300.

[0083] It should be understood that the embodiments of this application do not specifically limit the number of virtual channel holes. The number of virtual channel holes can be adjusted as needed, depending on the size of the three-dimensional memory.

[0084] For example, a plurality of virtual channel holes 700 and a top notch 800 can be formed in the stacked structure 200 by, for example, a dry etching process, such that the virtual channel holes 700 penetrate the stacked structure 200 along the thickness direction and extend into the substrate 100, and the top notch 800 can penetrate the buffer layer 610 to partially overlap with the first top notch structure 300. In other embodiments, the etching process can be stopped before the virtual channel holes 700 reach the substrate 100, and a subsequent stamping process can be performed to further extend the virtual channel holes 700 into the substrate 100.

[0085] The three-dimensional memory provided in this application embodiment overcomes the limitations of two-dimensional or planar flash memory by vertically stacking multiple layers of data storage units, enabling higher storage capacity in a smaller space, thereby effectively reducing cost and energy consumption. The virtual channel holes 700 in the three-dimensional memory serve as supports to prevent the overall structure from collapsing after the sacrificial layer 212 is removed.

[0086] In an exemplary embodiment of this application, such as Figure 9As shown, the virtual channel hole 700 and the top cutout 800 can be filled with a second filler material and a third filler material to form a virtual channel structure 710 and a second top cutout structure 810. Exemplarily, the materials of the third filler material and the second filler material can be the same as the material of the first filler material, or they can be different from the material of the first filler material 320. For example, the third filler material and the second filler material can include any suitable insulating material such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide doped with fluorine, carbon, nitrogen, and / or hydrogen. Figure 10 It shows Figure 9 The cross-sectional structure of the three-dimensional memory structure along the AA direction, from Figure 10 As can be seen, the overall height H of the second top notch structure 810 formed by etching and the first top notch structure 300 is less than the height of the channel structure 400 and the virtual channel structure 710.

[0087] For example, on a plane parallel to the substrate 100, the regions where the channel structure 400, the virtual channel hole 700, and the top notch 800 are located do not overlap with each other. In other words, on a plane parallel to the substrate 100, the regions where the channel structure 400, the virtual channel structure 710, and the second top notch structure 810 are located do not overlap with each other. It should be understood that in actual manufacturing processes, the positional relationships of the channel structure 400, the virtual channel structure 710, and the second top notch structure 810 can be specifically set according to actual size requirements.

[0088] Another aspect of this application provides a semiconductor structure.

[0089] The semiconductor structure may include a substrate 100, a stacked structure 200, and a first top notch structure 300. Figure 3 ), multiple steps 500 ( Figure 5 ), dielectric layer 600 and second top cut structure 810 ( Figure 9 ).

[0090] In exemplary embodiments of this application, the substrate 100 may be, for example, a polycrystalline silicon substrate, a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. In one embodiment, the substrate 100 may also be a stacked structure, such as Si / SiGe. In another embodiment, the substrate 100 may also be other epitaxial structures, such as silicon-germanium-on-insulator (SGOI).

[0091] In an exemplary embodiment of this application, the stacked structure 200 may be located on one side of the substrate 100 and includes multiple stacked layers. The formation of the stacked structure 200 on the substrate 100 can be achieved through one or more deposition processes. Deposition processes for forming the stacked structure 200 include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof.

[0092] In an exemplary embodiment of this application, the first top cutout structure 300 may extend along a first direction X parallel to the substrate 100 and may penetrate at least the stacked layer 220 furthest from the substrate 100 among a plurality of stacked layers.

[0093] In an exemplary embodiment of this application, the stepped step 500 may be located in the stacked structure 200. The dielectric layer 600 may cover the stepped step. The second top cutout structure 810 may extend along a first direction X parallel to the substrate 100, through the dielectric layer 600 and into the first top cutout structure 300 in the stepped step.

[0094] In an exemplary embodiment of this application, the semiconductor structure may further include a virtual channel structure 710. The virtual channel structure 710 may penetrate the stacked structure 200 and extend to the substrate 100. Exemplarily, the opening size of the virtual channel structure 710 may be larger than the width of the second top cutout structure 810. The width of the second top cutout structure 810 on the top surface of the dielectric layer 600 may be approximately equal to the width of the first top cutout structure 300.

[0095] In an exemplary embodiment of this application, the dielectric layer 600 may include a buffer layer 610 ( Figure 5 ) and insulating filler layer 620 ( Figure 6 The buffer layer 610 may be formed on the top surface of the multiple stepped steps. The insulating filler layer 620 may be formed on the top surface of the buffer layer 610 and the sidewalls of the stepped steps.

[0096] In an exemplary embodiment of this application, the material of the buffer layer 610 may include silicon nitride.

[0097] In an exemplary embodiment of this application, the second top notch structure 810 may extend in a direction parallel to the substrate 100 (such as the first direction X) and penetrate the buffer layer 610 formed on the top surface of the stepped step. It should be understood that, limited by the actual etching process, the formed second top notch structure 810 should be in a cone-like shape, that is, the width of the second top notch structure 810 near the top surface of the dielectric layer is greater than its width near the stepped step.

[0098] In an exemplary embodiment of this application, the semiconductor structure may further include a channel structure 400. The channel structure 400 may penetrate the stacked structure 200 and extend to the substrate 100.

[0099] For example, on a plane parallel to the substrate 100, the regions where the channel structure 400, the virtual channel hole 700, and the top notch 800 are located do not overlap with each other. In other words, on a plane parallel to the substrate 100, the regions where the channel structure 400, the virtual channel structure 710, and the second top notch structure 810 are located do not overlap with each other.

[0100] Figure 11 This is a schematic diagram of the structure of a three-dimensional memory according to one embodiment of this application.

[0101] like Figure 11 As shown, at least one embodiment of this application also provides a three-dimensional memory 1100. The three-dimensional memory 1100 may include a semiconductor structure 1110 and peripheral circuitry 1120. The semiconductor structure 1110 may be the same as the semiconductor structure described in any of the embodiments above, and will not be repeated here. The peripheral circuitry 1120 may be electrically connected to the semiconductor structure 1110.

[0102] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated here.

[0103] Although exemplary fabrication methods and structures of three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. Furthermore, the layers and materials described are merely exemplary.

[0104] Figure 12 This is a schematic diagram of the structure of a storage system 2000 according to one embodiment of this application.

[0105] like Figure 12 As shown, at least one embodiment of this application also provides a storage system 2000. The storage system 2000 may include a memory 2100 and a controller 2200. The memory 2100 may be the same as the memory described in any of the embodiments above, and will not be described again in this application. The storage system 2000 may be a two-dimensional storage system or a three-dimensional storage system; the following description uses a three-dimensional storage system as an example.

[0106] The three-dimensional storage system 2000 may include a three-dimensional memory 2100, a controller 2200, and a host 2300. The three-dimensional memory 2100 may be the same as the three-dimensional memory described in any of the embodiments above, and will not be repeated here. The controller 2200 controls the three-dimensional memory 2100 via channel CH, and the three-dimensional memory 2100 can perform operations based on the control of the controller 2200 in response to requests from the host 2300. The three-dimensional memory 2100 receives commands CMD and addresses ADDR from the controller 2300 via channel CH and accesses a region selected from the memory cell array in response to that address. In other words, the three-dimensional memory 2100 can perform internal operations corresponding to commands on the region selected by the address.

[0107] In some implementations, the three-dimensional storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC and Micro MMC, a Secure Digital Card in the form of SD, Mini SD and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card or Memory Stick, etc.

[0108] Figure 13 This is a schematic diagram of the structure of the electronic device 3000 provided in the embodiments of this application.

[0109] like Figure 13 As shown, at least one embodiment of this application also provides an electronic device 3000. The electronic device 3000 includes a memory 3100. The memory 3100 may be the same as the memory described in any of the embodiments above, and will not be repeated here. The electronic device 3000 may be a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device, power bank, or other device with storage capabilities. Therefore, other modules of the electronic device 3000, such as a controller, can be determined according to the specific device type of the electronic device 3000. Other modules can control the three-dimensional memory 3100 through channels, and the three-dimensional memory 3100 can receive commands CMD and addresses ADDR from other modules through channels, and access the region selected from the memory cell array in response to the address. This application does not limit this.

[0110] This application provides peripheral circuits, memory, storage systems, and electronic devices. Due to the metal interconnect structure provided in this application, they have the same beneficial effects as the metal interconnect structure described above, which will not be elaborated here.

[0111] The above description is merely a preferred embodiment of the present application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: A stacked structure comprising multiple stacked layers is formed on one side of the substrate; A first top cutout structure is formed in the stacked structure, the first top cutout structure extending along a first direction parallel to the substrate and penetrating at least one of the stacked layers on the side opposite to the substrate; Multiple stepped structures are formed in the stacked structure; A medium layer is formed covering the stepped steps; as well as A virtual channel hole and a top cut are formed, wherein the top cut extends along the first direction, passes through the dielectric layer along the stack thickness direction, and extends into the first top cut structure in the stepped step.

2. The preparation method according to claim 1, characterized in that, The virtual channel hole penetrates the stacked structure and extends to the substrate.

3. The preparation method according to claim 2, characterized in that, At the surface of the stacked structure, the opening size of the virtual channel hole is larger than the width of the top cutout.

4. The preparation method according to claim 1, characterized in that, Forming a first top cutout structure in the stacked structure includes: A first top cut through at least one of the stacked layers is formed in the stacked structure; and The first top cut is filled with a first filling material to form the first top cut structure.

5. The preparation method according to claim 3, characterized in that, The formation of the virtual channel hole and the top cut includes: A patterned etching mask layer is formed on the top surface of the stacked structure; The stacked structure is etched using the patterned etching mask layer as a mask to form the virtual channel holes and the top notch.

6. The preparation method according to claim 5, characterized in that, Forming a patterned etching mask layer on the top surface of the stacked structure includes: An etching mask layer is formed on the top surface of the stacked structure; and Virtual channel hole patterns and top notch patterns are formed in the etching mask layer to form the patterned etching mask layer, and Etching the stacked structure using the patterned etching mask layer as a mask includes: The stacked structure is simultaneously etched via the virtual channel hole pattern and the top cut pattern. The width of each of the top cut patterns is smaller than the opening size of each of the virtual channel hole patterns, so that etching via the top cut patterns automatically stops before etching via the virtual channel hole patterns stops.

7. The preparation method according to claim 1, characterized in that, The formation of multiple stepped steps in the stacked structure includes: A patterned mask is formed on the top surface of the stacked structure; and The stacked structure is etched using a patterned mask as a cover to form multiple stepped steps.

8. The preparation method according to claim 1, characterized in that, The dielectric layer includes a buffer layer and an insulating filler layer. The medium layer forming the layer covering the stepped steps includes: The buffer layer is formed on the top surface of the plurality of stepped steps; and The insulating filling layer is formed on the top surface of the buffer layer and the sidewalls of the stepped steps.

9. The preparation method according to claim 8, characterized in that, The top cut penetrates the buffer layer.

10. The preparation method according to claim 8, characterized in that, Forming the buffer layer on the top surface of the plurality of stepped steps includes: Forming a buffer layer covering the stepped steps; and Remove the portion of the buffer layer that covers the sidewall of the stepped steps.

11. The preparation method according to claim 4, characterized in that, The first filler material includes oxides.

12. The preparation method according to claim 8, characterized in that, The material of the buffer layer includes silicon nitride.

13. The preparation method according to claim 1, characterized in that, Before forming the first top cutout structure in the stacked structure, the method further includes: A channel structure is formed that penetrates the stacked structure and extends to the substrate.

14. The preparation method according to claim 13, characterized in that, On a plane parallel to the substrate, the regions where the channel structure, the virtual channel aperture, and the top cutout are located do not overlap with each other.

15. The preparation method according to claim 1, characterized in that, The method further includes: The virtual channel hole and the top cut are filled with a second filling material to form a virtual channel structure and a second top cut structure.

16. A semiconductor structure, characterized in that, include: Substrate; A stacked structure is located on one side of the substrate and includes multiple stacked layers; A first top cutout structure extends along a first direction parallel to the substrate and penetrates at least one of the plurality of stacked layers on the side opposite to the substrate; Multiple stepped structures are located within the stacked structure; A dielectric layer covers the stepped surface; The second top cut structure extends along the first direction, passes through the medium layer along the stack thickness direction, and extends into the first top cut structure in the stepped step.

17. The semiconductor structure according to claim 16, characterized in that, The semiconductor structure also includes: A virtual channel structure extends through the stacked structure and into the substrate, wherein the opening size of the virtual channel structure is larger than the width of the second top cutout structure.

18. The semiconductor structure according to claim 16, characterized in that, The dielectric layer includes: A buffer layer is located on the top surface of the plurality of stepped steps; and An insulating filler layer is located on the top surface of the buffer layer and the sidewall of the stepped step.

19. The semiconductor structure according to claim 18, characterized in that, The material of the buffer layer includes silicon nitride.

20. The semiconductor structure according to claim 18, characterized in that, The second top cut structure penetrates the buffer layer.

21. The semiconductor structure according to claim 17, characterized in that, The semiconductor structure also includes: A channel structure that penetrates the stacked structure and extends to the substrate.

22. The semiconductor structure according to claim 21, characterized in that, On a plane parallel to the substrate, the region containing the channel structure, the region containing the virtual channel structure, and the region containing the second top cutout structure do not overlap with each other.

23. The semiconductor structure according to claim 16, characterized in that, The width of the second top cut structure on the top surface of the medium layer is equal to the width of the first top cut structure.

24. A three-dimensional memory, characterized in that, The three-dimensional memory includes: The semiconductor structure according to any one of claims 16-23; and The peripheral circuit is electrically connected to the semiconductor structure.

25. A storage system, characterized in that, The storage system includes a controller and the three-dimensional memory of claim 24, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

26. An electronic device, characterized in that, include: The storage system of claim 25.

27. The electronic device according to claim 26, characterized in that, The electronic device includes at least one of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle-mounted equipment, wearable device, and power bank.

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