Filter circuit and integrated circuit for a transmit channel

Abstract

A filter circuit (500) comprises a first differential circuit (510) and a second differential circuit (520), the first differential circuit (510) comprises a first differential inductor (110), and the second differential circuit (520) comprises a second differential inductor (120); the magnetic force line directions of the first differential inductor (110) and the second differential inductor (120) are opposite when working, and then the magnetic fields formed by the first differential inductor (110) and the second differential inductor (120) can offset each other, and then the influence of the first differential inductor (110) and the second differential inductor (120) on each other and on the peripheral circuit devices can be reduced, so that the isolation between the first differential inductor (110) and the second differential inductor (120) can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the electrical field, and more particularly, to a filter circuit and an integrated circuit for a transmit channel. BACKGROUND

[0002] With the continuous development of the fifth generation mobile communication (5th Generation, 5G) technology, operators can provide large bandwidth, multi-channel base station chips to solve the application requirements of large-scale multiple-input multiple-output. In the architecture of the transmit channel in the multi-channel chip, both the filter and the modulator adopt a passive architecture to meet the low power consumption requirement, and in order to improve the common mode rejection, the filter circuit and the modulator circuit are in differential form.

[0003] Due to the large area of the multi-stage filter circuit in the system on chip, in order to save the area of the chip, the single transmit channel composed of the differential circuit with the input signal as in-phase (I) and the differential circuit with the input signal as quadrature (Q) is usually arranged closely, and each transmit channel in the multi-transmit channel is arranged closely, which will cause the intermediate frequency isolation of the adjacent IQ paths in the single transmit channel or the intermediate frequency isolation of the adjacent IQ paths in the adjacent channels in the multi-channel to be limited, which cannot meet the requirements of the system, so that the algorithm correction cannot be used to realize the image rejection performance required by the system. SUMMARY

[0004] The present application provides a filter circuit and an integrated circuit for a transmit channel, which can improve the isolation between the adjacent two differential inductors in the single transmit channel or the isolation between the adjacent two differential inductors in the adjacent two channels in the multi-transmit channel under the condition of limited chip area.

[0005] In a first aspect, a filter circuit is provided, comprising a first differential circuit and a second differential circuit, the first differential circuit comprising a first differential inductor, and the second differential circuit comprising a second differential inductor; the magnetic field lines of the first differential inductor and the second differential inductor are in opposite directions when working.

[0006] The first differential circuit and the second differential circuit can be two differential circuits arranged in parallel in a single transmit channel. Alternatively, the first differential circuit and the second differential circuit can be two differential circuits arranged in parallel in the adjacent channels in a multi-transmit channel.

[0007] The magnetic field directions of the first differential inductor and the second differential inductor are opposite when the first differential inductor and the second differential inductor work, and the magnetic fields formed by the first differential inductor and the second differential inductor can offset each other, thereby reducing the influence of the first differential inductor and the second differential inductor on each other and on peripheral circuit devices, so that the isolation between the first differential inductor and the second differential inductor can be improved, that is, the isolation between two adjacent differential inductors in a single channel or the isolation between two adjacent differential inductors in two adjacent channels in a multi-channel can be improved.

[0008] With reference to the first aspect, in a possible implementation manner, the first differential circuit includes a first positive input end and a first negative input end, the second differential circuit includes a second positive input end and a second negative input end, the first differential inductor and the second differential inductor are spiral inductors of the same winding mode, the first differential inductor and the second differential inductor each include a same first input end and a second input end, the first positive input end is coupled to the second input end of the first differential inductor, and the first negative input end is coupled to the first input end of the first differential inductor; the second positive input end is coupled to the first input end of the second differential inductor, and the second negative input end is coupled to the second input end of the second differential inductor.

[0009] With reference to the first aspect, in a possible implementation manner, the first differential inductor and the second differential inductor are in the magnetic field range of each other, so that the magnetic fields generated by the first differential inductor and the second differential inductor offset each other when the first differential inductor and the second differential inductor work.

[0010] The first differential inductor and the second differential inductor are in the magnetic field range of each other, so that the magnetic fields generated by the first differential inductor and the second differential inductor offset each other when the first differential inductor and the second differential inductor work, thereby reducing the influence of the first differential inductor and the second differential inductor on each other and on peripheral circuit devices, so that the isolation between the first differential inductor and the second differential inductor can be improved, that is, the isolation between two adjacent differential inductors in a single channel or the isolation between two adjacent differential inductors in two adjacent channels in a multi-channel can be improved.

[0011] With reference to the first aspect, in a possible implementation manner, when the signal is input to the first differential circuit by the first positive input end, the signal runs in the first differential inductor in a first direction; when the signal is input to the second differential circuit by the second positive input end, the signal runs in the second differential inductor in a second direction, and the second direction is opposite to the first direction.

[0012] In a possible implementation manner of the first aspect, the first differential circuit further includes a first positive output end and a first negative output end; the second differential circuit further includes a second positive output end and a second negative output end; the first differential inductor and the second differential inductor each include a same first output end and a second output end; the first output end of the first differential inductor is coupled to the first negative output end, the second output end of the first differential inductor is coupled to the first positive output end, the first output end of the second differential inductor is coupled to the second positive output end, and the second output end of the second differential inductor is coupled to the second negative output end; a connection line between the first positive input end and the first negative output end is parallel to a connection line between the first negative input end and the first positive output end; and a connection line between the second positive input end and the second negative output end is parallel to a connection line between the second negative input end and the second positive output end.

[0013] The connection manners of the output ends of the first differential inductor and the first differential circuit and the connection manners of the output ends of the second differential inductor and the second differential circuit can ensure consistency of directions of output signals of the first differential circuit and the second differential circuit.

[0014] In a possible implementation manner of the first aspect, a distance between the first differential inductor and the second differential inductor is less than or equal to a target distance.

[0015] In a possible implementation manner of the first aspect, signals input by the first differential circuit and signals input by the second differential circuit are quadrature signals.

[0016] The signals input by the first differential circuit and the signals input by the second differential circuit being quadrature signals can be understood as that the signals input by the first differential circuit and the signals input by the second differential circuit are 90 degrees out of phase.

[0017] In a possible implementation manner of the first aspect, the first differential circuit further includes a first positive output end and a first negative output end; the second differential circuit further includes a second positive output end and a second negative output end; the first differential inductor and the second differential inductor each include a same first output end and a second output end; the first output end of the first differential inductor is coupled to the first negative output end, the second output end of the first differential inductor is coupled to the first positive output end, the first output end of the second differential inductor is coupled to the second positive output end, and the second output end of the second differential inductor is coupled to the second negative output end; a connection line between the first positive input end and the first negative output end is parallel to a connection line between the first negative input end and the first positive output end; and a connection line between the second positive input end and the second negative output end is parallel to a connection line between the second negative input end and the second positive output end.

[0018] The first differential circuit and the second differential circuit can be two differential circuits arranged in parallel in a single transmitting channel. Alternatively, the first differential circuit and the second differential circuit can be two differential circuits arranged in parallel in adjacent channels in a multi-transmitting channel.

[0019] In the integrated circuit, the digital-to-analog converter, the modulator and the filter circuit are included. Magnetic field directions of the first differential inductor and the second differential inductor in the filter circuit are opposite when the first differential inductor and the second differential inductor work. The magnetic fields formed by the first differential inductor and the second differential inductor cancel each other, thereby reducing the influence of the first differential inductor and the second differential inductor on each other and on peripheral circuit devices. The isolation between the first differential inductor and the second differential inductor can be improved, i.e., the isolation between two adjacent differential inductors in a single channel or the isolation between two adjacent differential inductors in adjacent channels in a multi-channel can be improved.

[0020] With reference to the second aspect, in a possible implementation, the first differential circuit includes a first positive input end and a first negative input end, the second differential circuit includes a second positive input end and a second negative input end, the first differential inductor and the second differential inductor are spiral inductors of the same winding mode, the first differential inductor and the second differential inductor each include a same first input end and a same second input end, the first positive input end is coupled to the second input end of the first differential inductor, and the first negative input end is coupled to the first input end of the first differential inductor. The second positive input end is coupled to the first input end of the second differential inductor, and the second negative input end is coupled to the second input end of the second differential inductor.

[0021] With reference to the second aspect, in a possible implementation, the first differential inductor and the second differential inductor are in a magnetic field range of each other, so that the magnetic fields generated by the first differential inductor and the second differential inductor cancel each other when the first differential inductor and the second differential inductor work.

[0022] With reference to the second aspect, in a possible implementation, when a signal is input to the first differential circuit from the first positive input end, a direction of the signal in the first differential inductor is a first direction. When the signal is input to the second differential circuit from the second positive input end, a direction of the signal in the second differential inductor is a second direction, and the second direction is opposite to the first direction.

[0023] In a possible implementation manner of the second aspect, the first differential circuit further includes a first positive output end and a first negative output end; the second differential circuit further includes a second positive output end and a second negative output end; the first differential inductor further includes a first output end of the first differential inductor and a second output end of the first differential inductor; the second differential inductor further includes a first output end of the second differential inductor and a second output end of the second differential inductor; the first differential inductor and the second differential inductor both include the same first output end and the same second output end; the first output end of the first differential inductor is coupled to the first negative output end, the second output end of the first differential inductor is coupled to the first positive output end, the first output end of the second differential inductor is coupled to the second positive output end, and the second output end of the second differential inductor is coupled to the second negative output end; a connection line between the first positive input end and the first negative output end is parallel to a connection line between the first negative input end and the first positive output end; and a connection line between the second positive input end and the second negative output end is parallel to a connection line between the second negative input end and the second positive output end.

[0024] The output end of the first differential inductor and the output end of the first differential circuit are connected in a manner, and the output end of the second differential inductor and the output end of the second differential circuit are connected in a manner, so that consistency of directions of output signals of the first differential circuit and the second differential circuit can be ensured.

[0025] In a possible implementation manner of the second aspect, a distance between the first differential inductor and the second differential inductor is less than or equal to a target distance.

[0026] In a possible implementation manner of the second aspect, signals input by the first differential circuit and signals input by the second differential circuit are quadrature signals.

[0027] The signals input by the first differential circuit and the signals input by the second differential circuit being quadrature signals can be understood as that the signals input by the first differential circuit and the signals input by the second differential circuit are 90 degrees out of phase.

[0028] The third aspect provides a chip system including the filter circuit in the first aspect and any possible implementation manner of the first aspect.

[0029] The fourth aspect provides a chip system including the integrated circuit for a transmitting channel in the second aspect and any possible implementation manner of the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1A transmit architecture schematic in a single-channel chip is shown.

[0031] Figure 2 A transmit internal circuit module schematic in a single-channel chip is shown.

[0032] Figure 3 A structure schematic of a filter circuit 300 is shown.

[0033] Figure 4 A structure schematic of another filter circuit 400 is shown.

[0034] Figure 5 A structure schematic of a filter circuit 500 provided by an embodiment of the present application is shown.

[0035] Figure 6 A structure schematic of another filter circuit 600 provided by an embodiment of the present application is shown.

[0036] Figure 7 A structure schematic of yet another filter circuit 700 provided by an embodiment of the present application is shown.

[0037] Figure 8 A structure schematic of yet another filter circuit 800 provided by an embodiment of the present application is shown.

[0038] Figure 9 A structure schematic of yet another filter circuit 900 provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0039] The technical solutions in the present application will be described below with reference to the accompanying drawings.

[0040] The filter circuit or integrated circuit designed by the embodiments of the present application is mainly arranged in a single-channel or multi-channel network device chip. The single channel in the chip can be a single transmit channel or a single receive channel. The multi-channel in the chip can include N transmit channels and M receive channels, where N>1 and M>1. For example, when N=4 and M=4, the multi-channel in the chip can be four transmit channels and four receive channels; for another example, when N=8 and M=8, the multi-channel in the chip can be eight transmit channels and eight receive channels.

[0041] The filter circuit involved in the embodiments of the present application can be a filter circuit in a single channel or a filter circuit in a multi-channel. The two adjacent channels in the multi-channel designed by the embodiments of the present application can be understood as no other channel being arranged between the two channels.

[0042] It should be understood that the network device described above can be any device with wireless transceiver function. The device includes, but is not limited to, an evolved Node B (eNB), a radio network controller (RNC), a Node B (NB), a base station controller (BSC), a base transceiver station (BTS), a home base station (e.g., a Home eNB or HNB), a baseband unit (BBU), an access point (AP) in a wireless fidelity (WIFI) system, a wireless relay node, a wireless backhaul node, a transmission point (TP), or a transmission and reception point (TRP), etc., and can also be a gNB or a TP in a 5G (e.g., NR) system, one or a group (including multiple antenna panels) of antenna panels of a base station in a 5G system, or a network node constituting a gNB or a TP, such as a baseband unit (BBU) or a distributed unit (DU), etc.

[0043] In some deployments, a gNB can include a centralized unit (CU) and a DU. A gNB can also include an active antenna unit (AAU). The CU implements part of the functions of the gNB, and the DU implements part of the functions of the gNB. For example, the CU is responsible for processing non-real-time protocols and services, implementing the radio resource control (RRC) layer, and the functions of the packet data convergence protocol (PDCP) layer. The DU is responsible for processing the physical layer protocol and real-time services, implementing the functions of the radio link control (RLC) layer, the media access control (MAC) layer, and the physical (PHY) layer. The AAU implements part of the physical layer processing functions, radio frequency processing, and related functions of the active antenna. Since the information of the RRC layer eventually becomes the information of the PHY layer, or is transformed from the information of the PHY layer, in this architecture, high-layer signaling, such as RRC layer signaling, can also be considered as being sent by the DU, or by the DU+AAU. It can be understood that the network device can be a device including one or more of the CU node, the DU node, and the AAU node. In addition, the CU can be divided into a network device in a radio access network (RAN), or can be divided into a network device in a core network (CN), which is not limited in the present application.

[0044] In order to facilitate understanding of the embodiments of the present application, first, several concepts involved in the following are briefly described.

[0045] 1. Passive element: resistance, inductance, and capacitance elements, which have the common characteristic that they can work when there is a signal in the circuit without the need to add a power supply.

[0046] 2. Inductance is a property of a closed circuit, which is a physical quantity. When a coil passes through a current, a magnetic field is formed in the coil, and the induced magnetic field will generate an induced current to resist the current passing through the coil. The interaction between this current and the coil is called the electric inductance. The calculation formula of the inductance XL is: XL = ωL = 2πfL, where ω is the angular frequency, L is the inductance of the coil, and f is the working frequency. From the calculation formula of the inductance, it can be seen that with the increase of the frequency, the inductance also increases, that is, the resistance of the inductance to high-frequency signals increases. In other words, the inductance can play a role in hindering high-frequency signals in a high-frequency circuit, and the higher the frequency, the greater the resistance.

[0047] Among them, the frequency can be divided into low frequency, medium frequency and high frequency, the low frequency is generally 30-300 kHz, the medium frequency is generally 300-3000 kHz, and the high frequency is generally 3-30 MHz.

[0048] 3、Modulator refers to a device that modulates low frequency signals into high frequency signals for signal transmission through digital signal processing technology. Modulators are generally used to modulate two input signals (for example, in-phase (I) output of the modulated signal and quadrature (Q) output of the modulated signal). The frequency of the output signal of the modulator is equal to the sum, difference or other combination of the two input signal frequencies. A general modulator also needs to receive a local oscillator signal from a voltage-controlled oscillator, and its circuit works completely in the radio frequency band.

[0049] 4、Differential circuit is a circuit with the characteristics of "suppressing common-mode signals and amplifying differential-mode signals". The input end of the circuit is the input of two signals, and the difference between the two signals is the effective input signal of the circuit. The output of the circuit is the amplification of the difference between the two input signals. If there is an interference signal, it will produce the same interference to the two input signals. Through the difference between the two, the effective input of the interference signal is zero, which achieves the purpose of resisting common-mode interference.

[0050] 5、A differential inductor is formed by winding two separate inductors together to form four ports. The four ports of the differential inductor can be connected to other elements. Compared with the two separate inductors that make up a differential inductor, a differential inductor has a smaller area.

[0051] Figure 1 A schematic diagram of a transmit architecture in a multi-channel chip is shown. As shown in Figure 1 Each channel transmit architecture in the multi-channel chip includes two input signals, i.e. in-phase (I) and quadrature (Q). For example, as shown in Figure 1As shown, one path can include a digital-to-analog converter (DAC) 101, a filter 102, and a modulator 103; the other path can include a DAC 101', a filter 102', and a modulator 103'. The filter 102 can be a bandpass filter, used to allow signals within a certain frequency range to pass through. In some cases, the filter 102 can also be a low-pass filter, used to allow signals below the cutoff frequency to pass through. The transmitting architecture can also include an oscillator 105 and an amplifier 104. The following describes the components using the in-phase path as an example. The DAC 101 converts the digital signal into an analog signal, which can be a differential signal. The DAC then splits the analog signal into two paths (differential circuits) and sends it to the low-pass filter 102. The filter 102 allows signals below the cutoff frequency to pass through while filtering out signals above the cutoff frequency. Modulator 103 mixes the output signal of filter 102 with the local oscillator (LO) signal output of oscillator 105 to obtain a mixed signal. Modulator 103 converts the input differential signal into a mixed signal. This mixed radio frequency signal enters amplifier 104, which amplifies the mixed signal.

[0052] like Figure 2 The diagram shown is a schematic of the internal transmission circuit module in a single-channel chip. Figure 2 The dashed line indicates that it could be... Figure 1 One possible implementation of the filter 102 is as follows. The filter 102 can be a passive filter, typically composed of inductors and capacitors. To better suppress out-of-band noise and glitches generated by the pre-amplifier DAC, passive filters generally use multiple inductors and capacitors to implement multi-order filtering. The filter 102 can also be composed of a differential circuit with two input terminals, for example... Figure 2 The input terminals ① and ② shown are configured such that one is a positive input and the other is a negative input. The signals input to these two terminals can be the first signal to be processed and the second signal to be processed, respectively. The filter 102 can be a fifth-order passive filter, meaning that each path of the differential circuit of this fifth-order passive filter can include two inductors and three capacitors. For example... Figure 2 As shown, in one path of the differential circuit, the two inductors are L1 (122) and L2 (124), and the three capacitors are 121, 123, and 125; in the other path of the differential circuit, the two inductors are L1' and L2', and the three capacitors are 121', 123', and 125'. The signal to be processed is filtered by passive filter 102.

[0053] likeFigure 3 As shown in FIG. 1, a filter circuit 300 can include two differential circuits, i.e., a first differential circuit 310 and a second differential circuit 320, each of which can be Figure 2 As shown in FIG. 1, a filter circuit 300 can include two differential circuits, i.e., a first differential circuit 310 and a second differential circuit 320, each of which can be Figure 3The first differential circuit includes four ports, i.e., an input end 1 of the first differential circuit, an input end 2 of the first differential circuit, an output end 5 of the first differential circuit, and an output end 6 of the first differential circuit. The first differential circuit includes a first differential inductor 110, a capacitor C1, a capacitor C2, a capacitor C1', and a capacitor C2'. The first differential inductor 110 can include four ports, i.e., a port 1', a port 2', a port 5', and a port 6'. In the first differential circuit, one end of the capacitor C1 is grounded, and the other end is connected to the input end 1 of the first differential circuit; one end of the capacitor C1' is grounded, and the other end is connected to the input end 2 of the first differential circuit; one end of the capacitor C2 is grounded, and the other end is connected to the output end 5 of the first differential circuit; one end of the capacitor C2' is grounded, and the other end is connected to the output end 6 of the first differential circuit; the port 1' of the first differential inductor 110 is connected to the input end 1 of the first differential circuit, and the port 2' of the first differential inductor 110 is connected to the input end 2 of the first differential circuit; the port 5' of the first differential inductor 110 is connected to the output end 5 of the first differential circuit, and the port 6' of the first differential inductor 110 is connected to the output end 6 of the first differential circuit. The second differential circuit includes four ports, i.e., an input end 3 of the second differential circuit, an input end 4 of the second differential circuit, an output end 7 of the second differential circuit, and an output end 8 of the second differential circuit. The second differential circuit includes a second differential inductor 120, a capacitor C3, a capacitor C4, a capacitor C3', and a capacitor C4'. The second differential inductor 120 can include four ports, i.e., a port 3', a port 4', a port 7', and a port 8'. In the second differential circuit, one end of the capacitor C3 is grounded, and the other end is connected to the input end 3 of the second differential circuit; one end of the capacitor C3' is grounded, and the other end is connected to the input end 4 of the second differential circuit; one end of the capacitor C4 is grounded, and the other end is connected to the output end 7 of the second differential circuit; one end of the capacitor C4' is grounded, and the other end is connected to the output end 8 of the second differential circuit; the port 3' of the second differential inductor 120 is connected to the input end 3 of the second differential circuit, and the port 4' of the second differential inductor 120 is connected to the input end 4 of the second differential circuit; the port 7' of the second differential inductor 120 is connected to the output end 7 of the second differential circuit, and the port 8' of the second differential inductor 120 is connected to the output end 8 of the second differential circuit. The sign of the signal input by the input end 1 of the first differential circuit is the same as the sign of the signal input by the input end 3 of the second differential circuit, the sign of the signal input by the input end 2 of the first differential circuit is the same as the sign of the signal input by the input end 4 of the second differential circuit, the sign of the signal output by the output end 5 of the first differential circuit is the same as the sign of the signal output by the output end 7 of the second differential circuit, and the sign of the signal output by the output end 6 of the first differential circuit is the same as the sign of the signal output by the output end 8 of the second differential circuit.If the input terminal 1 of the first differential circuit is a positive signal, the input terminal 2 of the first differential circuit is a negative signal, the input terminal 3 of the second differential circuit is a positive signal, and the input terminal 4 of the second differential circuit is a negative signal, when the signals are input to the first differential circuit and the second differential circuit respectively, the signal (current) direction B in the second differential inductor 120 is the same as the signal (current) direction B in the first differential inductor 110.

[0054] like Figure 4 As shown, another filter circuit 400 is illustrated, which includes: a first differential circuit 410 and a second differential circuit 420, each differential circuit being... Figure 2 The circuit diagram inside filter 120 is shown. The first differential circuit 410 and the second differential circuit 420 can be two parallel differential circuits in a single channel, or they can be two parallel differential circuits in a multi-channel system. The filter circuit 400 shown can be a 5th-order passive filter, meaning each differential circuit in the filter circuit 400 includes two inductors and three capacitors. Similarly, in one implementation, to save area, the inductors of two different paths in the differential circuit can be wound together to form a differential inductor, such as... Figure 4The first differential circuit includes 4 ports, i.e., an input end 1 of the first differential circuit, an input end 2 of the first differential circuit, an output end 5 of the first differential circuit, and an output end 6 of the first differential circuit. The first differential circuit includes a first differential inductor 110, a third differential inductor 130, a capacitor C1, a capacitor C2, a capacitor C5, a capacitor C1', a capacitor C2', and a capacitor C5'. The first differential inductor 110 can include 4 ports, i.e., an input end 11, an input end 12, an output end 13, and an output end 14. The third differential inductor 130 can include 4 ports, i.e., an input end 31, an input end 32, an output end 33, and an output end 34. In the first differential circuit, one end of the capacitor C1 is grounded, and the other end is connected to the input end 1 of the first differential circuit. One end of the capacitor C1' is grounded, and the other end is connected to the input end 2 of the first differential circuit. One end of the capacitor C2 is grounded, and the other end is connected to the output end 5 of the first differential circuit. One end of the capacitor C5 is grounded, and the other end is connected to the output end 13 of the first differential inductor. One end of the capacitor C5' is grounded, and the other end is connected to the output end 14 of the first differential inductor. The input end 11 of the first differential inductor 110 is connected to the input end 1 of the first differential circuit. The input end 12 of the first differential inductor 110 is connected to the input end 2 of the first differential circuit. The output end 13 of the first differential inductor 110 is connected to the input end 31 of the third differential inductor 130. The output end 14 of the first differential inductor 110 is connected to the input end 32 of the third differential inductor 130. The output end 33 of the third differential inductor 130 is connected to the output end 5 of the first differential circuit. The output end 34 of the third differential inductor 130 is connected to the output end 6 of the first differential circuit.The second differential circuit comprises a second differential inductor 120, a capacitor C3, a capacitor C4, a capacitor C6, a capacitor C3', a capacitor C4' and a capacitor C6'. The second differential inductor 120 can comprise four ports, i.e., an input end 21, an input end 22, an output end 23 and an output end 24. The fourth differential inductor 140 can comprise four ports, i.e., an input end 41, an input end 42, an output end 43 and an output end 44. In the second differential circuit, one end of the capacitor C3 is grounded, and the other end is connected to the input end 3 of the second differential circuit. One end of the capacitor C3' is grounded, and the other end is connected to the input end 4 of the second differential circuit. One end of the capacitor C4 is grounded, and the other end is connected to the output end 7 of the second differential circuit. One end of the capacitor C4' is grounded, and the other end is connected to the output end 8 of the second differential circuit. One end of the capacitor C6 is grounded, and the other end is connected to the output end 23 of the second differential inductor. One end of the capacitor C6' is grounded, and the other end is connected to the output end 24 of the second differential inductor. The input end 21 of the second differential inductor 120 is connected to the input end 3 of the second differential circuit. The input end 22 of the second differential inductor 120 is connected to the input end 4 of the second differential circuit. The output end 23 of the second differential inductor 120 is connected to the input end 41 of the fourth differential inductor 140. The output end 24 of the second differential inductor 120 is connected to the input end 42 of the fourth differential inductor 140. The output end 43 of the fourth differential inductor 140 is connected to the output end 7 of the second differential circuit. The output end 44 of the fourth differential inductor 140 is connected to the output end 8 of the second differential circuit. The sign of the signal input into the input end 1 of the first differential circuit is the same as the sign of the signal input into the input end 3 of the second differential circuit. The sign of the signal input into the input end 2 of the first differential circuit is the same as the sign of the signal input into the input end 4 of the second differential circuit. The sign of the signal output from the output end 5 of the first differential circuit is the same as the sign of the signal output from the output end 7 of the second differential circuit. The sign of the signal output from the output end 6 of the first differential circuit is the same as the sign of the signal output from the output end 8 of the second differential circuit. If the input end 1 of the first differential circuit inputs a positive signal, the input end 2 of the first differential circuit inputs a negative signal, the input end 3 of the second differential circuit inputs a positive signal, and the input end 4 of the second differential circuit inputs a negative signal, when the signals are input into the first differential circuit and the second differential circuit respectively, the signal (current) direction B in the second differential inductor 120 is the same as the signal (current) direction B in the first differential inductor 110, and the signal (current) direction B in the third differential inductor 130 is the same as the signal (current) direction B in the fourth differential inductor 140.

[0055] Since a plurality of elements are included in the multi-stage filter, the multi-stage filter occupies a large area. In order to save the area occupied by the multi-stage filter on the chip, the first differential circuit and the second differential circuit are usually arranged close to each other, that is, two parallel differential circuits in a single transmission channel are arranged close to each other, or two parallel differential circuits between each single transmission channel in a multi-transmission channel are arranged close to each other. However, as shown in the above Figure 3 and Figure 4 When the signal is input to the first differential circuit and the second differential circuit, the directions of the signals (currents) in the differential inductors in the first differential circuit and the directions of the signals (currents) in the differential inductors in the second differential circuit are the same, that is, the directions of the magnetic fields generated in the differential inductors in the first differential circuit and the directions of the magnetic fields generated in the differential inductors in the second differential circuit are the same. Therefore, the magnetic fields generated in the differential inductors in the first differential circuit and the magnetic fields generated in the differential inductors in the second differential circuit will affect each other, which causes the isolation degree of the two adjacent differential inductors in the adjacent IQ channels in the single transmission channel or the isolation degree of the two adjacent differential inductors in the adjacent IQ channels in the two adjacent channels in the multi-channel to be unable to meet the requirements of the system, so that the image rejection performance required by the system cannot be realized through algorithm correction.

[0056] Therefore, it is urgent to provide a filter circuit which can improve the isolation degree of the two adjacent differential inductors in the adjacent IQ channels in the single transmission channel and the isolation degree of the two adjacent differential inductors in the adjacent IQ channels in the two adjacent channels in the multi-channel under the condition that the chip area is limited.

[0057] The differential inductor involved in the embodiments of the present application is formed by winding two ordinary inductors together to form four ports, and the four ports are connected to different input or output ports of the differential circuit. The shape of the differential inductor can be octagonal, and the shape of the differential inductor can also be square. The shape of the differential inductor is not limited in the present application.

[0058] The filter circuit provided by the present application will be described in detail below taking Figures 5 to 9 as an example.

[0059] The filter circuit provided by the present application includes a first differential circuit and a second differential circuit, the first differential circuit includes a first differential inductor, and the second differential circuit includes a second differential inductor; and the magnetic field lines of the first differential inductor and the second differential inductor are in opposite directions when the first differential inductor and the second differential inductor work.

[0060] Optionally, the distance between the first differential inductor and the second differential inductor is less than or equal to a target distance.

[0061] The target distance is a preset distance value.

[0062] The distance between the first differential inductor and the second differential inductor is less than or equal to the target distance, which means that the first differential inductor and the second differential inductor are two differential inductors arranged adjacent to each other.

[0063] In the case that the first differential inductor and the second differential inductor are arranged adjacent to each other, the first differential inductor and the second differential inductor are in the magnetic field range of each other, so that the magnetic fields generated by the first differential inductor and the second differential inductor when working cancel each other out.

[0064] Optionally, the first differential circuit and the second differential circuit can be two differential circuits arranged adjacent to each other in a single transmission channel (i.e., the same transmission channel). Alternatively, the first differential circuit and the second differential circuit can also be two differential circuits arranged adjacent to each other in adjacent channels in multiple transmission channels (i.e., different transmission channels). It can be understood that the two differential circuits arranged adjacent to each other are two differential circuits without other circuits or elements arranged between the two differential circuits.

[0065] It can be understood that the first differential inductor and the second differential inductor can be two differential inductors with a distance between the two differential inductors in the same channel less than or equal to the target distance. Alternatively, the first differential inductor and the second differential inductor can also be two differential inductors with a distance between the two differential inductors in adjacent channels less than or equal to the target distance.

[0066] Optionally, the first differential circuit includes a first positive input end and a first negative input end, the second differential circuit includes a second positive input end and a second negative input end, the first differential inductor and the second differential inductor are spiral inductors with the same winding mode, the first differential inductor and the second differential inductor each include a first input end and a second input end, the first positive input end is coupled to the second input end of the first differential inductor, and the first negative input end is coupled to the first input end of the first differential inductor; the second positive input end is coupled to the first input end of the second differential inductor, and the second negative input end is coupled to the second input end of the second differential inductor.

[0067] The first differential inductor and the second differential inductor are spiral inductors with the same winding mode, and the magnetic field directions of the first differential inductor and the second differential inductor when working are opposite. For example, the spiral inductors formed by the winding modes of the differential inductors 110, 120, 130, or 140 shown in FIGS. 1, 2, 3, or 4. Figure 3 Or Figure 4

[0068] In the embodiments of the present application, the winding mode of the differential inductor is not limited, and only the first differential inductor and the second differential inductor are two spiral inductors with the same winding mode.

[0069] ​Optionally, the signal inputted by the first differential circuit and the signal inputted by the second differential circuit are quadrature signals.

[0070] Optionally, the signal inputted by the first differential circuit and the signal inputted by the second differential circuit are quadrature signals can be understood as the signal inputted by the first differential circuit and the signal inputted by the second differential circuit are 90° out of phase, i.e. one of the input signals of the first differential circuit and the second differential circuit is an I signal and the other is a Q signal, i.e. the phase of the input signal of one of the first differential circuit and the second differential circuit is 0° or 180° and the phase of the input signal of the other is 90° or 270°. For example, the phase of the signal inputted by the first positive input terminal of the first differential circuit is 0°, the phase of the signal inputted by the first negative input terminal of the first differential circuit is 180°, the phase of the signal inputted by the second positive input terminal of the second differential circuit is 90°, and the phase of the signal inputted by the second negative input terminal of the second differential circuit is 270°. For another example, the phase of the signal inputted by the first positive input terminal of the first differential circuit is 90°, the phase of the signal inputted by the first negative input terminal of the first differential circuit is 270°, the phase of the signal inputted by the second positive input terminal of the second differential circuit is 0°, and the phase of the signal inputted by the second negative input terminal of the second differential circuit is 180°.

[0071] Optionally, when the signal is inputted to the first differential circuit by the first positive input terminal, the signal runs in the first direction in the first differential inductor; when the signal is inputted to the second differential circuit by the second positive input terminal, the signal runs in the second direction in the second differential inductor, and the second direction is opposite to the first direction.

[0072] Optionally, the above-mentioned signal can be a current.

[0073] Optionally, the first differential circuit further comprises a first positive output terminal and a first negative output terminal; the second differential circuit further comprises a second positive output terminal and a second negative output terminal; the first differential inductor further comprises a first output terminal of the first differential inductor and a second output terminal of the first differential inductor; the second differential inductor further comprises a first output terminal of the second differential inductor and a second output terminal of the second differential inductor; wherein the first output terminal of the first differential inductor is coupled to the first negative output terminal, the second output terminal of the first differential inductor is coupled to the first positive output terminal, the first output terminal of the second differential inductor is coupled to the second positive output terminal, and the second output terminal of the second differential inductor is coupled to the second negative output terminal; the connection line between the first positive input terminal and the first negative output terminal is parallel to the connection line between the first negative input terminal and the first positive output terminal; and the connection line between the second positive input terminal and the second negative output terminal is parallel to the connection line between the second negative input terminal and the second positive output terminal.

[0074] Optionally, the first differential circuit in the filter circuit can further include a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, wherein one end of the first capacitor is grounded, and the other end is connected with the first positive input end of the first differential circuit; one end of the second capacitor is grounded, and the other end is connected with the first negative input end; one end of the third capacitor is grounded, and the other end is connected with the first negative output end; and one end of the fourth capacitor is grounded, and the other end is connected with the first positive output end. The second differential circuit in the filter circuit can further include a fifth capacitor, a sixth capacitor, a seventh capacitor and an eighth capacitor, wherein one end of the fifth capacitor is grounded, and the other end is connected with the second positive input end of the first differential circuit; one end of the sixth capacitor is grounded, and the other end is connected with the second negative input end; one end of the seventh capacitor is grounded, and the other end is connected with the second negative output end; and one end of the eighth capacitor is grounded, and the other end is connected with the second positive output end.

[0075] For example, Figure 5is a structural schematic diagram of the filter circuit 500. Wherein, the first differential circuit can be 510, in the first differential circuit 510, the first positive input end can be 1, the first negative input end can be 2, the first positive output end can be 6, and the first negative output end can be 5; the first input end of the first differential inductor can be 1', the second input end of the first differential inductor can be 2', the first output end of the first differential inductor can be 5', and the second output end of the first differential inductor can be 6'; the first capacitor can be C1, the second capacitor can be C1', the third capacitor can be C2, and the fourth capacitor can be C2'; the connection line between the first positive input end 1 and the first negative output end 5 is parallel to the connection line between the first negative input end 2 and the first positive output end 6; one end of the first capacitor C1 is grounded, and the other end is connected with the first positive input end 1 of the first differential circuit 510; one end of the second capacitor C1' is grounded, and the other end is connected with the first negative input end 2; one end of the third capacitor C2 is grounded, and the other end is connected with the first negative output end 5, and one end of the fourth capacitor C2' is grounded, and the other end is connected with the first positive output end 6; the first positive input end 1 is connected with the second input end 2' of the first differential inductor, the first negative input end 2 is connected with the first input end 1' of the first differential inductor, the second output end 6' of the first differential inductor is connected with the first positive output end 6, and the first output end 5' of the first differential inductor is connected with the first negative output end 5. The second differential circuit can be 520, in the second differential circuit 520, the second positive input end can be 3, the second negative input end can be 4, the second positive output end can be 8, and the second negative output end can be 7; the first input end of the second differential inductor can be 3', the second input end of the second differential inductor can be 4', the first output end of the second differential inductor can be 7', and the second output end of the second differential inductor can be 8'; the connection line between the second positive input end 3 and the second negative output end 7 is parallel to the connection line between the second negative input end 4 and the second positive output end 8; one end of the fifth capacitor C3 is grounded, and the other end is connected with the second positive input end 3; one end of the sixth capacitor C3' is grounded, and the other end is connected with the second negative input end 4; one end of the seventh capacitor C4 is grounded, and the other end is connected with the second negative output end 7, and one end of the eighth capacitor C4' is grounded, and the other end is connected with the second positive output end 8; the second positive input end 3 is connected with the first input end 3' of the second differential inductor, and the second negative input end 4 is connected with the second input end 4' of the second differential inductor; the first output end 7' of the second differential inductor is connected with the second positive output end 8, and the second output end 8' of the second differential inductor is connected with the second negative output end 7. When the signals are input to the first differential circuit 510 and the second differential circuit 520 respectively, the direction A of the signal in the first differential inductor 110 and the direction B of the signal in the second differential inductor 120 are opposite.

[0076] By the connection mode of the first differential inductor and the input and output terminals of the first differential circuit, and the connection mode of the second differential inductor and the input and output terminals of the second differential circuit, when the first positive input terminal and the first negative input terminal of the first differential circuit, and the second positive input terminal and the second negative input terminal of the second differential circuit input signals respectively, the flow directions of the currents in the first differential inductor and the second differential inductor are opposite, so according to the right-hand rule, the directions of the magnetic fields formed by the first differential inductor and the second differential inductor are opposite, and then the magnetic fields formed by the first differential inductor and the second differential inductor will cancel each other out, thereby reducing the influence of the first differential inductor and the second differential inductor on each other and on the surrounding circuit devices, thereby improving the isolation of the first differential circuit and the second differential circuit, and the isolation can exceed the first threshold value, which can be 20dB, that is, by the technical solution of the present application, the isolation of two differential inductors in a single channel can be improved, or the isolation of two adjacent differential inductors in adjacent two channels in a multi-channel can be improved.

[0077] Optionally, the first differential circuit in the above filter circuit can further include a third differential inductor, a ninth capacitor and a tenth capacitor, and the second differential circuit can further include a fourth differential inductor, an eleventh capacitor and a twelfth capacitor. The third differential inductor and the fourth differential inductor each include the same first input terminal and second input terminal, and the third differential inductor and the fourth differential inductor each include the same first output terminal and second output terminal. The first differential inductor, the second differential inductor, the third differential inductor and the fourth differential inductor are spiral inductors with the same winding mode.

[0078] Hereinafter, the three connection modes between the elements in the above filter circuit are described in detail.

[0079] In the first differential circuit, a connection between the first positive input terminal and the first negative output terminal is parallel to a connection between the first negative input terminal and the first positive output terminal; a connection between a first output terminal of the first differential inductor and a first input terminal of the third differential inductor is parallel to a connection between a second output terminal of the first differential inductor and a second input terminal of the third differential inductor; a connection between a first output terminal of the third differential inductor and the first negative output terminal is parallel to a connection between a second output terminal of the third differential inductor and the first positive output terminal; one end of the first capacitor is grounded, and the other end is connected to the first positive input terminal of the first differential circuit; one end of the second capacitor is grounded, and the other end is connected to the first negative input terminal; one end of the third capacitor is grounded, and the other end is connected to the first negative output terminal; one end of the fourth capacitor is grounded, and the other end is connected to the first positive output terminal; one end of the ninth capacitor is grounded, and the other end is connected to the first input terminal of the third differential inductor; one end of the tenth capacitor is grounded, and the other end is connected to the second input terminal of the third differential inductor; the first positive input terminal is coupled to the second input terminal of the first differential inductor; the first negative input terminal is coupled to the first input terminal of the first differential inductor; the first output terminal of the first differential inductor is coupled to the first input terminal of the third differential inductor; the second output terminal of the first differential inductor is coupled to the second input terminal of the third differential inductor; the second output terminal of the third differential inductor is coupled to the first positive output terminal; and the first output terminal of the third differential inductor is coupled to the first negative output terminal. In the second differential circuit, a connection between the second positive input terminal and the second negative output terminal is parallel to a connection between the second negative input terminal and the second positive output terminal; a connection between a first output terminal of the second differential inductor and a first input terminal of the fourth differential inductor is parallel to a connection between a second output terminal of the second differential inductor and a second input terminal of the fourth differential inductor; a connection between a first output terminal of the fourth differential inductor and the first negative output terminal is parallel to a connection between a second output terminal of the fourth differential inductor and the first positive output terminal; one end of the fifth capacitor is grounded, and the other end is connected to the second positive input terminal; one end of the sixth capacitor is grounded, and the other end is connected to the second negative output terminal; one end of the seventh capacitor is grounded, and the other end is connected to the second negative output terminal; one end of the eighth capacitor is grounded, and the other end is connected to the second positive output terminal; one end of the eleventh capacitor is grounded, and the other end is connected to the first input terminal of the fourth differential inductor; one end of the twelfth capacitor is grounded, and the other end is connected to the second input terminal of the fourth differential inductor; the second positive input terminal is coupled to the first input terminal of the second differential inductor; the second negative input terminal is coupled to the second input terminal of the second differential inductor; the first output terminal of the second differential inductor is coupled to the second input terminal of the fourth differential inductor; the second output terminal of the second differential inductor is coupled to the first input terminal of the fourth differential inductor; the first output terminal of the fourth differential inductor is coupled to the second negative output terminal; and the second output terminal of the fourth differential inductor is coupled to the second positive output terminal.

[0080] Optionally, the distance between the third differential inductance and the fourth differential inductance is less than or equal to a target distance.

[0081] The target distance is a preset distance value.

[0082] The distance between the third differential inductance and the fourth differential inductance being less than or equal to a target distance can be understood as the third differential inductance and the fourth differential inductance being two differential inductances that are set adjacent enough.

[0083] In the case that the third differential inductance and the fourth differential inductance are set adjacent enough, the third differential inductance and the fourth differential inductance are in the magnetic field range of each other, so that the magnetic fields generated by the third differential inductance and the fourth differential inductance when working cancel each other out.

[0084] Optionally, the first differential circuit and the second differential circuit can be two differential circuits that are set adjacent and in parallel in a single transmission channel (i.e., the same transmission channel). Alternatively, the first differential circuit and the second differential circuit can also be two differential circuits that are set adjacent and in parallel in adjacent channels in multiple transmission channels (i.e., different transmission channels). It can be understood that the two differential circuits that are set adjacent and in parallel are two differential circuits between which no other circuits or elements are arranged.

[0085] It can be understood that the third differential inductance and the fourth differential inductance described above can be two differential inductances whose distance in the same channel is less than or equal to a target distance. Alternatively, the third differential inductance and the fourth differential inductance described above can also be two differential inductances whose distance in adjacent channels is less than or equal to a target distance.

[0086] The first differential inductance, the second differential inductance, the third differential inductance, and the fourth differential inductance are spiral inductances of the same winding mode, and the magnetic field lines of the first differential inductance and the second differential inductance when working are in opposite directions.

[0087] In the embodiments of the present application, the winding mode of the differential inductance is not limited, as long as the first differential inductance, the second differential inductance, the third differential inductance, and the fourth differential inductance are spiral inductances of the same winding mode.

[0088] Optionally, when the signal is input from the first positive input end to the first differential circuit, the signal in the first differential inductance is in a first direction A, and the signal in the third differential inductance is in the first direction A; when the signal is input from the second positive input end to the second differential circuit, the signal in the second differential inductance is in a second direction B, and the signal in the fourth differential inductance is in the first direction A, the second direction B and the first direction A being opposite.

[0089] Optionally, the signal can be a current.

[0090] For example, Figure 6is another structural diagram of the filter circuit 600. Wherein the first differential circuit can be 610, in the first differential circuit 610, the first differential inductance can be 110, the third differential inductance can be 130, the first positive input end can be 1, the first negative input end can be 2, the first positive output end can be 6, and the first negative output end can be 5; The first input end of the first differential inductance can be 11, the second input end of the first differential inductance can be 12, the first output end of the first differential inductance can be 13, and the second output end of the first differential inductance can be 14, the first input end of the third differential inductance can be 31, the second input end of the third differential inductance can be 32, the first output end of the third differential inductance can be 33, and the second output end of the third differential inductance can be 34; The first capacitor can be C1, the second capacitor can be C1', the third capacitor can be C2, the fourth capacitor can be C2', the ninth capacitor can be C5, and the tenth capacitor can be C5'; The connection line between the first positive input end 1 and the first negative output end 5 is parallel to the connection line between the first negative input end 2 and the first positive output end 6, the connection line between the second output end 14 of the first differential inductance and the second input end 32 of the third differential inductance is parallel to the connection line between the second output end 13 of the first differential inductance and the first input end 31 of the third differential inductance, the connection line between the first output end 33 of the third differential inductance and the first negative output end 5 is parallel to the connection line between the second output end 34 of the third differential inductance and the first positive output end 6, and one end of the first capacitor C1 is connected with the first positive input end 1 of the first differential circuit 610; One end of the second capacitor C1' is grounded, and the other end is connected with the first negative input end 2; One end of the third capacitor C2 is grounded, and the other end is connected with the first negative output end 5, one end of the fourth capacitor C2' is grounded, and the other end is connected with the first positive output end 6; One end of the ninth capacitor C5 is grounded, and the other end is connected with the first input end 31 of the third differential inductance, one end of the tenth capacitor C5' is grounded, and the other end is connected with the second input end 32 of the third differential circuit; The first positive input end 1 is connected with the second input end 12 of the first differential inductance, the first negative input end 2 is connected with the first input end 11 of the first differential inductance, the first output end 13 of the first differential inductance is connected with the first input end 31 of the third differential inductance, the second output end 14 of the first differential inductance is connected with the second input end 32 of the third differential inductance, the second output end 34 of the third differential inductance is connected with the first positive output end 6, and the first output end 33 of the third differential inductance is connected with the first negative output end 5.The second differential circuit can be 620, in which the second differential inductor can be 120, the fourth differential inductor can be 140, the second positive input end can be 3, the second negative input end can be 4, the second positive output end can be 8, and the second negative output end can be 7; the first input end of the second differential inductor can be 21, the second input end of the second differential inductor can be 22, the first output end of the second differential inductor can be 23, and the second output end of the second differential inductor can be 24; the first input end of the fourth differential inductor can be 41, the second input end of the fourth differential inductor can be 42, the first output end of the fourth differential inductor can be 43, and the second output end of the fourth differential inductor can be 44; the fifth capacitor can be C3, the sixth capacitor can be C3', the seventh capacitor can be C4, the eighth capacitor can be C4', the eleventh capacitor can be C6, and the twelfth capacitor can be C6'; a wire between the second positive input end 3 and the second negative output end 7 is parallel to a wire between the second negative input end 4 and the second positive output end 8, a wire between the second output end 24 of the second differential inductor and the second input end 42 of the fourth differential inductor is parallel to a wire between the first output end 23 of the second differential inductor and the first input end 41 of the fourth differential inductor, a wire between the first output end 43 of the fourth differential inductor and the first negative output end 7 is parallel to a wire between the second output end 44 of the fourth differential inductor and the second positive output end 8, and one end of the fifth capacitor C3 is grounded and the other end is connected to the second positive input end 3; one end of the sixth capacitor C3' is grounded and the other end is connected to the second negative input end 4; one end of the seventh capacitor C4 is grounded and the other end is connected to the second negative output end 7, one end of the eighth capacitor C4' is grounded and the other end is connected to the second positive output end 8; one end of the eleventh capacitor C6 is grounded and the other end is connected to the first input end 41 of the fourth differential inductor; one end of the twelfth capacitor C6' is grounded and the other end is connected to the second input end 42 of the fourth differential inductor; the second positive input end 3 is connected to the first input end 21 of the second differential inductor, the second negative input end 4 is connected to the second input end 22 of the second differential inductor, the first output end 23 of the second differential inductor is connected to the second input end 42 of the fourth differential inductor, the second output end 24 of the second differential inductor is connected to the first input end 41 of the fourth differential inductor, the second output end 44 of the fourth differential inductor is connected to the first positive output end 8, and the first output end 43 of the fourth differential inductor is connected to the first negative output end 7. When signals are input to the first differential circuit 610 and the second differential circuit 620 respectively, the direction A of the signal in the first differential inductor 110 is opposite to the direction B of the signal in the second differential inductor 120.

[0091] By, for example, Figure 6The connection mode of the first differential inductor 110 and the input and output terminals of the first differential circuit 610, and the connection mode of the second differential inductor 120 and the input and output terminals of the second differential circuit 620, when the first positive input terminal 1 and the first negative input terminal 2 of the first differential circuit 610, and the second positive input terminal 3 and the second negative input terminal 4 of the second differential circuit 620 input signals respectively, the flow direction of the current in the first differential inductor 110 and the current in the second differential inductor 120 is opposite, so according to the right-hand rule, the magnetic field direction formed by the first differential inductor 110 and the magnetic field direction formed by the second differential inductor 120 are opposite, and then the magnetic fields formed by the first differential inductor 110 and the second differential inductor 120 will cancel each other out, and then reduce the influence between the first differential inductor 110 and the second differential inductor 120 and the influence on the surrounding circuit devices, so as to improve the isolation between the first differential inductor 110 and the second differential inductor 120, and the isolation can exceed the first threshold value, which can be 20dB, that is, through the technical solution of the present application, the isolation of two differential inductors in a single channel can be improved, or the isolation of two adjacent differential inductors in adjacent two channels in a multi-channel can be improved.

[0092] In the first differential circuit, a connection line between the first positive input terminal and the first positive output terminal is parallel to a connection line between the first negative input terminal and the first negative output terminal; a connection line between the first output terminal of the first differential inductor and the first input terminal of the third differential inductor is parallel to a connection line between the second output terminal of the first differential inductor and the second input terminal of the third differential inductor; a connection line between the first output terminal of the third differential inductor and the first positive output terminal is parallel to a connection line between the second output terminal of the third differential inductor and the first negative output terminal; one end of the first capacitor is grounded, and the other end is connected to the first positive input terminal of the first differential circuit; one end of the second capacitor is grounded, and the other end is connected to the first negative input terminal; one end of the third capacitor is grounded, and the other end is connected to the first positive output terminal; one end of the fourth capacitor is grounded, and the other end is connected to the first negative output terminal; one end of the ninth capacitor is grounded, and the other end is connected to the first input terminal of the third differential inductor; one end of the tenth capacitor is grounded, and the other end is connected to the second input terminal of the third differential inductor; the first positive input terminal is coupled to the second input terminal of the first differential inductor; the first negative input terminal is coupled to the first input terminal of the first differential inductor; the first output terminal of the first differential inductor is coupled to the first input terminal of the third differential inductor; the second output terminal of the first differential inductor is coupled to the second input terminal of the third differential inductor; the second output terminal of the third differential inductor is coupled to the first positive output terminal; and the first output terminal of the third differential inductor is coupled to the first negative output terminal. In the second differential circuit, a connection line between the second positive input terminal and the second positive output terminal is parallel to a connection line between the second negative input terminal and the second negative output terminal; a connection line between the first output terminal of the second differential inductor and the first input terminal of the fourth differential inductor is parallel to a connection line between the second output terminal of the second differential inductor and the second input terminal of the fourth differential inductor; a connection line between the first output terminal of the fourth differential inductor and the first negative output terminal is parallel to a connection line between the second output terminal of the fourth differential inductor and the second positive output terminal; one end of the fifth capacitor is grounded, and the other end is connected to the second positive input terminal; one end of the sixth capacitor is grounded, and the other end is connected to the second negative output terminal; one end of the seventh capacitor is grounded, and the other end is connected to the second positive output terminal; one end of the eighth capacitor is grounded, and the other end is connected to the second negative output terminal; one end of the eleventh capacitor is grounded, and the other end is connected to the second input terminal of the fourth differential inductor; one end of the twelfth capacitor is grounded, and the other end is connected to the first input terminal of the fourth differential inductor; the second positive input terminal is coupled to the first input terminal of the second differential inductor; the second negative input terminal is coupled to the second input terminal of the second differential inductor; the first output terminal of the second differential inductor is coupled to the first input terminal of the fourth differential inductor; the second output terminal of the second differential inductor is coupled to the second input terminal of the fourth differential inductor; the first output terminal of the fourth differential inductor is coupled to the second positive output terminal; and the second output terminal of the fourth differential inductor is coupled to the second negative output terminal.

[0093] Optionally, the distance between the third differential inductance and the fourth differential inductance is less than or equal to the target distance.

[0094] The target distance is a preset distance value.

[0095] The distance between the third differential inductance and the fourth differential inductance being less than or equal to the target distance can be understood as that the third differential inductance and the fourth differential inductance are two differential inductances arranged adjacent to each other.

[0096] In the case that the third differential inductance and the fourth differential inductance are arranged adjacent to each other, the third differential inductance and the fourth differential inductance are in the magnetic field range of each other, so that the magnetic fields generated by the third differential inductance and the fourth differential inductance when working cancel each other out.

[0097] Optionally, the first differential circuit and the second differential circuit can be two differential circuits arranged adjacent to each other in a single transmission channel (i.e., the same transmission channel). Alternatively, the first differential circuit and the second differential circuit can also be two differential circuits arranged adjacent to each other in adjacent channels in a multi-transmission channel (i.e., different transmission channels). It can be understood that the two differential circuits arranged adjacent to each other are two parallel differential circuits without other circuits or elements arranged therebetween.

[0098] It can be understood that the third differential inductance and the fourth differential inductance can be two differential inductances with a distance between the two differential inductances in the same channel being less than or equal to the target distance. Alternatively, the third differential inductance and the fourth differential inductance can also be two differential inductances with a distance between the two differential inductances in adjacent channels being less than or equal to the target distance.

[0099] When the first differential inductance, the second differential inductance, the third differential inductance, and the fourth differential inductance are spiral inductances with the same winding mode, the directions of the magnetic lines of force when the first differential inductance and the second differential inductance work are opposite, and the directions of the magnetic lines of force when the third differential inductance and the fourth differential inductance work are opposite.

[0100] In the embodiments of the present application, the winding mode of the differential inductance is not limited, and only the first differential inductance, the second differential inductance, the third differential inductance, and the fourth differential inductance are spiral inductances with the same winding mode.

[0101] Optionally, when the signal is input from the first positive input end to the first differential circuit, the signal in the first differential inductance is in the first direction A, and the signal in the third differential inductance is in the first direction A; when the signal is input from the second positive input end to the second differential circuit, the signal in the second differential inductance is in the second direction B, and the signal in the fourth differential inductance is in the first direction B, the second direction B and the first direction A being opposite.

[0102] Optionally, the above-mentioned signal can be an electric current.

[0103] For another example, Figure 7is another structural diagram of the filter circuit 700. Wherein the first differential circuit can be 710, in the first differential circuit 710, the first differential inductor can be 110, the third differential inductor can be 130, the first positive input end can be 1, the first negative input end can be 2, the first positive output end can be 5, the first negative output end can be 6; The first input end of the first differential inductor can be 11, the second input end of the first differential inductor can be 12, the first output end of the first differential inductor can be 13 and the second output end of the first differential inductor can be 14, the first input end of the third differential inductor can be 31, the second input end of the third differential inductor can be 32, the first output end of the third differential inductor can be 33, and the second output end of the third differential inductor can be 34; The first capacitor can be C1, the second capacitor can be C1', the third capacitor can be C2, the fourth capacitor can be C2', the ninth capacitor can be C5, and the tenth capacitor can be C5'; The connection line between the first positive input end 1 and the first positive output end 5 is parallel to the connection line between the first negative input end 2 and the first negative output end 6, the connection line between the first output end 13 of the first differential inductor and the first input end 31 of the third differential inductor is parallel to the connection line between the second output end 14 of the first differential inductor and the second input end 32 of the third differential inductor, the connection line between the first output end 33 of the third differential inductor and the first positive output end 5 is parallel to the connection line between the second output end 34 of the third differential inductor and the first negative output end 6, and one end of the first capacitor C1 is grounded, and the other end is connected with the first positive input end 1; One end of the second capacitor C1' is grounded, and the other end is connected with the first negative input end 2; One end of the third capacitor C2 is grounded, and the other end is connected with the first positive output end 5, one end of the fourth capacitor C2' is grounded, and the other end is connected with the first negative output end 6; One end of the ninth capacitor C5 is grounded, and the other end is connected with the first input end 31 of the third differential inductor, one end of the tenth capacitor C5' is grounded, and the other end is connected with the second input end 32 of the third differential circuit; The first positive input end 1 is connected with the second input end 12 of the first differential inductor, the first negative input end 2 is connected with the first input end 11 of the first differential inductor, the first output end 13 of the first differential inductor is connected with the first input end 31 of the third differential inductor, the second output end 14 of the first differential inductor is connected with the second input end 32 of the third differential inductor, the second output end 34 of the third differential inductor is connected with the first positive output end 5, and the first output end 33 of the third differential inductor is connected with the first negative output end 6.The second differential circuit can be 720, in which the second differential inductor can be 120, the fourth differential inductor can be 140, the second positive input end can be 3, the second negative input end can be 4, the second positive output end can be 7, and the second negative output end can be 8; the first input end of the second differential inductor can be 21, the second input end of the second differential inductor can be 22, the first output end of the second differential inductor can be 23, and the second output end of the second differential inductor can be 24; the first input end of the fourth differential inductor can be 41, the second input end of the fourth differential inductor can be 42, the first output end of the fourth differential inductor can be 43, and the second output end of the fourth differential inductor can be 44; the fifth capacitor can be C3, the sixth capacitor can be C3', the seventh capacitor can be C4, the eighth capacitor can be C4', the eleventh capacitor can be C6, and the twelfth capacitor can be C6'; the connection line between the second positive input end 3 and the second positive output end 7 is parallel to the connection line between the second negative input end 4 and the second negative output end 8, the connection line between the first output end 23 of the second differential inductor and the first input end 41 of the fourth differential inductor is parallel to the connection line between the second output end 24 of the second differential inductor and the second input end 42 of the fourth differential inductor, the connection line between the first output end 43 of the fourth differential inductor and the second positive output end 7 is parallel to the connection line between the second output end 44 of the fourth differential inductor and the second negative output end 8, and one end of the fifth capacitor C3 is grounded and the other end is connected to the second positive input end 3; one end of the sixth capacitor C3' is grounded and the other end is connected to the second negative input end 4; one end of the seventh capacitor C4 is grounded and the other end is connected to the second positive output end 7, one end of the eighth capacitor C4' is grounded and the other end is connected to the second negative output end 8; one end of the eleventh capacitor C6 is grounded, and the other end of the eleventh capacitor C6 is connected to the second input end 42 of the fourth differential inductor; one end of the twelfth capacitor C6' is grounded, and the other end of the twelfth capacitor C6' is connected to the first input end 41 of the fourth differential inductor; the second positive input end 3 is connected to the first input end 21 of the second differential inductor, the second negative input end 4 is connected to the second input end 22 of the second differential inductor, the first output end 23 of the second differential inductor is connected to the non-grounded end of the twelfth capacitor C6', the second output end 24 of the second differential inductor is connected to the non-grounded end of the eleventh capacitor C6, the second output end 44 of the fourth differential inductor is connected to the second negative output end 8, and the first output end 43 of the fourth differential inductor is connected to the second positive output end 7. When signals are input to the first differential circuit 710 and the second differential circuit 720 respectively, the direction A of the signal in the first differential inductor 110 is opposite to the direction B of the signal in the second differential inductor 120, and the direction A of the signal in the third differential inductor 130 is opposite to the direction B of the signal in the fourth differential inductor 140.

[0104] By, for example,Figure 7 The connection mode of the first differential inductor 110 and the input and output terminals of the first differential circuit 710, and the connection mode of the second differential inductor 120 and the input and output terminals of the second differential circuit 720, when the first positive input terminal 1 and the first negative input terminal 2 of the first differential circuit 710, and the second positive input terminal 3 and the second negative input terminal 4 of the second differential circuit 720 input signals respectively, the directions of the currents in the first differential inductor 110 and the second differential inductor 120 are opposite, so the directions of the magnetic fields formed by the first differential inductor 110 and the second differential inductor 120 are opposite, and the magnetic fields formed by the first differential inductor 110 and the second differential inductor 120 will cancel each other out, thereby reducing the influence of the first differential inductor 110 and the second differential inductor 120 on each other and on the surrounding circuit devices. At the same time, through the connection mode of the third differential inductor 130 and the input and output terminals of the first differential circuit 710, and the connection mode of the fourth differential inductor 140 and the input and output terminals of the second differential circuit 720 in the above implementation mode, the directions of the currents in the third differential inductor 130 and the fourth differential inductor 140 are opposite, so the directions of the magnetic fields formed by the third differential inductor 130 and the fourth differential inductor 140 are opposite, and the magnetic fields formed by the third differential inductor 130 and the fourth differential inductor 140 will cancel each other out, thereby reducing the influence of the third differential inductor 130 and the fourth differential inductor 140 on each other and on the surrounding circuit devices. Thus, the isolation between the first differential inductor 110 and the second differential circuit 120, and the isolation between the third differential inductor 130 and the fourth differential circuit 140 can be improved, and the isolation can exceed a first threshold value, which can be 20dB. That is, through the technical solution of the present application, the isolation between two adjacent differential inductors in a single channel can be improved, or the isolation between two adjacent differential inductors in two adjacent channels in a multi-channel can be improved.

[0105] In the first differential circuit, the connection between the first positive input terminal and the first positive output terminal is parallel to the connection between the first negative input terminal and the first negative output terminal; the connection between the first output terminal of the first differential inductor and the first input terminal of the third differential inductor is parallel to the connection between the second output terminal of the first differential inductor and the second input terminal of the third differential inductor; the connection between the first output terminal of the third differential inductor and the first positive output terminal is parallel to the connection between the second output terminal of the third differential inductor and the first negative output terminal; one end of the first capacitor is grounded, and the other end is connected to the first positive input terminal of the first differential circuit; one end of the second capacitor is grounded, and the other end is connected to the first negative input terminal; one end of the third capacitor is grounded, and the other end is connected to the first positive output terminal; one end of the fourth capacitor is grounded, and the other end is connected to the first negative output terminal; one end of the ninth capacitor is grounded, and the other end is connected to the second input terminal of the third differential inductor; one end of the tenth capacitor is grounded, and the other end is connected to the first input terminal of the third differential inductor; the first positive input terminal is coupled to the second input terminal of the first differential inductor; the first negative input terminal is coupled to the first input terminal of the first differential inductor; the first output terminal of the first differential inductor is coupled to the second input terminal of the third differential inductor; the second output terminal of the first differential inductor is coupled to the first input terminal of the third differential inductor; the second output terminal of the third differential inductor is coupled to the first negative output terminal; and the first output terminal of the third differential inductor is coupled to the first positive output terminal. In the second differential circuit, the connection between the second positive input terminal and the second positive output terminal is parallel to the connection between the second negative input terminal and the second negative output terminal; the connection between the first output terminal of the second differential inductor and the first input terminal of the fourth differential inductor is parallel to the connection between the second output terminal of the second differential inductor and the second input terminal of the fourth differential inductor; the connection between the first output terminal of the fourth differential inductor and the first positive output terminal is parallel to the connection between the second output terminal of the fourth differential inductor and the first negative output terminal; one end of the fifth capacitor is grounded, and the other end is connected to the second positive input terminal; one end of the sixth capacitor is grounded, and the other end is connected to the second negative output terminal; one end of the seventh capacitor is grounded, and the other end is connected to the second positive output terminal; one end of the eighth capacitor is grounded, and the other end is connected to the second negative output terminal; one end of the eleventh capacitor is grounded, and the other end is connected to the first input terminal of the fourth differential inductor; one end of the twelfth capacitor is grounded, and the other end is connected to the second input terminal of the fourth differential inductor; the second positive input terminal is coupled to the first input terminal of the second differential inductor; the second negative input terminal is coupled to the second input terminal of the second differential inductor; the first output terminal of the second differential inductor is coupled to the second input terminal of the fourth differential inductor; the second output terminal of the second differential inductor is coupled to the first input terminal of the fourth differential inductor; the first output terminal of the fourth differential inductor is coupled to the second negative output terminal; and the second output terminal of the fourth differential inductor is coupled to the second positive output terminal.

[0106] Optionally, the distance between the third differential inductance and the fourth differential inductance is less than or equal to a target distance.

[0107] The target distance is a preset distance value.

[0108] The distance between the third differential inductance and the fourth differential inductance being less than or equal to a target distance can be understood as the third differential inductance and the fourth differential inductance being two differential inductances arranged adjacent to each other.

[0109] In the case that the third differential inductance and the fourth differential inductance are arranged adjacent to each other, the third differential inductance and the fourth differential inductance are in the magnetic field range of each other, so that the magnetic fields generated by the third differential inductance and the fourth differential inductance when working cancel each other out.

[0110] Optionally, the first differential circuit and the second differential circuit can be two differential circuits arranged adjacent to each other in a single transmission channel (i.e., the same transmission channel). Alternatively, the first differential circuit and the second differential circuit can also be two differential circuits arranged adjacent to each other in adjacent channels in a multi-transmission channel (i.e., different transmission channels). It can be understood that the two differential circuits arranged adjacent to each other are two parallel differential circuits without other circuits or elements arranged therebetween.

[0111] It can be understood that the third differential inductance and the fourth differential inductance can be two differential inductances with a distance between them in the same channel being less than or equal to a target distance. Alternatively, the third differential inductance and the fourth differential inductance can also be two differential inductances with a distance between them in adjacent channels being less than or equal to a target distance.

[0112] When the first differential inductance and the second differential inductance work, the directions of the magnetic lines of force are opposite, and when the third differential inductance and the fourth differential inductance work, the directions of the magnetic lines of force are opposite.

[0113] In the embodiments of the present application, the winding mode of the differential inductance is not limited, as long as the first differential inductance, the second differential inductance, the third differential inductance and the fourth differential inductance are the same spiral inductance.

[0114] Optionally, when the signal is input from the first positive input end to the first differential circuit, the signal in the first differential inductance is in a first direction A, and the signal in the third differential inductance is in a first direction B; when the signal is input from the second positive input end to the second differential circuit, the signal in the second differential inductance is in a second direction B, and the signal in the fourth differential inductance is in the first direction A, the second direction B and the first direction A being opposite.

[0115] Optionally, the above-mentioned signal can be an electric current.

[0116] For another example, Figure 8is another structural diagram of the filter circuit 800. Wherein the first differential circuit can be 810, in the first differential circuit 810, the first differential inductor can be 110, the third differential inductor can be 130, the first positive input end can be 1, the first negative input end can be 2, the first positive output end can be 5, the first negative output end can be 6; The first input end of the first differential inductor can be 11, the second input end of the first differential inductor can be 12, the first output end of the first differential inductor can be 13 and the second output end of the first differential inductor can be 14, the first input end of the third differential inductor can be 31, the second input end of the third differential inductor can be 32, the first output end of the third differential inductor can be 33, the second output end of the third differential inductor can be 34; The first capacitor can be C1, the second capacitor can be C1', the third capacitor can be C2, the fourth capacitor can be C2', the ninth capacitor can be C5, and the tenth capacitor can be C5'; The line between the first positive input end 1 and the first positive output end 5 is parallel to the line between the first negative input end 2 and the first negative output end 6, the line between the first output end 13 of the first differential inductor and the first input end 31 of the third differential inductor is parallel to the line between the second output end 14 of the first differential inductor and the second input end 32 of the third differential inductor, the line between the first output end 33 of the third differential inductor and the first positive output end 5 is parallel to the line between the second output end 34 of the third differential inductor and the first negative output end 6, and one end of the first capacitor C1 is grounded, and the other end is connected with the first positive input end 1; One end of the second capacitor C1' is grounded, and the other end is connected with the first negative input end 2; One end of the third capacitor C2 is grounded, and the other end is connected with the first positive output end 5, one end of the fourth capacitor C2' is grounded, and the other end is connected with the first negative output end 6; One end of the ninth capacitor C5 is grounded, and the other end is connected with the second input end 32 of the third differential inductor, one end of the tenth capacitor C5' is grounded, and the other end is connected with the first input end 31 of the third differential circuit; The first positive input end 1 is connected with the second input end 12 of the first differential inductor, the first negative input end 2 is connected with the first input end 11 of the first differential inductor, the first output end 13 of the first differential inductor is connected with the second input end 32 of the third differential inductor, the second output end 14 of the first differential inductor is connected with the first input end 31 of the third differential inductor, the second output end 34 of the third differential inductor is connected with the first negative output end 6, and the first output end 33 of the third differential inductor is connected with the first positive output end 5.The second differential circuit can be 820, in which the second differential inductor can be 120, the fourth differential inductor can be 140, the second positive input end can be 3, the second negative input end can be 4, the second positive output end can be 7, and the second negative output end can be 8; the first input end of the second differential inductor can be 21, the second input end of the second differential inductor can be 22, the first output end of the second differential inductor can be 23, and the second output end of the second differential inductor can be 24; the first input end of the fourth differential inductor can be 41, the second input end of the fourth differential inductor can be 42, the first output end of the fourth differential inductor can be 43, and the eighth output signal can be 44; the fifth capacitor can be C3, the sixth capacitor can be C3', the seventh capacitor can be C4, the eighth capacitor can be C4', the eleventh capacitor can be C6, and the twelfth capacitor can be C6'; a wire between the second positive input end 3 and the second positive output end 7 is parallel to a wire between the second negative input end 4 and the second negative output end 8, a wire between the first output end 23 of the second differential inductor and the first input end 41 of the fourth differential inductor is parallel to a wire between the second output end 24 of the second differential inductor and the second input end 42 of the fourth differential inductor, a wire between the first output end 43 of the fourth differential inductor and the second positive output end 7 is parallel to a wire between the second output end 44 of the fourth differential inductor and the second negative output end 8, and one end of the fifth capacitor C3 is grounded and the other end is connected to the second positive input end 3; one end of the sixth capacitor C3' is grounded and the other end is connected to the second negative input end 4; one end of the seventh capacitor C4 is grounded and the other end is connected to the second positive output end 7, one end of the eighth capacitor C4' is grounded and the other end is connected to the second negative output end 8; one end of the eleventh capacitor C6 is grounded and the other end is connected to the first input end 41 of the fourth differential inductor; one end of the twelfth capacitor C6' is grounded and the other end is connected to the second input end 42 of the fourth differential inductor; the second positive input end 3 is connected to the first input end 21 of the second differential inductor, the second negative input end 4 is connected to the second input end 22 of the second differential inductor, the first output end 23 of the second differential inductor is connected to the second input end 42 of the fourth differential inductor, the second output end 24 of the second differential inductor is connected to the first input end 41 of the fourth differential inductor, the second output end 44 of the fourth differential inductor is connected to the second positive output end 7, and the first output end 43 of the fourth differential inductor is connected to the second negative output end 8. When signals are input to the first differential circuit 810 and the second differential circuit 820 respectively, the direction A of the signal in the first differential inductor 110 is opposite to the direction B of the signal in the second differential inductor 120, and the direction B of the signal in the third differential inductor 130 is opposite to the direction A of the signal in the fourth differential inductor 140.

[0117] by means of Figure 8The connection mode of the first differential inductor 110 and the input and output ends of the first differential circuit 810, and the connection mode of the second differential inductor 120 and the input and output ends of the second differential circuit 820, when the first positive input end 1 and the first negative input end 2 of the first differential circuit 810, and the second positive input end 3 and the second negative input end 4 of the second differential circuit 820 input signals respectively, the directions of the currents in the first differential inductor 110 and the second differential inductor 120 are opposite, so that the directions of the magnetic fields formed by the first differential inductor 110 and the second differential inductor 120 are opposite, and then the magnetic fields formed by the first differential inductor 110 and the second differential inductor 120 will offset each other, thereby reducing the influence of the first differential inductor 110 and the second differential inductor 120 on each other and on the surrounding circuit devices. At the same time, through the connection mode of the third differential inductor 130 and the input and output ends of the first differential circuit 810, and the connection mode of the fourth differential inductor 140 and the input and output ends of the second differential circuit 820 in the above implementation mode, when the first positive input end 1 and the first negative input end 2 of the first differential circuit 810, and the second positive input end 3 and the second negative input end 4 of the second differential circuit 820 input signals respectively, the directions of the currents in the third differential inductor 130 and the fourth differential inductor 140 are opposite, so that the directions of the magnetic fields formed by the third differential inductor 130 and the fourth differential inductor 140 are opposite, and then the magnetic fields formed by the third differential inductor 130 and the fourth differential inductor 140 will offset each other, thereby reducing the influence of the third differential inductor 130 and the fourth differential inductor 140 on each other and on the surrounding circuit devices. Therefore, the isolation between the first differential inductor 110 and the second differential circuit 120, and the isolation between the third differential inductor 130 and the fourth differential circuit 140 can be improved, and the isolation can exceed a first threshold value, which can be 20dB. That is, through the technical solution of the present application, the isolation of two differential inductors in a single channel can be improved, or the isolation of two adjacent differential inductors in adjacent two channels in a multi-channel can be improved.

[0118] The application also provides another filter circuit, which comprises a first differential circuit and a second differential circuit, the first differential circuit comprising a fifth differential inductor and a seventh differential inductor, and the second differential circuit comprising a sixth differential inductor and an eighth differential inductor. The seventh differential inductor and the eighth differential inductor work in opposite directions of magnetic lines.

[0119] Optionally, the distance between the fifth differential inductor and the sixth differential inductor is less than or equal to a target distance, and the distance between the seventh differential inductor and the eighth differential inductor is less than or equal to the target distance.

[0120] The target distance is a preset distance value.

[0121] The distance between the fifth differential inductor and the sixth differential inductor being less than or equal to the target distance can be understood as that the fifth differential inductor and the sixth differential inductor are two differential inductors arranged adjacent to each other. The distance between the seventh differential inductor and the eighth differential inductor being less than or equal to the target distance can be understood as that the seventh differential inductor and the eighth differential inductor are two differential inductors arranged adjacent to each other.

[0122] In the case that the seventh differential inductor and the eighth differential inductor are arranged adjacent to each other, the seventh differential inductor and the eighth differential inductor are in the magnetic field range of each other, so that the magnetic fields generated by the seventh differential inductor and the eighth differential inductor when working cancel each other out.

[0123] Optionally, the first differential circuit and the second differential circuit can be two differential circuits arranged adjacent to each other in a single transmission channel (i.e., the same transmission channel). Alternatively, the first differential circuit and the second differential circuit can also be two differential circuits arranged adjacent to each other in adjacent channels in multiple transmission channels (i.e., different transmission channels). It can be understood that the two differential circuits arranged adjacent to each other are that no other circuits or elements are arranged between the two parallel differential circuits.

[0124] It can be understood that the fifth differential inductor and the sixth differential inductor can be two differential inductors with a distance between the two differential inductors in the same channel being less than or equal to the target distance. Alternatively, the fifth differential inductor and the sixth differential inductor can also be two differential inductors with a distance between the two differential inductors in adjacent channels being less than or equal to the target distance.

[0125] It can be understood that the seventh differential inductor and the eighth differential inductor can be two differential inductors with a distance between the two differential inductors in the same channel being less than or equal to the target distance. Alternatively, the seventh differential inductor and the eighth differential inductor can also be two differential inductors with a distance between the two differential inductors in adjacent channels being less than or equal to the target distance.

[0126] Optionally, the first differential circuit includes a first positive input terminal and a first negative input terminal, the second differential circuit includes a second positive input terminal and a second negative input terminal, the fifth differential inductor, the sixth differential inductor, the seventh differential inductor and the eighth differential inductor are spiral inductors with the same winding mode, the fifth differential inductor, the sixth differential inductor, the seventh differential inductor and the eighth differential inductor each include a first input terminal and a second input terminal, the first positive input terminal is coupled to the second input terminal of the fifth differential inductor, and the first negative input terminal is coupled to the first input terminal of the fifth differential inductor; the second positive input terminal is coupled to the first input terminal of the sixth differential inductor, and the second negative input terminal is coupled to the second input terminal of the sixth differential inductor.

[0127] In the embodiments of the present application, the winding mode of the differential inductors is not limited, and only the fifth differential inductor, the sixth differential inductor, the seventh differential inductor and the eighth differential inductor are the same spiral inductor.

[0128] Optionally, the signal input by the first differential circuit and the signal input by the second differential circuit are quadrature signals.

[0129] The signal input by the first differential circuit and the signal input by the second differential circuit are quadrature signals can be understood as that the signal input by the first differential circuit and the signal input by the second differential circuit are 90° out of phase, that is, one of the input signals of the first differential circuit and the second differential circuit is an I signal, and the other is a Q signal, that is, the phase of the input signal of one of the first differential circuit and the second differential circuit is 0° or 180°, and the phase of the input signal of the other is 90° or 270°. For example, the phase of the signal input by the first positive input terminal of the first differential circuit is 0°, the phase of the signal input by the first negative input terminal of the first differential circuit is 180°, the phase of the signal input by the second positive input terminal of the second differential circuit is 90°, and the phase of the signal input by the second negative input terminal of the second differential circuit is 270°. For another example, the phase of the signal input by the first positive input terminal of the first differential circuit is 90°, the phase of the signal input by the first negative input terminal of the first differential circuit is 270°, the phase of the signal input by the second positive input terminal of the second differential circuit is 0°, and the phase of the signal input by the second negative input terminal of the second differential circuit is 180°.

[0130] Optionally, the first differential circuit can further include a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a twenty-first capacitor and a twenty-second capacitor. The second differential circuit further includes a seventeenth capacitor, an eighteenth capacitor, a nineteenth capacitor, a twentieth capacitor, a twenty-third capacitor and a twenty-fourth capacitor.

[0131] Optionally, in the first differential circuit, a connection between the first positive input end and the first negative output port is parallel to a connection between the first negative input end and the first positive output end; a connection between a first output end of the fifth differential inductor and a first input end of the seventh differential inductor is parallel to a connection between a second output end of the fifth differential inductor and a second input end of the seventh differential inductor; a connection between the first output end of the seventh differential inductor and the first negative output end is parallel to a connection between the second output end of the seventh differential inductor and the first positive output end; one end of the thirteenth capacitor is grounded, and the other end is connected to the first positive input end of the first differential circuit; one end of the fourteenth capacitor is grounded, and the other end is connected to the first negative input end; one end of the fifteenth capacitor is grounded, and the other end is connected to the first negative output end; one end of the sixteenth capacitor is grounded, and the other end is connected to the first positive output end; one end of the twenty-first capacitor is grounded, and the other end is connected to the first input end of the seventh differential inductor; one end of the twenty-second capacitor is grounded, and the other end is connected to the second input end of the seventh differential inductor; the first positive input end is coupled to the first input end of the fifth differential inductor; the first negative input end is coupled to the second input end of the fifth differential inductor; the first output end of the fifth differential inductor is coupled to the first input end of the seventh differential inductor; the second output end of the fifth differential inductor is coupled to the second input end of the seventh differential inductor; the second output end of the seventh differential inductor is coupled to the first negative output end; and the first output end of the seventh differential inductor is coupled to the first positive output end.In the second differential circuit, the connection between the second positive input end and the second negative output end is parallel to the connection between the second negative input end and the second positive output end; the connection between the first output end of the sixth differential inductor and the first input end of the eighth differential inductor is parallel to the connection between the second output end of the sixth differential inductor and the second input end of the eighth differential inductor; the connection between the first output end of the eighth differential inductor and the first negative output end is parallel to the connection between the second output end of the eighth differential inductor and the first positive output end; one end of the seventeenth capacitor is grounded, and the other end is connected to the second positive input end; one end of the eighteenth capacitor is grounded, and the other end is connected to the second negative output end; one end of the nineteenth capacitor is grounded, and the other end is connected to the second negative output end; one end of the twentieth capacitor is grounded, and the other end is connected to the second positive output end; one end of the twenty-third capacitor is grounded, and the other end is connected to the second input end of the eighth differential inductor; one end of the twenty-fourth capacitor is grounded, and the other end is connected to the first input end of the eighth differential inductor; the second positive input end is coupled to the first input end of the sixth differential inductor, and the second negative input end is coupled to the second input end of the sixth differential inductor; the first output end of the sixth differential inductor is coupled to the second input end of the eighth differential inductor, the second output end of the sixth differential inductor is coupled to the first input end of the eighth differential inductor, the first output end of the eighth differential inductor is coupled to the second negative output end, and the second output end of the eighth differential inductor is coupled to the second positive output end.

[0132] Optionally, when the signal is input to the first differential circuit by the first positive input end, the signal in the fifth differential inductor is in the first direction B, and the signal in the seventh differential inductor is in the first direction B; when the signal is input to the second differential circuit by the second positive input end, the signal in the sixth differential inductor is in the second direction B, and the signal in the eighth differential inductor is in the first direction A, the second direction B and the first direction A are opposite.

[0133] Optionally, the above-mentioned signal can be a current.

[0134] For example, Figure 9is another structural schematic diagram of the filter circuit 900. Wherein the first differential circuit can be 910, in the first differential circuit 910, the fifth differential inductor can be 110', the seventh differential inductor can be 130', the first positive input end can be 1, the first negative input end can be 2, the first positive output end can be 6, the first negative output end can be 5; The first input end of the fifth differential inductor can be 11', the second input end of the fifth differential inductor can be 12', the first output end of the fifth differential inductor can be 13', the second output end of the fifth differential inductor can be 14', the first input end of the seventh differential inductor can be 31', the second input end of the seventh differential inductor can be 32', the first output end of the seventh differential inductor can be 33', the second output end of the seventh differential inductor can be 34'; The thirteenth capacitor can be C1, the fourteenth capacitor can be C1', the fifteenth capacitor can be C2, the sixteenth capacitor can be C2', the twenty-first capacitor can be C5, the twenty-second capacitor can be C5'; The connection between the first positive input end 1 and the first negative output end 5 is parallel to the connection between the first negative input end 2 and the first positive output end 6, the connection between the first output end 13' of the fifth differential inductor and the first input end 31' of the seventh differential inductor is parallel to the connection between the second output end 14' of the fifth differential inductor and the second input end 32' of the seventh differential inductor, the connection between the first output end 33' of the seventh differential inductor and the first negative output end 5 is parallel to the connection between the second output end 34' of the seventh differential inductor and the first positive output end 6, and one end of the thirteenth capacitor C1 is grounded, and the other end is connected with the first positive input end 1; One end of the fourteenth capacitor C1' is grounded, and the other end is connected with the first negative input end 2; One end of the fifteenth capacitor C2 is grounded, and the other end is connected with the first negative output end 5, one end of the sixteenth capacitor C2' is grounded, and the other end is connected with the first positive output end 6; One end of the twenty-first capacitor C5 is grounded, and the other end is connected with the first input end 31' of the seventh differential inductor, one end of the twenty-second capacitor C5' is grounded, and the other end is connected with the second input end 32' of the third differential circuit; The first positive input end 1 is connected with the first input end 11 of the fifth differential inductor, the first negative input end 2 is connected with the second input end 12' of the fifth differential inductor, the first output end 13' of the fifth differential inductor is connected with the first input end 31' of the seventh differential inductor, the second output end 14' of the fifth differential inductor is connected with the second input end 32' of the seventh differential inductor, the second output end 34' of the seventh differential inductor is connected with the first negative output end 5, and the first output end 33' of the seventh differential inductor is connected with the first positive output end 6.The second differential circuit can be 920, in which the sixth differential inductor can be 120', the eighth differential inductor can be 140', the second positive input end can be 3, the second negative input end can be 4, the second positive output end can be 8, and the second negative output end can be 7; the first input end of the sixth differential inductor can be 21', the second input end of the sixth differential inductor can be 22', the first output end of the sixth differential inductor can be 23', and the second output end of the sixth differential inductor can be 24'; the first input end of the eighth differential inductor can be 41', the second input end of the eighth differential inductor can be 42', the first output end of the eighth differential inductor can be 43', and the eighth output signal can be 44'; the seventeenth capacitor can be C3, the eighteenth capacitor can be C3', the nineteenth capacitor can be C4, the twentieth capacitor can be C4', the twenty-third capacitor can be C6, and the twenty-fourth capacitor can be C6'; the connection line between the second positive input end 3 and the second negative output end 7 is parallel to the connection line between the second negative input end 4 and the second positive output end 8, the connection line between the first output end 23' of the sixth differential inductor and the first input end 41' of the eighth differential inductor is parallel to the connection line between the second output end 24' of the sixth differential inductor and the second input end 42' of the eighth differential inductor, the connection line between the first output end 43' of the eighth differential inductor and the second negative output end 7 is parallel to the connection line between the second output end 44' of the eighth differential inductor and the second positive output end 8, and one end of the seventeenth capacitor C3 is grounded and the other end is connected to the second positive input end 3; one end of the eighteenth capacitor C3' is grounded and the other end is connected to the second negative input end 4; one end of the nineteenth capacitor C4 is grounded and the other end is connected to the second negative output end 7, one end of the twentieth capacitor C4' is grounded and the other end is connected to the second positive output end 8; one end of the twenty-third capacitor C6 is grounded and the other end is connected to the second input end 42' of the eighth differential inductor; one end of the twenty-fourth capacitor C6' is grounded and the other end is connected to the first input end 41' of the eighth differential inductor; the second positive input end 3 is connected to the first input end 21' of the sixth differential inductor, the second negative input end 4 is connected to the second input end 22' of the sixth differential inductor, the first output end 23' of the sixth differential inductor is connected to the second input end 42' of the eighth differential inductor, the second output end 24' of the sixth differential inductor is connected to the first input end 41' of the eighth differential inductor, the second output end 44' of the eighth differential inductor is connected to the second positive output end 8, and the first output end 43' of the eighth differential inductor is connected to the second negative output end 7. When signals are input to the first differential circuit 910 and the second differential circuit 920 respectively, the direction B of the signal in the seventh differential inductor 130' is opposite to the direction A of the signal in the eighth differential inductor 140'.

[0135] By, for example, Figure 9The connection mode of the seventh differential inductor 130' and the input end and the output end of the first differential circuit 910, and the connection mode of the eighth differential inductor 140' and the input end and the output end of the second differential circuit 920, when the first positive input end 1 and the first negative input end 2 of the first differential circuit 910, and the second positive input end 3 and the second negative input end 4 of the second differential circuit 920 input signals respectively, the directions of the current in the seventh differential inductor 130' and the current in the eighth differential inductor 140' are opposite, so that the directions of the magnetic fields formed by the seventh differential inductor 130' and the eighth differential inductor 140' are opposite, and then the magnetic fields formed by the seventh differential inductor 130' and the eighth differential inductor 140' will offset each other, and then reduce the influence of the seventh differential inductor 130' and the eighth differential inductor 140' on each other and on the surrounding circuit devices. Thus, the isolation between the seventh differential inductor 130' and the eighth differential inductor 140' can be improved, and the isolation can exceed a first threshold value, which can be 20dB. That is, through the technical solution of the present application, the isolation between two adjacent differential inductors in a single channel can be improved, or the isolation between two adjacent differential inductors in two adjacent channels in a multi-channel can be improved.

[0136] The embodiment of the present application further provides an integrated circuit, which comprises the filter circuit as described above, and details are not described herein.

[0137] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A filter circuit, characterized by comprises a first positive input terminal and a first negative input terminal, and the second differential circuit comprises a second positive input terminal and a second negative input terminal, the first differential circuit comprises a first differential inductor, and the second differential circuit comprises a second differential inductor, the first differential inductor and the second differential inductor are spiral inductors of the same winding mode, the first differential inductor and the second differential inductor each comprise a same first input terminal and a same second input terminal, the first positive input terminal is coupled to the second input terminal of the first differential inductor, the first negative input terminal is coupled to the first input terminal of the first differential inductor, the second positive input terminal is coupled to the first input terminal of the second differential inductor, and the second negative input terminal is coupled to the second input terminal of the second differential inductor; magnetic field lines of the first differential inductor and the second differential inductor are in opposite directions when the first differential inductor and the second differential inductor are working; the first differential circuit and the second differential circuit are two differential circuits arranged in parallel in a single transmission channel, or the first differential circuit and the second differential circuit are two differential circuits arranged in parallel in adjacent channels in a multi-transmission channel.

2. The filter circuit of claim 1, wherein, the first differential inductor and the second differential inductor are in the magnetic field range of each other, so that the magnetic fields generated by the first differential inductor and the second differential inductor when working cancel each other out.

3. The filter circuit of claim 1, wherein, when a signal is input to the first differential circuit from the first positive input terminal, the signal travels in the first differential inductor in a first direction; when the signal is input to the second differential circuit from the second positive input terminal, the signal travels in the second differential inductor in a second direction, and the second direction is opposite to the first direction.

4. The filter circuit of claim 1, wherein, the first differential circuit further comprises a first positive output terminal and a first negative output terminal; the second differential circuit further comprises a second positive output terminal and a second negative output terminal; the first differential inductor and the second differential inductor each comprise a same first output terminal and a same second output terminal; the first output terminal of the first differential inductor is coupled to the first negative output terminal, the second output terminal of the first differential inductor is coupled to the first positive output terminal, the first output terminal of the second differential inductor is coupled to the second positive output terminal, and the second output terminal of the second differential inductor is coupled to the second negative output terminal; a connection line between the first positive input terminal and the first negative output terminal is parallel to a connection line between the first negative input terminal and the first positive output terminal; a connection line between the second positive input terminal and the second negative output terminal is parallel to a connection line between the second negative input terminal and the second positive output terminal.

5. The filter circuit according to any one of claims 1 to 4, characterized in that, a distance between the first differential inductor and the second differential inductor is less than or equal to a target distance.

6. The filter circuit of claim 1, wherein, signals input by the first differential circuit and signals input by the second differential circuit are quadrature signals.

7. An integrated circuit for a transmit channel, characterized by comprises: a digital-to-analog converter; a modulator; The filter circuit comprises a first differential circuit and a second differential circuit, the first differential circuit comprises a first positive input end and a first negative input end, the second differential circuit comprises a second positive input end and a second negative input end, The first differential circuit comprises a first differential inductor, and the second differential circuit comprises a second differential inductor, the first differential inductor and the second differential inductor are spiral inductors of the same winding mode, the first differential inductor and the second differential inductor each comprise the same first input end and second input end, the first positive input end is coupled to the second input end of the first differential inductor, the first negative input end is coupled to the first input end of the first differential inductor, the second positive input end is coupled to the first input end of the second differential inductor, and the second negative input end is coupled to the second input end of the second differential inductor. The magnetic field directions of the first differential inductor and the second differential inductor are opposite when they work. The first differential circuit and the second differential circuit are two differential circuits arranged in parallel in a single transmission channel, or the first differential circuit and the second differential circuit are two differential circuits arranged in parallel in adjacent channels in a multi-transmission channel.

8. The integrated circuit of claim 7, wherein, The first differential inductor and the second differential inductor are in the magnetic field range of each other, so that the magnetic fields generated by the first differential inductor and the second differential inductor cancel each other out when they work.

9. The integrated circuit of claim 7, wherein, When a signal is input to the first differential circuit from the first positive input end, the signal travels in the first differential inductor in a first direction. When the signal is input to the second differential circuit from the second positive input end, the signal travels in the second differential inductor in a second direction, and the second direction is opposite to the first direction.

10. The integrated circuit of claim 7, wherein, The first differential circuit further comprises a first positive output end and a first negative output end. The second differential circuit further comprises a second positive output end and a second negative output end. The first differential inductor and the second differential inductor each comprise the same first output end and second output end. The first output end of the first differential inductor is coupled to the first negative output end, the second output end of the first differential inductor is coupled to the first positive output end, the first output end of the second differential inductor is coupled to the second positive output end, and the second output end of the second differential inductor is coupled to the second negative output end. The connection line between the first positive input end and the first negative output port is parallel to the connection line between the first negative input end and the first positive output end. The connection line between the second positive input end and the second negative output end is parallel to the connection line between the second negative input end and the second positive output end.

11. The integrated circuit of any one of claims 7 to 10, wherein, The distance between the first differential inductor and the second differential inductor is less than or equal to a target distance.

12. The integrated circuit of claim 7, wherein, The signal input by the first differential circuit and the signal input by the second differential circuit are orthogonal signals.

13. A chip system, characterized by A filter circuit as claimed in any one of claims 1 to 6, or an integrated circuit for a transmit channel as claimed in any one of claims 7 to 12.

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