A data acquisition method, a data analysis method and related devices

Abstract

The application provides a data collection method, a data analysis method and related equipment, and the data collection device is applied to a chip system, the chip system comprises a plurality of data nodes; the data collection device comprises at least two data collection channels; one data collection channel comprises a plurality of data collection ends and a target data output end; one data collection end is connected with one data node; the target data output end outputs target data corresponding to the target data node collected by the target data collection end based on the target data node configured by the data collection channel; the target data node is any data node in the plurality of data nodes; wherein different data collection channels are configured with different target data nodes. Since the actual collected target data can more accurately reflect the performance of the chip system, the accuracy of the chip system performance analysis can be improved, and the chip design and chip product can be more reasonably optimized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, specifically to a data acquisition method, a data analysis method, and related equipment. Background Technology

[0002] As chip integration scales increase, the verification time for chip functions also lengthens, leading to longer chip development cycles. To shorten development cycles and reduce verification time, most current methods involve simulating and testing each functional module of the chip separately. Simulation testing of the entire chip is only used to test port connections and data paths, and does not involve extensive testing of the chip as a whole. While the performance of each functional module can be analyzed using simulation test data, and thus the overall chip performance can be determined, the accuracy of this overall chip performance analysis needs further improvement. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a data acquisition method, a data analysis method, and related equipment to improve the accuracy of overall chip performance analysis.

[0004] To address the above problems, embodiments of the present invention provide the following technical solutions:

[0005] The first aspect of the present invention provides a data acquisition device applied to a chip system, the chip system including multiple data nodes; the data acquisition device includes at least two data acquisition channels;

[0006] The data acquisition channel includes multiple data acquisition terminals and a target data output terminal; one data acquisition terminal is connected to one of the multiple data nodes.

[0007] A data acquisition channel includes multiple data acquisition terminals and a target data output terminal; each data acquisition terminal is connected to a data node, wherein the data corresponding to the data node can be acquired by the connected data acquisition terminal; the target data output terminal outputs the target data corresponding to the target data node acquired by the target data acquisition terminal based on the target data node configured in the data acquisition channel; the target data node is any data node among the multiple data nodes; the target data acquisition terminal is the data acquisition terminal among the multiple data acquisition terminals connected to the target data node;

[0008] Different data acquisition channels are configured with different target data nodes to output different target data.

[0009] A second aspect of the present invention provides a data acquisition method applied to a chip system, the chip system including multiple data nodes, the data acquisition method comprising:

[0010] Configure at least two data acquisition channels for the target data node. One data acquisition channel includes multiple data acquisition ends and a target data output end. One data acquisition end is connected to one data node. The target data node is any data node among the multiple data nodes.

[0011] For any data acquisition channel, based on the target data node configured for the data acquisition channel, the target data corresponding to the target data node acquired by the target data acquisition terminal is output through the target data output terminal; the target data acquisition terminal is the data acquisition terminal connected to the target data node among the plurality of data acquisition terminals;

[0012] Different data acquisition channels are configured with different target data nodes to output different target data.

[0013] A third aspect of the present invention provides a chip system including multiple data nodes and a data acquisition device as described in any of the preceding claims.

[0014] A fourth aspect of the present invention provides an electronic device including a chip system as described in any of the preceding claims.

[0015] A fifth aspect of the present invention provides a data analysis method applied to a chip system, the chip system including multiple data nodes, the data analysis method comprising:

[0016] Acquire basic analysis data, which includes data output from at least two data acquisition channels. The data includes target data corresponding to different target data nodes in the chip system. The target data node can be any data node among the plurality of data nodes. The data acquisition channels can acquire and output the target data corresponding to the configured target data nodes.

[0017] Based on the target data corresponding to the different target data nodes, perform corresponding performance analysis on the different target data nodes.

[0018] The data acquisition method, data analysis method, and related equipment provided in this invention configure at least two data acquisition channels in a chip system and target data nodes for each data acquisition channel. After acquiring target data corresponding to the configured target data nodes through the target data acquisition terminals of the data acquisition channels, the performance of the chip system is analyzed based on the actually acquired target data. Since the actually acquired target data more accurately reflects the overall performance of the chip system, the accuracy of the overall performance analysis of the chip system can be improved, thereby enabling more reasonable optimization of chip design and chip products. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0020] Figure 1 A schematic diagram of the structure of various functional modules of a chip system is shown.

[0021] Figure 2 This is a schematic diagram of the structure of a data acquisition device provided in one embodiment of the present invention;

[0022] Figure 3 A schematic diagram of the structure of a chip system provided in another embodiment of the present invention;

[0023] Figure 4 A schematic diagram of the structure of a data acquisition device provided in another embodiment of the present invention;

[0024] Figure 5 A timing diagram of data acquisition timing provided for one embodiment of the present invention;

[0025] Figure 6 A schematic diagram of the structure of a chip system and a data acquisition device provided in another embodiment of the present invention;

[0026] Figure 7 This is a schematic diagram of the structure of a data acquisition channel provided in one embodiment of the present invention;

[0027] Figure 8 A schematic diagram of the structure of a data acquisition channel provided in another embodiment of the present invention;

[0028] Figure 9 A flowchart illustrating a data acquisition method provided in one embodiment of the present invention;

[0029] Figure 10A flowchart of a data analysis method provided in one embodiment of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] The creation of a chip can be divided into two stages: design and manufacturing. In chip design, a hardware description language is first used to describe the chip circuitry as register-transfer level logic code. Then, simulation tools are used to verify the logic code. Next, synthesis tools convert the logic code into a gate-level circuit netlist, and finally, automatic placement and routing tools convert the netlist into the desired circuit routing structure. In chip manufacturing, the required chip is produced based on the circuit routing structure obtained from the chip design.

[0032] In the simulation and verification process of chip design, to shorten the verification time, each functional module of the chip design is simulated and tested separately to verify whether the function of each module is consistent with the expected function. Although the performance of each functional module can be analyzed through simulation test data, and the overall chip performance can be analyzed and the chip design optimized based on the analysis results, this analysis method has poor accuracy. Therefore, it cannot accurately analyze the overall chip performance and thus cannot reasonably optimize the chip design.

[0033] Figure 1 A schematic diagram of the structure of various functional modules of a chip system is shown. The chip system may include: a CPU (Central Processing Unit) module 11, a first logic control module 12, a level 1 cache module 13, a second logic control module 14, a level 2 cache module 15, and other modules (not shown in the figure).

[0034] Although the processing delay between two adjacent nodes of a functional module can be obtained through the simulation test data of any functional module, such as the processing delay between nodes A1 and A2 obtained through the simulation test data (such as simulation waveform) of the first logic control module 12, the overall performance of the chip system can be analyzed through the processing delay.

[0035] However, since the simulation process cannot completely and correctly simulate the behavior of the CPU module 11 and the L1 cache module 13, it cannot completely and correctly simulate the impact of the CPU module 11 and the L1 cache module 13 on the first logic control module 12. Therefore, it cannot completely and correctly obtain the simulation test data of the first logic control module 12, and consequently cannot completely and correctly obtain the processing delay of the A1 node and the A2 node, and consequently cannot completely and correctly analyze the overall performance of the chip system.

[0036] While it's possible to analyze chip system performance through simulation, the increasing scale of chip integration leads to significantly longer simulation times, often measured in months. This is extremely detrimental to chip system performance analysis. Furthermore, even after simulating the entire chip system, the resulting simulation data files are enormous, often inaccessible to most servers, making it impossible to analyze the overall chip system performance.

[0037] To address the aforementioned issues, this invention collects actual data from the chip system to accurately analyze the overall performance of the chip system, and then optimizes the chip design based on the analysis results.

[0038] Based on the above-described inventive concept, this invention provides a data acquisition device applied to a chip system for acquiring data from the chip system. The chip system includes multiple data nodes, and the data acquisition device includes at least two data acquisition channels. For example... Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of a data acquisition device provided in one embodiment of the present invention. The chip system includes multiple data nodes A. 11 To A 1N A 21 To A 2N A 31 To A 3N A 41 A 42 A 51 A 52 The data acquisition device includes data acquisition channels S1 to S2. M M and N are natural numbers greater than 1.

[0039] Each data acquisition channel includes multiple data acquisition terminals and a target data output terminal. Each data acquisition terminal connects to a data node in the chip system, and the data corresponding to the data node can be acquired by the connected data acquisition terminal. For example... Figure 2 As shown, the data acquisition channel S1 includes multiple data acquisition terminals B. 11 To B 1N B21 To B 2N B 31 To B 3N B 41 B 42 B 51 B 52 And the target data output terminal OUT1, and multiple data acquisition terminals B 11 To B 1N B 21 To B 2N B 31 To B 3N B 41 B 42 B 51 B 52 With multiple data nodes A 11 To A 1N A 21 To A 2N A 31 To A 3N A 41 A 42 A 51 A 52 Each corresponds to a separate connection. Data acquisition channel S M Includes multiple data acquisition terminals Y 11 To Y 1N Y 21 To Y 2N Y 31 To Y 3N Y 41 Y 42 Y 51 Y 52 and target data output terminal OUT M Furthermore, multiple data acquisition terminals Y 11 To Y 1N Y 21 To Y 2N Y 31 To Y 3N Y 41 Y 42 Y 51 Y 52 With multiple data nodes A 11 To A 1N A 21 To A 2N A 31 To A 3N A 41 A 42 A 51 A 52 Each corresponds to a separate connection.

[0040] Furthermore, the target data output terminal outputs the target data corresponding to the target data node acquired by the target data acquisition terminal, based on the target data node configured in the data acquisition channel. The target data node can be any data node among multiple data nodes, and the target data acquisition terminal is the data acquisition terminal connected to the target data node among multiple data acquisition terminals.

[0041] Assume that the target data node configured for data acquisition channel S1 is A. 11 Then data acquisition channel S1 passes through the target data acquisition terminal B. 11 Collect target data node A 11 The corresponding target data is obtained and output through the target data output terminal OUT1. The target data acquisition terminal B... 11 For the multiple data acquisition terminals of data acquisition channel S1, the target data node A is connected. 11 The data acquisition terminal.

[0042] Since each data acquisition channel is connected to multiple data nodes in the chip system, it can be configured to acquire data from any data node among these nodes. Each data acquisition channel can be configured with one or more target data nodes. However, to analyze the overall performance of the chip system, different data acquisition channels need to be configured with different target data nodes.

[0043] This invention provides an embodiment of a chip system that includes a data acquisition channel and a target data node configured for that channel. The target data corresponding to the configured target data node is acquired through the target data acquisition terminal of the data acquisition channel, allowing for performance analysis of the chip system based on the actual acquired target data. Since the actual acquired target data more accurately reflects the overall performance of the chip system, the accuracy of the overall chip system performance analysis is improved, leading to more reasonable optimization of chip design and products. Furthermore, this eliminates the need to generate waveform data for overall chip system performance analysis during simulation testing, significantly improving simulation testing efficiency.

[0044] It should be noted that in this embodiment of the invention, configuration information can be pre-stored in registers to configure target data nodes for the data acquisition channel according to the configuration information. Of course, the invention is not limited to this; in other embodiments, the data acquisition channel and target data nodes can be configured through other methods, such as inputting configuration commands, which will not be elaborated upon here.

[0045] In some embodiments of the present invention, such as Figure 3 As shown, Figure 3The schematic diagram of a chip system provided in another embodiment of the present invention is shown. The chip system includes multiple functional modules, including a CPU module 11, a first logic control module 12, a level 1 cache module 13, a second logic control module 14, and a level 2 cache module 15. Of course, the present invention is not limited to this. The chip system may also include a level 3 cache module and other modules, which will not be described in detail here.

[0046] The CPU module 11 includes multiple CPU cores, the first logic control module 12 includes multiple first logic control units, and the L1 cache module 13 includes multiple L1 cache units. The multiple CPU cores and multiple first logic control units are respectively configured to correspond to each other, and the multiple first logic control units and multiple L1 cache units are respectively configured to correspond to each other. The first logic control module 12 transmits data from the corresponding CPU core to the corresponding L1 cache unit, and transmits data from the corresponding L1 cache unit to the corresponding CPU core.

[0047] Based on this, multiple data nodes include: data nodes between functional modules, and / or data nodes within a functional module. For example... Figure 3 As shown, multiple data nodes include data node A between CPU module 11 and the first logic control module 12. 11 To A 1N Data node A between the first logic control module 12 and the first-level cache module 13 21 To A 2N Data node A between the first-level cache module 13 and the second logic control module 14 31 To A 3N Data node A between the second logic control module 14 and the second-level cache module 15 41 and A 42 Data node A between the secondary cache module 15 and other modules 51 and A 52 .

[0048] It should be noted that, Figure 3 The example described here only uses data nodes between functional modules, but it is not limited to this. In other embodiments, data nodes can also be data nodes within functional modules such as CPU module 11, first logic control module 12, first-level cache module 13, second logic control module 14, and second-level cache module 15.

[0049] It should also be noted that the data nodes in the embodiments of the present invention can be either data nodes for input data or data nodes for output data. For example... Figure 3 As shown, data node A 11 Data node A is the data node that outputs data from CPU module 11 to the first logic control module 12. 12The data node is for the first logic control module 12 to input data to the CPU module 11.

[0050] In some embodiments of the present invention, analyzing the performance of the chip system can specifically involve analyzing the data processing latency of the chip system. Analyzing the data processing latency requires collecting data from two data nodes on the same data transmission chain; that is, it requires configuring two target data nodes on the same data transmission chain for each of the two data acquisition channels.

[0051] like Figure 4 As shown, Figure 4 This is a schematic diagram of a data acquisition device provided in another embodiment of the present invention. The data acquisition device includes a first data acquisition channel S1 and a second data acquisition channel S2.

[0052] The first data acquisition channel S1 is configured with the first target data node A. 11 And by the first target data acquisition terminal B 11 Collect first target data node A 11 The corresponding first target data. The target data output terminal OUT1 of the first data acquisition channel S1 outputs the first target data acquisition terminal B. 11 The first target data collected.

[0053] The second data acquisition channel S2 is configured with the second target data node A. 21 And by the second target data acquisition terminal C 21 Collect data from the second target node A 21 The corresponding second target data. The target data output terminal OUT2 of the second data acquisition channel S2 outputs the second target data acquisition terminal C. 21 The second target data collected.

[0054] Among them, the first target data and the second target data are used to analyze the first target data node A. 11 Second target data node A 21 The data processing delay between them. Furthermore, the first target data node A... 11 Second target data node A 21 They are located on the same data transmission chain.

[0055] Based on the above embodiments, in some embodiments of the present invention, the data corresponding to the data node carries data acquisition time information. Furthermore, the data acquisition time information includes the data acquisition time of the target data, so as to analyze the first target data node A based on the difference between the data acquisition time of the first target data and the data acquisition time of the second target data. 11 Second target data node A 21The data processing delay is analyzed, and then the first target data node A is determined based on the analyzed data processing delay. 11 Second target data node A 21 The performance of the structure can be assessed to optimize the design and manufacture of the product.

[0056] However, since general chip systems lack a unified timer, it is difficult to standardize the data acquisition time for different target data. Therefore, in some embodiments of the present invention, the data acquisition time information includes a data acquisition timing time, which is combined with a timing offset time to obtain the data acquisition time.

[0057] In some embodiments of the present invention, the data acquisition timing refers to the time from the start of timing after the reset is canceled until the target data is acquired. Since each functional module of the chip system receives the reset cancellation command sequentially, and the time difference between the receipt of the reset cancellation command by each functional module is fixed, in some embodiments of the present invention, timing is performed with reference to the reset cancellation command or the reset cancellation time to obtain a standardized data acquisition time.

[0058] The reset / cancel command is used to control the resetting and restarting of various functional modules. Of course, this invention is not limited to this; in other embodiments, other commands may be used for timing, which will not be elaborated upon here.

[0059] Since the time difference between each functional module receiving the reset / cancel command is fixed, the timing offset time of each functional module or each data node is fixed. Therefore, the data acquisition time of the target data can be obtained based on the data acquisition timing time and timing offset time in the acquired target data.

[0060] In some embodiments of the present invention, the data acquisition timing can be obtained by setting timers at various functional modules or data nodes of the chip system. For example... Figure 5 As shown, Figure 5 This is a timing diagram for data acquisition timing provided in one embodiment of the present invention. Wherein, clk is the timing clock, t is one clock cycle, and data node A... 11 The corresponding timer, in the reset / cancel instruction A 11_reset After the level changes from low to high, the timing starts from 0. Data node A 11 The timing time is as follows: A 11_time As shown. Similarly, data node A 21 The corresponding timer, in the reset / cancel instruction A 21_reset After the level changes from low to high, the timing starts from 0. Data node A 21 The timing time is as follows: A21_time As shown. Data Node A 31 The corresponding timer, in the reset / cancel instruction A 31_reset After the level changes from low to high, the timing starts from 0. Data node A 31 The timing time is as follows: A 31_time As shown.

[0061] Assume the first target data node A 11 The data acquisition timing for the first target data is (I+1)t, and the timing for the second target data node A is... 21 The data acquisition time for the second target data is 2t, while from Figure 5 The first target data node A can be seen from this. 11 Second target data node A 21 If the timing offset is It, then the data acquisition time for the first target data is (I+1)t, and the data acquisition time for the second target data is It+2t. Therefore, the first target data node A... 11 Second target data node A 21 The data processing delay is equal to It + 2t - (I + 1)t = t, which is the delay of the first target data node A. 11 Second target data node A 21 The data processing delay is one clock cycle t. Here, I is a natural number greater than or equal to 3.

[0062] It should be noted that, in this embodiment of the invention, not only can the data processing delay be analyzed based on the collected target data, but also the function of the module can be analyzed based on the target data corresponding to the input data node and output data node of the same functional module. These details will not be elaborated here.

[0063] In some embodiments of the present invention, such as Figure 6 As shown, Figure 6 This is a schematic diagram of a chip system and data acquisition device provided in another embodiment of the present invention, showing the target data output terminals OUT1 to OUT2. M The target data is stored in memory via the chip system's bus. Of course, in some embodiments, the target data output terminals OUT1 to OUT2 are... M It can also be connected to the chip system's memory via the chip system's bus and memory controller, which will not be elaborated here.

[0064] In some embodiments of the present invention, the target data output terminal of each data acquisition channel is connected to a bus, and the target data is stored in memory via the bus, so that analysis devices such as computers can retrieve the target data from memory and analyze the performance of the chip system based on the target data. The connection between the target data output terminal and the bus can be achieved by adding a bus interface or reusing a bus interface.

[0065] Based on this, the data acquisition device can share the memory of the chip system, thus eliminating the need for additional storage and reducing costs. Of course, the invention is not limited to this; in other embodiments, the target data output terminal can also output and store the acquired target data to other memories, which will not be elaborated upon here.

[0066] Based on the above embodiments, in some embodiments of the present invention, the data corresponding to the data node carries a data identifier, and the data identifier is transmitted between the data nodes processing the data. Therefore, after storing target data corresponding to different data nodes in the same memory, the same target data can be found from the data corresponding to different data nodes in the memory based on the data identifier. For example, data of the same signal can be found from the data corresponding to different data nodes based on the data identifier, thereby obtaining the data processing delay between the two data nodes based on the data acquisition time of the same signal data in the two data nodes.

[0067] In some embodiments of the present invention, such as Figure 7 As shown, Figure 7 This is a schematic diagram of a data acquisition channel provided in one embodiment of the present invention. The data acquisition channel includes multiple acquisition units connected in sequence, such as data acquisition channel S1 including multiple acquisition units 70a to 70e. Each acquisition unit includes multiple data input terminals and one data output terminal.

[0068] For two acquisition units connected sequentially in a plurality of acquisition units, the data output terminal of the previous acquisition unit is connected to one data input terminal of the next acquisition unit, and the other data input terminals of the next acquisition unit serve as data acquisition terminals for connecting data nodes. The data output terminal of the last acquisition unit in the plurality of acquisition units is the target data output terminal for outputting the target data. For example, the data output terminal of acquisition unit 70d is connected to one data input terminal of acquisition unit 70e, and the other data input terminals of acquisition unit 70e serve as data acquisition terminals B. 51 B 52 The data output terminal of the acquisition unit 70e is the target data output terminal OUT1.

[0069] Based on this, after the acquisition unit acquires the data corresponding to the target data node through the data input end, it transmits the data to the next acquisition unit connected to it through the output end. The next acquisition unit transmits the data sequentially until the last acquisition unit outputs the data to memory or other storage devices through the target data output end.

[0070] In some embodiments of the present invention, such as Figure 7 As shown, multiple acquisition units are connected sequentially according to the connection order of multiple functional modules. The data acquisition terminal of the same acquisition unit connects to the data nodes of functional modules in the same order, or the data acquisition terminal of the same acquisition unit connects to the data nodes of different functional modules. The data nodes between functional modules include the input data nodes and output data nodes of the functional modules.

[0071] In other words, multiple acquisition units collect data nodes between multiple functional modules. A single acquisition unit can collect data nodes located between the same functional modules; for example, acquisition unit 70a collects data node A between CPU module 11 and the first logic control module 12. 11 To A 1N The acquisition unit 70b acquires data node A between the first logic control module 12 and the first-level cache module 13. 21 To A 2N The acquisition unit 70c acquires data node A between the first-level cache module 13 and the second logic control module 14. 31 To A 3N The acquisition unit 70d acquires data node A between the second logic control module 14 and the second-level cache module 15. 41 and A 42 The acquisition unit 70e acquires data nodes A between the secondary cache module 15 and other modules. 51 and A 52 .

[0072] Of course, the same acquisition unit can also acquire data nodes between different functional modules, such as... Figure 8 As shown, Figure 8 This is a schematic diagram of the data acquisition channel provided in another embodiment of the present invention. The acquisition unit 70d acquires data node A between the second logic control module 14 and the secondary cache module 15. 41 and A 42 Data node A between the secondary cache module 15 and other modules 51 and A 52 This reduces the number of data acquisition units and lowers costs.

[0073] In some embodiments of the present invention, the acquisition unit includes a multiplexer. The multiplexer includes multiple transistors, the gates of which are connected to a control terminal, the sources of which are connected to a data input terminal of the acquisition unit, and the drains of which are connected to a data output terminal of the acquisition unit. When a signal from the control terminal turns on the transistor connected to the target data node, the data input terminal connected to that transistor is connected to the data output terminal. The target data node transmits target data to the data output terminal through the data input terminal, and finally transmits the data to the target data output terminal through the sequentially connected acquisition units.

[0074] It should be noted that in some embodiments of the present invention, signals can be stored in registers to control whether the transistors of the multiplexer are turned on or off. Of course, the present invention is not limited to this; in other embodiments, the acquisition unit may also employ other logic gate circuits, etc.

[0075] This invention also provides a data acquisition method applied to a chip system, the chip system including multiple data nodes, such as... Figure 9 As shown, Figure 9 A flowchart of a data acquisition method provided in one embodiment of the present invention, the data acquisition method comprising:

[0076] S901: Configure at least two data acquisition channels for target data nodes. One data acquisition channel includes multiple data acquisition ends and target data output ends. One data acquisition end is connected to one data node. The target data node is any data node among the multiple data nodes.

[0077] refer to Figure 2 The chip system includes multiple data nodes A 11 To A 1N A 21 To A 2N A 31 To A 3N A 41 A 42 A 51 A 52 At least two data acquisition channels, including data acquisition channel S1 to data acquisition channel S2. M M and N are natural numbers greater than 1.

[0078] Each data acquisition channel includes multiple data acquisition terminals and a target data output terminal. Each data acquisition terminal connects to a data node in the chip system, and the data corresponding to the data node can be acquired by the connected data acquisition terminal. For example... Figure 2 As shown, the data acquisition channel S1 includes multiple data acquisition terminals B. 11 To B 1N B 21 To B2N B 31 To B 3N B 41 B 42 B 51 B 52 And the target data output terminal OUT1, and multiple data acquisition terminals B 11 To B 1N B 21 To B 2N B 31 To B 3N B 41 B 42 B 51 B 52 With multiple data nodes A 11 To A 1N A 21 To A 2N A 31 To A 3N A 41 A 42 A 51 A 52 Each corresponds to a separate connection.

[0079] Since each data acquisition channel is connected to multiple data nodes in the chip system, it can be configured to acquire data from any of these data nodes. Each data acquisition channel can be configured with one or more target data nodes. However, to analyze the overall performance of the chip system, different data acquisition channels need to acquire data from different target data nodes.

[0080] S902: For any data acquisition channel, based on the target data node configured for the data acquisition channel, the target data corresponding to the target data node acquired by the target data acquisition terminal is output through the target data output terminal; the target data acquisition terminal is the data acquisition terminal connected to the target data node among multiple data acquisition terminals;

[0081] Assume that the target data node configured for data acquisition channel S1 is A. 11 Then data acquisition channel S1 passes through the target data acquisition terminal B. 11 Collect target data node A 11 The target data is obtained and output through the target data output terminal OUT1. The target data acquisition terminal B... 11 For the multiple data acquisition terminals of data acquisition channel S1, the target data node A is connected. 11 The data acquisition terminal.

[0082] This invention provides an embodiment of a chip system that includes a data acquisition channel and a target data node configured for that channel. The target data corresponding to the configured target data node is acquired through the target data acquisition terminal of the data acquisition channel, allowing for performance analysis of the chip system based on the actual acquired target data. Since the actual acquired target data more accurately reflects the overall performance of the chip system, the accuracy of the overall chip system performance analysis is improved, leading to more reasonable optimization of chip design and chip products.

[0083] In some embodiments of the present invention, analyzing the overall performance of the chip system can specifically involve analyzing the data processing latency of the chip system. Analyzing the data processing latency requires collecting data from two data nodes on the same data transmission chain; that is, it requires configuring two target data nodes on the same data transmission chain for each of the two data acquisition channels.

[0084] In some embodiments of the present invention, the target data node configured with at least two data acquisition channels includes: a first target data node configured with a first data acquisition channel, and a second target data node configured with a second data acquisition channel. For example, the first target data node configured with the first data acquisition channel S1 is A. 11 Configure the second target data node of the second data acquisition channel S2 as A. 21 Among them, the first target data node A 11 Second target data node A 21 They are located on the same data transmission chain.

[0085] Based on this, for any data acquisition channel, and based on the target data node configured for the data acquisition channel, the target data corresponding to the target data node acquired by the target data acquisition terminal is output through the target data output terminal, including:

[0086] Based on the first target data node configured in the first data acquisition channel, the first target data corresponding to the first target data node acquired by the first target data acquisition terminal is output through the target data output terminal of the first data acquisition channel.

[0087] And, based on the second target data node configured in the second data acquisition channel, the second target data corresponding to the second target data node acquired by the second target data acquisition terminal is output through the target data output terminal of the second data acquisition channel;

[0088] The first target data and the second target data are used to analyze the data processing delay between the first target data node and the second target data node.

[0089] For example, the first data acquisition channel S1 passes through the first target data acquisition terminal B. 11 Collect first target data node A11 The first target data is output through the target data output terminal OUT1. The second data acquisition channel S2 outputs the first target data through the second target data acquisition terminal C. 21 Collect data from the second target node A 21 The second target data is output through the target data output terminal OUT2. The first and second target data are used to analyze the first target data node A. 11 Second target data node A 21 Data processing delay between them.

[0090] Based on the above embodiments, in some embodiments of the present invention, the data corresponding to the data node carries data acquisition time information. Furthermore, the data acquisition time information includes the data acquisition time of the target data, so as to analyze the first target data node A based on the difference between the data acquisition time of the first target data and the data acquisition time of the second target data. 11 Second target data node A 21 Data processing delay.

[0091] However, the present invention is not limited thereto. In some other embodiments, the data acquisition time information includes a data acquisition timing time, so as to obtain the data acquisition time based on the data acquisition timing time. The specific process of obtaining the data acquisition time based on the data acquisition timing time has been described in the above embodiments and will not be repeated here.

[0092] In some embodiments of the present invention, the data corresponding to a data node carries a data identifier, and the data identifier is transmitted between the data nodes processing the data. Based on this, after storing target data corresponding to different data nodes in the same memory, the same target data can be found from the data corresponding to different data nodes in the memory according to the data identifier. For example, data of the same signal can be found from the data corresponding to different data nodes according to the data identifier, thereby obtaining the data processing delay of the two data nodes based on the data acquisition time of the same signal data in the two data nodes.

[0093] It should be noted that, in this embodiment of the invention, not only can the data processing delay be analyzed based on the collected target data, but also the function of the module can be analyzed based on the target data corresponding to the input data node and output data node of the same functional module. These details will not be elaborated here.

[0094] This invention also provides a chip system including multiple data nodes and a data acquisition device as provided in any of the above embodiments.

[0095] In some embodiments of the present invention, the chip system further includes multiple timers; the multiple timers are respectively configured to correspond to multiple data nodes or multiple functional modules, such as one timer being configured within one functional module, or one timer being configured within the module corresponding to one data node. The timers are used to obtain the data acquisition timing of the corresponding data node or functional module, and the data acquisition timing is combined with the timing offset time to obtain the data acquisition time.

[0096] This invention also provides an electronic device, including the chip system provided in any of the above embodiments.

[0097] This invention also provides a data analysis method applied to a chip system, which includes multiple data nodes, such as... Figure 10 As shown, Figure 10 A flowchart of a data analysis method provided in one embodiment of the present invention, the data analysis method including:

[0098] S1001: Acquire and analyze basic data. The basic data includes data output from at least two data acquisition channels. The data includes target data corresponding to different target data nodes in the chip system. The target data node can be any data node among multiple data nodes. The data acquisition channel can acquire and output the target data corresponding to the configured target data node.

[0099] S1002: Based on the target data corresponding to different target data nodes, perform corresponding performance analysis on different target data nodes.

[0100] After at least two data acquisition channels in the data acquisition device acquire data corresponding to the target data nodes in the chip system, an analysis device, such as a computer, obtains the data output from the at least two data acquisition channels in the data acquisition device, i.e., acquires the basic data for analysis. The analysis device can acquire integrated analysis data by connecting to the target data output terminal of the data acquisition device, or by connecting to the memory of the chip system.

[0101] After acquiring the basic data for analysis, performance analysis is performed on different target data nodes based on the target data corresponding to those nodes. In some embodiments of this invention, the performance analysis of the chip system can specifically involve analyzing the data processing latency corresponding to different target data nodes of the chip system.

[0102] In some embodiments of the present invention, performance analysis of different target data nodes based on the target data corresponding to different target data nodes includes:

[0103] Based on the first target data of the first target data node and the second target data of the second target data node, the data processing delay between the first target data node and the second target data node is analyzed.

[0104] The first target data is the target data corresponding to the first target data node acquired and output by the first data acquisition channel, and the second target data is the target data corresponding to the second target data node acquired and output by the second data acquisition channel.

[0105] In some embodiments of the present invention, the data corresponding to the data node carries a data identifier. Before analyzing the data processing delay between the first target data node and the second target data node based on the first target data of the first target data node and the second target data of the second target data node, the method further includes:

[0106] Based on the data identifier, the first target data is determined from the data corresponding to the first target data node, and the second target data is determined from the data corresponding to the second target data node.

[0107] In some embodiments of the present invention, the first target data includes a first data acquisition timing time, and the second target data includes a second data acquisition timing time. Analyzing the data processing delay between the first target data node and the second target data node based on the first target data of the first target data node and the second target data of the second target data node includes:

[0108] Based on the timing of the first data acquisition, the timing of the second data acquisition, and the timing offset between the first target data node and the second target data node, the data processing delay between the first target data node and the second target data node is analyzed.

[0109] Specifically, the process of analyzing the data processing delay between the first target data node and the second target data node based on the first data acquisition timing time, the second data acquisition timing time, and the timing offset time between the first target data node and the second target data node has been explained in the above embodiments and will not be repeated here.

[0110] Similarly, the analysis method in this embodiment of the invention can not only analyze data processing delay based on the collected target data, but also analyze whether the function of the same functional module is normal based on the target data corresponding to the input data nodes and output data nodes of the same functional module, etc., which will not be elaborated here.

[0111] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0112] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data acquisition device, characterized in that, The data acquisition device is applied to a chip system, which includes multiple data nodes; the data acquisition device includes at least two data acquisition channels. A data acquisition channel includes multiple data acquisition terminals and a target data output terminal; each data acquisition terminal is connected to a data node, wherein the data corresponding to the data node can be acquired by the connected data acquisition terminal; the target data output terminal outputs the target data corresponding to the target data node acquired by the target data acquisition terminal based on the target data node configured in the data acquisition channel; the target data node is any data node among the multiple data nodes; the target data acquisition terminal is the data acquisition terminal among the multiple data acquisition terminals connected to the target data node; Different data acquisition channels are configured with different target data nodes; The data acquisition device includes a first data acquisition channel and a second data acquisition channel; The first data acquisition channel is configured with a first target data node, and the first target data acquisition terminal acquires the first target data corresponding to the first target data node; the target data output terminal of the first data acquisition channel outputs the first target data acquired by the first target data acquisition terminal. The second data acquisition channel is configured with a second target data node, and the second target data acquisition terminal acquires the second target data corresponding to the second target data node; the target data output terminal of the second data acquisition channel outputs the second target data acquired by the second target data acquisition terminal. The first target data and the second target data are used to analyze the data processing latency between the first target data node and the second target data node.

2. The data acquisition device according to claim 1, characterized in that, The chip system has multiple functional modules, and the multiple data nodes include: data nodes between the functional modules, and / or data nodes within the functional modules.

3. The data acquisition device according to claim 1 or 2, characterized in that, The data acquisition channel includes multiple acquisition units connected in sequence; each acquisition unit includes multiple data input terminals and one data output terminal. For two acquisition units connected sequentially among the plurality of acquisition units, the data output terminal of the previous acquisition unit is connected to a data input terminal of the next acquisition unit, and the other data input terminals of the next acquisition unit serve as data acquisition terminals for connecting data nodes; the data output terminal of the last acquisition unit among the plurality of acquisition units is the target data output terminal for outputting target data.

4. The data acquisition device according to claim 3, characterized in that, The multiple acquisition units are connected sequentially according to the connection order of multiple functional modules in the chip system; the data acquisition end of one acquisition unit is connected to the data nodes between functional modules in the same order; the data nodes between functional modules include the input data nodes and output data nodes of the functional modules.

5. The data acquisition device according to claim 3, characterized in that, The acquisition unit includes a multiplexer.

6. The data acquisition device according to claim 1, characterized in that, The data corresponding to the data node carries a data identifier, and the data identifier is transmitted between the data nodes that process the data.

7. The data acquisition device according to claim 1, characterized in that, The data corresponding to the data node carries data acquisition time information, which includes data acquisition timing time. The data acquisition timing time is used to combine with timing offset time to obtain the data acquisition time.

8. The data acquisition device according to claim 1, characterized in that, The target data output terminal is connected to the memory of the chip system through the chip system bus to store the target data in the memory.

9. A data acquisition method, characterized in that, The data acquisition method is applied to a chip system, the chip system including multiple data nodes, and the data acquisition method includes: Configure at least two data acquisition channels for target data nodes. Each data acquisition channel includes multiple data acquisition ends and a target data output end. Each data acquisition end is connected to a data node. The target data node is any data node among the multiple data nodes. For any data acquisition channel, based on the target data node configured for the data acquisition channel, the target data corresponding to the target data node acquired by the target data acquisition terminal is output through the target data output terminal; the target data acquisition terminal is the data acquisition terminal connected to the target data node among the plurality of data acquisition terminals; Different data acquisition channels are configured with different target data nodes; The target data nodes configured with at least two data acquisition channels include: Configure the first target data node of the first data acquisition channel and the second target data node of the second data acquisition channel; For any data acquisition channel, based on the target data node configured for the data acquisition channel, the target data corresponding to the target data node acquired by the target data acquisition terminal is output through the target data output terminal, including: Based on the first target data node configured in the first data acquisition channel, the first target data corresponding to the first target data node acquired by the first target data acquisition terminal is output through the target data output terminal of the first data acquisition channel. And, based on the second target data node configured in the second data acquisition channel, the second target data corresponding to the second target data node acquired by the second target data acquisition terminal is output through the target data output terminal of the second data acquisition channel; The first target data and the second target data are used to analyze the data processing latency between the first target data node and the second target data node.

10. The data acquisition method according to claim 9, characterized in that, The data corresponding to the data node carries a data identifier, and the data identifier is transmitted between the data nodes that process the data.

11. The data acquisition method according to claim 9, characterized in that, The data corresponding to the data node carries data acquisition time information, which includes data acquisition timing time. The data acquisition timing time is used to combine with timing offset time to obtain the data acquisition time.

12. A chip system, characterized in that, It includes multiple data nodes and the data acquisition device as described in any one of claims 1 to 8.

13. The chip system according to claim 12, characterized in that, The chip system also includes multiple timers; the multiple timers are respectively configured to correspond to multiple data nodes or multiple functional modules of the chip system. The timer is used to obtain the data acquisition timing of the corresponding data node or the corresponding functional module. The data acquisition timing is combined with the timing offset time to obtain the data acquisition time.

14. An electronic device, characterized in that, Includes the chip system described in any one of claims 12 to 13.

15. A data analysis method, characterized in that, The data analysis method is applied to a chip system, which includes multiple data nodes. The data analysis method includes: Acquire basic analysis data, which includes data output from at least two data acquisition channels. The data includes target data corresponding to different target data nodes in the chip system. The target data node can be any data node among the plurality of data nodes. The data acquisition channels can acquire and output the target data corresponding to the configured target data nodes. Based on the target data corresponding to the different target data nodes, perform corresponding performance analysis on the different target data nodes; The step of performing corresponding performance analysis on the different target data nodes based on the target data corresponding to the different target data nodes includes: Based on the first target data of the first target data node and the second target data of the second target data node, the data processing delay between the first target data node and the second target data node is analyzed; The first target data is the target data corresponding to the first target data node acquired and output by the first data acquisition channel, and the second target data is the target data corresponding to the second target data node acquired and output by the second data acquisition channel.

16. The data analysis method according to claim 15, characterized in that, The data corresponding to the data node carries a data identifier. Before analyzing the data processing delay between the first target data node and the second target data node based on the first target data of the first target data node and the second target data of the second target data node, the method further includes: Based on the data identifier, the first target data is determined from the data corresponding to the first target data node, and the second target data is determined from the data corresponding to the second target data node.

17. The data analysis method according to claim 16, characterized in that, The first target data includes a first data acquisition timing time, and the second target data includes a second data acquisition timing time. The step of analyzing the data processing delay between the first target data node and the second target data node based on the first target data from the first target data node and the second target data from the second target data node includes: Based on the first data acquisition timing time, the second data acquisition timing time, and the timing offset time between the first target data node and the second target data node, the data processing delay between the first target data node and the second target data node is analyzed.

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