Direct memory access circuit, operation method and access instruction generation method

Abstract

The embodiment of the present application discloses a direct memory access circuit, an operation method and a method for generating access instructions. The direct memory access circuit is used to access a memory according to an instruction, and includes a first-in-first-out buffer, a first channel controller and a second channel controller. The operation method of the direct memory access circuit includes: decoding the instruction to obtain a first channel code and a second channel code, wherein the first channel code corresponds to the first channel controller, and the second channel code corresponds to the second channel controller; obtaining a state of the first channel controller from the first-in-first-out buffer according to the first channel code; selecting the second channel controller according to the second channel code; and controlling the second channel controller according to the state.

Description

Technical Field

[0001] The present application relates to the field of memory access technology, and in particular to a direct memory access circuit, an operation method, and a method for generating access instructions. Background Art

[0002] When the electronic device calculates the following formula (1), the detailed steps are: (i) calculating C11 (i.e., formula (1a)); (ii) storing data C11 into a target location of a memory; (iii) reading data C11 from the target location of the memory; and (iv) calculating E11 (i.e., formula (1b)).

[0003] "E11=A11×B+D" (1)

[0004] "C11=A11×B" (1a)

[0005] "E11=C11+D" (1b)

[0006] "E12=A12×B+D" (2)

[0007] When conventional computers or electronic devices calculate equations (1) and (2), they use an operator-wide synchronization method to perform the calculations to ensure that the results are correct. Operator-wide synchronization means that the computer or electronic device will first complete the calculation of equation (1) (i.e., after obtaining the result E11) before performing the calculation of equation (2). However, the multiplication operation of equation (2) (i.e., "A12×B") does not need to wait until equation (1) is completed before starting. More specifically, because reading data A12 does not affect the calculation of equation (1), the computer or electronic device can preferably read data A12 from the memory at the same time as executing the multiplication operation of equation (1) (i.e., "A11×B") to improve computing performance.

[0008] However, some data (e.g., data C11 in equations (1a) and (1b)) cannot be accessed or modified at any time (i.e., data C11 must be stored before it can be read out), otherwise it will lead to erroneous calculation results. In other words, the memory space storing the data cannot be read or written at any time. Therefore, a method for generating a memory access instruction and a related direct memory access (DMA) circuit and its operation method are needed to improve the performance of a computer or electronic device. Summary of the invention

[0009] In view of the deficiencies of the prior art, an object of the present application is to provide a direct memory access circuit, an operation method and an access instruction generation method to improve the deficiencies of the prior art.

[0010] An embodiment of the present application provides a direct memory access circuit for accessing a memory according to an instruction, comprising: a first channel controller, a second channel controller, a decoder, a first-in-first-out buffer, and a controller. The first and second channel controllers are used to access the memory. The decoder is used to decode the instruction to obtain a first channel code and a second channel code, the first channel code corresponds to the first channel controller, and the second channel code corresponds to the second channel controller. The first-in-first-out buffer is used to store a state of the first channel controller. The controller is coupled to the decoder and the first-in-first-out buffer, and is used to perform the following steps: obtaining the state from the first-in-first-out buffer according to the first channel code; selecting the second channel controller according to the second channel code; and controlling the second channel controller according to the state.

[0011] Another embodiment of the present application provides an operation method of a direct memory access circuit, the direct memory access circuit is used to access a memory according to an instruction, the direct memory access circuit includes a first-in-first-out buffer, a first channel controller and a second channel controller, the method includes: decoding the instruction to obtain a first channel code and a second channel code, wherein the first channel code corresponds to the first channel controller, and the second channel code corresponds to the second channel controller; obtaining a state of the first channel controller from the first-in-first-out buffer according to the first channel code; selecting the second channel controller according to the second channel code; and controlling the second channel controller according to the state.

[0012] Another embodiment of the present application provides a method for generating a memory access instruction, wherein a memory block is accessed by a first instruction and a second instruction in succession, the second instruction being immediately after the first instruction, the method comprising: when one of the first instruction and the second instruction is a read instruction and the other is a write instruction, using a native channel code of the first instruction as a parameter of the second instruction. The native channel code corresponds to a channel controller of a direct memory access circuit, and the channel controller is used to execute the first instruction.

[0013] The present application controls memory access according to the dependency of consecutive memory access instructions. Compared with the prior art, the electronic device or chip using the direct memory access circuit of the present application can perform calculations in a more efficient manner, thereby improving computing performance.

[0014] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A flowchart of an embodiment of a method for generating a memory access instruction of the present application;

[0017] Figure 2 An embodiment of the instruction format of the present application;

[0018] Figure 3 Another embodiment of the instruction format of the present application;

[0019] Figure 4 A functional block diagram of an embodiment of a direct memory access circuit of the present application;

[0020] Figure 5 An example of a state table for a channel controller;

[0021] Figure 6 A flowchart of an embodiment of a method for operating a direct memory access circuit;

[0022] Figure 7 is a flowchart of an embodiment of step S670; and

[0023] Figure 8 This is a functional block diagram of an embodiment of a channel controller of the present application. DETAILED DESCRIPTION

[0024] The technical terms used in the following descriptions refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification.

[0025] The disclosure of this application includes a direct memory access circuit, an operation method, and a method for generating access instructions. Since some components included in the direct memory access circuit of this application may be known components individually, the details of the known components will be omitted in the following description without affecting the full disclosure and feasibility of the device invention.

[0026] During the product development process, a product development tool (e.g., a computer) analyzes data dependencies for a certain computing model (e.g., a neural network model) and an intelligent processing unit (IPU) or direct memory access hardware, and then generates memory access instructions based on the data dependencies. The product is, for example, hardware with computing capabilities such as an electronic device or a chip, and the product uses a direct memory access circuit to control access (reading or writing) of a memory (including but not limited to a cache or a random access memory). More specifically, the data to be computed by the computing model is divided into a plurality of data pages using software, each of which has a size of, for example, 4KB, and a memory (cache or random access memory) is correspondingly divided into a plurality of memory blocks, each of which has a size corresponding to the size of the data page, and the product development tool is used to track the data dependencies of each data page. In one embodiment, each data page is written into or read from a certain memory block through a corresponding access instruction, and the product development tool can track the data dependencies of a data page by analyzing a plurality of access instructions to a certain memory block (hereinafter referred to as a target memory block, used to store a target data page). The product development tool determines whether to add a data dependency message (or data synchronization message) by analyzing two consecutive instructions (a first instruction and a second instruction, the second instruction immediately follows the first instruction, and the first instruction is the previous instruction of the second instruction) operating the target memory block, and generates a memory access instruction for the target data page accordingly. The detailed process is as follows: Figure 1 As shown, the following steps are included.

[0027] Step S110: Obtain a continuous first instruction and a second instruction, the first instruction and the second instruction access a target memory block (i.e., the first instruction and the second instruction read a target data page from the target memory block, write the target data page to the target memory block, or update the target data page in the target memory block (equivalent to a write operation)). In detail, the product development tool can obtain a continuous first instruction and a second instruction for an access operation to a target data page in a certain operation of the product, the operation first accesses the target memory block with the first instruction, and then accesses the target memory block with the second instruction, and no other instructions for accessing the target memory block are included between the first instruction and the second instruction.

[0028] It should be noted that an instruction (i.e., the first instruction or the second instruction mentioned above) includes or carries a native channel code, and the native channel code corresponds to a channel controller of a direct memory access circuit. In other words, when the direct memory access circuit executes a read (or write) instruction, a channel controller is designated to perform a read (or write) operation with the native channel code of the read (or write) instruction.

[0029] Step S120: The product development tool determines whether the first instruction and the second instruction include a read instruction and a write instruction. If yes (i.e., one of the first instruction and the second instruction is a read instruction and the other is a write instruction), it means that the first instruction and the second instruction have data dependency, and the product development tool executes step S130; otherwise (i.e., the first instruction and the second instruction are both read instructions or both write instructions), the product development tool executes step S140.

[0030] Step S130: The product development tool uses the channel code of the first instruction as a parameter of the second instruction (ie, the dependent channel code described below), and this parameter is the data dependent information. Figure 2 , Figure 2 An embodiment of the instruction format of the present application is shown. Figure 2 The format is for example only and is not intended to limit this application. Figure 2 In the example, an instruction may include five parameters: "read / write", "own channel code", "dependent channel code", "address" and "write content". The first instruction is a write (indicated by "W") instruction, and the second instruction is a read (indicated by "R") instruction. The dependent channel code "FF" of the first instruction is a default value (it can also be "0" or other values). Figure 2 As shown, the "own channel code" parameter of the first instruction and the "dependent channel code" parameter of the second instruction are both "ID1", indicating that the second instruction is dependent on the first instruction. "FF" means that the first instruction is not dependent on its previous instruction.

[0031] Step S140: The product development tool sets the dependent channel code of the second instruction to a default value. Figure 3 , Figure 3 Another embodiment of the instruction format of the present application is shown. Figure 3 The format is for example only and is not intended to limit this application. Figure 3 In the example, the first and second instructions are both read instructions, so the product development tool sets the second instruction's dependent channel code to the default value "FF", which means that the second instruction is not dependent on the first instruction. Please note that when the first and second instructions are both write instructions, the second instruction's dependent channel code is also the default value "FF".

[0032] Product development tools continue Figure 1 The process is used to scan the access instructions of the operation to each data page to determine whether each instruction is dependent on its previous instruction. In some embodiments, Figure 1 The process is implemented in software; in other words, product development tools complete the process by executing program code or program instructions. Figure 1 process.

[0033] The following will describe how the direct memory access circuit operates according to the “own channel code” and the “dependent channel code”.

[0034] Figure 4 It is a functional block diagram of an embodiment of the direct memory access circuit of the present application. Figure 4 The component is a part of the aforementioned product, including a processor 10, a direct memory access circuit 20 and a memory 25 (including but not limited to a cache 30 and a random access memory 40). The processor 10 accesses the cache 30 and the random access memory 40 through the direct memory access circuit 20. The direct memory access circuit 20 includes a decoder 210, a first-in-first-out buffer 220, a controller 230, a bus 250, m channel controllers 260 (260_1, 260_2, ..., 260_m, m is an integer greater than 1) and a bus 270. The channel codes of the m channel controllers 260 are ID1, ID2, ... and IDm respectively.

[0035] When the processor 10 wants to write a target data page into the memory 25 or read it from the memory 25, the processor 10 sends a target instruction to the direct memory access circuit 20. The decoder 210 decodes the target instruction sent by the processor 10 to obtain all parameters of the target instruction, and transmits the parameters to the controller 230. The first-in-first-out buffer 220 stores the status of the m channel controllers 260. The controller 230 is coupled to the decoder 210 and the first-in-first-out buffer 220, and is used to control the corresponding channel controller 260 to execute the task of the target instruction according to the own channel code of the target instruction. In addition to accessing the cache 30 or the random access memory 40, the channel controller 260 also updates its own status in the first-in-first-out buffer 220. Please refer to Figure 5 , Figure 5 is an example of a state table 500 of the channel controller 260, which is stored in the FIFO buffer 220. "BUSY" represents that the channel controller is busy (eg, accessing the cache 30 or the RAM 40), and "IDLE" represents that the channel controller is idle.

[0036] Figure 6 FIG. 1 is a flow chart of an embodiment of a method for operating a direct memory access circuit. Figure 6 The operation of the direct memory access circuit 20 will be described.

[0037] Step S610: The DMA circuit 20 receives a target instruction from the processor 10. The target instruction carries a first channel code (ie, a dependent channel code) and a second channel code (ie, a native channel code). For example, when the target instruction is Figure 2When the second instruction is executed, the first channel code is "ID1" and the second channel code is "ID2".

[0038] Step S620: The decoder 210 decodes the target instruction to obtain the first channel code, the second channel code and other parameters of the target instruction. The processor 10 encodes the target instruction in a certain encoding method, and the decoder 210 decodes the target instruction in a decoding method relative to the encoding method. The decoding operation is well known to those with ordinary knowledge in the art, so it is not repeated here.

[0039] Step S630: The controller 230 selects a second channel controller according to the second channel code. Figure 2 The controller 230 selects the second channel controller 260_2 corresponding to the second channel code “ID2”.

[0040] Step S640: The controller 230 determines whether the first channel code is a default value. If the first channel code is a default value (indicating that the target instruction is not dependent on the previous instruction, that is, the target instruction and the previous instruction are the same operation (both are read operations or both are write operations)), the controller 230 executes step S650. If the first channel code is not a default value (indicating that the target instruction is dependent on the previous instruction, that is, the target instruction and the previous instruction are not the same operation (one is a read operation and the other is a write operation)), the controller 230 executes steps S660 and S670. Here, the previous instruction and the target instruction are consecutive instructions for operating the target memory block, that is, for the target memory block, the target instruction is immediately after the previous instruction. However, for the processor 10 and the controller 230, there may be other instructions between the previous instruction and the target instruction, and the one or those other instructions do not access the target memory block.

[0041] Step S650 : the controller 230 controls the second channel controller 260_2 to access the memory 25 , that is, the channel controller 260_2 executes the task of the target instruction.

[0042] Step S660: The controller 230 obtains a state of a first channel controller from the FIFO buffer 220 according to the first channel code. Figure 2 The second instruction, and the state of the channel controller 260 is as follows Figure 5 As shown), the controller 230 uses the first channel code "ID1" as an index and searches the state table 500 to find that the state of the first channel controller 260_1 corresponding to "ID1" is busy.

[0043] Step S670: The controller 230 controls the second channel controller 260_2 according to the state of the first channel controller 260_1. The details of step S670 are as follows: Figure 7 Describe in detail.

[0044] See also Figure 7 , Figure 7 The flowchart of an embodiment of step S670 is shown, including the following steps.

[0045] Step S710: The controller 230 determines whether the state of the first channel controller 260_1 is an idle state. If not, steps S720, S730 and S740 are executed; if yes, steps S750 and S740 are executed.

[0046] Step S720: The controller 230 waits for the state of the first channel controller 260_1 to change to an idle state. After completing a task (e.g., completing a read operation or a write operation), any channel controller 260 changes its own state in the state table 500 to an idle state. Conversely, after receiving a task, any channel controller 260 changes its own state in the state table 500 to a busy state. In other words, in step S720, the controller 230 waits for the first channel controller 260_1 to complete the current task to ensure that the data is correct.

[0047] Step S730: After the state of the first channel controller 260_1 changes to the idle state, the controller 230 controls the second channel controller 260_2 to access the memory 25. Step S730 is the same as step S650.

[0048] Step S740: After receiving the task, the second channel controller 260_2 changes its own state in the state table 500 to a non-idle state (ie, a busy state).

[0049] Step S750: The controller 230 controls the second channel controller 260_2 to access the memory 25. Step S750 is the same as steps S730 and S650.

[0050] Figure 8The functional block diagram of an embodiment of the channel controller 260 of the present application is shown. The channel controller 260 includes a finite state machine 262, a read / write controller 264, and a buffer group 266. The buffer group 266 stores system parameters (including but not limited to information of the bus 250 and the bus 270, the width of each read / write data, the parameters of the direct memory access circuit 20, the parameters of the random access memory 40, etc.). The finite state machine 262 controls the read / write controller 264 to perform read operations and write operations according to the system parameters stored in the buffer group 266 and the various parameters of the target instruction. In addition, the finite state machine 262 also switches the state (idle or busy) according to whether the channel controller 260 is executing a task, and updates the corresponding field of the state table 500 stored in the first-in-first-out buffer 220.

[0051] A person skilled in the art can design the controller 230 according to the above disclosure. In some embodiments, the controller 230 can be implemented by a circuit or hardware such as a programmable logic device (PLD); in other embodiments, the controller 230 can perform the above operations by executing program codes or program instructions.

[0052] In summary, the direct memory access circuit 20 and its operation method of the present application tracks the dependency of each data page according to the continuous instructions, and controls the channel controller accordingly, which can ensure that the read operation immediately after the write operation and the write operation immediately after the read operation will not cause data errors. In this way, the electronic device or chip using the direct memory access circuit 20 can perform calculations in a more efficient manner. Taking the aforementioned formula (1) and formula (2) as an example, by finding the dependency of data C11 in formula (1a) and formula (1b) (that is, by specifying the dependent channel code), the present application can ensure that the correct data C11 is obtained when calculating formula (1b); in this way, compared with the overall synchronization of operators in the prior art, the present application can calculate formula (2) in advance. In other words, the present application can arrange data operations more finely, so the computing performance can be improved.

[0053] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. A person having ordinary knowledge in the technical field may make changes to the technical features of the present application based on the explicit or implicit contents of the present application. All these changes may fall within the scope of patent protection sought by the present application. In other words, the scope of patent protection of the present application shall be subject to the scope of the patent application defined in this specification.

[0054] Explanation of symbols:

[0055] 10: Processor;

[0056] 20: direct memory access circuit;

[0057] 25: memory;

[0058] 30: cache;

[0059] 40: Random access memory;

[0060] 210: decoder;

[0061] 220: First-in-first-out buffer;

[0062] 230: controller;

[0063] 250,270: bus;

[0064] 260,260_2,260_1,260_m: channel controller;

[0065] ID1, ID2, IDm: channel code;

[0066] 500: status table;

[0067] 262: finite state machine;

[0068] 264: read-write controller;

[0069] 266: Buffer group;

[0070] S110, S120, S130, S140, S610, S620, S630, S640, S650, S660, S670, S710, S720, S730, S740, S750: steps.

Claims

1. A direct memory access circuit for accessing a memory according to a target instruction, characterized in that: include: a first channel controller, used for accessing the memory; a second channel controller, used for accessing the memory; a decoder, for decoding the target instruction to obtain a first channel code and a second channel code, wherein the first channel code is a dependent channel code, the second channel code is a native channel code, the first channel code corresponds to the first channel controller, and the second channel code corresponds to the second channel controller; a first-in-first-out buffer for storing a state of the first channel controller; as well as A controller is coupled to the decoder and the FIFO buffer, and is used to perform the following steps: determining whether the first channel code is a default value, if the first channel code is not a default value, it means that the target instruction is dependent on a previous instruction, and the previous instruction and the target instruction are consecutive instructions for operating a target memory block; Obtain the state from the FIFO buffer according to the first channel code; selecting the second channel controller according to the second channel code; as well as controlling the second channel controller according to the state; Before receiving the target instruction, the direct memory access circuit receives a previous instruction, the previous instruction controls the first channel controller to perform a read operation on a memory block of the memory, and the target instruction controls the second channel controller to perform a write operation on the memory block of the memory.

2. The direct memory access circuit according to claim 1, wherein: The step of controlling the second channel controller according to the state comprises: When the state indicates that the first channel controller is not in an idle state, the method waits for the first channel controller to be in an idle state, and then controls the second channel controller to access the memory.

3. The direct memory access circuit according to claim 2, characterized in that The state is a first state, the FIFO buffer further stores a second state of the second channel controller, and when the second channel controller starts to access the memory, the second channel controller changes the second state to a non-idle state.

4. The direct memory access circuit according to claim 1, wherein: The step of controlling the second channel controller according to the state comprises: When the state indicates that the first channel controller is in an idle state, the controller controls the second channel controller to access the memory.

5. The direct memory access circuit according to claim 4, characterized in that: The state is a first state, the FIFO buffer further stores a second state of the second channel controller, and when the second channel controller starts to access the memory, the second channel controller changes the second state to a non-idle state.

6. A method for operating a direct memory access circuit, characterized in that: The direct memory access circuit is used to access a memory according to a target instruction. The direct memory access circuit includes a first-in-first-out buffer, a first channel controller and a second channel controller. The method includes: Decoding the target instruction to obtain a first channel code and a second channel code, wherein the first channel code is a dependent channel code and the second channel code is a native channel code, wherein the first channel code corresponds to the first channel controller and the second channel code corresponds to the second channel controller; determining whether the first channel code is a default value, if the first channel code is not a default value, it means that the target instruction is dependent on a previous instruction, and the previous instruction and the target instruction are consecutive instructions for operating a target memory block; Obtain a state of the first channel controller from the first-in-first-out buffer according to the first channel code; selecting the second channel controller according to the second channel code; and controlling the second channel controller according to the state; Before receiving the target instruction, the direct memory access circuit receives a previous instruction, the previous instruction controls the first channel controller to perform a read operation on a memory block of the memory, and the target instruction controls the second channel controller to perform a write operation on the memory block of the memory.

7. The operating method according to claim 6, characterized in that: The step of controlling the second channel controller according to the state comprises: When the state indicates that the first channel controller is not in an idle state, the method waits for the first channel controller to be in an idle state, and then controls the second channel controller to access the memory.

8. The operating method according to claim 7, characterized in that: The state is a first state, the FIFO buffer further stores a second state of the second channel controller, and the method further includes: When the second channel controller starts to access the memory, the second state is changed to a non-idle state.

9. The operating method according to claim 6, characterized in that: The step of controlling the second channel controller according to the state comprises: When the state indicates that the first channel controller is in an idle state, the second channel controller is controlled to access the memory.

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