Test system for interface boards, user equipment and CPU

Abstract

The present invention provides a testing system for an interface card, user equipment, and a CPU. The interface card includes: at least one physical layer (PHY) chip; at least one interface connected to the at least one PHY chip, the interface being used to connect to the testing equipment; a PCIe (PCIe) finger connected to the at least one PHY chip; and the PCIe finger being used to connect to the CPU motherboard. This invention enables a single interface card to test and verify the compatibility of at least one PHY chip with the CPU, saving R&D costs.

Description

Technical Field

[0001] The present invention relates to the field of testing technology, and in particular to a testing system for an interface board, user equipment and a CPU. Background Art

[0002] With advancements in CPU (Central Processing Unit) chip design, high-speed CPU interfaces can now be configured through software to implement different protocol types and functions. This means the same signal can be configured as a PCIe (Peripheral Component Interconnect Express) interface, a network interface, or a SATA (Serial Advanced Technology Attachment) storage interface.

[0003] Currently, testing adapter chips uses mature motherboards with the PHY (physical layer) chip directly integrated into the motherboard. This solution provides a simple interconnect link without the interference of other connectors or other devices. However, it is not flexible enough. If the PHY chip needs to be replaced or tested with a different model, the motherboard needs to be redesigned, which is relatively expensive to develop. Summary of the Invention

[0004] The interface board, user equipment, and CPU testing system provided by the present invention enables an interface board to test and verify the compatibility performance of at least one PHY chip and a CPU, thereby saving R&D costs.

[0005] The present invention provides an interface board, comprising:

[0006] At least one PHY chip;

[0007] at least one interface connected to at least one of the PHY chips, the interface being configured to connect to the test equipment;

[0008] A PCIe Finger connected to at least one of the PHY chips; the PCIe Finger is used to connect to the CPU mainboard.

[0009] Optionally, when there are at least two PHY chips, there are at least two interfaces;

[0010] At least two of the PHY chips are of the same type or different types.

[0011] Optionally, when one of the PHY chips has at least two channels, the number of the interfaces is at least two.

[0012] Optionally, the interface board further includes:

[0013] First jumper;

[0014] The MDIO pin of the PHY chip is connected to the first end of the first jumper;

[0015] The second end of the first jumper is used to connect to the RSVD pin of the PCIe finger defined as an MDIO signal.

[0016] Optionally, the interface board further includes:

[0017] Second jumper;

[0018] The MDIO pin of the PHY chip is connected to the first end of the second jumper;

[0019] The second end of the second jumper is used to connect to the MDIO signal outside the interface board.

[0020] Optionally, the interface board further includes: an MCU;

[0021] The MDIO pin of the PHY chip is connected to the MDIO pin of the MCU.

[0022] Optionally, the interface is an RJ45 interface.

[0023] Optionally, the interface protocol for connecting the PCIe Finger to the CPU mainboard is SGMII Gigabit Media Independent Interface or KR.

[0024] The present invention also provides a user equipment, which includes the above-mentioned interface board.

[0025] The present invention also provides a CPU testing system, comprising:

[0026] CPU motherboard, test equipment, and interface boards;

[0027] The CPU mainboard is connected to the test equipment via the interface board;

[0028] The interface board includes: at least one PHY chip;

[0029] at least one interface connected to at least one of the PHY chips, the interface being configured to connect to the test equipment;

[0030] A PCIe Finger connected to at least one of the PHY chips; the PCIe Finger is used to connect to the CPU mainboard.

[0031] The present invention provides a test system for an interface card, user equipment, and CPU. The interface card includes at least one PHY chip; at least one interface connected to the at least one PHY chip, the interface being used to connect to the test equipment; a PCIe finger connected to the at least one PHY chip; and the PCIe finger being used to connect to the CPU motherboard. This allows a single interface card to be used to test the compatibility of at least one PHY chip with the CPU. Multiple single-channel and dual-channel PHY chips of different brands can be integrated on a single card, thereby saving R&D costs. Furthermore, CPU product testing is facilitated by using an existing motherboard. As long as the motherboard has a PCIe finger configurable as an SGMII network interface, compatibility testing of RJ45-related network chips can be performed. The system has low requirements for the motherboard and strong versatility. The card is designed to the standard PCIe card size, making it easy to fit inside a standard chassis. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic structural diagram of a CPU testing system according to an embodiment of the present invention;

[0033] Figure 2 This is a schematic diagram of the connection of a board according to an embodiment of the present invention;

[0034] Figure 3 This is a schematic structural diagram of a board card according to another embodiment of the present invention. DETAILED DESCRIPTION

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0036] The embodiment of the present invention provides a CPU testing system, such as Figure 1 The CPU test system includes:

[0037] Interface board 1, CPU mainboard 2, test equipment 3;

[0038] The CPU mainboard 2 is connected to the test equipment 3 via the interface board 1 .

[0039] like Figure 2 As shown, the interface board 1 includes: at least one PHY chip 11;

[0040] at least one interface 12 connected to at least one of the PHY chips 11, the interface being configured to connect to the test device 3;

[0041] A PCIe Finger (Peripheral Component Interconnect Express) 13 connected to at least one of the PHY chips 11; the PCIe Finger is used to connect to the CPU mainboard.

[0042] In the above embodiment, one interface board can be used to test the compatibility performance between at least one PHY chip and a CPU, thereby saving R&D costs.

[0043] like Figure 2 As shown, when there are at least two PHY chips, there are at least two interfaces; and at least two PHY chips are of the same type or different types. Figure 2 8 are shown in FIG. Therefore, the adaptability of the dual-path two PHY chips and the CPU network interface can be verified.

[0044] like Figure 2 As shown, when one of the PHY chips has at least two channels, there are at least two interfaces. Figure 2 The BCM5482S8 shown in Figure 1 is dual-channel. Therefore, the compatibility between the dual-channel PHY chip and the CPU network interface can be verified.

[0045] like Figure 3 As shown, in one embodiment, the interface board further includes:

[0046] First jumper 14;

[0047] The MDIO (Management Data Input / Output) pin of the PHY chip 11 is connected to the first end of the first jumper 14;

[0048] The second end of the first jumper 15 is used to connect to the RSVD (reserved) pin of the PCIe finger 13 defined as an MDIO signal.

[0049] In the above embodiment, the test can be performed by selecting the MDIO of the RJ45 test board of the present invention to be connected to the defined MDIO signal on the RSVD of the PCIefinger through a jumper cap.

[0050] like Figure 3 As shown, in one embodiment, the interface board further includes:

[0051] Second jumper 15;

[0052] The MDIO pin of the PHY chip 11 is connected to the first end of the second jumper 15;

[0053] The second end of the second jumper 15 is used to connect to the MDIO signal outside the interface board.

[0054] In the above embodiment, the MDIO of the RJ45 test board of the present invention can be selected to be connected to an external pin through a jumper cap to perform testing.

[0055] like Figure 3 As shown, the interface board also includes: MCU (Microcontroller Unit, micro control unit) 16;

[0056] The MDIO pin of the PHY chip 11 is connected to the MDIO pin of the MCU 16 .

[0057] In the above embodiment, the onboard MCU can be selected through a jumper cap to configure the PHY chip for testing.

[0058] The interface 12 may be an RJ45 interface.

[0059] The interface protocol for connecting the PCIe Finger to the CPU mainboard is SGMII (Serial Gigabit Media Independent Interface) or KR.

[0060] An embodiment of the present invention further provides a user equipment, which includes the interface board as described above.

[0061] The following describes the application scenarios of the present invention:

[0062] The present invention is mainly aimed at the adaptation of network interfaces. On the product motherboard, due to the product form, the hardware is generally adapted to a specific network chip, with a fixed interface connector externally, and the software is configured to the corresponding interface protocol. In CPU development, it is necessary to test the adaptation of network chips of different manufacturers and models, and test the adaptation performance so as to recommend a suitable solution to the whole machine manufacturer. The main protocol tested in this invention is the SGMII interface, which is converted to a gigabit RJ45 interface through a PHY chip and then interconnected with another board or switch through a gigabit network cable for testing.

[0063] The embodiment of the present invention realizes a gigabit RJ45 interface card that integrates multiple types of PHY chips and is connected to the CPU mainboard through a PCIe slot. In this way, one card can test and verify the compatibility performance of multiple types of PHY chips with the CPU, saving R&D costs.

[0064] like Figure 2 The RJ45 interface card of this invention is a PCIe plug-in card with two integrated PCIe fingers. It is a double-sided PCIe gold finger card with the same dimensions as a standard PCIe full-height, half-length card. The fingers are standard PCIe finger forms, and the PHY chip can be of different brands with different channel counts, such as a 4-channel PHY chip.

[0065] Figure 2 This is a block diagram of a dual-gold finger RJ45 interface card. The RJ45 interface card of the present invention includes two modules.

[0066] Module 1:

[0067] The four chips include an RTL8211FS PHY chip, a YT8521SH chip, an 88E1512 chip, and an 88E1514 chip. These four chips are all single-channel PHY chips and are from different manufacturers.

[0068] These four chips are connected to a Gigabit RJ45 port respectively and connected to the CPU motherboard via PCIe Finger, using the SGMII interface protocol.

[0069] In this way, through module one, the compatibility performance of single-channel PHY chips of different brands and CPU network interfaces can be verified.

[0070] Module 2:

[0071] The motherboard includes a BCM5482 dual-channel PHY chip, a BCM54616 single-channel PHY chip, and a VSC8211 single-channel PHY chip, along with four corresponding Gigabit RJ45 ports. The latter two PHY chips are of the same brand. These three chips connect to the CPU motherboard via PCIe Finger, using the SGMII interface protocol.

[0072] In this way, through module 2, the adaptability performance of the dual-channel PHY chip and the CPU network interface can be verified, and the verification of single-channel PHY chips from two brands can be added.

[0073] in addition, Figure 3 The MDIO connection topology diagram of the RJ45 test board is shown below. The MDIO interface is integrated on the RJ45 test board of the present invention, as follows:

[0074] 2 modules with the same design:

[0075] The PCIe finger has multiple undefined RSVD pins. Some motherboards define some RSVD pins as MDIO signals. Therefore, the RJ45 test board of the present invention also defines the corresponding RSVD pins as MDIO signals. A jumper cap determines whether the MDIO pins of the RJ45 test board of the present invention are connected to the defined MDIO signals on the RSVD of the PCIe finger or to an external pin. If the motherboard PCIe slot does not have an MDIO interface, an external pin can be used to connect the MDIO.

[0076] In addition, if Figure 3 As shown, the RJ45 test board of the present invention also includes an MCU, which is also connected to each PHY chip via MDIO. This allows users to choose whether to configure the PHY chip via the CPU via MDIO or via the onboard MCU. The latter option is suitable for situations where the CPU has specific restrictions on the PHY address of the PHY chip, that is, the CPU cannot configure PHY chips with PHY addresses outside a certain range.

[0077] The test system for the interface board, user equipment, and CPU provided by the embodiment of the present invention has the following beneficial effects:

[0078] 1. It is convenient for CPU product testing. You can use existing motherboards. As long as the motherboard has a PCIe Finger that can be configured as an SGMII network interface, you can perform RJ45-related network chip adaptation testing. It has low requirements for the motherboard and is highly versatile.

[0079] 2. It can integrate multiple single-channel and dual-channel PHY chips of different brands on one board, saving R&D costs.

[0080] 3. The board is designed according to the standard PCIe card size, which is convenient for application inside a standard chassis.

[0081] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. An interface board, characterized in that: include: At least one port physical layer PHY chip; at least one interface connected to at least one of the PHY chips, the interface being configured to connect to a test device; A high-speed peripheral component interconnection gold finger PCIe Finger connected to at least one of the PHY chips; the PCIe Finger is used to connect to the central processing unit CPU motherboard; The interface board also includes: a microcontroller unit MCU, wherein the MCU is connected to each PHY chip via an MDIO pin; The configuration of the PHY chip is configured by the CPU through the MDIO, or configured by the MCU.

2. The interface board according to claim 1, wherein: When there are at least two PHY chips, there are at least two interfaces; At least two of the PHY chips are of the same type or different types.

3. The interface board according to claim 1, wherein: When one of the PHY chips has at least two channels, the number of interfaces is at least two.

4. The interface board according to claim 1, wherein: Also includes: First jumper; The management data input and output MDIO pin of the PHY chip is connected to the first end of the first jumper; The second end of the first jumper is used to connect to the reserved RSVD pin of the PCIe finger defined as an MDIO signal.

5. The interface board according to claim 1, wherein: Also includes: Second jumper; The MDIO pin of the PHY chip is connected to the first end of the second jumper; The second end of the second jumper is used to connect to the management data input and output MDIO signal outside the interface board.

6. The interface board according to claim 1, wherein: The interface is an RJ45 interface.

7. The interface board according to claim 1, wherein: The interface protocol for connecting the PCIe Finger to the CPU mainboard is Serial Gigabit Media Independent Interface SGMII or High Speed ​​Serial Protocol KR.

8. A user equipment, characterized in that The user equipment comprises the interface board according to any one of claims 1 to 7.

9. A CPU testing system, characterized in that: include: CPU motherboard, test equipment, and interface boards; The CPU mainboard is connected to the test equipment via the interface board; The interface board includes: at least one PHY chip; at least one interface connected to at least one of the PHY chips, the interface being configured to connect to the test equipment; A PCIe Finger connected to at least one of the PHY chips; the PCIe Finger is used to connect to the CPU motherboard; The interface board also includes: an MCU, wherein the MCU is connected to each PHY chip via MDIO; The configuration of the PHY chip is configured by the CPU through the MDIO, or configured by the MCU.

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