Control method, device, storage medium and electronic device for low-frequency high-performance chip

Abstract

The embodiments of the present application disclose a control method, device, storage medium and electronic device for a low-frequency high-performance chip, and relate to the field of control. The control method includes: selecting at least one algorithm module from N algorithm modules, and forming a control loop using the selected algorithm module; providing an input signal to the control loop; starting the control loop to calculate the input signal; reading the calculation result of the control loop. The present application makes full use of the computing power of each algorithm module in the coprocessor, and hardly consumes the computing power of the main processor, so there is no need to increase the size of the processor. In addition, directly using modular algorithm modules to reconstruct the control loop can reduce the difficulty of developing control algorithms and improve development efficiency.

Description

Technical Field

[0001] The present invention relates to the field of control, and in particular to a control method, device, storage medium and electronic equipment for a low-main-frequency high-performance chip. Background Art

[0002] With the continuous improvement of industrial intelligence, the functions required of industrial products are becoming more diversified and complex, and the corresponding performance requirements for the main control chips in industrial products are also getting higher and higher. In order to improve the processing performance of the main control chip, the efficiency of program execution (especially algorithms) is generally improved by increasing the main frequency of the main control chip. Therefore, many main control chips in the industrial control field are developing in the direction of high main frequency. At the same time, in order to meet the needs of users for multiple algorithms, the chip memory size is continuously expanded, resulting in an increase in the size of the chip. Summary of the invention

[0003] The control method, device, storage medium and electronic device of a low-frequency high-performance chip provided in the embodiments of the present application can solve the problem of large processor size caused by improving the processing performance by increasing the chip's frequency in the related art. The technical solution is as follows:

[0004] In a first aspect, an embodiment of the present application provides a control method for a low-frequency high-performance chip, which is applied to a main processor and a coprocessor, wherein the main processor is connected to the coprocessor via a bus, and the coprocessor includes N algorithm modules, where N is an integer greater than 1, and each algorithm module is implemented in hardware form;

[0005] The control method comprises:

[0006] Selecting at least one algorithm module from the N algorithm modules, and forming a control loop using the selected algorithm module;

[0007] providing an input signal to the control loop;

[0008] Starting the control loop to calculate the input signal;

[0009] The calculation result of the control loop is read.

[0010] In a second aspect, the present application provides a control device, comprising:

[0011] A selection unit, used to select at least one algorithm module from the N algorithm modules, and to form a control loop using the selected algorithm module;

[0012] An input unit, used for providing an input signal to the control loop;

[0013] A starting unit, used for starting the control loop to calculate the input signal;

[0014] A reading unit, used to read the calculation result of the control loop

[0015] In a third aspect, the present application provides an electronic device, comprising: any one of the above-mentioned control devices.

[0016] The beneficial effects brought about by the technical solutions provided by some embodiments of the present application include at least:

[0017] Based on the dual-core architecture that combines a reconfigurable coprocessor with a main controller, multiple algorithm modules are integrated into one coprocessor. At the same time, multiple access methods to the coprocessor are used to ensure user flexibility, ultimately allowing low-frequency chips to achieve the performance of high-frequency chips. At the same time, users do not need to write algorithm programs in the control field, which saves development and design difficulty, reduces the storage space required for the chip, and reduces chip costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 is a flowchart of a control method for a low-frequency high-performance chip provided by an embodiment of the present invention;

[0020] Figure 2 It is a schematic diagram of the principle of the connection relationship of the configuration algorithm module provided in an embodiment of the present invention;

[0021] Figure 3 It is a schematic diagram of the principle of the connection relationship of the configuration algorithm module provided in an embodiment of the present invention;

[0022] Figure 4 is a structural diagram of a control device provided by an embodiment of the present invention;

[0023] Figure 5 is another structural diagram of a control device provided by an embodiment of the present invention;

[0024] Figure 6 is another structural diagram of the control device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] See also Figure 1 , is a flow chart of a control method for a low-frequency high-performance chip provided in an embodiment of the present application. In the embodiment of the present application, the method includes:

[0027] S101 . Select at least one algorithm module from N algorithm modules, and use the selected algorithm module to form a control loop.

[0028] Among them, the control method of the low main frequency high performance chip of the present application is applied to the main processor and the coprocessor, and the coprocessor includes N algorithm modules, N is an integer greater than 1, and each algorithm module is implemented in hardware. The main processor can select at least one algorithm module from the N algorithm modules according to the actual control requirements, and use the selected algorithm modules to form a control loop. In the control loop, the number of algorithm modules of the same type may be multiple, for example: the control loop includes 2 FFT modules; the output of one algorithm module may be the input of another algorithm module, and the topological structure of the control loop can be determined according to the actual control requirements, and this application does not limit it.

[0029] In one or more possible embodiments, the method of forming a control loop includes:

[0030] At least one algorithm module is selected from the N algorithm modules according to the configuration information in the register, and a control loop is formed using the selected algorithm module.

[0031] Among them, there are multiple registers, and flag bits are stored in the registers. The main processor selects the algorithm module (selects at least one algorithm module from N algorithm modules), determines the topology structure (determines the previous node and the next node of the current algorithm module), selects the input signal (one or more input signals can be selected from an external signal source or an internal signal source), and determines the method for reading the calculation results (interrupt method or status flag bit) according to the value of the flag bit.

[0032] For example, the registers configured in the event management module are shown in Table 1.

[0033] name Offset Size (x32) illustrate CH_ENA 0x00 1 Channel enable control. CH_INT_ENA 0x04 1 Channel interrupt enable control. CPU_KST 0x08 1 CPU channel startup control. CH_PND_CLR 0x10 1 Clear control of channel Pending. CH_CPU_PND 0x14 1 CPU pending flag of the channel CH_HW_PND 0x18 1 The hardware pending flag of the channel. CH_MODE0 0x1C 1 Channel mode selection control. SRC_CH_CON0 0x20-0x5C 1 Source channel trigger signal selection control. SRC_CH_CON1 0x60-0x9C 1 Source channel trigger signal selection control. DST_CH_CON0 0xA0-0xDC 1 Destination channel enable control.

[0034] Table 1

[0035] In one or more possible embodiments, the method of forming a control loop includes:

[0036] Displaying the control loop editing interface via the display unit;

[0037] Draw a topological relationship diagram on the control loop editing interface according to the user's editing instructions;

[0038] After the editing is completed, at least one algorithm module is selected from the N algorithm modules according to the topological relationship diagram, and a control loop is formed using the selected algorithm module.

[0039] Among them, the control loop editing interface includes an algorithm module set, and the algorithm module set includes controls of N algorithm modules. The user can use the mouse to drag each control to the canvas, and connect the topological relationship between each control through connecting lines to draw a topological relationship diagram. After the drawing is completed, the topological connection relationship of the topological relationship diagram is obtained, and at least one algorithm module is selected at the hardware level to form a control loop according to the topological connection relationship. The present application configures the control loop through a visual editing method, which can simplify the configuration process of the control loop and improve the configuration efficiency.

[0040] Optionally, when configuring the connection relationship of a certain algorithm module, you can refer to Figure 2 The method selects a group from the source signal list and the destination signal list and connects them to a certain algorithm module (that is, the algorithm module is also called a channel).

[0041] For example: See Figure 2 The connection relationship of a certain channel is: source signal 1 to destination signal 1, destination signal 1 to source signal A, source signal A to destination signal B, and then output the final interrupt flag. The present application can configure a trigger number M for each triggered destination signal, where M is an integer greater than 1, indicating that after source signal 1 triggers destination signal 1, destination signal 1 needs to run M times before triggering source signal A.

[0042] Optionally, select a group from the source signal list and the destination signal list to connect to a channel, see Figure 3 As shown. Figure 3 As shown, source signal 1 can trigger destination signal 0, destination signal 1 and destination signal B at the same time. When all signals are completed, source signal A is triggered, and then source signal A triggers destination signal 2, and finally an interrupt signal is generated.

[0043] S102. Provide an input signal for a control loop.

[0044] The input signal is the initial signal of the control loop, and the output signal may come from the inside of the main processor or coprocessor, or from outside the main control device. There may be multiple external signal sources or internal signal sources, and at least one signal is selected from the multiple external signal sources or external signal sources, and the selected signal is provided as an input signal to the control loop.

[0045] S103: Start the control loop to calculate the input signal.

[0046] After receiving the input signal, the control loop uses each algorithm module included in the control loop to calculate the input signal, and then stores the calculation result in the memory. In addition, each algorithm module is configured with a fixed storage space in the memory to store the intermediate results of each algorithm module respectively.

[0047] S104, reading the calculation result of the control loop.

[0048] Among them, the main processor reads the calculation result in the following manner: the control loop initiates an interrupt request after completing the calculation process, temporarily stores the calculation result, and the main processor reads the calculation result after detecting the interrupt request; or the control loop temporarily stores the calculation result after completing the calculation process, and then sets the status flag of the register to 1. After starting the control loop, the main processor periodically polls the value of the status flag, and reads the calculation result of the control loop when the value of the status flag is 1.

[0049] In one or more possible embodiments, the method further includes: sending the calculation result to an external device via a communication interface; or

[0050] The calculation result is processed by a PWM module to obtain a PWM signal, and the PWM signal is sent to an external device, and the external device is controlled by the output signal.

[0051] In one or more possible embodiments, the processor cores and control loops are enabled in parallel, which can improve processing efficiency.

[0052] For example: the processor core selects the DFT module, ARCTAN module, SIN module, MATRIX module 1, IIR module 1, FFT module, HCC module, MATRIX module 2, IIR module 2 and addition module in the coprocessor. The above algorithm modules form a control loop. The topological relationship of each algorithm module in the control loop refers to Figure 5As shown, no further description is given here. The control loop processes the digital signals input from AD modules 1 to 3 and then outputs them through the PWM module. The processor core processes the digital signals input from the AD module and then outputs them through the communication interface. The processor core and the control loop operate independently of each other, which can improve the processing efficiency of the control device.

[0053] The chip of the embodiment of the present application adopts a dual-core architecture of a reconfigurable coprocessor + main processor; multiple connection relationships between the main processor and the coprocessor: Connection relationship 1, the main processor can access the resources of the coprocessor through the bus, saving the time of the main processor occupied by a large number of algorithm operation units, and improving the processing task capability and algorithm operation efficiency. Connection relationship 2, through the event management unit module of the main processor, the algorithm module of the coprocessor and the module of the main controller are reconstructed and managed to achieve the effect of multi-core simultaneous operation. These two connection methods can meet the user's needs for the use of a single algorithm module, and can also meet the user's needs for the use of multiple modules in series and parallel. They are widely applicable to scenarios and highly flexible, and are very suitable for engineers in the field of industrial control to debug and control controls from multiple angles and directions. In addition, in order to improve the efficiency of the coprocessor in performing algorithm operations, a separate data storage space is allocated for each algorithm module to avoid affecting the data throughput speed in the algorithm module due to bus congestion.

[0054] The following is an embodiment of the device of the present application, which can be used to execute the embodiment of the method of the present application. For details not disclosed in the embodiment of the device of the present application, please refer to the embodiment of the method of the present application.

[0055] See also Figure 4 , which shows a schematic diagram of the structure of a control device provided by an exemplary embodiment of the present application, hereinafter referred to as device 4. The device 4 can be implemented as all or part of a computer device through software, hardware or a combination of both. The device 4 includes: a selection unit 401, an input unit 402, a start unit 403 and a reading unit 404.

[0056] A selection unit 401, configured to select at least one algorithm module from the N algorithm modules, and to form a control loop using the selected algorithm module;

[0057] An input unit 402, used to provide an input signal for the control loop;

[0058] A starting unit 403, used for starting the control loop to calculate the input signal;

[0059] The reading unit 404 is used to read the calculation result of the control loop.

[0060] In one or more possible embodiments, selecting at least one algorithm module from the N algorithm modules, and using the selected algorithm module to form a control loop, includes:

[0061] selecting at least one algorithm module from the N algorithm modules according to the configuration information of the register, and forming a control loop using the selected algorithm module; or

[0062] Displaying the control loop editing interface via the display unit;

[0063] Draw a topological relationship diagram on the control loop editing interface according to the user's editing instructions;

[0064] After the editing is completed, at least one algorithm module is selected from the N algorithm modules according to the topological relationship diagram, and a control loop is formed using the selected algorithm module.

[0065] In one or more possible embodiments, providing an input signal for the control loop includes:

[0066] Select at least one signal from multiple external signal sources or internal signal sources;

[0067] The selected signal is provided as an input signal to the control loop.

[0068] In one or more possible embodiments, each algorithm module is configured with a fixed storage space in the memory.

[0069] In one or more possible embodiments, reading the calculation result of the control loop includes:

[0070] Reading the calculation result of the control loop by interruption; or

[0071] The calculation result of the control loop is read through the status flag bit.

[0072] In one or more possible embodiments, it further includes:

[0073] An output unit, used to send the calculation result to an external device through a communication interface; or

[0074] The calculation result is processed by a PWM module to obtain a PWM signal, and the PWM signal is sent to an external device.

[0075] In one or more possible embodiments, the main processor and the control loop operate in parallel.

[0076] It should be noted that the device 4 can be a chip or a device. When the device 4 provided in the above embodiment executes the control method, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the control device and the control method embodiment provided in the above embodiment belong to the same concept, and the implementation process thereof is detailed in the method embodiment, which will not be repeated here.

[0077] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0078] See also Figure 5 The present invention provides a schematic diagram of the structure of a control device of an embodiment, the control device includes: a main processor, a coprocessor and a memory, and the main processor, the coprocessor and the memory are connected through a bus. The main processor includes a processor core, and the number of the processor cores can be one or more. The processor core is the core of the processor and is used to process all instructions and data. The processor core is connected to N algorithm modules through a bus.

[0079] The bus is used to realize the connection and communication between these components.

[0080] The control device of the present application may further include a communication interface, which is used to communicate with an external device to control the external device, for example, the external device is a motor, a switching power supply or an inverter, etc. For example, the communication interface may include a standard wired interface or a wireless interface (such as a WI-FI interface).

[0081] Among them, the control device of the present application may also include a user interface, and the user interface may include a display screen (Display) and a camera (Camera). The optional user interface may also include a standard wired interface and a wireless interface.

[0082] Among them, the main processor may include one or more processor cores. The main processor uses various interfaces and lines to connect the various parts of the entire control device, and executes various functions of the control device and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory, and calling data stored in the memory. Optionally, the main processor can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The main processor can integrate one or more combinations of central processing unit (Central Processing Unit, CPU), image processor (Graphics Processing Unit, GPU) and modem. Among them, the CPU mainly processes the operating system, user interface and application program; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; the modem is used to process wireless communication. It can be understood that the above-mentioned modem may not be integrated into the main processor, but implemented by a single chip.

[0083] Among them, the memory may include a random access memory (Random Access Memory, RAM) and may also include a read-only memory (Read-Only Memory). Optionally, the memory 505 includes a non-transitory computer-readable storage medium. The memory 505 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 405 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned method embodiments, etc.; the data storage area may store data involved in the above-mentioned method embodiments, etc. The memory may also be optionally at least one storage device located away from the aforementioned main processor. As Figure 5 As shown, the memory as a computer storage medium may include an operating system, a network communication module, a user interface module, and an application program.

[0084] The coprocessor includes N algorithm modules, where N is an integer greater than 1. Each algorithm module is a hardware-implemented module, for example, the algorithm module can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). For example, the algorithm module may be: FFT (Fast Fourier Transform) module, DFT (Discrete Fourier Transform) module, IIR (Infinite Impulse Response) module, FIR (Finite Impulse Response) module, SIN (sine) module, COS (cosine) module, ARCTAN (inverse tangent) module, MATRIX (matrix operation) module, SINH (hyperbolic sine function) module, COSH (hyperbolic cosine function) module, DIV (integer division) module, HCC module, RMS (root mean square) module or ECU module, wherein the number of algorithm modules of the same type may be multiple, for example, the coprocessor includes 2 FFT modules.

[0085] See also Figure 6 FIG. 1 is another schematic diagram of the structure of the control device provided in an embodiment of the present application. Figure 6 In the embodiment, the main processor includes an event management module and a processor core. The event management module is implemented in hardware. The number of the processor core is one or more. The event management module is connected to each processor core. The event management module is connected to each algorithm module through an off-chip bus.

[0086] exist Figure 5 or Figure 6 In the control device shown in FIG. 1 , the main processor can be used to call the application program or computer code stored in the memory and specifically execute the following steps: Figure 1 The method described.

[0087] The electronic device provided in the embodiment of the present application may further include, in addition to the above-mentioned control device, a housing for accommodating various components.

[0088] The above-described implementation methods do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described implementation methods shall be included in the protection scope of the technical solution.

Claims

1. A control method for a low-frequency high-performance chip, characterized in that: Applied to a main processor and a coprocessor, the main processor is connected to the coprocessor via a bus, the coprocessor includes N algorithm modules, N is an integer greater than 1, and each algorithm module is implemented in hardware form; The control method comprises: At least one algorithm module is selected from N algorithm modules according to the configuration information in the register, and a control loop is formed by using the selected algorithm module; wherein the number of the registers is multiple, and a flag bit is stored in the register, and the value of the flag bit is used to select the algorithm module, determine the topology structure, select the input signal, and determine the reading method of the calculation result; providing an input signal to the control loop; Starting the control loop to calculate the input signal; The calculation result of the control loop is read.

2. The method according to claim 1, characterized in that Providing an input signal to the control loop includes: Select at least one signal from multiple external signal sources or internal signal sources; The selected signal is provided as an input signal to the control loop.

3. The method according to claim 2, characterized in that Each algorithm module is configured with a fixed storage space in the memory.

4. The method according to claim 1 or 3, characterized in that: The reading of the calculation result of the control loop includes: Reading the calculation result of the control loop by interruption; or The calculation result of the control loop is read through the status flag bit.

5. The method according to claim 4, characterized in that Also includes: Send the calculation results to external devices through the communication interface; or The calculation result is processed by a PWM module to obtain a PWM signal, and the PWM signal is sent to an external device.

6. The method according to claim 5, characterized in that The main processor and the control loop operate in parallel.

7. A control device, characterized in that: include: A selection unit, used to select at least one algorithm module from N algorithm modules according to the configuration information in the register, and to form a control loop using the selected algorithm module; wherein the number of registers is multiple, and a flag bit is stored in the register, and the value of the flag bit is used to select the algorithm module, determine the topology structure, select the input signal, and determine the reading method of the calculation result; An input unit, used for providing an input signal to the control loop; A starting unit, used for starting the control loop to calculate the input signal; A reading unit is used to read the calculation result of the control loop.

8. A computer storage medium, characterized in that: The computer storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor and executing the method steps according to any one of claims 1 to 6.

9. An electronic device, characterized in that: include: A main processor, a coprocessor and a memory; wherein the memory stores a computer program, and the computer program is suitable for being loaded by the main processor and executing the method steps as claimed in any one of claims 1 to 6.

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