Timing adjustment method and time-invariant computer readable medium

Abstract

The present invention relates to a timing adjustment method and a time-invariant computer-readable medium for adjusting the propagation delay of each path of an integrated circuit. The timing adjustment method includes determining whether the propagation delay of a selected path exceeds the timing requirement in a worst-case mode; determining whether the propagation delay of the selected path exceeds the timing requirement in a path mode; and reducing the worst-case cell delay of each cell in the selected path when the selected path does not exceed the timing requirement in the path mode.

Description

Technical Field

[0001] The present invention relates to a method for eliminating fake faults in gate-level simulation and shortening the design process. Background Art

[0002] In the automated design of integrated circuits, static timing analysis (STA) is used to check the propagation delay of each path in the integrated circuit. In traditional static timing analysis, timing signoff is used to accurately determine the propagation delay of each path in the integrated circuit, and then the results of the timing signoff are used to determine the maximum and minimum values ​​of the cell delay of each cell in each path in the gate level simulation (referred to as the "worst mode" in the following paragraphs).

[0003] When it is determined that the integrated circuit does not meet the timing requirements in the gate level simulation, it is determined whether any false errors have occurred in the integrated circuit. When it is determined that at least one false error has occurred in the circuit, the traditional static timing analysis requires reducing the corresponding cell delay of the cell and the corresponding transmission delay of the path to eliminate the false error, and then re-execute the gate level simulation. Then, the gate level simulation is repeated multiple times until the circuit meets the timing requirements.

[0004] However, the corresponding cell delay and the corresponding propagation delay are usually reduced manually, and the number of repetitions is unpredictable, resulting in time-consuming operations and low efficiency. In order to shorten the design process and efficiently determine the propagation delay in the integrated circuit, there is a need for a method that can speed up static timing analysis. Summary of the invention

[0005] The present invention proposes a static timing analysis to eliminate false errors before gate level simulation, so that the design process can be shortened. The present invention also proposes a timing adjustment method to eliminate false errors. Therefore, false errors of integrated circuits can be automatically eliminated, thereby shortening the design time.

[0006] The present invention provides a timing adjustment method for adjusting the propagation delay of each path of an integrated circuit. The timing adjustment method comprises: in a worst-case mode, determining whether a propagation delay of a selected path exceeds a timing requirement; in a path mode, determining whether the propagation delay of the selected path exceeds the timing requirement; and when the propagation delay of the selected path in the path mode does not exceed the timing requirement, reducing the worst-case mode unit delay of each unit in the selected path.

[0007] According to an embodiment of the present invention, a cell delay of each cell of each path is obtained by a timing sign-off to determine a propagation delay of each path of the integrated circuit in the path mode. A maximum cell delay and a minimum cell delay of each cell of each path are obtained by the timing sign-off to determine a propagation delay of each path of the integrated circuit in the worst mode.

[0008] According to an embodiment of the present invention, the step of reducing the worst-mode unit delay of each unit in the selected path further comprises: reducing a maximum unit delay of the worst mode of each unit in the selected path by a proportion.

[0009] According to an embodiment of the present invention, the timing adjustment method further includes: when the transmission delay of the selected path in the path mode does not exceed the timing requirement, determining whether the transmission delay of another selected path from a test pool in the path mode exceeds the timing requirement.

[0010] According to an embodiment of the present invention, the timing adjustment method further includes: when the propagation delay of the selected path in the path mode exceeds the timing requirement, determining whether the propagation delay of the selected path exceeds a threshold value compared to the timing requirement; when the propagation delay of the selected path does not exceed the threshold value compared to the timing requirement, reducing the cell delay of each cell of the selected path, wherein update information of the updated cell delay of at least one cell in the selected path is stored in a register; and when the propagation delay of the selected path exceeds the threshold value compared to the timing requirement, popping up a warning message and determining whether the propagation delay of another selected path from a test pool in the path mode exceeds the timing requirement.

[0011] According to an embodiment of the present invention, the timing adjustment method further comprises: after the step of reducing the unit delay of each unit of the selected path, determining whether the transfer delay of another selected path from the test pool in the path mode exceeds the timing requirement.

[0012] According to one embodiment of the present invention, the timing adjustment method also includes: after the step of determining whether the transmission delay of another selected path from the test pool in the path mode exceeds the timing requirement, determining whether the test pool is empty; when the test pool is empty, determining whether the register is empty; when the test pool is not empty, selecting another selected path from the test pool; when the test pool and the register are both empty, terminating the timing adjustment method; when the test pool is empty and the test pool is not empty, updating the transmission delay of each path of the integrated circuit in the worst mode according to the update unit delay of the register; and after the step of updating the transmission delay of each path of the integrated circuit in the worst mode, collecting a first predetermined number of paths that violate the timing requirement into the test pool.

[0013] According to one embodiment of the present invention, the step of determining whether the test pool is empty, the step of determining whether the register is empty, the step of delaying updating the transmission delay of each path of the integrated circuit in the worst mode according to the update unit of the register, and the step of collecting the first predetermined number of paths that violate the timing requirement into the test pool are repeatedly performed a second predetermined number of times.

[0014] According to an embodiment of the present invention, when the second predetermined number is smaller than the first predetermined number, the first predetermined number is kept fixed in the next repetition.

[0015] According to an embodiment of the present invention, when the second predetermined number increases by 1, the first predetermined number also increases by 1.

[0016] The present invention also provides a time-invariant computer-readable medium for storing a plurality of program codes to determine the propagation delay of each path in an integrated circuit. The program code includes a set of instructions. When a computer executes the instructions, the computer performs the following steps: in a worst-case mode, determine whether a propagation delay of a selected path exceeds a timing requirement; in a path mode, determine whether the propagation delay of the selected path exceeds the timing requirement; and when the propagation delay of the selected path in the path mode does not exceed the timing requirement, reduce the worst-case mode unit delay of each unit in the selected path.

[0017] According to an embodiment of the present invention, a cell delay of each cell of each path is obtained by a timing sign-off to determine a propagation delay of each path of the integrated circuit in the path mode. A maximum cell delay and a minimum cell delay of each cell of each path are obtained by the timing sign-off to determine a propagation delay of each path of the integrated circuit in the worst mode.

[0018] According to an embodiment of the present invention, the step of reducing the worst-mode unit delay of each unit in the selected path further comprises: reducing a maximum unit delay of the worst mode of each unit in the selected path by a proportion.

[0019] According to one embodiment of the present invention, the computer further performs the following steps: when the transmission delay of the selected path in the path mode does not exceed the timing requirement, determining whether the transmission delay of another selected path from a test pool in the path mode exceeds the timing requirement.

[0020] According to an embodiment of the present invention, the computer further performs the following steps: when the propagation delay of the selected path in the path mode exceeds the timing requirement, determining whether the propagation delay of the selected path exceeds a threshold value compared to the timing requirement; when the propagation delay of the selected path does not exceed the threshold value compared to the timing requirement, reducing the cell delay of each cell of the selected path, wherein update information of the updated cell delay of at least one cell in the selected path is stored in a register; and when the propagation delay of the selected path exceeds the threshold value compared to the timing requirement, popping up a warning message and determining whether the propagation delay of another selected path from a test pool in the path mode exceeds the timing requirement.

[0021] According to one embodiment of the present invention, the computer further performs the following steps: after the step of reducing the unit delay of each unit of the selected path, determining whether the transmission delay of another selected path from the test pool in the path mode exceeds the timing requirement.

[0022] According to one embodiment of the present invention, the computer further performs the following steps: after the step of determining whether the transmission delay of another selected path from the test pool in the path mode exceeds the timing requirement, determining whether the test pool is empty; when the test pool is empty, determining whether the register is empty; when the test pool is not empty, selecting another selected path from the test pool; when the test pool and the register are both empty, terminating the timing adjustment method; when the test pool is empty and the test pool is not empty, updating the transmission delay of each path of the integrated circuit in the worst mode according to the update unit delay of the register; and after the step of updating the transmission delay of each path of the integrated circuit in the worst mode, collecting a first predetermined number of paths that violate the timing requirement into the test pool.

[0023] According to one embodiment of the present invention, the step of determining whether the test pool is empty, the step of determining whether the register is empty, the step of delaying updating the transmission delay of each path of the integrated circuit in the worst mode according to the update unit of the register, and the step of collecting the first predetermined number of paths that violate the timing requirement into the test pool are repeatedly performed a second predetermined number of times.

[0024] According to an embodiment of the present invention, when the second predetermined number is smaller than the first predetermined number, the first predetermined number is kept fixed in the next repetition.

[0025] According to an embodiment of the present invention, when the second predetermined number increases by 1, the first predetermined number also increases by 1. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a flow chart showing static timing analysis according to an embodiment of the present invention;

[0027] Figure 2 is a schematic diagram showing the delay of an integrated circuit according to an embodiment of the present invention; and

[0028] Figure 3 The flowchart shows a method for adjusting timing of an integrated circuit according to an embodiment of the present invention.

[0029]

Explanation of symbols

[0030] S11-S15: Process Step 200: Integrated Circuit

[0031] 210: First logic gate

[0032] 220: Second logic gate

[0033] 211: First signal path

[0034] 212: Second signal path

[0035] 213: Third signal path

[0036] 300: Adjust timing method

[0037] S31~S38 process steps DETAILED DESCRIPTION

[0038] The following description is an embodiment of the present invention. Its purpose is to illustrate the general principles of the present invention and should not be regarded as a limitation of the present invention. The scope of the present invention shall be determined by the scope of the patent application.

[0039] It is understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present disclosure.

[0040] It is noteworthy that the content disclosed below can provide multiple embodiments or examples for practicing the different features of the present invention. The special component examples and arrangements described below are only used to simply and concisely explain the spirit of the present invention, and are not used to limit the scope of the present invention. In addition, the following description may reuse the same component symbols or words in multiple examples. However, the purpose of reuse is only to provide a simplified and clear description, and is not used to limit the relationship between multiple embodiments and / or configurations discussed below. In addition, a feature described in the following description is connected to, coupled to, and / or formed on the description of another feature, and can actually include multiple different embodiments, including that these features are directly in contact, or include other additional features formed between these features, etc., so that these features are not in direct contact.

[0041] Figure 1 FIG. 1 is a flowchart showing a static timing analysis according to an embodiment of the present invention. Figure 1 As shown, when static timing analysis 100 is performed on an integrated circuit, a timing sign-off is first performed on the integrated circuit (step S11 ).

[0042] Figure 2 FIG. 1 is a schematic diagram showing the delay of an integrated circuit according to an embodiment of the present invention. Figure 2 As shown, the integrated circuit 200 includes a first logic gate 210 and a second logic gate 220 . The integrated circuit 200 also includes three signal paths, namely a first signal path 211 , a second signal path 212 and a third signal path 213 , all from the input end of the first logic gate 210 to the output end of the second logic gate 220 .

[0043] In step S11, it is determined that the delay of the first path 211 is 1 plus 7, the delay of the second path 212 is 4 plus 1, and the delay of the third path 213 is 1 plus 2. In other words, the unit delays of the first logic gate 210 corresponding to different paths are 1, 4, and 1, and the unit delays of the second logic gate 220 corresponding to different paths are 7, 1, and 2. Figure 2 The delay is for illustrative purposes only and is not intended to be limiting in any way.

[0044] refer to Figure 1 After the timing sign-off, the delay of the integrated circuit is adjusted (step S12) to perform gate level simulation. According to some embodiments of the present invention, the delay of the integrated circuit is adjusted to reduce false errors in the gate level simulation. Then, the worst-based mode delay of each unit in the integrated circuit is recorded to perform gate level simulation (step S13).

[0045] Based on the delay recorded in step S13, gate level simulation is performed (step S14) to determine whether the integrated circuit meets the timing requirements. When it is determined in step S14 that the integrated circuit meets the timing requirements, the static timing analysis is completed. When it is determined in step S14 that the integrated circuit does not meet the timing requirements, it means that the design of the integrated circuit needs to be modified to meet the timing requirements. Therefore, the design is adjusted in step S15, and the static timing analysis 100 returns to step S11.

[0046] According to some embodiments of the present invention, since the delay of the integrated circuit has been adjusted before the gate level simulation, no false errors will appear in the result of the gate level simulation. That is, when it is determined that the integrated circuit does not meet the timing requirement of step S14, it means that the design of the integrated circuit needs to be adjusted to meet the timing requirement. Therefore, the designer does not need to manually eliminate the false errors in the result of the gate level simulation or re-execute the gate level simulation, thereby shortening the design process and efficiently determining the transfer delay of the integrated circuit.

[0047] Figure 3 FIG. 1 is a flow chart showing a method for adjusting timing of an integrated circuit according to an embodiment of the present invention. Figure 3 As shown, the timing adjustment method 300 corresponds to Figure 1 In step S12, a first predetermined number of paths exceeding the timing requirement in the integrated circuit are collected into a test pool, wherein the delay of each path is determined based on a worst-case model.

[0048] According to an embodiment of the present invention, in the worst mode, only the maximum cell delay and the minimum cell delay of each cell of each path are used to determine the propagation delay of each path in the integrated circuit, wherein the maximum cell delay and the minimum cell delay are obtained by timing signoff.

[0049] like Figure 2As shown, the maximum unit delay and the minimum unit delay of the second logic gate 220 are 7 and 1, respectively. Therefore, the transmission delays of the first path 211, the second path 212, and the third path 213 are (1+7=8), (4+7=11), and (1+7=8), respectively. According to an embodiment of the present invention, when the timing requirement is 10, the slack of the second path 212 is -1. This means that the transmission delay of the second path 212 exceeds the timing requirement. Therefore, the second path 212 will be collected into the test pool in step S31.

[0050] like Figure 3 As shown, it is determined whether the test pool is empty (step S32). When the test pool is not empty, a selected path is selected from the test pool (step S33) to determine whether the path-based mode transmission delay of the selected path exceeds the timing requirement (step S34).

[0051] As shown in FIG. 2 , since the margin of the second path 212 is determined to be −1, it is further determined whether the transmission delay of the path pattern of the second path 212 exceeds the timing requirement. Figure 2 As shown, the transfer delay of the path pattern of the second path 212 is (4+1=5), so the margin of the second path 212 is actually 5, not -1.

[0052] According to one embodiment of the present invention, when it is determined in step S34 that the transmission delay of the path pattern of the selected path still exceeds the timing requirement, the selected path is recorded in the database, and the timing adjustment method 300 returns to step S32, and the next path is selected from the test pool. According to one embodiment of the present invention, since the delay of the path pattern of the selected path still exceeds the timing requirement, only by modifying the design can this violation be eliminated. According to another embodiment of the present invention, when it is determined in step S34 that the transmission delay of the path pattern of the selected path does not exceed the timing requirement, the timing adjustment method 300 executes step S35 to further determine whether the transmission delay of the worst mode of the selected path minus the timing requirement exceeds a threshold value.

[0053] According to an embodiment of the present invention, when it is determined in step S35 that Figure 2 When the worst-case propagation delay minus the timing requirement (e.g., 10) of the second path 212 exceeds the threshold value (e.g., 5), it means that the violation of the second path 212 is too large to be repaired. Therefore, a warning message will pop up on the screen, and the timing adjustment method 300 returns to step S32 to select the next path in the test pool.

[0054] According to another embodiment of the present invention, when it is determined in step S35 that Figure 2When the worst-case propagation delay minus the timing requirement (eg, 10) of the second path 212 does not exceed the threshold, the Figure 2 The worst-case maximum cell delay of each cell in the second path 212 is calculated (step S36), and updated information about the corresponding cell delay is stored in a register.

[0055] According to an embodiment of the present invention, the step of reducing the worst mode cell delay of at least one cell in the selected path is to reduce the maximum cell delay of each cell in the selected path by a ratio selected by a designer.

[0056] After step S36, the timing adjustment method 300 returns to step S32. When it is determined in step S32 that the test pool is empty, it is determined whether the register is empty (step S37), wherein the register is used to store update information about the unit delay. According to an embodiment of the present invention, when the register is empty, the timing adjustment method 300 ends and executes Figure 1 Step S13.

[0057] According to another embodiment of the present invention, when the register is not empty, the worst-case propagation delay of each path of the integrated circuit is updated according to the updated cell delay stored in the register (step S38). After updating the propagation delay of each path of the integrated circuit, the timing adjustment method 300 returns to step S31 to collect a first predetermined number of paths having propagation delays exceeding the timing requirement into a test pool.

[0058] According to some embodiments of the present invention, step S31, step S32, step S37 and step S38 are repeated for a second predetermined number of times to adjust the timing of the integrated circuit. However, to collect more (i.e., the first predetermined number) paths into the test pool, it is necessary to repeat step S31, step S32, step S37 and step S38 for more (i.e., the second predetermined number) times to complete the timing adjustment method 300.

[0059] According to one embodiment of the present invention, when the second predetermined number increases by 1, the first predetermined number also increases by 1, and the initial value of the first predetermined number is 1. According to one embodiment of the present invention, when the second predetermined number is lower than the first predetermined number, the first predetermined number remains fixed in the next repetition.

[0060] That is, the first predetermined number must be small at the beginning to adjust a small number of paths in the integrated circuit to meet the timing requirements, so that the number of repetitions of step S31, step S32, step S37 and step S38 is small. After some paths of the integrated circuit have been adjusted and there are still other paths to be adjusted, the first predetermined number can be gradually increased. For example, the first predetermined number can be 1, 2, 3, ... and so on.

[0061] When the adjustment timing method 300 is finished, execute Figure 1 Step S13 is used to record the worst-case cell delay of each cell in the integrated circuit. Since all false errors are eliminated in step S12 (i.e., the timing adjustment method 300), there are no false errors in the gate level simulation results. In other words, when it is determined in step S14 that the transfer delay of the integrated circuit exceeds the timing requirement, since the false errors have been eliminated in step S12, the errors in the gate level simulation are true errors, and the design needs to be modified so that the transfer delay can meet the timing requirement.

[0062] The present invention proposes a static timing analysis to eliminate false errors before gate level simulation, so that the design process can be shortened. The present invention also proposes a timing adjustment method to eliminate false errors. Therefore, false errors of integrated circuits can be automatically eliminated, thereby shortening the design time.

[0063] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person with ordinary knowledge in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the art can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure of some embodiments of the present disclosure. As long as the same functions can be implemented or the same results can be obtained in the embodiments described herein, they can be used according to some embodiments of the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each patent application constitutes a separate embodiment, and the scope of protection of the present disclosure also includes the combination of each patent application and the embodiment.

Claims

1. A timing adjustment method for adjusting the propagation delay of each path of an integrated circuit, wherein the timing adjustment method comprises: In a worst-case mode, determining whether a propagation delay of a selected path exceeds a timing requirement; In a path mode, determining whether the propagation delay of the selected path exceeds the timing requirement; and When the transmission delay of the selected path in the path mode does not exceed the timing requirement, reducing the worst mode cell delay of each cell in the selected path; When the transmission delay of the selected path in the path mode exceeds the timing requirement, determining whether the transmission delay of the selected path exceeds a threshold value compared with the timing requirement; When the propagation delay of the selected path does not exceed the threshold value compared with the timing requirement, reducing the cell delay of each cell of the selected path, wherein update information of the updated cell delay of at least one cell in the selected path is stored in a register; When the transfer delay of the selected path exceeds the threshold value compared with the timing requirement, a warning message is displayed and it is determined whether the transfer delay of another selected path from a test pool in the path mode exceeds the timing requirement; After the step of determining whether the transfer delay of another selected path from the test pool in the path pattern exceeds the timing requirement, determining whether the test pool is empty; When the test pool is empty, determining whether the temporary register is empty; When the test pool is not empty, selecting another selected path from the test pool; When the test pool and the register are both empty, the timing adjustment method is terminated; When the test pool is empty and the test pool is not empty, updating the propagation delay of each path of the integrated circuit in the worst mode according to the update unit delay of the register; and After the step of updating the propagation delay of each path of the integrated circuit in the worst mode, a first predetermined number of paths violating the timing requirement are collected into the test pool.

2. The timing adjustment method according to claim 1, characterized in that: A cell delay of each cell of each path is obtained by a timing signoff to determine a propagation delay of each path of the integrated circuit in the path mode, wherein a maximum cell delay and a minimum cell delay of each cell of each path are obtained by the timing signoff to determine a propagation delay of each path of the integrated circuit in the worst mode.

3. The timing adjustment method according to claim 1, characterized in that: The step of reducing the worst mode cell delay of each cell in the selected path further comprises: A maximum unit delay of the worst mode of each unit of the selected path is reduced by a ratio.

4. The timing adjustment method according to claim 1, characterized in that: Also includes: When the transfer delay of the selected path in the path pattern does not exceed the timing requirement, it is determined whether the transfer delay of another selected path from a test pool in the path pattern exceeds the timing requirement.

5. The timing adjustment method according to claim 1, wherein: Also includes: After the step of reducing the cell delay of each cell of the selected path, it is determined whether the transfer delay of another selected path from the test pool in the path pattern exceeds the timing requirement.

6. The timing adjustment method according to claim 1, wherein: The steps of determining whether the test pool is empty, determining whether the register is empty, updating the transmission delay of each path of the integrated circuit in the worst mode according to the update unit delay of the register, and collecting the first predetermined number of paths that violate the timing requirement into the test pool are repeatedly performed a second predetermined number of times.

7. The timing adjustment method according to claim 6, characterized in that: When the second predetermined number is smaller than the first predetermined number, the first predetermined number is kept fixed in the next repetition.

8. The timing adjustment method according to claim 6, wherein: When the second predetermined number increases by 1, the first predetermined number increases by 1 accordingly.

9. A time-invariant computer-readable medium for storing a plurality of program codes for determining a propagation delay of each path in an integrated circuit, wherein the program codes include a set of instructions, wherein when a computer executes the instructions, the computer performs the following method for adjusting timing, the method comprising the following steps: In a worst-case mode, determining whether a propagation delay of a selected path exceeds a timing requirement; In a path mode, determining whether the transmission delay of the selected path exceeds the timing requirement; When the transmission delay of the selected path in the path mode does not exceed the timing requirement, reducing the worst mode cell delay of each cell in the selected path; When the transmission delay of the selected path in the path mode exceeds the timing requirement, determining whether the transmission delay of the selected path exceeds a threshold value compared with the timing requirement; When the propagation delay of the selected path does not exceed the threshold value compared with the timing requirement, reducing the cell delay of each cell of the selected path, wherein update information of the updated cell delay of at least one cell in the selected path is stored in a register; When the transfer delay of the selected path exceeds the threshold value compared with the timing requirement, a warning message is displayed and it is determined whether the transfer delay of another selected path from a test pool in the path mode exceeds the timing requirement; After the step of determining whether the transfer delay of another selected path from the test pool in the path pattern exceeds the timing requirement, determining whether the test pool is empty; When the test pool is empty, determining whether the temporary register is empty; When the test pool is not empty, selecting another selected path from the test pool; When the test pool and the register are both empty, the timing adjustment method is terminated; When the test pool is empty and the test pool is not empty, updating the propagation delay of each path of the integrated circuit in the worst mode according to the update unit delay of the register; and After the step of updating the propagation delay of each path of the integrated circuit in the worst mode, a first predetermined number of paths violating the timing requirement are collected into the test pool.

10. The time-invariant computer-readable medium of claim 9, wherein: A cell delay of each cell of each path is obtained by a timing signoff to determine a propagation delay of each path of the integrated circuit in the path mode, wherein a maximum cell delay and a minimum cell delay of each cell of each path are obtained by the timing signoff to determine a propagation delay of each path of the integrated circuit in the worst mode.

11. The time-invariant computer-readable medium of claim 9, wherein: The step of reducing the worst mode cell delay of each cell in the selected path further comprises: A maximum unit delay of the worst mode of each unit of the selected path is reduced by a ratio.

12. The time-invariant computer-readable medium of claim 9, wherein: The above computer also performs the following steps: When the transfer delay of the selected path in the path pattern does not exceed the timing requirement, it is determined whether the transfer delay of another selected path from a test pool in the path pattern exceeds the timing requirement.

13. The time-invariant computer-readable medium of claim 9, wherein: The above computer also performs the following steps: After the step of reducing the cell delay of each cell of the selected path, it is determined whether the propagation delay of another selected path from the test pool in the path pattern exceeds the timing requirement.

14. The time-invariant computer-readable medium of claim 9, wherein: The steps of determining whether the test pool is empty, determining whether the register is empty, updating the transmission delay of each path of the integrated circuit in the worst mode according to the update unit delay of the register, and collecting the first predetermined number of paths that violate the timing requirement into the test pool are repeatedly performed a second predetermined number of times.

15. The time-invariant computer-readable medium of claim 14, wherein: When the second predetermined number is smaller than the first predetermined number, the first predetermined number is kept fixed in the next repetition.

16. The time-invariant computer-readable medium of claim 14, wherein: When the second predetermined number increases by 1, the first predetermined number increases by 1 accordingly.

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