Generate views using one or more neural networks

Abstract

The present invention discloses generating views using one or more neural networks, and specifically presents apparatuses, systems, and techniques for generating images or video content representing at least one perspective. In at least one embodiment, the one or more neural networks generate one or more images of one or more objects from a first perspective based at least in part on one or more images of the one or more objects from a second perspective.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] At least one embodiment relates to processing resources for performing and facilitating artificial intelligence. For example, at least one embodiment relates to a processor or computing system for training neural networks according to the various novel techniques described herein. Technical Field

[0003] As more and more image and video content is captured or generated digitally, the demand for flexibility and manipulation of this digital content is increasing accordingly. For example, a camera may be used to capture an image at a physical location, but it may be necessary to generate a version of that image that appears to have been captured from a different location or at a different perspective. While image warping has been used to handle perspective changes, perspective changes can involve rendering different parts of an object, even objects that were not previously represented, filling in or generating new image content for parts that were not visible from the previous perspective, and generating views of those objects adapted to the different perspectives. Prior art methods do not provide at least these capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Various embodiments according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0005] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and Figure 1E images showing a scene from different perspectives according to at least one embodiment;

[0006] Figure 2 A content generation system according to at least one embodiment is shown;

[0007] Figure 3 Components of a content generator according to at least one embodiment are shown;

[0008] Figure 4A 、 Figure 4B and Figure 4C A diagram illustrating an object according to at least one embodiment;

[0009] Figure 5A and Figure 5B A process for generating an image according to at least one embodiment is shown;

[0010] Figure 6A Inference and / or training logic according to at least one embodiment is shown;

[0011] Figure 6B Inference and / or training logic according to at least one embodiment is shown;

[0012] Figure 7 An example data center system is shown in accordance with at least one embodiment;

[0013] Figure 8 A computer system according to at least one embodiment is shown;

[0014] Figure 9 A computer system according to at least one embodiment is shown;

[0015] Figure 10 A computer system according to at least one embodiment is shown;

[0016] Figure 11 A computer system according to at least one embodiment is shown;

[0017] Figure 12A A computer system according to at least one embodiment is shown;

[0018] Figure 12B A computer system according to at least one embodiment is shown;

[0019] Figure 12C A computer system according to at least one embodiment is shown;

[0020] Figure 12D A computer system according to at least one embodiment is shown;

[0021] Figure 12E and Figure 12F illustrates a shared programming model according to at least one embodiment;

[0022] Figure 13 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0023] Figures 14A-14B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0024] Figures 15A-15B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0025] Figure 16 A computer system according to at least one embodiment is shown;

[0026] Figure 17A A parallel processor according to at least one embodiment is shown;

[0027] Figure 17B shows a partition unit according to at least one embodiment;

[0028] Figure 17Cillustrates a processing cluster according to at least one embodiment;

[0029] Figure 17D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0030] Figure 18 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0031] Figure 19 A graphics processor according to at least one embodiment is shown;

[0032] Figure 20 shows a microarchitecture of a processor according to at least one embodiment;

[0033] Figure 21 A deep learning application processor according to at least one embodiment is shown;

[0034] Figure 22 An example neuromorphic processor is shown in accordance with at least one embodiment;

[0035] Figure 23 and Figure 24 illustrates at least a portion of a graphics processor according to at least one embodiment;

[0036] Figure 25 illustrates at least a portion of a graphics processor core according to at least one embodiment;

[0037] Figures 26A-26B illustrates at least a portion of a graphics processor core according to at least one embodiment;

[0038] Figure 27 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0039] Figure 28 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0040] Figure 29 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0041] Figure 30 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0042] Figure 31 is an example data flow diagram for an advanced computing pipeline according to at least one embodiment;

[0043] Figure 32is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline in accordance with at least one embodiment;

[0044] Figure 33A A data flow diagram illustrating a process for training a machine learning model according to at least one embodiment; and

[0045] Figure 33B is an example illustration of a client-server architecture for enhancing an annotation tool with a pre-trained annotation model, according to at least one embodiment. DETAILED DESCRIPTION

[0046] In at least one embodiment, at least one image, video frame, or other instance of image content may be captured, generated, or otherwise obtained. In at least one embodiment, the “image” may represent one or more objects in a scene or environment from a certain perspective. In at least one embodiment, image 100 (such as Figure 1A ) can represent one or more objects, such as background objects, enemies 102, and a portion of a player avatar 104 for a game frame, from this perspective. In at least one embodiment, the perspective can be determined based on the position and orientation of a physical camera capturing the representation of the scene, or based on the position and orientation of a virtual camera used to generate the representation, among other such options. In at least one embodiment, this can be a single image with no other images or video frames representing objects in the scene or environment.

[0047] In at least one embodiment, it may be desirable to obtain versions of the image representing the scene from different perspectives. In at least one embodiment, this may include obtaining Figure 1BThe player avatar is then presented with a third-person perspective, as shown in image 120, rather than the first-person perspective shown in image 100. In at least one embodiment, this may include positioning the virtual camera at a greater distance from one or more objects in the scene, such as enemies and background objects. In at least one embodiment, this may also include positioning the virtual camera behind the player avatar, which results in generating a representation 122 of the avatar that was not previously represented in first-person view image 100. In at least one embodiment, this may involve determining appropriate sizes for various objects, such as enemies and background objects, for the new perspective. In at least one embodiment, this may also include generating a representation of the player avatar 122, and in this case, another player's avatar 124. In at least one embodiment, these representations should not only be generated at an appropriate size for this perspective, but also with an appearance appropriate for these objects or elements, even if the original image 100 did not include a similar view of these objects. In at least one embodiment, this may then involve generating graphical content that may be appropriate for these player avatars 122, 124, for this perspective. In at least one embodiment, other video frames in the video file may provide views of the avatars that are useful for generating these representations, but there may be no such video frames in the file, or the image may be a single image with no other object references available. In at least one embodiment, one or more neural networks may be used to infer how to render these objects from the new perspective and may also generate any additional image content necessary to provide a complete and realistic representation of these objects from the new perspective. In at least one embodiment, the initial image may be the third-person perspective image 120, and the process is used to generate the first-person perspective image 104.

[0048] In at least one embodiment, various other perspectives can be selected for image generation. In at least one embodiment, this can include selecting different third person views, such as Figure 1C , where a more complete representation of these avatars 142, 144 is visible. In at least one embodiment, the perspective can also be slightly higher in the environment to provide a different view of the environment. In at least one embodiment, a similar third person perspective can be generated, such as Figure 1D, but in that image the new perspective corresponds to the perspective of another player's avatar 164, rather than the first player's avatar 162. In at least one embodiment, this may be desirable when providing streaming video of a game, and enabling a viewer to switch between different players' views when those views are not otherwise available or selectable from the current video stream. In at least one embodiment, this approach may also enable views that may not be available from within the game or video, such as game content that is only available from the perspective of a player's character. In at least one embodiment, this may be desirable for videos or movies that only take snapshots of scenes from a single perspective, in order to obtain different perspectives of those scenes. In at least one embodiment, it may be desirable to obtain views of a scene from the perspectives of different characters or objects in the scene. In at least one embodiment, other views may also be available, such as a top-down perspective, such as Figure 1E 180 in . In at least one embodiment, any point in the environment can be used as a viewpoint or location for a virtual camera, although the accuracy of the generated image may decrease as such view changes relative to the original viewpoint increase. In at least one embodiment, a fixed set of viewpoints may be provided to enable a user to obtain different perspectives of a scene, but with greater control over the accuracy or realism of those views. In at least one embodiment, the availability of different views may improve the viewing experience and may also provide increased replay value because repeated viewings may be made from different viewpoints. In at least one embodiment, different views may also be valuable for replay or highlighting of a scene, such as providing additional information or context that may not be visible from the original viewpoint.

[0049] In at least one embodiment, the image content may be digital image content captured by a physical camera. In at least one embodiment, the image content may include animation, virtual reality (VR), augmented reality (AR), game content, or other digital content generated by an image or video generation system. In at least one embodiment, this may include representations of various types of features or objects, such as players or non-player characters (NPCs), weapons, collectibles, scenery, environmental objects (e.g., doors or rocks), or other such objects. In at least one embodiment, the image content may be captured using a camera such as Figure 2 The content server 220 shown in the illustrated system 200 may generate or otherwise provide the content.

[0050] In at least one embodiment, the content may be provided or rendered locally on the client device 202. In at least one embodiment, at least a portion of the content may be provided by a content server 220 (such as a game server or provider system) over at least one network 240, such as Figure 2, as shown in the system architecture 200. In at least one embodiment, the content to be presented may include various types of content, such as virtual reality (VR), augmented reality (AR), images, text, audio, tactile, or video content. In at least one embodiment, the client device 202 may include or comprise a device such as a desktop computer, a laptop computer, a game console, a smart phone, a tablet computer, a VR head-mounted display, AR goggles, a wearable computer, or a smart TV. In at least one embodiment, a content application 224 (e.g., a game or streaming application) executed on a content server 220 may initiate a session associated with at least the client device 202, such as by utilizing a session manager 226 and user data stored in a user database 234, and if required by this type of content or platform, may be rendered using a rendering engine 228 and transmitted to the client device 202 using an appropriate transmission manager 222. In at least one embodiment, a client device 202 receiving the content may provide the content to a corresponding content presentation application 204, which may also or alternatively include a rendering engine 210 for rendering at least some of the content for presentation via the client device 202, such as presenting video content via a display 206 and presenting audio (such as voice and music) via at least one audio playback device 208 (such as a speaker or headphones). In at least one embodiment, at least some of the content may already be stored on the client device 202, rendered on the client device 202, or accessible to the client device 202, thereby eliminating the need for transmission over the network 240. In at least one embodiment, a transmission mechanism such as data streaming may be used to transmit the content from the server 220 or content database 234 to the client device 202.

[0051] In at least one embodiment, the content application 224 includes a content manager 230 that can analyze content before transmitting it to the client device 202. In at least one embodiment, the content manager 230 can also include, or work in conjunction with, one or more view managers 232 that can generate image or video content from one or more specified perspectives. In at least one embodiment, the view manager 232 includes one or more neural networks that can analyze image or video content and generate versions of the image or video content in which one or more objects are represented from different perspectives. In at least one embodiment, these views can be generated automatically or in response to viewer input, among other such options. In at least one embodiment, the analysis of image data and the generation of image content from different perspectives can be performed or at least directed using a view manager on the client device 202 or a view manager 252 provided by a third-party content service 250 or provider system. In at least one embodiment, the view manager can include any combination of hardware and software that can accept and analyze image-related content and generate image-related content from one or more additional perspectives. In at least one embodiment, generated image or video content showing the object from different perspectives may also be provided or made available to other client devices 260, such as for download or streaming from a media source storing a copy of the image or video content.

[0052] In at least one embodiment, Figure 3 As shown in the architecture 300 of , a content generator 304 can be used to generate image or video content including representations of objects from different perspectives. In at least one embodiment, the content generator 304 can be part of a content streaming system, service, module or component, or used by a content streaming system, service, module or component. In at least one embodiment, one or more images 302 or video frames can be provided as input to the content generator 304. In at least one embodiment, these can be captured or generated images, including single images, image sequences, or frames of a video file or video stream, among other such options. In at least one embodiment, each input image will be processed by an image partitioning module 306, which can partition the image into a determined number of regions, such as can correspond to four regions (e.g., quadrants), such as top left, top right, bottom left, and bottom right.

[0053] In at least one embodiment, the image data (before or after segmentation) can be provided as input to a feature extraction module 308. In at least one embodiment, the module can utilize an instance segmentation algorithm or model to identify different objects in the input image or video frame. In at least one embodiment, this can include identifying the type of object and discriminatively identifying each instance of that type of object in the image. In at least one embodiment, instance segmentation can be performed using a convolutional neural network (CNN), such as a three-dimensional (3D-CNN) or region-based (R-CNN). In at least one embodiment, this can include identifying various types of objects, such as those related to weapons, collectibles, background objects, vehicles, non-player characters, and other such object types. In at least one embodiment, instance segmentation will output a set of features for each of these detected objects. In at least one embodiment, these can include any type of features determined to represent the respective object in some way, such as differentiating between different instances of the same type of object in the image.

[0054] In at least one embodiment, the features output from the feature extraction module 308 can be converted into one or more feature vectors of a specified format or pattern. In at least one embodiment, a pattern such as a JavaScript Object Notation (JSON) pattern can be used, which stores data as key-value pairs, for example, where each object can be a key in the pattern and possible interactions can be set to the value of the key. In at least one embodiment, the determination of the object can enable interactions to be determined from the pattern. In at least one embodiment, data from feature vectors that conform to the pattern can be encoded into a latent space. In at least one embodiment, there may be different converters for various types of objects that can be identified. In at least one embodiment, each type of input is converted into a feature vector of a specific type, such as a text feature vector that adheres to a specified pattern.

[0055] In at least one embodiment, these feature vectors that follow a common pattern can be encoded into a latent space. In at least one embodiment, this encoding can be performed by at least one neural network-based encoder, which can be part of or correspond to at least one variational autoencoder (VAE) 310. In at least one embodiment, the encoder 310 can be a multi-dimensional state encoder with cache capabilities. In at least one embodiment, the encoder takes these feature vectors as input and encodes them into a single or common latent space. In at least one embodiment, the VAE 310 can determine whether it is feasible to generate image or video content for one or more viewpoints. In at least one embodiment, the VAE can be a deep learning model trained using unsupervised learning to understand and encode object views. In at least one embodiment, this unsupervised training will not utilize labeled training data, or if available, some amount of labeled training data can be utilized. In at least one embodiment, the VAE 310 is trained to capture information about these views and encode this information into a latent space. In at least one embodiment, this latent space will represent a basic understanding of the input image and all of its components. In at least one embodiment, the encodings stored in this latent space may also include features or data related to the current object state, historical data, current player state or abilities, instance identifiers of objects, game themes, types of scenes or levels, the direction and position of the player, and the direction and position of the object. In at least one embodiment, there may be multiple VAEs, each trained to determine objects and extract features of different types of objects. In at least one embodiment, a mixture of experts (MoE)-based approach may be used to select the VAE that produces the most accurate results for a particular type of object or feature. In at least one embodiment, any new or additional views or partial views learned or determined by the VAE 310 when analyzing a video or image may be encoded into this latent space. In at least one embodiment, these encodings may include information about which views are associated with different perspectives.

[0056] In at least one embodiment, the encoding of the latent space can be provided as input to a generator 312 or generative model. In at least one embodiment, the generator can include a generative adversarial network (GAN). In at least one embodiment, the decoder portion of the VAE 310 can be used, which can receive the encoding from the encoder portion of the VAE 310. In at least one embodiment, the generator 312 can also receive as input a specified viewpoint of the image to be generated and at least one input image 302 showing the initial viewpoint of the objects. In at least one embodiment, cached image data can also be provided as input from a local cache 320, as will be discussed later herein with respect to video or image sequences or collections. In at least one embodiment, the GAN 312 can regenerate content from the input image 302, but represent the content from a different viewpoint in the output image 318, appropriately preserving the original features from the input image 302 to generate an enhanced version as one or more output images 318.

[0057] In at least one embodiment, the generator can generate one or more images from one or more viewpoints, as specified by the provided input 314 and determined to be available for generation based on the encoding from the VAE 310 in the input latent space. In at least one embodiment, the generator 312 can generate one or more images, video frames, or video sequences for each such viewpoint or at least one determined or specified viewpoint. In at least one embodiment, if a potential viewpoint fails to generate a generated image with a minimum confidence, is not sufficiently different from the current viewpoint, or fails to meet at least one image generation criterion, then the potential viewpoint will not be used to generate content. In at least one embodiment, the one or more generators 312 can generate output images 318 from the one or more viewpoints, from which a viewer can select. In at least one embodiment, a certain amount of post-processing can be performed, such as to change the resolution or color depth of the image, or to format the content in a specific format, among other such processing options.

[0058] In at least one embodiment, the image 400 may be divided into two or more regions, such as Figure 4AAs shown. In at least one embodiment, this can include any suitable number of regions, and the number of regions can depend at least in part on the type of image or video content. In at least one embodiment, this can include two or four regions for still images or standard video, or six regions for 360 degree content, such as can be mapped to a cube map for image generation. In at least one embodiment, a different model can be trained for each image region. In at least one embodiment, a set of points 402, 404, 406 can be provided from which a user or viewer can select to render the image or video content from a perspective based on the position of that point relative to the scene. In at least one embodiment, the content of each region of the image can be inferred using a corresponding generator model based on the selected point. In at least one embodiment, grouping objects by quadrants can simplify image generation. In at least one embodiment, a user or viewer may be able to select any point in the virtual three dimensional space of the scene or environment represented in the image content. In at least one embodiment, generating image content from different perspectives can result in one or more parts of an object being represented in an image for which there is no reference image data. In at least one embodiment, this can include Figure 4B Take an object, such as cube 430, in the front view and change it to Figure 4C 460 in a slightly perspective view of the cube 460 in FIG. In at least one embodiment, shaded areas 462 corresponding to the sides of the cube will be represented in the generated image, but those faces were not represented in the previous image. In at least one embodiment, the generative model must then reason about this image data. In at least one embodiment, if the image is one of a sequence or stream, the image content of the sides of the (or another) cube can be stored in a cache, as described with respect to FIG. Figure 3 As discussed. In at least one embodiment, this information can be extracted from the cache (if available) and used to fill in these areas. In at least one embodiment, generating a video or image sequence from a new perspective may always go through at least two passes, where the first pass will cause image information of the represented object to be stored in the cache, and the second pass will use this cached information to generate new image or video content from the specified perspective. In at least one embodiment, this second pass will use this information to attempt to infer any missing areas. In at least one embodiment, this first pass may also attempt to fill in these areas, where the second pass replaces any of these filled areas where actual image content exists, and then updates any remaining filled areas.

[0059] In at least one embodiment, image reconstruction from different viewpoints can utilize only available information from one or more input images. In at least one embodiment, this can result in some loss of information from other directions. In at least one embodiment, a trained neural network can reason about how to change the representation of an object from different viewpoints. In at least one embodiment, this is particularly challenging for photographs or single images where data only exists for a single viewpoint, and image generation or inpainting is used to fill in areas that are only visible from a different viewpoint. In at least one embodiment, a neural network trained to perform extrapolation based on, for example, portions of an object that are visible or available in a cache can be used to generate one or more additional portions of the object now visible in the image from the new viewpoint. In at least one embodiment, extrapolation for filling in areas can be preferred over warping the image to fill in newly visible object areas.

[0060] In at least one embodiment, a region- or quadrant-based generative process works well for groups of objects. In at least one embodiment, an image comprising a representation of a landscape can be provided as input. In at least one embodiment, the image may contain multiple people viewing the landscape. In at least one embodiment, the perspective can be changed to that of one of these people. This not only provides a representation from the visitor's perspective, but also eliminates the visibility of all other people in the image from this new perspective. In at least one embodiment, this may require the generative network to generate or inpaint portions of the image that were previously obscured by the person. In at least one embodiment, the model for the quadrant containing the points corresponding to the new perspective can then begin generating new images from that perspective, with models for other quadrants subsequently generated. In at least one embodiment, a single model can be used for the entire image without dividing it into separate segments, regions, or quadrants. In at least one embodiment, multiple images can be generated from multiple perspectives and presented to a user or other such entity for selection. In at least one embodiment, a single model can be used to provide these different perspectives. In at least one embodiment, multiple models can be run in parallel to provide these different perspectives.

[0061] In at least one embodiment, such a process can leverage deep learning to alter the perspective of image or video content. In at least one embodiment, applying such alterations, particularly to photo-based content captured with a physical camera, is otherwise non-trivial. In at least one embodiment, there may not be sufficient available image content in the content to generate a version with the target perspective. In at least one embodiment, ensuring that the generated content from different perspectives is sufficiently similar in appearance to the objects in the original captured image can also be challenging. In at least one embodiment, a neural network, such as a variational autoencoder (VAE), can be used, which can group content based on target locations and use this grouping to condition the latent space. In at least one embodiment, the neural network can also use the filtered position data and the input content as generation constraints to reconstruct the content from the content. In at least one embodiment, the image generation can provide consistency with the input image data, including extrapolation in every direction of a cubemap or other such representation. In at least one embodiment, a GAN can also be used to ensure that the final output image or frame adheres to similarity constraints with respect to the input image data.

[0062] In at least one embodiment, generating output video based on input video can present additional challenges because the perspective of the cameras in a scene may not be consistent across the scene. In at least one embodiment, the camera position may move across the scene, such as for panning motion, or the perspective may switch back and forth between different perspectives, such as for a multi-camera scene. In at least one embodiment, this can result in different objects being represented at different times and with different perspectives or visible areas. In at least one embodiment, features of each input video frame may be encoded, and this information may be cached. In at least one embodiment, this cache may store all image data obtained for each object throughout the video clip, and this cached data may be used as constraints for generating video frames, including representations of these objects. In at least one embodiment, each frame is re-encoded for a new focal point, and this information may also be cached so that the newly generated image data can also be used as constraints for other representations of these objects when they are visible in other video frames. In at least one embodiment, this may include, for example, ensuring that the representation of a newly added player avatar in a third-person perspective remains consistent across different scenes that include the player avatar. In at least one embodiment, a first generated video frame may include an extrapolation of an object, where the actual image content of the extrapolated area will come into view in a later video frame. In at least one embodiment, to ensure consistency, this actual image content may be included in at least a second pass, where any remaining areas including the actual image content are extrapolated from the view of the object. In at least one embodiment, extrapolation may not be performed on the first pass, but only on the second pass after all image content has been determined for the object represented in the video. In at least one embodiment, two generation passes may be sufficient for this approach, but additional passes may be used to enhance consistency if necessary. In at least one embodiment, performing extrapolation only after the first pass based on observed image data can reduce the amount of noise present in the final output video. In at least one embodiment, the first pass can also be used to attempt to capture any camera motion to be represented in the output video. This information can then be encoded into the associated latent space to serve as a constraint for generation. In at least one embodiment, the results of the first pass can include directional information for each frame, as well as any impact on the selected viewing angle used for generation. In at least one embodiment, this approach can also be used for other image sequences, such as animated .gif images.

[0063] In at least one embodiment, perspective changes can also be implemented for 360-degree content. In at least one embodiment, image content in all directions will already be available as part of the content. In at least one embodiment, the change in perspective can then be used to generate a new 360-degree view, such as based on a new cubemap with slight modifications based on this change in perspective. In at least one embodiment, transitioning from a first-person perspective to a third-person perspective in 360-degree content can be challenging if the content does not already include a representation of that person. In at least one embodiment, auxiliary data can be accepted as input, such as to provide a three-dimensional model or representation of a person or character for the third-person perspective.

[0064] In at least one embodiment, the process 500 for generating image content may be performed as follows: Figure 5A As shown. In at least one embodiment, at least one input image representing one or more objects in a scene from a first perspective may be received 502. In at least one embodiment, there may be multiple images of a video sequence or video frame, as well as other types of image content. In at least one embodiment, an object detector model may be used to determine 504 one or more objects represented in the input image. In at least one embodiment, these objects may be determined for different portions (e.g., quadrants) of the input image. In at least one embodiment, features of these objects may be encoded 506 into a latent space using at least one encoder, such as a variational autoencoder (VAE). In at least one embodiment, the encoder may also determine 508 that a probability of reconstruction from a second perspective at least satisfies a minimum probability threshold. In at least one embodiment, multiple perspectives may be considered. In at least one embodiment, the input image and an indication of the second perspective may be provided 510 as input to a generative model, such as a conditional generative adversarial network (GAN), and the latent space, which may serve as a constraint on image generation. In at least one embodiment, one or more output images representing one or more objects of the input image from a second perspective may be generated 512, wherein new image content is generated for portions of those objects not otherwise represented in the one or more input images. In at least one embodiment, any generated output images may then be provided 514 for presentation for other such purposes.

[0065] In at least one embodiment, the Figure 5BA process 550 for generating an image is shown being performed. In at least one embodiment, one or more objects may be identified 552 in one or more images from a first perspective. In at least one embodiment, data for those identified objects may be provided 554 as input to one or more neural networks. In at least one embodiment, one or more images or video frames representing those identified objects from a second perspective may be generated 506. In at least one embodiment, multiple images may be generated as part of an image sequence or video, and multiple images may be generated for more than one perspective. In at least one embodiment, at least some portions of those objects may be generated based on portions of those objects visible in one or more input images.

[0066] Reasoning and training logic

[0067] Figure 6A Inference and / or training logic 615 is shown for performing inference and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided.

[0068] In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to, code and / or data storage 601 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 615 may include or be coupled to code and / or data storage 601 for storing graph code or other software to control timing and / or sequence, wherein weights and / or other parameter information are loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the code and / or data storage 601 stores input / output data during training and / or inference using aspects of one or more embodiments and / or weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of weight parameters. In at least one embodiment, any portion of code and / or data storage 601 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0069] In at least one embodiment, any portion of code and / or data storage 601 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 601 may be cache memory, dynamic random addressable memory ("DRAM"), static random addressable memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 601 is internal or external to a processor, e.g., or composed of DRAM, SRAM, flash memory, or some other type of storage, may depend on the available storage space on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0070] In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to, code and / or data storage 605 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in accordance with aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, the code and / or data storage 605 stores weight parameters and / or input / output data for each layer of the neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, the training logic 615 may include or be coupled to code and / or data storage 605 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 605 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 605 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 605 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 605 is internal or external to the processor, for example, whether it is composed of DRAM, SRAM, flash memory, or some other type of storage, depends on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or some combination of these factors.

[0071] In at least one embodiment, code and / or data store 601 and code and / or data store 605 may be separate storage structures. In at least one embodiment, code and / or data store 601 and code and / or data store 605 may be the same storage structure. In at least one embodiment, code and / or data store 601 and code and / or data store 605 may be partially the same storage structure and partially separate storage structures. In at least one embodiment, any portion of code and / or data store 601 and code and / or data store 605 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0072] In at least one embodiment, inference and / or training logic 615 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 610 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 620, which are functions of input / output and / or weight parameter data stored in code and / or data storage 601 and / or code and / or data storage 605. In at least one embodiment, activations stored in activation storage 620 are generated according to linear algebra and / or matrix-based mathematics performed by ALU 610 in response to executing instructions or other code, with weight values ​​stored in code and / or data storage 605 and / or in code and / or data storage 601 used as operands, as well as other values ​​such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 605 or code and / or data storage 601 or other on-chip or off-chip storage.

[0073] In at least one embodiment, one or more ALUs 610 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 610 may be external to the processor or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, one or more ALUs 610 may be included within an execution unit of a processor or otherwise included in an ALU bank accessible by the execution unit of the processor, which may be within the same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 601, code and / or data storage 605, and activation storage 620 may be on the same processor or other hardware logic device or circuit, while in another embodiment, they may be on different processors or other hardware logic devices or circuits, or on some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 620 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0074] In at least one embodiment, activation storage 620 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 620 may be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, activation storage 620 may be internal or external to the processor, for example, or comprise DRAM, SRAM, flash memory, or other storage types, based on available on-chip versus off-chip storage, latency requirements for performing training and / or inference functions, batch sizes of data used in inferring and / or training neural networks, or some combination of these factors. In at least one embodiment, Figure 6A The inference and / or training logic 615 shown in FIG can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 6A The illustrated inference and / or training logic 615 may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware, such as a field programmable gate array (“FPGA”).

[0075] Figure 6B Inference and / or training logic 615 is shown in accordance with at least one embodiment. In at least one embodiment, inference and / or training logic 615 may include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise used exclusively in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 6B The inference and / or training logic 615 shown in FIG can be used in conjunction with an application specific integrated circuit (ASIC), such as the ASIC from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 6BThe inference and / or training logic 615 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 615 includes, but is not limited to, code and / or data storage 601 and code and / or data storage 605, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 6B In at least one embodiment shown in FIG, code and / or data storage 601 and code and / or data storage 605 are each associated with dedicated computing resources, such as computing hardware 602 and computing hardware 606, respectively. In at least one embodiment, computing hardware 602 and computing hardware 606 each include one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 601 and code and / or data storage 605, respectively, with the results of the functions being stored in activation storage 620.

[0076] In at least one embodiment, each of the code and / or data stores 601 and 605 and the corresponding computing hardware 602 and 606 corresponds to a different layer of a neural network, such that activations from one "storage / compute pair 601 / 602" of the code and / or data store 601 and computing hardware 602 are provided as input to the next "storage / compute pair 605 / 606" of the code and / or data store 605 and computing hardware 606, reflecting the conceptual organization of the neural network. In at least one embodiment, each storage / compute pair 601 / 602 and 605 / 606 can correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) can be included in the inference and / or training logic 615 after or in parallel with the storage / compute pairs 601 / 602 and 605 / 606.

[0077] Data Center

[0078] Figure 7 An example data center 700 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0079] In at least one embodiment, Figure 7As shown, the data center infrastructure layer 710 may include a resource coordinator 712, group computing resources 714, and node computing resources ("node CRs") 716(1)-716(N), where "N" represents a positive integer. In at least one embodiment, the node CRs 716(1)-716(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules. In at least one embodiment, one or more of the node CRs 716(1)-716(N) may be servers having one or more of the above-mentioned computing resources.

[0080] In at least one embodiment, the grouped computing resources 714 may include separate groups of node CRs housed in one or more racks (not shown), or may include many racks (also not shown) housed in data centers at various geographic locations. The separate groups of node CRs within the grouped computing resources 714 may include computing, networking, memory, or storage resources that may be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs comprising a CPU or processor may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0081] In at least one embodiment, resource coordinator 712 may configure or otherwise control one or more nodes CR 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource coordinator 712 may comprise a software design infrastructure ("SDI") management entity for data center 700. In at least one embodiment, resource coordinator 712 may comprise hardware, software, or some combination thereof.

[0082] In at least one embodiment, Figure 7As shown, framework layer 720 includes a job scheduler 722, a configuration manager 724, a resource manager 726, and a distributed file system 728. In at least one embodiment, framework layer 720 may include a framework that supports software 732 of software layer 730 and / or one or more applications 742 of application layer 740. In at least one embodiment, software 732 or applications 742 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 720 may include, but is not limited to, a free and open source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark"), which can utilize distributed file system 728 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 732 may include a Spark driver to facilitate scheduling workloads supported by various layers of data center 700. In at least one embodiment, configuration manager 724 may be capable of configuring different layers, such as software layer 730 and framework layer 720, including Spark and a distributed file system 728 for supporting large-scale data processing. In at least one embodiment, the resource manager 726 can manage clustered or grouped computing resources that are mapped to or allocated to support the distributed file system 728 and the job scheduler 722. In at least one embodiment, the clustered or grouped computing resources can include grouped computing resources 714 on the data center infrastructure layer 710. In at least one embodiment, the resource manager 726 can coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0083] In at least one embodiment, the software 732 included in the software layer 730 may include software used by at least a portion of the node CRs 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 728 of the framework layer 720. The one or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0084] In at least one embodiment, the one or more applications 742 included in the application layer 740 may include one or more types of applications used by at least a portion of the node CRs 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 728 of the framework layer 720. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0085] In at least one embodiment, any of configuration manager 724, resource manager 726, and resource coordinator 712 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 700 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0086] In at least one embodiment, the data center 700 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to the data center 700. In at least one embodiment, using the weight parameters calculated using one or more training techniques described herein, a trained machine learning model corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to the data center 700.

[0087] In at least one embodiment, a data center can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0088] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6BProvides details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be Figure 7 for use in a system for inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function and / or architecture, or a neural network use case as described herein.

[0089] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these graphs to generate one or more images or video frames for one or more interactions available with one or more objects. This logic can be used with the components of these graphs to generate one or more images or video frames for one or more viewpoints.

[0090] Computer system

[0091] Figure 8 800 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include execution units to execute instructions. In at least one embodiment, in accordance with the present disclosure, such as the embodiments described herein, computer system 800 may include, but is not limited to, components such as processor 802, whose execution units include logic to execute algorithms for processing data. In at least one embodiment, computer system 800 may include a processor such as the Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 800 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0092] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0093] In at least one embodiment, the computer system 800 may include, but is not limited to, a processor 802, which may include, but is not limited to, one or more execution units 808 to perform machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, the computer system 800 is a single-processor desktop or server system, but in another embodiment, the computer system 800 may be a multi-processor system. In at least one embodiment, the processor 802 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 802 may be coupled to a processor bus 810, which may transmit data signals between the processor 802 and other components in the computer system 800.

[0094] In at least one embodiment, processor 802 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 804. In at least one embodiment, processor 802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 802. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 806 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0095] In at least one embodiment, an execution unit 808, including but not limited to logic to perform integer and floating point operations, is also located in the processor 802. In at least one embodiment, the processor 802 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 808 may include logic for processing a packed instruction set 809. In at least one embodiment, by including the packed instruction set 809 in the instruction set of the general-purpose processor, and the associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 802. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may not require transferring smaller units of data on the processor's data bus to perform one or more operations one data element at a time.

[0096] In at least one embodiment, execution unit 808 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, computer system 800 may include, but is not limited to, memory 820. In at least one embodiment, memory 820 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 820 may store instructions 819 and / or data 821 represented by data signals that may be executed by processor 802.

[0097] In at least one embodiment, a system logic chip can be coupled to the processor bus 810 and the memory 820. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 816, and the processor 802 can communicate with the MCH 816 via the processor bus 810. In at least one embodiment, the MCH 816 can provide a high-bandwidth memory path 818 to the memory 820 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 816 can initiate data signals between the processor 802, the memory 820, and other components in the computer system 800, and bridge data signals between the processor bus 810, the memory 820, and the system I / O interface 822. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 816 can be coupled to the memory 820 via the high-bandwidth memory path 818, and the graphics / video card 812 can be coupled to the MCH 816 via an Accelerated Graphics Port ("AGP") interconnect 814.

[0098] In at least one embodiment, the computer system 800 may utilize a system I / O interface 822, which is a proprietary hub interface bus that couples the MCH 816 to an I / O controller hub ("ICH") 830. In at least one embodiment, the ICH 830 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 820, chipset, and processor 802. Examples may include, but are not limited to, an audio controller 829, a firmware hub ("Flash BIOS") 828, a wireless transceiver 826, a data store 824, a legacy I / O controller 823 including a user input and keyboard interface 825, a serial expansion port 827 (e.g., a universal serial bus (USB)), and a network controller 834. The data store 824 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0099] In at least one embodiment, Figure 8 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 8 An exemplary system on a chip (SoC) may be shown. In at least one embodiment, Figure 8The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 800 are interconnected using a Compute Express Link (CXL) interconnect.

[0100] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Provides details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be Figure 8 for use in a system for inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function and / or architecture, or a neural network use case as described herein.

[0101] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0102] Figure 9 is a block diagram illustrating an electronic device 900 for utilizing a processor 910 in accordance with at least one embodiment. In at least one embodiment, the electronic device 900 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0103] In at least one embodiment, the system 900 may include, but is not limited to, a processor 910 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, the processor 910 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Figure 9 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 9 An exemplary system on a chip (SoC) may be shown. In at least one embodiment, Figure 9 The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 9 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0104] In at least one embodiment, Figure 9 The system may include a display 924, a touch screen 925, a touchpad 930, a near field communication unit ("NFC") 945, a sensor hub 940, a thermal sensor 946, a fast chipset ("EC") 935, a trusted platform module ("TPM") 938, a BIOS / firmware / flash memory ("BIOS, FW Flash") 922, a DSP 960, a drive 920 (e.g., a solid-state disk ("SSD") or a hard disk drive ("HDD")), a wireless local area network unit ("WLAN") 950, a Bluetooth unit 952, a wireless wide area network unit ("WWAN") 956, a global positioning system (GPS) 955, a camera ("USB 3.0 camera") 954 (e.g., a USB 3.0 camera), and / or a low-power double data rate ("LPDDR") memory unit ("LPDDR3") 915 implemented using, for example, the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0105] In at least one embodiment, other components may be communicatively coupled to the processor 910 through the components described herein. In at least one embodiment, an accelerometer 941, an ambient light sensor (“ALS”) 942, a compass 943, and a gyroscope 944 may be communicatively coupled to the sensor hub 940. In at least one embodiment, a thermal sensor 939, a fan 937, a keyboard 936, and a touchpad 930 may be communicatively coupled to the EC 935. In at least one embodiment, a speaker 963, an earpiece 964, and a microphone (“mic”) 965 may be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 962, which in turn may be communicatively coupled to the DSP 960. In at least one embodiment, the audio unit 962 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a SIM card (“SIM”) 957 may be communicatively coupled to the WWAN unit 956. In at least one embodiment, components such as the WLAN unit 950 and the Bluetooth unit 952 and the WWAN unit 956 may be implemented as a next generation form factor (NGFF).

[0106] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Provides details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be Figure 9for use in a system for inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function and / or architecture, or a neural network use case as described herein.

[0107] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0108] Figure 10 A computer system 1000 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1000 is configured to implement the various processes and methods described throughout this disclosure.

[0109] In at least one embodiment, computer system 1000 includes, but is not limited to, at least one central processing unit ("CPU") 1002 connected to a communication bus 1010 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1000 includes, but is not limited to, main memory 1004 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data may be stored in main memory 1004 in the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1022 provides an interface to other computing devices and networks for receiving data from computer system 1000 and transmitting data to other systems.

[0110] In at least one embodiment, computer system 1000 includes, but is not limited to, input device 1008, parallel processing system 1012, and display device 1006, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diodes ("LEDs"), plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1008 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the aforementioned modules can be located on a single semiconductor platform to form a processing system.

[0111] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6BProvides details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be Figure 10 for use in a system for inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function and / or architecture, or a neural network use case as described herein.

[0112] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0113] Figure 11 A computer system 1100 is shown according to at least one embodiment. In at least one embodiment, computer system 1100 includes, but is not limited to, a computer 1110 and a USB drive 1120. In at least one embodiment, computer 1110 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1110 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0114] In at least one embodiment, the USB disk 1120 includes, but is not limited to, a processing unit 1130, a USB interface 1140, and USB interface logic 1150. In at least one embodiment, the processing unit 1130 can be any instruction execution system, device, or device capable of executing instructions. In at least one embodiment, the processing unit 1130 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1130 includes an application-specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1130 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing core 1130 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0115] In at least one embodiment, USB interface 1140 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1140 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1140 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1150 can include any number and type of logic that enables processing unit 1130 to connect to a device (e.g., computer 1110) via USB connector 1140.

[0116] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Provides details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be Figure 11 for use in a system for inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function and / or architecture, or a neural network use case as described herein.

[0117] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0118] Figure 12A An exemplary architecture is shown in which multiple GPUs 1210-1213 are communicatively coupled to multiple multi-core processors 1205-1206 via high-speed links 1240-1243 (e.g., buses / point-to-point interconnects, etc.). In one embodiment, high-speed links 1240-1243 support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0119] Furthermore, in one embodiment, two or more GPUs 1210-1213 are interconnected via high-speed links 1229-1230, which may be implemented using the same or different protocols / links as used for high-speed links 1240-1243. Similarly, two or more multi-core processors 1205-1206 may be connected via high-speed link 1228, which may be a symmetric multiprocessor (SMP) bus running at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links may be used (e.g., via a common interconnect fabric) to accomplish this. Figure 12A All communications between the various system components shown in .

[0120] In one embodiment, each multi-core processor 1205-1206 is communicatively coupled to processor memory 1201-1202 via memory interconnects 1226-1227, respectively, and each GPU 1210-1213 is communicatively coupled to GPU memory 1220-1223 via GPU memory interconnects 1250-1253, respectively. Memory interconnects 1226-1227 and 1250-1253 can utilize the same or different memory access technologies. By way of example and not limitation, processor memory 1201-1202 and GPU memory 1220-1223 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the processor memory 1201-1202 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0121] As described below, although the various processors 1205-1206 and GPUs 1210-1213 may each be physically coupled to a specific memory 1201-1202, 1220-1223, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across the various physical memories. For example, the processor memories 1201-1202 may each contain 64GB of system memory address space, and the GPU memories 1220-1223 may each contain 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0122] Figure 12B1246 and the graphics acceleration module 1246. The graphics acceleration module 1246 may include one or more GPU chips integrated on a line card that is coupled to the processor 1207 via the high-speed link 1240. Alternatively, the graphics acceleration module 1246 may be integrated on the same package or chip with the processor 1207.

[0123] In at least one embodiment, the illustrated processor 1207 includes a plurality of cores 1260A-1260D, each having a translation lookaside buffer 1261A-1261D and one or more caches 1262A-1262D. In at least one embodiment, the cores 1260A-1260D may include various other components, not shown, for executing instructions and processing data. The caches 1262A-1262D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1256 may be included in the caches 1262A-1262D and shared by each group of cores 1260A-1260D. For example, one embodiment of the processor 1207 includes 24 cores, each having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. The processor 1207 and the graphics acceleration module 1246 are connected to the system memory 1214, which may include Figure 12A Processor memory 1201-1202 in.

[0124] Coherence is maintained for data and instructions stored in the various caches 1262A-1262D, 1256, and system memory 1214 via inter-core communication over a coherence bus 1264. In at least one embodiment, for example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 1264 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 1264 to snoop cache accesses.

[0125] In at least one embodiment, proxy circuitry 1225 communicatively couples graphics acceleration module 1246 to coherence bus 1264, thereby allowing graphics acceleration module 1246 to participate in a cache coherence protocol as a peer of cores 1260A-1260D. In particular, in at least one embodiment, interface 1235 provides connectivity to proxy circuitry 1225 via high-speed link 1240 (e.g., a PCIe bus, NVLink, etc.), and interface 1237 connects graphics acceleration module 1246 to link 1240.

[0126] In one implementation, the accelerator integrated circuit 1236 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1231, 1232, N of the graphics acceleration module 1246. In at least one embodiment, the graphics processing engines 1231, 1232, N may each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1231, 1232, N may comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1246 may be a GPU having multiple graphics processing engines 1231-1232, N, or the graphics processing engines 1231-1232, N may be individual GPUs integrated into a common package, line card, or chip.

[0127] In one embodiment, the accelerator integrated circuit 1236 includes a memory management unit (MMU) 1239 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1214. The MMU 1239 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 1238 stores commands and data for efficient access by the graphics processing engines 1231-1232, N. In one implementation, data stored in cache 1238 and graphics memory 1233-1234, M, is kept consistent with the core caches 1262A-1262D, 1256, and system memory 1214. As previously described, this task may be accomplished via proxy circuitry 1225 acting on behalf of cache 1238 and graphics memory 1233-1234, M (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1262A-1262D, 1256 to cache 1238 and receiving updates from cache 1238).

[0128] In at least one embodiment, a set of registers 1245 stores context data for threads executed by graphics processing engines 1231-1232, N, and context management circuitry 1248 manages thread contexts. For example, context management circuitry 1248 can perform save and restore operations to save and restore the context of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1248 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​can then be restored upon returning to context. In one embodiment, interrupt management circuitry 1247 receives and processes interrupts received from system devices.

[0129] In one implementation, the MMU 1239 translates virtual / effective addresses from the graphics processing engine 1231 into real / physical addresses in the system memory 1214. In at least one embodiment, the accelerator integrated circuit 1236 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1246 and / or other accelerator devices. The graphics accelerator module 1246 can be dedicated to a single application executing on the processor 1207, or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1231-1232, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0130] In at least one embodiment, the accelerator integrated circuit 1236 acts as a bridge to the system for the graphics acceleration module 1246 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 1236 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1231-1232, N.

[0131] Because the hardware resources of graphics processing engines 1231-1232, N are explicitly mapped into the real address space seen by host processor 1207, any host processor can directly address these resources using effective address values. One function of accelerator integrated circuit 1236 is to physically separate graphics processing engines 1231-1232, N so that they appear as independent units to the system.

[0132] In at least one embodiment, one or more graphics memories 1233-1234, M are respectively coupled to each graphics processing engine 1231-1232, N. Graphics memories 1233-1234, M store instructions and data, which are processed by each graphics processing engine 1231-1232, N. In at least one embodiment, graphics memories 1233-1234, M may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0133] In one embodiment, to reduce data traffic on link 1240, a biasing technique is used to ensure that the data stored in graphics memories 1233-1234, M is the data most frequently used by graphics processing engines 1231-1232, N, and preferably is not used (at least not frequently) by cores 1260A-1260D. Similarly, the biasing mechanism attempts to keep data needed by a core (and preferably not graphics processing engines 1231-1232, N) in the core's caches 1262A-1262D, 1256 and system memory 1214.

[0134] Figure 12C Another exemplary embodiment is shown in which an accelerator integrated circuit 1236 is integrated into the processor 1207. In this embodiment, the graphics processing engines 1231-1232, N communicate directly with the accelerator integrated circuit 1236 via the interface 1237 and the interface 1235 (which may also utilize any form of bus or interface protocol) through the high-speed link 1240. The accelerator integrated circuit 1236 can perform operations related to Figure 12B The operations described above are identical to those described above. However, due to its close proximity to the coherence bus 1264 and caches 1262A-1262D, 1256, higher throughput is possible. At least one embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which can include a programming model controlled by the accelerator integrated circuit 1236 and a programming model controlled by the graphics acceleration module 1246.

[0135] In at least one embodiment, graphics processing engines 1231-1232, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1231-1232, N, thereby providing virtualization within a VM / partition.

[0136] In at least one embodiment, graphics processing engines 1231-1232,N can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 1231-1232,N to allow each operating system to access them. For a single-partition system without a hypervisor, the operating system owns graphics processing engines 1231-1232,N. In at least one embodiment, the operating system can virtualize graphics processing engines 1231-1232,N to provide access to each process or application.

[0137] In at least one embodiment, the graphics acceleration module 1246 or individual graphics processing engines 1231-1232,N use a process handle to select a process element. In at least one embodiment, the process element is stored in the system memory 1214 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1231-1232,N (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0138] Figure 12D An exemplary accelerator integrated slice 1290 is shown. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integrated circuit 1236. The application effective address space 1282 in the system memory 1214 stores process elements 1283. In one embodiment, the process element 1283 is stored in response to a GPU call 1281 from an application 1280 executing on the processor 1207. The process element 1283 contains the process state of the corresponding application 1280. The work descriptor (WD) 1284 contained in the process element 1283 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 1284 is a pointer to a job request queue in the address space 1282 of the application.

[0139] The graphics acceleration module 1246 and / or the individual graphics processing engines 1231-1232, N can be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure for setting process state and sending WD 1284 to the graphics acceleration module 1246 to start a job in a virtualized environment can be included.

[0140] In at least one embodiment, a dedicated process programming model is implementation-specific. In this model, a single process owns a graphics acceleration module 1246 or an individual graphics processing engine 1231. When a graphics acceleration module 1246 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 1236 for the owned partition. When a graphics acceleration module 1246 is assigned, the operating system initializes the accelerator integrated circuit 1236 for the owned process.

[0141] In operation, the WD fetch unit 1291 in the accelerator integrated slice 1290 fetches the next WD 1284, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 1246. Data from the WD 1284 can be stored in registers 1245 and used by the MMU 1239, interrupt management circuitry 1247, and / or context management circuitry 1248, as shown. For example, one embodiment of the MMU 1239 includes segment / page roaming circuitry for accessing segment / page tables 1286 within the OS virtual address space 1285. The interrupt management circuitry 1247 can process interrupt events 1292 received from the graphics acceleration module 1246. When executing graphics operations, the effective addresses 1293 generated by the graphics processing engines 1231-1232, N are converted into real addresses by the MMU 1239.

[0142] In one embodiment, the same set of registers 1245 is replicated for each graphics processing engine 1231-1232, N, and / or graphics acceleration module 1246, and the registers 1245 can be initialized by the hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 1290. Example registers that can be initialized by the hypervisor are shown in Table 1.

[0143]

[0144]

[0145] Example registers that may be initialized by the operating system are shown in Table 2.

[0146]

[0147] In at least one embodiment, each WD 1284 is specific to a particular graphics acceleration module 1246 and / or graphics processing engine 1231-1232, N. It contains all the information necessary for the graphics processing engine 1231-1232, N to complete the work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0148] Figure 12E1296 , which virtualizes the graphics acceleration module engine for the operating system 1295.

[0149] In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 1246. There are two programming models in which the graphics acceleration module 1246 is shared by multiple processes and partitions, namely, time-sliced ​​sharing and graphics-directed sharing.

[0150] In at least one embodiment, in this model, the hypervisor 1296 owns the graphics acceleration module 1246 and makes its functionality available to all operating systems 1295. For the graphics acceleration module 1246 to support virtualization through the hypervisor 1296, the graphics acceleration module 1246 may adhere to the following requirements: 1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1246 must provide a context save and restore mechanism, 2) the graphics acceleration module 1246 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1246 provides the ability to preempt job processing, and 3) fairness between graphics acceleration module 1246 processes must be ensured when operating in a directed shared programming model.

[0151] In at least one embodiment, an application 1280 is required to make an operating system 1295 system call using a graphics acceleration module 1246 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1246 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 1246 type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1246 and can take the form of a graphics acceleration module 1246 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure describing work to be performed by the graphics acceleration module 1246. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of an application setting the AMR. If the implementation of the accelerator integrated circuit 1236 and graphics acceleration module 1246 does not support the User Authority Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 1296 can optionally apply the current privilege mask overwrite register (AMOR) value before placing the AMR into the process element 1283. In at least one embodiment, the CSRP is one of the registers 1245 that contains the effective address of an area in the application's effective address space 1282 for the graphics acceleration module 1246 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area can be fixed system memory.

[0152] Upon receiving the system call, the operating system 1295 may verify that the application 1280 has been registered and granted permission to use the graphics acceleration module 1246. The operating system 1295 then uses

[0153] The information shown in Table 3 is used to call the management program 1296.

[0154]

[0155]

[0156] Upon receiving the hypervisor call, the hypervisor 1296 verifies that the operating system 1295 has registered and been granted permission to use the graphics acceleration module 1246. The hypervisor 1296 then places the process element 1283 into a linked list of process elements of the corresponding graphics acceleration module 1246 type. The process element may include the information shown in Table 4.

[0157]

[0158] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1290 registers 1245 .

[0159] like Figure 12F As shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memories 1201-1202 and GPU memories 1220-1223. In this implementation, operations executed on GPUs 1210-1213 utilize the same virtual / effective memory address space to access processor memories 1201-1202, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1201, a second portion is allocated to second processor memory 1202, a third portion is allocated to GPU memory 1220, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1201-1202 and GPU memories 1220-1223, allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0160] In one embodiment, bias / coherency management circuitry 1294A-1294E within one or more MMUs 1239A-1239E ensures cache coherency between the caches of one or more host processors (e.g., 1205) and GPUs 1210-1213 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. Figure 12F Multiple instances of bias / coherence management circuits 1294A- 1294E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1205 and / or within an accelerator integrated circuit 1236 .

[0161] One embodiment allows GPU-attached memory 1220-1223 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU-attached memory 1220-1223 as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows software on the host processor 1205 to set operands and access computation results without the overhead of traditional I / O DMA data copies. Such traditional copies include driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU-attached memory 1220-1223 without cache coherence overhead can be critical to the execution time of offloaded computations. For example, in situations with large amounts of streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 1210-1213. In at least one embodiment, efficiency of operand setup, efficiency of result access, and efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0162] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, with or without a bias cache in GPUs 1210-1213 (e.g., to cache frequently / recently used entries in the bias table), the bias table can be implemented in the stolen memory range of one or more GPU-attached memories 1220-1223. Alternatively, the entire bias table can be maintained within the GPU.

[0163] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU-attached memory 1220-1223 is accessed, resulting in the following operations. First, local requests from GPUs 1210-1213 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1220-1223. Local requests from the GPU whose pages are found in the host bias are forwarded to processor 1205 (e.g., via the high-speed link described herein). In one embodiment, requests from processor 1205 to find the requested page in the host processor bias complete a request similar to a normal memory read. Alternatively, requests directed to GPU bias pages can be forwarded to GPUs 1210-1213. In at least one embodiment, if the GPU is not currently using the page, the GPU can subsequently migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in limited cases, a purely hardware-based mechanism.

[0164] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1205 bias to GPU bias, but not for the reverse migration.

[0165] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1205. To access these pages, processor 1205 may request access from GPU 1210, which may or may not immediately grant access. Therefore, to reduce communication between processor 1205 and GPU 1210, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the host processor 1205, and vice versa.

[0166] Reasoning and / or training logic 615 is used to execute one or more embodiments. Figure 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided.

[0167] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0168] Figure 13 An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0169] Figure 13 is a block diagram illustrating an exemplary system on a chip integrated circuit 1300 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 1300 includes one or more application processors 1305 (e.g., CPUs), at least one graphics processor 1310, and may additionally include an image processor 1315 and / or a video processor 1320, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1300 includes peripheral or bus logic, including a USB controller 1325, a UART controller 1330, an SPI / SDIO controller 1335, and an I22S / I22C controller 1340. In at least one embodiment, integrated circuit 1300 may include a display device 1345 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1350 and a Mobile Industry Processor Interface (MIPI) display interface 1355. In at least one embodiment, storage may be provided by a flash memory subsystem 1360, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1365 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1370 .

[0170] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in integrated circuit 1300 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0171] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0172] Figures 14A-14B An exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein are shown. In addition to what is shown, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0173] Figures 14A-14B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 14A An exemplary graphics processor 1410 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores in accordance with at least one embodiment is shown. Figure 14B An additional exemplary graphics processor 1440 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment is shown. In at least one embodiment, Figure 14A The graphics processor 1410 is a low-power graphics processor core. In at least one embodiment, Figure 14B The graphics processor 1440 is a higher performance graphics processor core. In at least one embodiment, each of the graphics processors 1410, 1440 can be Figure 13 A variant of the graphics processor 1310.

[0174] In at least one embodiment, the graphics processor 1410 includes a vertex processor 1405 and one or more fragment processors 1415A-1415N (e.g., 1415A, 1415B, 1415C, 1415D through 1415N-1 and 1415N). In at least one embodiment, the graphics processor 1410 can execute different shader programs via separate logic, such that the vertex processor 1405 is optimized to perform operations for a vertex shader program, while the one or more fragment processors 1415A-1415N perform fragment (e.g., pixel) shading operations for a fragment or pixel shader program. In at least one embodiment, the vertex processor 1405 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1415A-1415N use the primitives and vertex data generated by the vertex processor 1405 to generate a frame buffer for display on a display device. In at least one embodiment, fragment processors 1415A-1415N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs as provided in the Direct 3D API.

[0175] In at least one embodiment, graphics processor 1410 additionally includes one or more memory management units (MMUs) 1420A-1420B, one or more caches 1425A-1425B, and one or more circuit interconnects 1430A-1430B. In at least one embodiment, one or more MMUs 1420A-1420B provide virtual-to-physical address mapping for graphics processor 1410 (including for vertex processor 1405 and / or fragment processors 1415A through 1415N), which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1425A-1425B. In at least one embodiment, one or more MMUs 1420A-1420B may synchronize with other MMUs within the system, including with one or more application processors 1305, graphics processor 1315, and / or Figure 13 One or more MMUs associated with the video processor 1320 of the SoC enable each processor 1305-1320 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1430A-1430B enable the graphics processor 1410 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0176] In at least one embodiment, graphics processor 1440 includes Figure 14A1420B, one or more caches 1425A-1425B, and one or more circuit interconnects 1430A-1430B of the graphics processor 1410. In at least one embodiment, the graphics processor 1440 includes one or more shader cores 1455A-1455N (e.g., 1455A, 1455B, 1455C, 1455D, 1455E, 1455F through 1455N-1 and 1455N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1440 includes an inter-core task manager 1445 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1455A-1455N and a tiling unit 1458 to accelerate tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within the scene or to optimize use of internal caches.

[0177] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B

[0066] Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 can be used in integrated circuits 14A and / or 14B to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, the logic can be used with the components of these figures to generate one or more images or video frames for one or more view angles.

[0178] Figures 15A-15B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figure 15A Shows that can be included in Figure 13 Graphics core 1500 within graphics processor 1310 of FIG. 1 , and in at least one embodiment, may be such as Figure 14B Unified shader cores 1455A-1455N are shown. Figure 15B A highly parallel, general-purpose graphics processing unit 1530 suitable for deployment on a multi-chip module in at least one embodiment is shown.

[0179] In at least one embodiment, graphics core 1500 includes a shared instruction cache 1502, texture units 1518, and cache / shared memory 1520, which are common to execution resources within graphics core 1500. In at least one embodiment, graphics core 1500 may include multiple slices 1501A-1501N, or partitions of each core, and the graphics processor may include multiple instances of graphics core 1500. Slices 1501A-1501N may include support logic including local instruction caches 1504A-1504N, thread schedulers 1506A-1506N, thread dispatchers 1508A-1508N, and a set of registers 1510A-1510N. In at least one embodiment, slices 1501A-1501N may include a set of additional function units (AFUs 1512A-1512N), floating point units (FPUs 1514A-1514N), integer arithmetic logic units (ALUs 1516A-1516N), address calculation units (ACUs 1513A-1513N), double-precision floating point units (DPFPUs 1515A-1515N), and matrix processing units (MPUs 1517A-1517N).

[0180] In at least one embodiment, the FPUs 1514A-1514N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1515A-1515N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1516A-1516N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1517A-1517N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1517-1517N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 1512A-1512N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0181] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6BDetails are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics core 1500 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network usage scenarios described herein.

[0182] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0183] Figure 15B A general purpose processing unit (GPGPU) 1530 is shown in at least one embodiment, which can be configured to enable highly parallel computing operations to be performed by a group of graphics processing units. In at least one embodiment, GPGPU 1530 can be directly linked to other instances of GPGPU 1530 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1530 includes a host interface 1532 to enable connection to a host processor. In at least one embodiment, host interface 1532 is a PCI Express interface. In at least one embodiment, host interface 1532 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 1530 receives commands from the host processor and uses a global scheduler 1534 to assign execution threads associated with those commands to a group of compute clusters 1536A-1536H. In at least one embodiment, compute clusters 1536A-1536H share a cache memory 1538. In at least one embodiment, cache memory 1538 may serve as a higher level of cache for cache memory within compute clusters 1536A-1536H.

[0184] In at least one embodiment, GPGPU 1530 includes memory 1544A-1544B coupled to compute clusters 1536A-1536H via a set of memory controllers 1542A-1542B. In at least one embodiment, memory 1544A-1544B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0185] In at least one embodiment, computing clusters 1536A-1536H each include a set of graphics cores, e.g. Figure 15AThe graphics core 1500 may include multiple types of integer and floating-point logic units that can perform computational operations at various precision ranges, including precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 1536A-1536H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0186] In at least one embodiment, multiple instances of GPGPU 1530 can be configured to function as a compute cluster. In at least one embodiment, the communications used by compute clusters 1536A-1536H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 1530 communicate via host interface 1532. In at least one embodiment, GPGPU 1530 includes an I / O hub 1539 that couples GPGPU 1530 to a GPU link 1540, enabling direct connections to other instances of GPGPU 1530. In at least one embodiment, GPU link 1540 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1530. In at least one embodiment, GPU link 1540 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1530 reside in separate data processing systems and communicate via a network device accessible through host interface 1532. In at least one embodiment, GPU link 1540 may be configured to enable connection to a host processor in addition to or as an alternative to host interface 1532 .

[0187] In at least one embodiment, GPGPU 1530 can be configured to train neural networks. In at least one embodiment, GPGPU 1530 can be used within an inference platform. In at least one embodiment, where GPGPU 1530 is used for inference, GPGPU 1530 can include fewer compute clusters 1536A-1536H than when GPGPU 1530 is used to train a neural network. In at least one embodiment, the memory technology associated with memory 1544A-1544B can differ between the inference and training configurations, with higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of GPGPU 1530 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0188] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in GPGPU 1530 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network usage scenarios described herein.

[0189] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0190] Figure 16 A block diagram of a computer system 1600 is shown, according to at least one embodiment. In at least one embodiment, computer system 1600 includes a processing subsystem 1601 having one or more processors 1602 and a system memory 1604, which communicates via an interconnect path that may include a memory hub 1605. In at least one embodiment, memory hub 1605 may be a separate component within a chipset assembly or may be integrated within one or more processors 1602. In at least one embodiment, memory hub 1605 is coupled to an I / O subsystem 1611 via a communication link 1606. In one embodiment, I / O subsystem 1611 includes an I / O hub 1607, which enables computer system 1600 to receive input from one or more input devices 1608. In at least one embodiment, I / O hub 1607 enables a display controller, which may be included in one or more processors 1602, to provide output to one or more display devices 1610A. In at least one embodiment, the one or more display devices 1610A coupled to the I / O hub 1607 may include local, internal, or embedded display devices.

[0191] In at least one embodiment, the processing subsystem 1601 includes one or more parallel processors 1612 coupled to the memory hub 1605 via a bus or other communication link 1613. In at least one embodiment, the communication link 1613 can use any of a number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 1612 form a parallel or vector processing system in a computational cluster, which can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 1612 form a graphics processing subsystem that can output pixels to one of one or more display devices 1610A coupled via the I / O hub 1607. In at least one embodiment, the one or more parallel processors 1612 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 1610B.

[0192] In at least one embodiment, system storage unit 1614 can be connected to I / O hub 1607 to provide a storage mechanism for computer system 1600. In at least one embodiment, I / O switch 1616 can be used to provide an interface mechanism to enable connections between I / O hub 1607 and other components, such as network adapter 1618 and / or wireless network adapter 1619 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 1620. In at least one embodiment, network adapter 1618 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1619 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0193] In at least one embodiment, computer system 1600 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1607. In at least one embodiment, interconnection may be achieved using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol. Figure 16 Communication paths for various components in a SoC, such as NV-Link high-speed interconnect or interconnect protocol.

[0194] In at least one embodiment, one or more parallel processors 1612 include circuits optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1612 include circuits optimized for general-purpose processing. In at least one embodiment, the components of computer system 1600 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, parallel processors 1612, memory hub 1605, processor 1602, and I / O hub 1607 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computer system 1600 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computer system 1600 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computer system.

[0195] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 can be used in system 1600 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network usages described herein.

[0196] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0197] processor

[0198] Figure 17A 1700 in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 1700 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 1700 is shown as a processor according to an exemplary embodiment. Figure 16 A variation of the one or more parallel processors 1612 is shown.

[0199] In at least one embodiment, parallel processor 1700 includes parallel processing unit 1702. In at least one embodiment, parallel processing unit 1702 includes an I / O unit 1704 that enables communication with other devices, including other instances of parallel processing unit 1702. In at least one embodiment, I / O unit 1704 can be directly connected to other devices. In at least one embodiment, I / O unit 1704 connects to other devices using a hub or switch interface (e.g., memory hub 1605). In at least one embodiment, the connection between memory hub 1605 and I / O unit 1704 forms communication link 1613. In at least one embodiment, I / O unit 1704 is connected to a host interface 1706 and a memory crossbar switch 1716, where host interface 1706 receives commands for performing processing operations and memory crossbar switch 1716 receives commands for performing memory operations.

[0200] In at least one embodiment, when host interface 1706 receives command buffers via I / O unit 1704, host interface 1706 can direct work operations to execute those commands to front end 1708. In at least one embodiment, front end 1708 is coupled to scheduler 1710, which is configured to distribute commands or other work items to processing cluster array 1712. In at least one embodiment, scheduler 1710 ensures that processing cluster array 1712 is properly configured and in a valid state before distributing tasks to processing cluster array 1712. In at least one embodiment, scheduler 1710 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1710 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 1712. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 1712 through one of multiple graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 1712 by scheduler 1710 logic within a microcontroller that includes scheduler 1710 .

[0201] In at least one embodiment, processing cluster array 1712 may include up to "N" processing clusters (e.g., cluster 1714A, cluster 1714B, through cluster 1714N). In at least one embodiment, each cluster 1714A-1714N of processing cluster array 1712 may execute a large number of concurrent threads. In at least one embodiment, scheduler 1710 may allocate work to clusters 1714A-1714N of processing cluster array 1712 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling may be handled dynamically by scheduler 1710 or may be assisted in part by compiler logic during the compilation of program logic configured to be executed by processing cluster array 1712. In at least one embodiment, different clusters 1714A-1714N of processing cluster array 1712 may be assigned to process different types of programs or to perform different types of computations.

[0202] In at least one embodiment, processing cluster array 1712 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 1712 can be configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 1712 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0203] In at least one embodiment, processing cluster array 1712 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 1712 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 1712 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 1702 may transfer data from system memory via I / O units 1704 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1722) during processing and then written back to system memory.

[0204] In at least one embodiment, when parallel processing unit 1702 is used to perform graphics processing, scheduler 1710 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 1714A-1714N of processing cluster array 1712. In at least one embodiment, portions of processing cluster array 1712 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 1714A-1714N can be stored in a buffer to allow the intermediate data to be transferred between clusters 1714A-1714N for further processing.

[0205] In at least one embodiment, processing cluster array 1712 may receive processing tasks to be executed via scheduler 1710 , which receives commands defining the processing tasks from front end 1708 .

[0206] In at least one embodiment, a processing task may include an index of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is to be processed (e.g., what program to execute). In at least one embodiment, the scheduler 1710 may be configured to obtain an index corresponding to a task, or may receive the index from the front end 1708. In at least one embodiment, the front end 1708 may be configured to ensure that the processing cluster array 1712 is configured in a valid state before starting a workload specified by an incoming command buffer (e.g., a batch-buffer, a push buffer, etc.).

[0207] In at least one embodiment, each of one or more instances of parallel processing unit 1702 can be coupled to parallel processor memory 1722. In at least one embodiment, parallel processor memory 1722 can be accessed via memory crossbar 1716, which can receive memory requests from processing cluster array 1712 and I / O unit 1704. In at least one embodiment, memory crossbar 1716 can access parallel processor memory 1722 via memory interface 1718. In at least one embodiment, memory interface 1718 can include a plurality of partition units (e.g., partition unit 1720A, partition unit 1720B, through partition unit 1720N), which can each be coupled to a portion of parallel processor memory 1722 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 1720A-1720N are configured to be equal to the number of memory cells, such that the first partition unit 1720A has a corresponding first memory cell 1724A, the second partition unit 1720B has a corresponding memory cell 1724B, and the Nth partition unit 1720N has a corresponding Nth memory cell 1724N. In at least one embodiment, the number of partition units 1720A-1720N may not be equal to the number of memory devices.

[0208] In at least one embodiment, memory units 1724A-1724N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1724A-1724N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 1724A-1724N, allowing partition units 1720A-1720N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 1722. In at least one embodiment, local instances of parallel processor memory 1722 may be eliminated in favor of a unified memory design that utilizes system memory in combination with local cache memory.

[0209] In at least one embodiment, any of the clusters 1714A-1714N in the processing cluster array 1712 can process data to be written to any memory unit 1724A-1724N within the parallel processor memory 1722. In at least one embodiment, the memory crossbar 1716 can be configured to transmit the output of each cluster 1714A-1714N to any partition unit 1720A-1720N or another cluster 1714A-1714N, which can perform other processing operations on the output. In at least one embodiment, each cluster 1714A-1714N can communicate with a memory interface 1718 via the memory crossbar 1716 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 1716 has connections to memory interface 1718 for communicating with I / O unit 1704, and to local instances of parallel processor memory 1722, thereby enabling processing units within different processing clusters 1714A-1714N to communicate with system memory or other memory that is not local to parallel processing unit 1702. In at least one embodiment, memory crossbar 1716 may use virtual channels to separate traffic flows between clusters 1714A-1714N and partition units 1720A-1720N.

[0210] In at least one embodiment, multiple instances of parallel processing unit 1702 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 1702 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1702 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 1702 or parallel processor 1700 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0211] Figure 17B is a block diagram of a partition unit 1720 according to at least one embodiment. In at least one embodiment, the partition unit 1720 is Figure 17A1720N。In at least one embodiment, the partition unit 1720 includes an L2 cache 1721, a frame buffer interface 1725, and a raster operations unit ("ROP") 1726. The L2 cache 1721 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 1716 and the ROP 1726. In at least one embodiment, the L2 cache 1721 outputs read misses and urgent writeback requests to the frame buffer interface 1725 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 1725 for processing. In at least one embodiment, the frame buffer interface 1725 communicates with memory units in the parallel processor memory, such as Figure 17A interacts with one of the memory units 1724A-1724N (e.g., within parallel processor memory 1722).

[0212] In at least one embodiment, ROP 1726 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 1726 then outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 1726 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The compression logic implemented by ROP 1726 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0213] In at least one embodiment, ROP 1726 is included within each processing cluster (e.g., Figure 17A In at least one embodiment, read and write requests for pixel data are transmitted through the memory crossbar 1716 rather than through the pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device such as a Figure 16 1610), routed by processor 1602 for further processing, or by Figure 17A One of the processing entities within parallel processor 1700 is routed for further processing.

[0214] Figure 17C is a block diagram of a processing cluster 1714 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Figure 17AIn at least one embodiment, one or more of the processing clusters 1714 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a group of processing engines within each processing cluster.

[0215] In at least one embodiment, the operation of the processing cluster 1714 can be controlled by a pipeline manager 1732 that assigns processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 1732 Figure 17A Scheduler 1710 receives instructions and manages the execution of these instructions via graphics multiprocessor 1734 and / or texture unit 1736. In at least one embodiment, graphics multiprocessor 1734 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within processing cluster 1714. In at least one embodiment, one or more instances of graphics multiprocessor 1734 may be included within processing cluster 1714. In at least one embodiment, graphics multiprocessor 1734 may process data, and data crossbar 1740 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, pipeline manager 1732 may facilitate the distribution of processed data by specifying a destination for the processed data to be distributed via data crossbar 1740.

[0216] In at least one embodiment, each graphics multiprocessor 1734 within a processing cluster 1714 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0217] In at least one embodiment, instructions transmitted to processing cluster 1714 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 1734. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within graphics multiprocessor 1734. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop by the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within graphics multiprocessor 1734. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor 1734, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 1734.

[0218] In at least one embodiment, the graphics multiprocessor 1734 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 1734 can abandon the internal cache and use cache memory within the processing cluster 1714 (e.g., L1 cache 1748). In at least one embodiment, each graphics multiprocessor 1734 can also access a partition unit (e.g., Figure 17A L2 cache within partition units 1720A-1720N) of the graphics multiprocessor 1734 is shared across all processing clusters 1714 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1734 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1702 can be used as global memory. In at least one embodiment, processing cluster 1714 includes multiple instances of graphics multiprocessor 1734, which can share common instructions and data, which can be stored in L1 cache 1748.

[0219] In at least one embodiment, each processing cluster 1714 may include a memory management unit ("MMU") 1745 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1745 may reside in Figure 17A1718. In at least one embodiment, the MMU 1745 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 1745 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 1734 or L1 cache or processing cluster 1714. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0220] In at least one embodiment, the processing clusters 1714 can be configured such that each graphics multiprocessor 1734 is coupled to a texture unit 1736 to perform texture mapping operations, which determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1734, and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 1734 outputs processed tasks to a data crossbar 1740 to provide the processed tasks to another processing cluster 1714 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 1716. In at least one embodiment, a preROP 1742 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 1734 and direct the data to a ROP unit, which can communicate with a partition unit (e.g., a partition unit) as described herein. Figure 17A In at least one embodiment, the PreROP 1742 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0221] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics processing cluster 1714 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network usages described herein.

[0222] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0223] Figure 17D A graphics multiprocessor 1734 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 1734 is coupled to a pipeline manager 1732 of a processing cluster 1714. In at least one embodiment, the graphics multiprocessor 1734 has an execution pipeline that includes, but is not limited to, an instruction cache 1752, an instruction unit 1754, an address mapping unit 1756, a register file 1758, one or more general purpose graphics processing unit (GPGPU) cores 1762, and one or more load / store units 1766. The GPGPU cores 1762 and the load / store units 1766 are coupled to a cache memory 1772 and a shared memory 1770 via a memory and cache interconnect 1768.

[0224] In at least one embodiment, the instruction cache 1752 receives a stream of instructions to be executed from the pipeline manager 1732. In at least one embodiment, the instructions are cached in the instruction cache 1752 and dispatched for execution by the instruction unit 1754. In one embodiment, the instruction unit 1754 can dispatch instructions as thread groups (e.g., warps), assigning each thread group to a different execution unit within the GPGPU core 1762. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 1756 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 1766.

[0225] In at least one embodiment, register file 1758 provides a set of registers for the functional units of graphics multiprocessor 1734. In at least one embodiment, register file 1758 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 1762, load / store unit 1766) connected to graphics multiprocessor 1734. In at least one embodiment, register file 1758 is divided between each functional unit such that a dedicated portion of register file 1758 is allocated to each functional unit. In at least one embodiment, register file 1758 is divided between the different warps being executed by graphics multiprocessor 1734.

[0226] In at least one embodiment, the GPGPU cores 1762 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1734. The GPGPU cores 1762 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 1762 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 1734 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0227] In at least one embodiment, the GPGPU core 1762 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 1762 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0228] In at least one embodiment, memory and cache interconnect 1768 is an interconnect network that connects each functional unit of graphics multiprocessor 1734 to register file 1758 and shared memory 1770. In at least one embodiment, memory and cache interconnect 1768 is a crossbar interconnect that allows load / store unit 1766 to perform load and store operations between shared memory 1770 and register file 1758. In at least one embodiment, register file 1758 can operate at the same frequency as GPGPU core 1762, resulting in very low latency for data transfers between GPGPU core 1762 and register file 1758. In at least one embodiment, shared memory 1770 can be used to enable communication between threads executing on functional units within graphics multiprocessor 1734. In at least one embodiment, cache memory 1772 can be used, for example, as a data cache to cache texture data communicated between functional units and texture unit 1736. In at least one embodiment, shared memory 1770 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 1772, threads executing on GPGPU core 1762 may programmatically store data in shared memory.

[0229] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0230] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6BDetails are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics multiprocessor 1734 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network usages described herein.

[0231] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0232] Figure 18 A multi-GPU computing system 1800 is shown in accordance with at least one embodiment. In at least one embodiment, multi-GPU computing system 1800 may include a processor 1802 coupled to a plurality of general purpose graphics processing units (GPGPUs) 1806A-D via a host interface switch 1804. In at least one embodiment, host interface switch 1804 is a PCI Express switch device that couples processor 1802 to a PCI Express bus, over which processor 1802 can communicate with GPGPUs 1806A-D. GPGPUs 1806A-D may be interconnected via a collection of high-speed, point-to-point GPU-to-GPU links 1816. In at least one embodiment, GPU-to-GPU links 1816 connect to each of GPGPUs 1806A-D via dedicated GPU links. In at least one embodiment, P2P GPU links 1816 enable direct communication between each of GPGPUs 1806A-D without requiring communication over host interface bus 1804 to which processor 1802 is connected. In at least one embodiment, host interface bus 1804 remains available for system memory access or communication with other instances of multi-GPU computing system 1800, for example, via one or more network devices, through GPU-to-GPU traffic directed to P2P GPU link 1816. Although in at least one embodiment, GPGPUs 1806A-D are connected to processor 1802 via host interface switch 1804, in at least one embodiment, processor 1802 includes direct support for P2P GPU link 1816 and can connect directly to GPGPUs 1806A-D.

[0233] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6BDetails are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in multi-GPU computing system 1800 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network usages described herein.

[0234] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0235] Figure 19 FIG1 is a block diagram of a graphics processor 1900 according to at least one embodiment. In at least one embodiment, graphics processor 1900 includes a ring interconnect 1902, a pipeline front end 1904, a media engine 1937, and graphics cores 1980A-1980N. In at least one embodiment, ring interconnect 1902 couples graphics processor 1900 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 1900 is one of many processors integrated within a multi-core processing system.

[0236] In at least one embodiment, graphics processor 1900 receives batches of commands via ring interconnect 1902. In at least one embodiment, the incoming commands are interpreted by a command streamer 1903 in pipeline front end 1904. In at least one embodiment, graphics processor 1900 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 1980A-1980N. In at least one embodiment, for 3D geometry processing commands, command streamer 1903 provides the commands to geometry pipeline 1936. In at least one embodiment, for at least some media processing commands, command streamer 1903 provides the commands to video front end 1934, which is coupled to media engine 1937. In at least one embodiment, media engine 1937 includes a video quality engine (VQE) 1930 for video and image post-processing, and a multi-format encoding / decoding (MFX) 1933 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 1936 and the media engine 1937 each generate execution threads for thread execution resources provided by at least one graphics core 1980A.

[0237] In at least one embodiment, graphics processor 1900 includes scalable thread execution resources featuring modular cores 1980A-1980N (sometimes referred to as core slices), each of which has multiple sub-cores 1950A-1950N, 1960A-1960N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 1900 can have any number of graphics cores 1980A through 1980N. In at least one embodiment, graphics processor 1900 includes graphics core 1980A having at least a first sub-core 1950A and a second sub-core 1960A. In at least one embodiment, graphics processor 1900 is a low-power processor having a single sub-core (e.g., 1950A). In at least one embodiment, graphics processor 1900 includes multiple graphics cores 1980A-1980N, each of which includes a set of first sub-cores 1950A-1950N and a set of second sub-cores 1960A-1960N. In at least one embodiment, each of the first sub-cores 1950A-1950N includes at least a first set of execution units 1952A-1952N and media / texture samplers 1954A-1954N. In at least one embodiment, each of the second sub-cores 1960A-1960N includes at least a second set of execution units 1962A-1962N and samplers 1964A-1964N. In at least one embodiment, each of the sub-cores 1950A-1950N, 1960A-1960N shares a set of shared resources 1970A-1970N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0238] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics processor 1900 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0239] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0240] Figure 20is a block diagram illustrating a microarchitecture for a processor 2000 that may include logic circuitry for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2000 may execute instructions including x86 instructions, ARM instructions, specialized instructions for an application-specific integrated circuit (ASIC), and the like. In at least one embodiment, the processor 2000 may include registers for storing packed data, such as the 64-bit wide MMX registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. TM Registers. In at least one embodiment, MMX registers available in integer and floating point form can operate with packed data elements that accompany Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technology can hold such packed data operands. In at least one embodiment, processor 2000 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0241] In at least one embodiment, the processor 2000 includes an in-order front end ("front end") 2001 to fetch instructions to be executed and prepare the instructions for later use in the processor pipeline. In at least one embodiment, the front end 2001 may include several units. In at least one embodiment, an instruction prefetcher 2026 retrieves instructions from memory and provides the instructions to an instruction decoder 2028, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2028 decodes the received instructions into one or more operations called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "micro-instructions") that the machine can execute. In at least one embodiment, the instruction decoder 2028 parses the instructions into an opcode and corresponding data and control fields, which can be used by the microarchitecture to perform the operations according to at least one embodiment. In at least one embodiment, the trace cache 2030 can assemble the decoded microinstructions into a program-ordered sequence or trace in the microinstruction queue 2034 for execution. In at least one embodiment, when trace cache 2030 encounters a complex instruction, microcode ROM 2032 provides the microinstructions necessary to complete the operation.

[0242] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2028 may access the microcode ROM 2032 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2028. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2032. In at least one embodiment, the trace cache 2030 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from the microcode ROM 2032 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2032 completes the micro-op sequencing for the instruction, the front end 2001 of the machine may resume fetching micro-ops from the trace cache 2030.

[0243] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2003 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. In at least one embodiment, the OOO engine 2003 includes, but is not limited to, an allocator / register renamer 2040, a memory microinstruction queue 2042, an integer / floating-point microinstruction queue 2044, a memory scheduler 2046, a fast scheduler 2002, a slow / general purpose floating-point scheduler ("slow / general purpose FP scheduler") 2004, and a simple floating-point scheduler ("simple FP scheduler") 2006. In at least one embodiment, the fast scheduler 2002, the slow / general purpose floating-point scheduler 2004, and the simple floating-point scheduler 2006 are also collectively referred to as "microinstruction schedulers 2002, 2004, 2006." In at least one embodiment, the allocator / register renamer 2040 allocates the machine buffers and resources required for each microinstruction to execute in sequence. In at least one embodiment, the allocator / register renamer 2040 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2040 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 2042 for memory operations and an integer / floating-point microinstruction queue 2044 for non-memory operations, preceding the memory scheduler 2046 and the microinstruction schedulers 2002, 2004, and 2006. In at least one embodiment, the microinstruction schedulers 2002, 2004, and 2006 determine when a microinstruction is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2002 of at least one embodiment can schedule every half of the main clock cycle, while the slow / general floating-point scheduler 2004 and the simple floating-point scheduler 2006 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2002, 2004, 2006 arbitrate among dispatch ports to schedule microinstructions for execution.

[0244] In at least one embodiment, execution block 2011 includes, but is not limited to, integer register file / branch network 2008, floating-point register file / branch network ("FP register file / branch network") 2010, address generation units ("AGUs") 2012 and 2014, fast arithmetic logic units ("fast ALUs") 2016 and 2018, slow arithmetic logic unit ("slow ALU") 2020, floating-point ALU ("FP") 2022, and floating-point move unit ("FP move") 2024. In at least one embodiment, integer register file / branch network 2008 and floating-point register file / bypass network 2010 are also referred to herein as "register files 2008, 2010." In at least one embodiment, AGUs 2012 and 2014, fast ALUs 2016 and 2018, slow ALU 2020, floating-point ALU 2022, and floating-point move unit 2024 are also referred to herein as "execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024." In at least one embodiment, execution block 2011 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0245] In at least one embodiment, register files 2008 and 2010 may be arranged between microinstruction schedulers 2002, 2004, and 2006 and execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024. In at least one embodiment, integer register file / branch network 2008 performs integer operations. In at least one embodiment, floating-point register file / branch network 2010 performs floating-point operations. In at least one embodiment, each of register files 2008 and 2010 may include, but is not limited to, a branch network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register files 2008 and 2010 can communicate data with each other. In at least one embodiment, integer register file / branch network 2008 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2010 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0246] In at least one embodiment, execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024 may execute instructions. In at least one embodiment, register files 2008 and 2010 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 2000 may include, but is not limited to, any number of execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024, and combinations thereof. In at least one embodiment, floating-point ALU 2022 and floating-point move unit 2024 may execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2022 may include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware may be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to the fast ALUs 2016 and 2018. In at least one embodiment, the fast ALUs 2016 and 2018 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to the slow ALU 2020, as the slow ALU 2020 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by the AGUs 2012 and 2014. In at least one embodiment, the fast ALUs 2016, 2018, and slow ALU 2020 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALUs 2016, 2018, and slow ALU 2020 can be implemented to support a variety of data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, the floating point ALU 2022 and floating point shift unit 2024 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 2022 and floating point shift unit 2024 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0247] In at least one embodiment, microinstruction schedulers 2002, 2004, and 2006 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 2000, processor 2000 can also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations.

[0248] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0249] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be incorporated into the execution block 2011 and other memories or registers, whether shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein can use one or more ALUs shown in the execution block 2011. Additionally, weight parameters can be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the execution block 2011 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0250] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0251] Figure 21 A deep learning application processor 2100 is shown in accordance with at least one embodiment. In at least one embodiment, the deep learning application processor 2100 uses instructions that, if executed by the deep learning application processor 2100, cause the deep learning application processor 2100 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2100 is an application-specific integrated circuit (ASIC). In at least one embodiment, the application processor 2100 performs matrix multiplication operations or "hardwires" them into hardware as a result of executing one or more instructions, or both. In at least one embodiment, the deep learning application processor 2100 includes, but is not limited to, processing clusters 2110(1)-2110(12), inter-chip links (“ICLs”) 2120(1)-2120(12), inter-chip controllers (“ICCs”) 2130(1)-2130(2), memory controllers (“Mem Ctrlr”) 2142(1)-2142(4), high bandwidth memory physical layer (“HBM PHY”) 2144(1)-2144(4), a management controller central processing unit (“management controller CPU”) 2150, a peripheral component interconnect express controller and direct memory access block (“PCIe controller and DMA”) 2170, and a sixteen-lane peripheral component interconnect express port (“PCI Express x 16”) 2180.

[0252] In at least one embodiment, the processing cluster 2110 can perform deep learning operations, including inference or prediction operations based on weight parameters calculated by one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2110 can include, but is not limited to, any number and type of processors. In at least one embodiment, the deep learning application processor 2100 can include any number and type of processing clusters 2100. In at least one embodiment, the inter-chip link 2120 is bidirectional. In at least one embodiment, the inter-chip link 2120 and the inter-chip controller 2130 enable multiple deep learning application processors 2100 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2100 can include any number (including zero) and type of ICLs 2120 and ICCs 2130.

[0253] In at least one embodiment, HBM2 2140 provides a total of 32GB of memory. HBM2 2140(i) is associated with both a memory controller 2142(i) and an HBM PHY 2144(i). In at least one embodiment, any number of HBM2 2140 can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controllers 2142 and HBM PHYs 2144. In at least one embodiment, SPI, I2C, GPIO 3360, PCIe controller 2160, DMA 2170, and / or PCIe 2180 can be replaced with any number and type of blocks to implement any number and type of communication standards in any technically feasible manner.

[0254] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Provides details regarding the inference and / or training logic 615. In at least one embodiment, the deep learning application processor 2100 is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2100. In at least one embodiment, the deep learning application processor 2100 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2100. In at least one embodiment, the processor 2100 can be used to perform one or more of the neural network use cases described herein.

[0255] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0256] Figure 22 is a block diagram of a neuromorphic processor 2200 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2200 can receive one or more inputs from a source external to the neuromorphic processor 2200. In at least one embodiment, these inputs can be transmitted to one or more neurons 2202 within the neuromorphic processor 2200. In at least one embodiment, the neurons 2202 and their components can be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2200 can include, but is not limited to, thousands of instances of neurons 2202, although any suitable number of neurons 2202 can be used. In at least one embodiment, each instance of a neuron 2202 can include a neuron input 2204 and a neuron output 2206. In at least one embodiment, a neuron 2202 can generate an output that can be transmitted to the inputs of other instances of the neuron 2202. In at least one embodiment, the neuron input 2204 and the neuron output 2206 can be interconnected via a synapse 2208.

[0257] In at least one embodiment, the neurons 2202 and synapses 2208 can be interconnected so that the neuromorphic processor 2200 operates to process or analyze information received by the neuromorphic processor 2200. In at least one embodiment, the neuron 2202 can send an output pulse (or "trigger" or "spike") when the input received through the neuron input 2204 exceeds a threshold. In at least one embodiment, the neuron 2202 can sum or integrate the signal received at the neuron input 2204. For example, in at least one embodiment, the neuron 2202 can be implemented as a leaky integrate-and-trigger neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, the neuron 2202 can generate an output (or "trigger") using a transfer function such as a sigmoid or threshold function. In at least one embodiment, the leaky integrate-and-trigger neuron can sum the signal received at the neuron input 2204 into a membrane potential and can apply an application attenuation factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may trigger if multiple input signals are received at neuron input 2204 quickly enough to exceed a threshold (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, neuron 2202 may be implemented using circuitry or logic that receives input, integrates the input into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neuron 2202 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 2206 when the result of applying the transfer function to neuron input 2204 exceeds a threshold. In at least one embodiment, once neuron 2202 triggers, it may ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2202 may resume normal operation after a suitable period of time (or recovery period).

[0258] In at least one embodiment, neurons 2202 can be interconnected via synapses 2208. In at least one embodiment, synapses 2208 can be operable to transmit a signal from an output of a first neuron 2202 to an input of a second neuron 2202. In at least one embodiment, a neuron 2202 can transmit information across more than one instance of synapse 2208. In at least one embodiment, one or more instances of a neuron output 2206 can be connected to an instance of a neuron input 2204 in the same neuron 2202 via an instance of synapse 2208. In at least one embodiment, an instance of a neuron 2202 that generates an output to be transmitted across an instance of synapse 2208 can be referred to as a "presynaptic neuron" relative to that instance of synapse 2208. In at least one embodiment, an instance of a neuron 2202 that receives an input transmitted across an instance of synapse 2208 can be referred to as a "postsynaptic neuron" relative to an instance of synapse 2208. In at least one embodiment, with respect to the various instances of synapses 2208, because an instance of neuron 2202 can receive input from one or more instances of synapses 2208 and can also transmit output through one or more instances of synapses 2208, a single instance of neuron 2202 can be both a "pre-synaptic neuron" and a "post-synaptic neuron."

[0259] Neurons 2202 can be organized into one or more layers. Each instance of a neuron 2202 can have a neuron output 2206 that can fan out to one or more neuron inputs 2204 via one or more synapses 2208. In at least one embodiment, the neuron output 2206 of a neuron 2202 in a first layer 2210 can be connected to the neuron input 2204 of a neuron 2202 in a second layer 2212. In at least one embodiment, the layer 2210 can be referred to as a "feed-forward layer." In at least one embodiment, each instance of a neuron 2202 in an instance of the first layer 2210 can fan out to each instance of a neuron 2202 in the second layer 2212. In at least one embodiment, the first layer 2210 can be referred to as a "fully connected feed-forward layer." In at least one embodiment, each instance of a neuron 2202 in each instance of the second layer 2212 can fan out to fewer than all instances of a neuron 2202 in the third layer 2214. In at least one embodiment, the second layer 2212 can be referred to as a "sparsely connected feed-forward layer." In at least one embodiment, neurons 2202 in a second layer 2212 can fan out to neurons 2202 in multiple other layers, including fanning out to neurons 2202 in the (same) second layer 2212. In at least one embodiment, the second layer 2212 can be referred to as a "recurrent layer." In at least one embodiment, the neuromorphic processor 2200 can include, but is not limited to, any suitable combination of recurrent layers and feed-forward layers, including, but not limited to, sparsely connected feed-forward layers and fully connected feed-forward layers.

[0260] In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, a reconfigurable interconnect architecture or a dedicated hardwired interconnect to connect synapses 2208 to neurons 2202. In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2202 as needed based on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, synapses 2208 may be connected to neurons 2202 using an interconnect architecture such as a network on a chip or through dedicated connections. In at least one embodiment, the synaptic interconnect and its components may be implemented using circuitry or logic.

[0261] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0262] Figure 2323. A processing system according to at least one embodiment is shown. In at least one embodiment, system 2300 includes one or more processors 2302 and one or more graphics processors 2308, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2302 or processor cores 2307. In at least one embodiment, system 2300 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0263] In at least one embodiment, the system 2300 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console, including a gaming and media console. In at least one embodiment, the system 2300 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 2300 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2300 is a television or set-top box device having one or more processors 2302 and a graphical interface generated by one or more graphics processors 2308.

[0264] In at least one embodiment, one or more processors 2302 each include one or more processor cores 2307 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2307 is configured to process a specific instruction set 2309. In at least one embodiment, the instruction set 2309 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, the processor cores 2307 can each process a different instruction set 2309, which can include instructions that facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 2307 can also include other processing devices, such as a digital signal processor (DSP).

[0265] In at least one embodiment, the processor 2302 includes a cache memory 2304. In at least one embodiment, the processor 2302 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared among various components of the processor 2302. In at least one embodiment, the processor 2302 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can be shared among the processor cores 2307 using known cache coherence techniques. In at least one embodiment, the processor 2302 further includes a register file 2306. The processor can include different types of registers (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) for storing different types of data. In at least one embodiment, the register file 2306 can include general purpose registers or other registers.

[0266] In at least one embodiment, one or more processors 2302 are coupled to one or more interface buses 2310 to transmit communication signals, such as address, data, or control signals, between the processors 2302 and other components in the system 2300. In at least one embodiment, the interface bus 2310 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 2310 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2302 includes an integrated memory controller 2316 and a platform controller hub 2330. In at least one embodiment, the memory controller 2316 facilitates communication between memory devices and other components of the processing system 2300, while the platform controller hub (PCH) 2330 provides connections to input / output (I / O) devices via a local I / O bus.

[0267] In at least one embodiment, the memory device 2320 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or other suitable memory device for use as processor memory. In at least one embodiment, the memory device 2320 can be used as system memory for the processing system 2300 to store data 2322 and instructions 2321 for use when one or more processors 2302 execute applications or processes. In at least one embodiment, the memory controller 2316 is also coupled to an optional external graphics processor 2312, which can communicate with one or more graphics processors 2308 in the processor 2302 to perform graphics and media operations. In at least one embodiment, a display device 2311 can be connected to the processor 2302. In at least one embodiment, the display device 2311 can include one or more internal display devices, such as in a mobile electronic device or laptop device, or an external display device connected via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 2311 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0268] In at least one embodiment, the platform controller hub 2330 enables peripheral devices to connect to the storage device 2320 and the processor 2302 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 2346, a network controller 2334, a firmware interface 2328, a wireless transceiver 2326, a touch sensor 2325, and a data storage device 2324 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 2324 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2325 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2326 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2328 enables communication with the system firmware and can be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, a network controller 2334 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2310. In at least one embodiment, an audio controller 2346 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 2300 includes an optional legacy I / O controller 2340 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. In at least one embodiment, the platform controller hub 2330 can also be connected to one or more universal serial bus (USB) controllers 2342 that connect input devices such as a keyboard and mouse 2343 combination, a camera 2344, or other USB input devices.

[0269] In at least one embodiment, instances of the memory controller 2316 and the platform controller hub 2330 may be integrated into a discrete external graphics processor, such as the external graphics processor 2312. In at least one embodiment, the platform controller hub 2330 and / or the memory controller 2316 may be external to one or more processors 2302. For example, in at least one embodiment, the system 2300 may include the external memory controller 2316 and the platform controller hub 2330, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 2302.

[0270] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6BDetail is provided regarding the inference and / or training logic 615. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the graphics processor 2300. For example, in at least one embodiment, the training and / or inference techniques described herein may utilize one or more ALUs embodied in the graphics processor 2312. Additionally, in at least one embodiment, the inference and / or training operations described herein may utilize a number of ALUs other than the ALUs. Figure 6A or Figure 6B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2300 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0271] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0272] Figure 24 is a block diagram of a processor 2400 having one or more processor cores 2402A-2402N, an integrated memory controller 2414, and an integrated graphics processor 2408, in accordance with at least one embodiment. In at least one embodiment, the processor 2400 may include additional cores, up to and including the additional core 2402N represented by the dashed box. In at least one embodiment, each processor core 2402A-2402N includes one or more internal cache units 2404A-2404N. In at least one embodiment, each processor core may also have access to one or more shared cache units 2406.

[0273] In at least one embodiment, the internal cache units 2404A-2404N and the shared cache unit 2406 represent a cache memory hierarchy within the processor 2400. In at least one embodiment, the cache memory units 2404A-2404N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is categorized as LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2406 and 2404A-2404N.

[0274] In at least one embodiment, the processor 2400 may also include a set of one or more bus controller units 2416 and a system agent core 2410. In at least one embodiment, the one or more bus controller units 2416 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2410 provides management functions for various processor components. In at least one embodiment, the system agent core 2410 includes one or more integrated memory controllers 2414 to manage access to various external memory devices (not shown).

[0275] In at least one embodiment, one or more processor cores 2402A-2402N include support for simultaneous multithreading. In at least one embodiment, system agent core 2410 includes components for coordinating and operating cores 2402A-2402N during multithreaded processing. In at least one embodiment, system agent core 2410 may additionally include a power control unit (PCU) that includes logic and components for regulating one or more power states of processor cores 2402A-2402N and graphics processor 2408.

[0276] In at least one embodiment, the processor 2400 further includes a graphics processor 2408 for performing graphics processing operations. In at least one embodiment, the graphics processor 2408 is coupled to a shared cache unit 2406 and a system agent core 2410 including one or more integrated memory controllers 2414. In at least one embodiment, the system agent core 2410 further includes a display controller 2411 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2411 may also be a separate module coupled to the graphics processor 2408 via at least one interconnect, or may be integrated within the graphics processor 2408.

[0277] In at least one embodiment, a ring-based interconnect 2412 is used to couple the internal components of the processor 2400. In at least one embodiment, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2408 is coupled to the ring interconnect 2412 via an I / O link 2413.

[0278] In at least one embodiment, I / O link 2413 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2418 (e.g., an eDRAM module). In at least one embodiment, each of the processor cores 2402A-2402N and the graphics processor 2408 uses the embedded memory module 2418 as a shared last-level cache.

[0279] In at least one embodiment, the processor cores 2402A-2402N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2402A-2402N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 2402A-2402N execute a common instruction set, while one or more other processor cores 2402A-2402N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 2402A-2402N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 2400 can be implemented on one or more chips or as a SoC integrated circuit.

[0280] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B 2402N, or the like. Figure 24 Furthermore, in at least one embodiment, the inference and / or training operations described herein may use other than Figure 6A or Figure 6B In at least one embodiment, weight parameters that configure the ALU of the graphics processor 2400 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein may be stored in on-chip or off-chip memory and / or registers (shown or not shown).

[0281] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0282] Figure 25 is a block diagram of the hardware logic of a graphics processor core 2500 according to at least one embodiment described herein. In at least one embodiment, graphics processor core 2500 is included within a graphics core array. In at least one embodiment, graphics processor core 2500 (sometimes referred to as a core slice) can be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 2500 is an example of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2500 may include a fixed function block 2530 coupled to multiple sub-cores 2501A-2501F (also referred to as sub-slices), the fixed function blocks including modular blocks having general purpose and fixed function logic.

[0283] In at least one embodiment, fixed function block 2530 includes geometry and fixed function pipelines 2536, which may be shared by all sub-cores in graphics processor 2500, for example, in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry and fixed function pipelines 2536 include a 3D fixed function pipeline, a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0284] In at least one fixed embodiment, fixed function block 2530 also includes a graphics SoC interface 2537, a graphics microcontroller 2538, and a media pipeline 2539. In at least one embodiment, graphics SoC interface 2537 provides an interface between graphics core 2500 and other processor cores in the on-chip integrated circuit system. In at least one embodiment, graphics microcontroller 2538 is a programmable subprocessor that can be configured to manage various functions of graphics processor 2500, including thread dispatching, scheduling, and preemption. In at least one embodiment, media pipeline 2539 includes logic that facilitates decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 2539 implements media operations via requests to computational or sampling logic within sub-cores 2501-2501F.

[0285] In at least one embodiment, the SoC interface 2537 enables the graphics core 2500 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as a shared last-level cache, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2537 may also enable communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enable the use and / or implementation of global memory atomics that can be shared between the graphics core 2500 and the CPU within the SoC. In at least one embodiment, the SoC interface 2537 may also implement power management controls for the graphics core 2500 and enable interfaces between the clock domain of the graphics core 2500 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2537 enables receiving command buffers from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to the media pipeline 2539 when media operations are to be performed, or to the geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 2536, geometry and fixed function pipeline 2514) when graphics processing operations are to be performed.

[0286] In at least one embodiment, the graphics microcontroller 2538 can be configured to perform various scheduling and management tasks for the graphics core 2500. In at least one embodiment, the graphics microcontroller 2538 can perform graphics and / or compute workload scheduling on the various graphics parallel engines within the execution unit (EU) arrays 2502A-2502F, 2504A-2504F in the sub-cores 2501A-2501F. In at least one embodiment, host software executing on a CPU core of a SoC including the graphics core 2500 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In at least one embodiment, the graphics microcontroller 2538 may also facilitate low power or idle states for the graphics core 2500, thereby providing the graphics core 2500 with the ability to save and restore registers across low power state transitions within the graphics core 2500 independent of the operating system and / or graphics driver software on the system.

[0287] In at least one embodiment, graphics core 2500 may have up to N modular sub-cores, more or less than the sub-cores 2501A-2501F shown. For each set of N sub-cores, in at least one embodiment, graphics core 2500 may also include shared function logic 2510, shared and / or cache memory 2512, geometry / fixed function pipelines 2514, and additional fixed function logic 2516 to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic 2510 may include logic units (e.g., samplers, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores within graphics core 2500. In at least one embodiment, shared and / or cache memory 2512 may be the last level cache for the N sub-cores 2501A-2501F within graphics core 2500 and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2514 may be included in place of geometry / fixed function pipeline 2536 within fixed function block 2530 and may include the same or similar logic units.

[0288] In at least one embodiment, graphics core 2500 includes additional fixed-function logic 2516, which may include various fixed-function acceleration logic for use by graphics core 2500. In at least one embodiment, additional fixed-function logic 2516 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and within geometry and fixed-function pipelines 2514, 2536, there are at least two geometry pipelines, which are the full geometry pipeline and the culling pipeline, which may be included in additional fixed-function logic 2516. In at least one embodiment, the culling pipeline is a modified version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of an application, each with a separate context. In at least one embodiment, position-only shading can hide long culling runs for discarded triangles, allowing shading to complete earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed function logic 2516 can execute position shaders in parallel with the main application and generally generate critical results faster than the full pipeline because the culling pipeline obtains and masks the position attributes of the vertices without having to perform rasterization and render the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether those triangles are culled. In at least one embodiment, the full pipeline (which in this case may be called a replay pipeline) can consume visibility information to skip culled triangles to mask only visible triangles that are ultimately passed to the rasterization stage.

[0289] In at least one embodiment, the additional fixed-function logic 2516 may also include machine learning acceleration logic, such as fixed-function matrix multiplication logic, to implement optimizations including for machine learning training or inference.

[0290] In at least one embodiment, a set of execution resources is included within each graphics sub-core 2501A-2501F that can be used to perform graphics, media, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader programs. In at least one embodiment, the graphics sub-core 2501A-2501F includes a plurality of EU arrays 2502A-2502F, 2504A-2504F, thread dispatch and inter-thread communication (TD / IC) logic 2503A-2503F, 3D (e.g., texture) samplers 2505A-2505F, media samplers 2506A-2506F, shader processors 2507A-2507F, and shared local memory (SLM) 2508A-2508F. Each of the EU arrays 2502A-2502F and 2504A-2504F includes multiple execution units, which are general-purpose graphics processing units capable of servicing graphics, media, or compute operations, executing floating-point and integer / fixed-point logic operations, including graphics, media, or compute shader programs. In at least one embodiment, the TD / IC logic 2503A-2503F performs local thread dispatch and thread control operations for the execution units within the sub-core and facilitates communication between threads executing on the execution units of the sub-core. In at least one embodiment, the 3D samplers 2505A-2505F can read texture or other 3D graphics-related data into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, the media samplers 2506A-2506F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2501A-2501F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 2501A-2501F may utilize shared local memory 2508A-2508F within each sub-core, enabling threads executing within a thread group to execute using a common pool of on-chip memory.

[0291] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6BDetail is provided regarding the inference and / or training logic 615. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the graphics processor 2510. For example, in at least one embodiment, the training and / or inference techniques described herein may be used on the graphics processor 2312, graphics microcontroller 2538, geometry and fixed function pipelines 2514 and 2536, or Figure 25 Furthermore, in at least one embodiment, the inference and / or training operations described herein may use the addition Figure 6A or Figure 6B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2500 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0292] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0293] Figures 26A-26B Thread execution logic 2600 is shown for an array of processing elements comprising a graphics processor core, in accordance with at least one embodiment. Figure 26A At least one embodiment is shown in which thread execution logic 2600 is used. Figure 26B Illustrative internal details of an execution unit are shown in accordance with at least one embodiment.

[0294] like Figure 26AAs shown in FIG, in at least one embodiment, thread execution logic 2600 includes a shader processor 2602, a thread dispatcher 2604, an instruction cache 2606, a scalable execution unit array including a plurality of execution units 2608A-2608N, a sampler 2610, a data cache 2612, and a data port 2614. In at least one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 2608A, 2608B, 2608C, 2608D through 2608N-1 and 2608N), for example, based on the computational requirements of the workload. In at least one embodiment, the scalable execution units are interconnected via an interconnect structure that links to each execution unit. In at least one embodiment, thread execution logic 2600 includes one or more connections to memory (such as system memory or cache memory) through instruction cache 2606, data port 2614, sampler 2610, and one or more of execution units 2608A-2608N. In at least one embodiment, each execution unit (e.g., 2608A) is an independent programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 2608A-2608N is scalable to include any number of individual execution units.

[0295] In at least one embodiment, execution units 2608A-2608N are primarily used to execute shader programs. In at least one embodiment, shader processor 2602 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2604. In at least one embodiment, thread dispatcher 2604 includes logic for arbitrating thread initialization requests from graphics and media pipelines and instantiating requested threads on one or more execution units in execution units 2608A-2608N. For example, in at least one embodiment, the geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher 2604 can also handle runtime thread generation requests from executing shader programs.

[0296] In at least one embodiment, execution units 2608A-2608N support an instruction set that includes native support for many standard 3D graphics shader instructions, enabling shader programs from graphics libraries such as Direct3D and OpenGL to execute with minimal translation. In at least one embodiment, the execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders). In at least one embodiment, each execution unit 2608A-2608N includes one or more arithmetic logic units (ALUs) capable of multi-issue single instruction, multiple data (SIMD) and multi-threaded operation, enabling an efficient execution environment despite higher latency memory accesses. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. In at least one embodiment, execution is multiple issues per clock to the pipeline, which is capable of integer, single-precision, and double-precision floating-point operations, SIMD branching functions, logical operations, transcendental operations, and other operations. In at least one embodiment, while waiting for data from memory or one of the shared functions, dependency logic within execution units 2608A-2608N causes the waiting thread to sleep until the requested data is returned. In at least one embodiment, while the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, in at least one embodiment, during the delay associated with vertex shader operations, the execution unit can perform operations on a pixel shader, a fragment shader, or another type of shader program (including a different vertex shader).

[0297] In at least one embodiment, each of execution units 2608A-2608N operates on an array of data elements. In at least one embodiment, the number of data elements is the "execution size" or number of lanes of an instruction. In at least one embodiment, an execution lane is the logic used to perform data element access, masking, and flow control within an instruction. In at least one embodiment, the number of lanes can be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) used for a particular graphics processor. In at least one embodiment, execution units 2608A-2608N support integer and floating point data types.

[0298] In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, various data elements can be stored in registers as packed data types, and the execution unit will process various elements based on the data size of those elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit packed data elements (quad word (QW) size data elements), eight separate 32-bit packed data elements (double word (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

[0299] In at least one embodiment, one or more execution units can be combined into fused execution units 2609A-2609N having thread control logic (2607A-2607N) shared with the fused EU. In at least one embodiment, multiple EUs can be merged into one EU group. In at least one embodiment, the number of EUs in the fused EU group can be configured to execute separate SIMD hardware threads. The number of EUs in the fused EU group can vary according to various embodiments. In at least one embodiment, each EU can execute various SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit 2609A-2609N includes at least two execution units. For example, in at least one embodiment, the fused execution unit 2609A includes a first EU 2608A, a second EU 2608B, and thread control logic 2607A shared with the first EU 2608A and the second EU 2608B. In at least one embodiment, thread control logic 2607A controls threads executing on fused graphics execution unit 2609A, allowing each EU within fused execution units 2609A-2609N to execute using a common instruction pointer register.

[0300] In at least one embodiment, one or more internal instruction caches (e.g., 2606) are included in thread execution logic 2600 to cache thread instructions for the execution units. In at least one embodiment, one or more data caches (e.g., 2612) are included to cache thread data during thread execution. In at least one embodiment, a sampler 2610 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, sampler 2610 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution units.

[0301] During execution, in at least one embodiment, the graphics and media pipeline sends thread initiation requests to thread execution logic 2600 via thread spawning and dispatching logic. In at least one embodiment, once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 2602 is invoked to further calculate output information and cause the results to be written to output surfaces (e.g., color buffer, depth buffer, stencil buffer, etc.). In at least one embodiment, the pixel shader or fragment shader calculates the values ​​of various vertex attributes to be interpolated across the rasterized objects. In at least one embodiment, the pixel processor logic within shader processor 2602 then executes the pixel or fragment shader program provided by an application program interface (API). In at least one embodiment, to execute the shader program, shader processor 2602 dispatches threads to execution units (e.g., 2608A) via thread dispatcher 2604. In at least one embodiment, shader processor 2602 uses texture sampling logic in sampler 2610 to access texture data stored in texture maps in memory. In at least one embodiment, arithmetic operations on texture data and input geometry data calculate pixel color data for each geometry fragment, or discard one or more pixels for further processing.

[0302] In at least one embodiment, data port 2614 provides a memory access mechanism for thread execution logic 2600 to output processed data to memory for further processing on the graphics processor output pipeline. In at least one embodiment, data port 2614 includes or is coupled to one or more cache memories (e.g., data cache 2612) to cache data for memory access via the data port.

[0303] like Figure 26BAs shown, in at least one embodiment, graphics execution unit 2608 may include an instruction fetch unit 2637, a general register file array (GRF) 2624, an architectural register file array (ARF) 2626, a thread arbiter 2622, an issue unit 2630, a branch unit 2632, a set of SIMD floating point units (FPUs) 2634, and, in at least one embodiment, a set of dedicated integer SIMD ALUs 2635. GRF 2624 and ARF 2626 include a set of general register files and architectural register files associated with each simultaneous hardware thread that can be active in graphics execution unit 2608. In at least one embodiment, per-thread architectural state is maintained in ARF 2626, while data used during thread execution is stored in GRF 2624. In at least one embodiment, the execution state of each thread, including the instruction pointer of each thread, may be maintained in thread-specific registers in ARF 2626.

[0304] In at least one embodiment, graphics execution unit 2608 has an architecture that is a combination of simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). In at least one embodiment, the architecture has a modular configuration that can be fine-tuned at design time based on the target number of simultaneous threads and the number of registers per execution unit, where execution unit resources are logically allocated for executing multiple simultaneous threads.

[0305] In at least one embodiment, graphics execution unit 2608 can collectively issue multiple instructions, each of which can be a different instruction. In at least one embodiment, the thread arbiter 2622 of a graphics execution unit thread 2608 can dispatch instructions to one of the issue unit 2630, branch unit 2632, or SIMD FPU 2634 for execution. In at least one embodiment, each execution thread can access 128 general purpose registers in GRF 2624, each of which can store 32 bytes and can be accessed as a SIMD 8-element vector of 32-bit data elements. In at least one embodiment, each execution unit thread can access 4KB of GRF 2624, although embodiments are not limited thereto and more or fewer register resources may be provided in other embodiments. In at least one embodiment, a maximum of seven threads can execute simultaneously, although the number of threads per execution unit may vary depending on the embodiment. In at least one embodiment where seven threads have access to 4KB, GRF 2624 can store a total of 28KB. In at least one embodiment, flexible addressing modes may allow registers to be addressed together to efficiently build wider registers or rectangular block data structures representing strides.

[0306] In at least one embodiment, memory operations, sampler operations, and other longer latency system communications are scheduled via "send" instructions executed by message passing send unit 2630. In at least one embodiment, dispatching branch instructions to dedicated branch unit 2632 facilitates SIMD divergence and eventual convergence.

[0307] In at least one embodiment, the graphics execution unit 2608 includes one or more SIMD floating point units (FPUs) 2634 to perform floating point operations. In at least one embodiment, one or more FPUs 2634 also support integer computations. In at least one embodiment, one or more FPUs 2634 can SIMD perform up to M 32-bit floating point (or integer) operations, or SIMD perform up to 2M 16-bit integer or 16-bit floating point operations. In at least one embodiment, at least one FPU provides extended math capabilities to support high-throughput transcendental math functions and double-precision 64-bit floating point. In at least one embodiment, a set of 8-bit integer SIMD ALUs 2635 are also present and can be specifically optimized to perform operations related to machine learning computations.

[0308] In at least one embodiment, an array of multiple instances of graphics execution unit 2608 may be instantiated in graphics sub-core groupings (e.g., sub-slices). In at least one embodiment, execution unit 2608 may execute instructions across multiple execution lanes. In at least one embodiment, each thread executing on graphics execution unit 2608 executes on a different lane.

[0309] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Provides details about the reasoning and / or training logic 615. In at least one embodiment, some or all of the reasoning and / or training logic 615 may be incorporated into the execution logic 2600. Additionally, in at least one embodiment, other than Figure 6A or Figure 6B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution logic 2600 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0310] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0311] Figure 27 A parallel processing unit ("PPU") 2700 is shown in accordance with at least one embodiment. In at least one embodiment, PPU 2700 is configured with machine-readable code that, if executed by PPU 2700, causes PPU 2700 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, PPU 2700 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a group of instructions configured to be executed by PPU 2700. In at least one embodiment, PPU 2700 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device, such as a liquid crystal display ("LCD") device. In at least one embodiment, the PPU 2700 is used to perform computations such as linear algebra operations and machine learning operations. Figure 27 The example parallel processor is shown for illustrative purposes only and should be construed as a non-limiting example of a processor architecture contemplated within the scope of the present disclosure, and any suitable processor may be employed in addition and / or in place thereof.

[0312] In at least one embodiment, one or more PPUs 2700 are configured to accelerate high-performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, the PPU 2700 is configured to accelerate deep learning systems and applications, including the following non-limiting examples: autonomous vehicle platforms, deep learning, high-precision speech, image, and text recognition systems, intelligent video analysis, molecular simulation, drug discovery, disease diagnosis, weather forecasting, big data analysis, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimization, and personalized user recommendations.

[0313] In at least one embodiment, the PPU 2700 includes, but is not limited to, an input / output ("I / O") unit 2706, a front-end unit 2710, a scheduler unit 2712, a work distribution unit 2714, a hub 2716, a crossbar switch ("Xbar") 2720, one or more general processing clusters ("GPCs") 2718, and one or more partitioning units ("memory partitioning units") 2722. In at least one embodiment, the PPU 2700 is connected to a host processor or other PPUs 2700 via one or more high-speed GPU interconnects ("GPU interconnects") 2708. In at least one embodiment, the PPU 2700 is connected to a host processor or other peripheral devices via interconnect 2702. In one embodiment, the PPU 2700 is connected to local memory including one or more memory devices ("memory") 2704. In at least one embodiment, the memory devices 2704 include, but are not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as a high bandwidth memory ("HBM") subsystem with multiple DRAM dies stacked within each device.

[0314] In at least one embodiment, the high-speed GPU interconnect 2708 may refer to a wire-based, multi-lane communication link that a system uses to scale and includes one or more PPUs 2700 in conjunction with one or more central processing units ("CPUs"), supporting cache coherency between the PPUs 2700 and the CPUs, as well as CPU mastering. In at least one embodiment, the high-speed GPU interconnect 2708 transmits data and / or commands to other units of the PPU 2700, such as one or more copy engines, video encoders, video decoders, power management units, and / or other processors, via a hub 2716. Figure 27 Other components that may not be explicitly shown.

[0315] In at least one embodiment, the I / O unit 2706 is configured to receive data from the host processor ( Figure 272706). In at least one embodiment, the I / O unit 2706 communicates with the host processor directly through the system bus 2702 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, the I / O unit 2706 can communicate with one or more other processors (e.g., one or more PPUs 2700) via the system bus 2702. In at least one embodiment, the I / O unit 2706 implements a Peripheral Component Interconnect Express ("PCIe") interface for communicating over the PCIe bus. In at least one embodiment, the I / O unit 2706 implements an interface for communicating with external devices.

[0316] In at least one embodiment, the I / O unit 2706 decodes packets received via the system bus 2702. In at least one embodiment, at least some of the packets represent commands configured to cause the PPU 2700 to perform various operations. In at least one embodiment, the I / O unit 2706 sends the decoded commands to various other units of the PPU 2700 as specified by the commands. In at least one embodiment, the commands are sent to the front end unit 2710 and / or to the hub 2716 or other units of the PPU 2700, such as one or more replication engines, video encoders, video decoders, power management units, etc. Figure 27 In at least one embodiment, I / O unit 2706 is configured to route communications between the various logical units of PPU 2700.

[0317] In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 2700 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., read / write) by both the host processor and the PPU 2700—the host interface unit can be configured to access the buffer in system memory connected to the system bus 2702 via memory requests transmitted via the I / O unit 2706 over the system bus 2702. In at least one embodiment, the host processor writes a command stream into the buffer and then sends a pointer indicating the beginning of the command stream to the PPU 2700, so that the front end unit 2710 receives pointers to one or more command streams and manages the one or more command streams, reading commands from the command streams and forwarding the commands to the various units of the PPU 2700.

[0318] In at least one embodiment, the front end unit 2710 is coupled to a scheduler unit 2712 that configures the various GPCs 2718 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2712 is configured to track state information related to the various tasks managed by the scheduler unit 2712, where the state information may indicate which GPC 2718 the task is assigned to, whether the task is active or inactive, a priority associated with the task, and the like. In at least one embodiment, the scheduler unit 2712 manages multiple tasks that execute on one or more GPCs 2718.

[0319] In at least one embodiment, the scheduler unit 2712 is coupled to a work distribution unit 2714, which is configured to dispatch tasks for execution on the GPCs 2718. In at least one embodiment, the work distribution unit 2714 tracks a plurality of scheduled tasks received from the scheduler unit 2712 and manages a pending task pool and an active task pool for each GPC 2718. In at least one embodiment, the pending task pool includes a plurality of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 2718; the active task pool may include a plurality of time slots (e.g., 4 time slots) for tasks actively being processed by the GPC 2718, such that as a task in a GPC 2718 completes execution, the task is evicted from the active task pool of the GPC 2718, and one of the other tasks is selected from the pending task pool and scheduled for execution on the GPC 2718. In at least one embodiment, if an active task is idle on a GPC 2718, such as while waiting for a data dependency to be resolved, the active task is evicted from the GPC 2718 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on the GPC 2718.

[0320] In at least one embodiment, work distribution unit 2714 communicates with one or more GPCs 2718 via XBar 2720. In at least one embodiment, XBar 2720 is an interconnect network that couples many units of PPU 2700 to other units of PPU 2700 and can be configured to couple work distribution unit 2714 to a specific GPC 2718. In at least one embodiment, one or more other units of PPU 2700 can also be connected to XBar 2720 through hub 2716.

[0321] In at least one embodiment, tasks are managed by a scheduler unit 2712 and assigned to one of the GPCs 2718 by a work distribution unit 2714. The GPCs 2718 are configured to process tasks and produce results. In at least one embodiment, the results can be consumed by other tasks in the GPC 2718, routed to a different GPC 2718 via an XBar 2720, or stored in memory 2704. In at least one embodiment, the results can be written to memory 2704 via a partition unit 2722, which implements a memory interface for writing data to or reading data from memory 2704. In at least one embodiment, the results can be transferred to another PPU 2704 or a CPU via a high-speed GPU interconnect 2708. In at least one embodiment, the PPU 2700 includes, but is not limited to, U partition units 2722, which is equal to the number of separate and distinct memory devices 2704 coupled to the PPU 2700. In at least one embodiment, the partition units 2722 will be discussed below in conjunction with Figure 29 Describe in more detail.

[0322] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2700. In one embodiment, multiple computing applications are executed simultaneously by the PPU 2700, and the PPU 2700 provides isolation, quality of service ("QoS"), and independent address spaces for the multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 2700, and the driver core outputs the tasks to one or more streams processed by the PPU 2700. In at least one embodiment, each task includes one or more related groups of threads, which may be referred to as warps. In at least one embodiment, a warp includes multiple related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads that include instructions for performing tasks and exchanging data through shared memory. In at least one embodiment, in combination Figure 29 Threads and cooperating threads are described in greater detail according to at least one embodiment.

[0323] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6BProvides details regarding inference and / or training logic 615. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the PPU 2700. In at least one embodiment, the PPU 2700 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or the PPU 2700. In at least one embodiment, the PPU 2700 can be used to perform one or more of the neural network use cases described herein.

[0324] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0325] Figure 28 A general processing cluster ("GPC") 2800 is shown in accordance with at least one embodiment. In at least one embodiment, the GPC 2800 is Figure 27 2718. In at least one embodiment, each GPC 2800 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2800 includes, but is not limited to, a pipeline manager 2802, a pre-raster operations unit ("preROP") 2804, a raster engine 2808, a work distribution crossbar ("WDX") 2816, a memory management unit ("MMU") 2818, one or more data processing clusters ("DPCs") 2806, and any suitable combination of components.

[0326] In at least one embodiment, the operation of the GPC 2800 is controlled by a pipeline manager 2802. In at least one embodiment, the pipeline manager 2802 manages the configuration of one or more DPCs 2806 to process tasks assigned to the GPC 2800. In at least one embodiment, the pipeline manager 2802 configures at least one of the one or more DPCs 2806 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, a DPC 2806 is configured to execute vertex shader programs on a programmable streaming multiprocessor ("SM") 2814. In at least one embodiment, the pipeline manager 2802 is configured to route data packets received from a work distribution unit to appropriate logic within the GPC 2800, and in at least one embodiment, some data packets may be routed to fixed-function hardware units in the preROP 2804 and / or raster engine 2808, while other data packets may be routed to a DPC 2806 for processing by a primitive engine 2812 or an SM 2814. In at least one embodiment, pipeline manager 2802 configures at least one of DPCs 2806 to implement a neural network model and / or a computational pipeline.

[0327] In at least one embodiment, the preROP unit 2804 is configured to route data generated by the raster engine 2808 and the DPC 2806 to the raster operations ("ROP") unit in the partition unit 2722 in at least one embodiment, in conjunction with Figure 27 Described in more detail. In at least one embodiment, the preROP unit 2804 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, the raster engine 2808 includes, but is not limited to, a plurality of fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, the raster engine 2808 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to the coarse raster engine to generate coverage information for the primitives (e.g., an x, y coverage mask for the tile); the output of the coarse raster engine is passed to the culling engine, where fragments associated with primitives that fail the z test are culled, and to the clipping engine, where fragments outside the viewing frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to a fine raster engine to generate properties for the pixel fragments based on a plane equation generated by the setup engine. In at least one embodiment, the output of the raster engine 2808 includes fragments to be processed by any appropriate entity (e.g., by a fragment shader implemented within the DPC 2806).

[0328] In at least one embodiment, each DPC 2806 included in a GPC 2800 includes, but is not limited to, an M-pipeline controller ("MPC") 2810; a primitive engine 2812; one or more SMs 2814; and any suitable combination thereof. In at least one embodiment, the MPC 2810 controls the operation of the DPC 2806, routing packets received from the pipeline manager 2802 to appropriate units within the DPC 2806. In at least one embodiment, packets associated with vertices are routed to the primitive engine 2812, which is configured to fetch vertex attributes associated with the vertices from memory; conversely, data packets associated with shader programs may be sent to the SM 2814.

[0329] In at least one embodiment, SM 2814 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, SM 2814 is multithreaded and configured to simultaneously execute multiple threads (e.g., 32 threads) from a particular thread group and implements a single instruction, multiple data ("SIMD") architecture, in which each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instructions. In at least one embodiment, SM 2814 implements a single instruction, multiple thread ("SIMT") architecture, in which each thread in a group of threads is configured to process a different set of data based on the same instruction set, but in which individual threads in a thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby enabling concurrency between warps and serial execution within a warp when threads in the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby enabling equal concurrency between all threads within a warp and between warps. In at least one embodiment, execution state is maintained for each individual thread, and threads executing the same instruction can be converged and executed in parallel to improve efficiency. At least one embodiment of SM 2814 is described in more detail below.

[0330] In at least one embodiment, the MMU 2818 provides a communication channel between the GPC 2800 and the memory partition unit (e.g., Figure 27 The MMU 2818 provides an interface between the memory and the partition unit 2722, and provides virtual to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 2818 provides one or more translation lookaside buffers ("TLBs") for performing translation of virtual addresses to physical addresses in memory.

[0331] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 6A and / or Figure 6B Provides details regarding inference and / or training logic 615. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the GPC 2800. In at least one embodiment, the GPC 2800 is used to infer or predict information based on a machine learning model (e.g., a neural network) that has been trained by another processor or system or the GPC 2800. In at least one embodiment, the GPC 2800 can be used to perform one or more of the neural network use cases described herein.

[0332] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0333] Figure 29 A memory partition unit 2900 of a parallel processing unit ("PPU") is shown in accordance with at least one embodiment. In at least one embodiment, the memory partition unit 2900 includes, but is not limited to, a raster operations ("ROP") unit 2902; a level 2 ("L2") cache 2904; a memory interface 2906; and any suitable combination thereof. In at least one embodiment, the memory interface 2906 is coupled to a memory. In at least one embodiment, the memory interface 2906 can implement a 32-, 64-, 128-, 1024-bit data bus, or a similar implementation for high-speed data transfer. In at least one embodiment, the PPU includes U memory interfaces 2906, one memory interface 2906 for each pair of partition units 2900, wherein each pair of partition units 2900 is connected to a corresponding memory device. For example, in at least one embodiment, the PPU can be connected to up to Y memory devices, such as a high-bandwidth memory stack or graphics double data rate version 5 synchronous dynamic random access memory ("GDDR5 SDRAM").

[0334] In at least one embodiment, the memory interface 2906 implements a High Bandwidth Memory 2nd Generation ("HBM2") memory interface, and Y is equal to half of U. In at least one embodiment, the HBM2 memory stack is located on the same physical package as the PPU, providing significant power and area savings compared to traditional GDDR5 SDRAM systems. In at least one embodiment, each HBM2 stack includes, but is not limited to, four memory dies, and Y is equal to 4, with each HBM2 stack including two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits. In at least one embodiment, the memory supports single error correction, double error detection ("SECDED") error correction code ("ECC") to protect data. In at least one embodiment, ECC provides higher reliability for computing applications that are sensitive to data corruption.

[0335] In at least one embodiment, the PPU implements a multi-level memory hierarchy. In at least one embodiment, the memory partitioning unit 2900 supports unified memory to provide a single unified virtual address space for the central processing unit ("CPU") and PPU memory, thereby enabling data sharing between virtual memory systems. In at least one embodiment, the frequency of PPU accesses to memory located on other processors is tracked to ensure that memory pages are moved to the physical memory of the PPU that accesses the pages more frequently. In at least one embodiment, the high-speed GPU interconnect 2708 supports address translation services that allow the PPU to directly access the CPU's page tables and provide full access to the CPU's memory through the PPU.

[0336] In at least one embodiment, the copy engine transfers data between multiple PPUs or between a PPU and a CPU. In at least one embodiment, the copy engine can generate a page fault for an address that is not mapped in a page table, and the memory partition unit 2900 then services the page fault, maps the address into a page table, and then the copy engine performs the transfer. In at least one embodiment, fixed (i.e., non-pageable) memory is operated for multiple copy engines between multiple processors, thereby substantially reducing the available memory. In at least one embodiment, in the event of a hardware page fault, the address can be passed to the copy engine without regard to whether it resides in the memory page, and the copy process is transparent.

[0337] According to at least one embodiment, Figure 27Data from memory 2704 or other system memory is retrieved by the memory partition unit 2900 and stored in the L2 cache 2904, which is located on-chip and shared between the various GPCs. In at least one embodiment, each memory partition unit 2900 includes, but is not limited to, at least a portion of the L2 cache associated with the corresponding memory device. In at least one embodiment, lower-level caches are implemented in various units within the GPC. In at least one embodiment, each SM 2814 may implement a level 1 ("L1") cache, where the L1 cache is private memory dedicated to a particular SM 2814, and data is retrieved from the L2 cache 2904 and stored in each L1 cache for processing in the functional units of the SM 2814. In at least one embodiment, the L2 cache 2904 is coupled to the memory interface 2906 and the XBar 2720.

[0338] In at least one embodiment, ROP unit 2902 performs graphics raster operations related to pixel color, such as color compression, pixel blending, and the like. In at least one embodiment, ROP unit 2902 performs depth testing in conjunction with raster engine 2808, receiving the depth of a sample location associated with a pixel fragment from the culling engine of raster engine 2808. In at least one embodiment, the depth is tested against the corresponding depth in the depth buffer associated with the sample location of the fragment. In at least one embodiment, if the fragment passes the depth test for the sample location, ROP unit 2902 updates the depth buffer and sends the result of the depth test to raster engine 2808. It will be appreciated that the number of partition units 2900 can differ from the number of GPCs, and therefore, in at least one embodiment, each ROP unit 2902 can be coupled to each GPC. In at least one embodiment, ROP unit 2902 tracks packets received from different GPCs and determines to which the results generated by ROP unit 2902 are routed via XBar 2720.

[0339] Figure 30 Streaming Multiprocessor ("SM") 3000 is shown in accordance with at least one embodiment. In at least one embodiment, SM 3000 is Figure 28SM 2814. In at least one embodiment, SM 3000 includes, but is not limited to, an instruction cache 3002; one or more scheduler units 3004; a register file 3008; one or more processing cores ("cores") 3010; one or more special function units ("SFUs") 3012; one or more load / store units ("LSUs") 3014; an interconnect network 3016; a shared memory / level 1 ("L1") cache 3018; and any suitable combination thereof. In at least one embodiment, a work distribution unit schedules tasks for execution on general processing clusters ("GPCs") of parallel processing units ("PPUs"), with each task being assigned to a specific data processing cluster ("DPC") within the GPC, and if the task is associated with a shader program, the task is assigned to one of SMs 3000. In at least one embodiment, scheduler unit 3004 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 3000. In at least one embodiment, the scheduler unit 3004 schedules thread blocks for execution as warps of parallel threads, where each thread block is assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, the scheduler unit 3004 manages a plurality of different thread blocks, assigns warps to different thread blocks, and then dispatches instructions from a plurality of different cooperating groups to various functional units (e.g., processing core 3010, SFU 3012, and LSU 3014) during each clock cycle.

[0340] In at least one embodiment, cooperative groups can refer to a programming model for organizing groups of communicating threads that allows developers to express the granularity at which threads are communicating, thereby enabling the expression of richer, more efficient decompositions of parallelism. In at least one embodiment, a cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, applications of conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads() function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than a thread block and synchronize within the defined group to achieve higher performance, design flexibility, and software reuse in the form of a collective group-wide function interface. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at sub-block (i.e., down to a single thread) and multi-block granularity and perform collective operations, such as synchronizing threads within a cooperative group. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing libraries and utility functions to safely synchronize in their local environment without making assumptions about convergence. In at least one embodiment, the cooperation group primitive enables new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

[0341] In at least one embodiment, the dispatch unit 3006 is configured to send instructions to one or more of the functional units, and the scheduler unit 3004 includes, but is not limited to, two dispatch units 3006 that enable two different instructions from the same warp to be dispatched during each clock cycle. In at least one embodiment, each scheduler unit 3004 includes a single dispatch unit 3006 or additional dispatch units 3006.

[0342] In at least one embodiment, each SM 3000 includes, but is not limited to, a register file 3008 that provides a set of registers for the functional units of SM 3000. In at least one embodiment, register file 3008 is partitioned between each functional unit, allocating a dedicated portion of register file 3008 to each functional unit. In at least one embodiment, register file 3008 is partitioned between the different warps executed by SM 3000, and register file 3008 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM 3000 includes, but is not limited to, a plurality of L processing cores 3010. In at least one embodiment, SM 3000 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 3010. In at least one embodiment, each processing core 3010 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing core 3010 includes, but is not limited to, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

[0343] According to at least one embodiment, the tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing core 3010. In at least one embodiment, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiplication and accumulation operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0344] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating-point matrices, and the accumulation matrices C and D are 16-bit floating-point or 32-bit floating-point matrices. In at least one embodiment, the tensor core performs a 32-bit floating-point accumulation operation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations and results in a full-precision product, which is then accumulated with other intermediate products using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API (such as the CUDA 9 C++ API) exposes specialized matrix load, matrix multiplication and accumulation, and matrix store operations to efficiently use the tensor cores from a CUDA-C++ program. In at least one embodiment, at the CUDA level, the warp-level interface assumes a 16×16 matrix size that spans all 32 warp threads.

[0345] In at least one embodiment, each SM 3000 includes, but is not limited to, M SFUs 3012 that perform specialized functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs 3012 include, but are not limited to, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs 3012 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture units are configured to load texture maps (e.g., 2D arrays of texels) from memory and sample the texture maps to generate sampled texture values ​​for use by shader programs executed by the SM 3000. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 3018. In at least one embodiment, the texture units implement texture operations (such as filtering operations) using mip-maps (e.g., texture maps with different levels of detail), according to at least one embodiment. In at least one embodiment, each SM 3000 includes, but is not limited to, two texture units.

[0346] In at least one embodiment, each SM 3000 includes, but is not limited to, N LSUs 3014 that implement load and store operations between the shared memory / L1 cache 3018 and the register file 3008. In at least one embodiment, each SM 3000 includes, but is not limited to, an interconnection network 3016 that connects each functional unit to the register file 3008 and connects the LSUs 3014 to both the register file 3008 and the shared memory / L1 cache 3018. In at least one embodiment, the interconnection network 3016 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 3008 and to connect the LSUs 3014 to memory locations in the register file 3008 and the shared memory / L1 cache 3018.

[0347] In at least one embodiment, shared memory / L1 cache 3018 is an array of on-chip memory that, in at least one embodiment, allows for data storage and communication between the SM 3000 and the primitive engines, as well as between threads within the SM 3000. In at least one embodiment, shared memory / L1 cache 3018 includes, but is not limited to, 128KB of storage capacity and is located in the path from the SM 3000 to the partition unit. In at least one embodiment, shared memory / L1 cache 3018 is used, in at least one embodiment, to cache reads and writes. In at least one embodiment, one or more of shared memory / L1 cache 3018, L2 cache, and memory is a backing store.

[0348] In at least one embodiment, combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory accesses. In at least one embodiment, capacity is used by programs that do not use the shared memory or use it as a cache, for example, if the shared memory is configured to use half of its capacity, and texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within shared memory / L1 cache 3018 enables shared memory / L1 cache 3018 to function as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, when configured for general-purpose parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, the fixed-function graphics processing unit is bypassed, creating a simpler programming model. In at least one embodiment, in a general-purpose parallel computing configuration, the work distribution unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, threads in a block execute the same program, use unique thread IDs in computations to ensure that each thread generates unique results, use SM 3000 to execute the program and perform computations, use shared memory / L1 cache 3018 to communicate between threads, and use LSU 3014 to read and write global memory through shared memory / L1 cache 3018 and a memory partitioning unit. In at least one embodiment, when configured for general-purpose parallel computation, SM 3000 writes commands to scheduler unit 3004 that can be used to start new work on a DPC.

[0349] In at least one embodiment, the PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smartphone (e.g., wireless, handheld device), a personal digital assistant ("PDA"), a digital camera, a vehicle, a head-mounted display, a handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-chip ("SoC") along with one or more other devices (e.g., an additional PPU, memory, a reduced instruction set computer ("RISC") CPU, one or more memory management units ("MMUs"), a digital-to-analog converter ("DAC"), etc.

[0350] In at least one embodiment, the PPU can be included on a graphics card that includes one or more storage devices. The graphics card can be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU can be an integrated graphics processing unit ("iGPU") included in a chipset on the motherboard.

[0351] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations related to one or more embodiments. Figure 6A and / or Figure 6B Provides details regarding inference and / or training logic 615. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the SM 3000. In at least one embodiment, the SM 3000 is used to infer or predict information based on a machine learning model (e.g., a neural network) that has been trained by another processor or system or by the SM 3000. In at least one embodiment, the SM 3000 can be used to perform one or more of the neural network use cases described herein.

[0352] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic can be used with the components of these figures to generate one or more images or video frames for one or more viewpoints.

[0353] In at least one embodiment, a single semiconductor platform can refer to a single semiconductor-based integrated circuit or chip. In at least one embodiment, a multi-chip module with increased connectivity can be used, which emulates on-chip operations and provides substantial improvements over traditional central processing unit ("CPU") and bus implementations. In at least one embodiment, the various modules can also be placed separately or in various combinations of semiconductor platforms, depending on user needs.

[0354] In at least one embodiment, a computer program in the form of machine-readable executable code or computer control logic algorithms is stored in main memory 1004 and / or secondary storage. According to at least one embodiment, if executed by one or more processors, the computer program enables system 1000 to perform various functions. In at least one embodiment, memory 1004, storage, and / or any other storage are possible examples of computer-readable media. In at least one embodiment, secondary storage can refer to any suitable storage device or system, such as a hard drive and / or removable storage drive, which represents a floppy disk drive, a tape drive, an optical drive, a digital versatile disk ("DVD") drive, a recording device, a universal serial bus ("USB") flash memory, etc. In at least one embodiment, the architecture and / or functionality of each of the previous figures is implemented in the context of any suitable combination of CPU 1002; parallel processing system 1012; an integrated circuit capable of having at least some of the capabilities of two CPUs 1002; parallel processing system 1012; a chipset (e.g., a group of integrated circuits designed to operate and sell as a unit to perform related functions, etc.); and integrated circuits.

[0355] In at least one embodiment, the architecture and / or functionality of the various previous figures are implemented in the context of a general-purpose computer system, a circuit board system, a game console system dedicated for entertainment purposes, a dedicated system, etc. In at least one embodiment, the computer system 1000 can take the form of a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smartphone (e.g., wireless, handheld device), a personal digital assistant ("PDA"), a digital camera, a vehicle, a head-mounted display, a handheld electronic device, a mobile telephone device, a television, a workstation, a game console, an embedded system, and / or any other type of logic.

[0356] In at least one embodiment, parallel processing system 1012 includes, but is not limited to, multiple parallel processing units ("PPUs") 1014 and associated memory 1016. In at least one embodiment, PPUs 1014 are connected to a host processor or other peripheral devices via an interconnect 1018 and a switch 1020 or multiplexer. In at least one embodiment, parallel processing system 1012 distributes computational tasks across parallelizable PPUs 1014, for example, as part of distributing computational tasks across multiple graphics processing unit ("GPU") thread blocks. In at least one embodiment, memory is shared and accessed (e.g., for read and / or write access) between some or all of PPUs 1014, although such shared memory may incur a performance penalty relative to using local memory and registers resident on the PPUs 1014. In at least one embodiment, the operation of the PPUs 1014 is synchronized using a command (such as __syncthreads()), where all threads in a block (e.g., executing across multiple PPUs 1014) reach a certain code execution point before proceeding.

[0357] Virtualized computing platform

[0358] Embodiments are disclosed that relate to a virtualized computing platform for advanced computing, such as image reasoning and image processing. Figure 31, which is an example data flow diagram of a process 3100 for generating and deploying an image processing and reasoning pipeline according to at least one embodiment. In at least one embodiment, process 3100 can be deployed for use with imaging equipment, processing equipment, genomics equipment, gene sequencing equipment, radiology equipment, and / or other equipment types at one or more facilities 3102, such as medical facilities, hospitals, medical institutions, clinics, research or diagnostic laboratories, etc. In at least one embodiment, process 3100 can be deployed to perform genomic analysis and reasoning on sequencing data. Examples of genomic analysis that can be performed using the systems and methods described herein include, but are not limited to, variant calling, mutation detection, and gene expression quantification. Process 3100 can be executed within training system 3104 and / or deployment system 3106. In at least one embodiment, training system 3104 can be used to train, deploy, and implement machine learning models (e.g., neural networks, object detection algorithms, computer vision algorithms, etc.) for use in deployment system 3106. In at least one embodiment, deployment system 3106 can be configured to offload processing and computing resources in a distributed computing environment to reduce infrastructure requirements at facility 3102. In at least one embodiment, the deployment system 3106 can provide a streamlined platform for selecting, customizing, and implementing virtual instruments for use with imaging devices (e.g., MRI, CT scan, X-ray, ultrasound, etc.) or sequencing devices at the facility 3102. In at least one embodiment, the virtual instrument can include a software-defined application for performing one or more processing operations on imaging data generated by the imaging device, sequencing device, radiology device, and / or other device types. In at least one embodiment, one or more applications in the pipeline can use or call services (e.g., reasoning, visualization, computation, AI, etc.) of the deployment system 3106 during the execution of the application.

[0359] In at least one embodiment, some of the applications used in the high-level processing and reasoning pipeline may use a machine learning model or other AI to perform one or more processing steps. In at least one embodiment, the machine learning model may be trained at the facility 3102 using data 3108 (such as imaging data) generated at the facility 3102 (and stored on one or more picture archiving and communication system (PACS) servers at the facility 3102), may be trained using imaging or sequencing data 3108 from another or more facilities (e.g., a different hospital, laboratory, clinic, etc.), or a combination thereof. In at least one embodiment, the training system 3104 may be used to provide applications, services, and / or other resources for generating working, deployable machine learning models for the deployment system 3106.

[0360] In at least one embodiment, the model registry 3124 can be supported by an object store that can support versioning and object metadata. In at least one embodiment, the object store can be supported by, for example, cloud storage (e.g., Figure 32 3226) is accessible from within the cloud platform through an application programming interface (API) compatible with the cloud. In at least one embodiment, machine learning models within the model registry 3124 can be uploaded, listed, modified, or deleted by developers or partners of the system interacting with the API. In at least one embodiment, the API can provide access to a method that allows a user with appropriate credentials to associate a model with an application so that the model can be executed as part of the execution of a containerized instantiation of the application.

[0361] In at least one embodiment, the training pipeline 3204 ( Figure 32 ) may include scenarios in which the facility 3102 is training its own machine learning model or has an existing machine learning model that needs to be optimized or updated. In at least one embodiment, imaging data 3108 generated by one or more imaging devices, sequencing devices, and / or other device types may be received. In at least one embodiment, once the imaging data 3108 is received, AI-assisted annotation 3110 may be used to help generate annotations corresponding to the imaging data 3108 to serve as ground truth data for the machine learning model. In at least one embodiment, the AI-assisted annotation 3110 may include one or more machine learning models (e.g., convolutional neural networks (CNNs)) that can be trained to generate annotations corresponding to certain types of imaging data 3108 (e.g., from certain devices) and / or certain types of abnormalities in the imaging data 3108. In at least one embodiment, the AI-assisted annotation 3110 can then be used directly, or can be adjusted or fine-tuned using an annotation tool (e.g., by researchers, clinicians, doctors, scientists, etc.) to generate ground truth data. In at least one embodiment, in some examples, labeled clinical data 3112 (e.g., annotations provided by clinicians, doctors, scientists, technicians, etc.) can be used as ground truth data for training machine learning models. In at least one embodiment, AI-assisted annotations 3110, labeled clinical data 3112, or a combination thereof can be used as ground truth data for training machine learning models. In at least one embodiment, the trained machine learning model can be referred to as an output model 3116 and can be used by the deployment system 3106, as described herein.

[0362] In at least one embodiment, the training pipeline 3204 ( Figure 32) may include scenarios where facility 3102 requires a machine learning model for performing one or more processing tasks of one or more applications in deployed system 3106, but facility 3102 may not currently have such a machine learning model (or may not have an optimized, efficient, or effective model for such a purpose). In at least one embodiment, an existing machine learning model may be selected from model registry 3124. In at least one embodiment, model registry 3124 may include machine learning models that have been trained to perform a variety of different inference tasks on imaging data. In at least one embodiment, the machine learning models in model registry 3124 may have been trained on imaging data from a facility different from facility 3102 (e.g., a remotely located facility). In at least one embodiment, the machine learning model may have been trained on imaging data from one location, two locations, or any number of locations. In at least one embodiment, when training is performed on imaging data from a particular location, the training may occur at that location, or at least in a manner that protects the confidentiality of the imaging data or restricts the transmission of the imaging data off-site (e.g., to comply with HIPAA regulations, privacy regulations, etc.). In at least one embodiment, once a model is trained or partially trained at one location, the machine learning model can be added to the model registry 3124. In at least one embodiment, the machine learning model can then be retrained or updated at any number of other facilities, and the retrained or updated model can be made available in the model registry 3124. In at least one embodiment, the machine learning model can then be selected from the model registry 3124—and referred to as an output model 3116—and can be used in the deployment system 3106 to perform one or more processing tasks for one or more applications of the deployment system.

[0363] In at least one embodiment, the training pipeline 3204 ( Figure 32), a scenario may include a facility 3102 that requires a machine learning model to perform one or more processing tasks for one or more applications in a deployed system 3106, but the facility 3102 may not currently have such a machine learning model (or may not have an optimized, efficient, or effective model for such a purpose). In at least one embodiment, the machine learning model selected from the model registry 3124 may not be fine-tuned or optimized for the imaging data 3108 generated at the facility 3102 due to population differences, genetic variation, robustness of the training data used to train the machine learning model, the diversity of abnormalities in the training data, and / or other issues with the training data. In at least one embodiment, AI-assisted annotation 3110 can be used to help generate annotations corresponding to the imaging data 3108, which is used as ground truth data for retraining or updating the machine learning model. In at least one embodiment, labeled clinical data 3112 (e.g., annotations provided by clinicians, doctors, scientists, etc.) can be used as ground truth data for training the machine learning model. In at least one embodiment, retraining or updating the machine learning model can be referred to as model training 3114. In at least one embodiment, model training 3114 (e.g., AI-assisted annotation 3110, labeled clinical data 3112, or a combination thereof) can be used as ground truth data for retraining or updating the machine learning model. In at least one embodiment, the trained machine learning model can be referred to as an output model 3116 and can be used by the deployment system 3106, as described herein.

[0364] In at least one embodiment, the deployment system 3106 may include software 3118, services 3120, hardware 3122, and / or other components, features, and functionality. In at least one embodiment, the deployment system 3106 may include a software "stack" such that the software 3118 may be built on top of the services 3120 and may use the services 3120 to perform some or all processing tasks, and the services 3120 and software 3118 may be built on top of the hardware 3122 and use the hardware 3122 to perform processing, storage, and / or other computing tasks of the deployment system 3106. In at least one embodiment, the software 3118 may include any number of different containers, each of which may perform an instantiation of an application. In at least one embodiment, each application may perform one or more processing tasks (e.g., reasoning, object detection, feature detection, segmentation, image enhancement, calibration, etc.) in a high-level processing and reasoning pipeline. In at least one embodiment, for each type of imaging device (e.g., CT, MRI, X-ray, ultrasound, sonography, echocardiography, etc.), sequencing device, radiology device, genomics device, etc., there can be any number of containers that can perform data processing tasks with respect to the imaging data 3108 (or other data types, such as those described herein) generated by the device. In at least one embodiment, a high-level processing and reasoning pipeline can be defined based on the selection of different containers desired or required to process the imaging data 3108, in addition to the containers that receive and configure the imaging data for use by each container and / or for use by the facility 3102 after processing through the pipeline (e.g., converting the output back into a usable data type, such as Digital Imaging and Communications in Medicine (DICOM) data, Radiology Information System (RIS) data, Clinical Information System (CIS) data, Remote Procedure Call (RPC) data, data substantially conforming to a Representational State Transfer (REST) ​​interface, data substantially conforming to a file-based interface, and / or raw data for storage and display at the facility 3102). In at least one embodiment, a combination of containers within software 3118 (e.g., a combination of containers that make up a pipeline) may be referred to as a virtual tool (as described in more detail herein), and the virtual tool may utilize services 3120 and hardware 3122 to perform some or all of the processing tasks of the application instantiated in the container.

[0365] In at least one embodiment, the data processing pipeline can receive input data (e.g., imaging data 3108) in DICOM, RIS, CIS, REST-compatible, RPC, raw, and / or other formats in response to an inference request (e.g., a request from a user of the deployment system 3106 (such as a clinician, doctor, radiologist, etc.). In at least one embodiment, the input data can represent one or more images, videos, and / or other data representations generated by one or more imaging devices, sequencing devices, radiology devices, genomics devices, and / or other device types. In at least one embodiment, the data can undergo pre-processing as part of the data processing pipeline to prepare the data for processing by one or more applications. In at least one embodiment, post-processing can be performed on the output of one or more inference tasks or other processing tasks of the pipeline to prepare the output data for the next application and / or prepare the output data for transmission and / or use by a user (e.g., in response to the inference request). In at least one embodiment, the inference task can be performed by one or more machine learning models, such as a trained or deployed neural network, which can include the output model 3116 of the training system 3104.

[0366] In at least one embodiment, the tasks of a data processing pipeline may be encapsulated in one or more containers, each of which represents a discrete, fully functional instantiation of an application and a virtualized computing environment capable of referencing a machine learning model. In at least one embodiment, the containers or applications may be published to a private (e.g., restricted access) area of ​​a container registry (described in more detail herein), and the trained or deployed models may be stored in the model registry 3124 and associated with one or more applications. In at least one embodiment, an image of the application (e.g., a container image) may be available in the container registry, and once selected by a user from the container registry for deployment in a pipeline, the image may be used to generate a container for the instantiation of the application for use by the user's system.

[0367] In at least one embodiment, developers (e.g., software developers, clinicians, doctors, etc.) can develop, publish, and store applications (e.g., as containers) for performing image processing and / or reasoning on provided data. In at least one embodiment, development, publishing, and / or storage can be performed using a software development kit (SDK) associated with the system (e.g., to ensure that the developed applications and / or containers are compatible or compliant with the system). In at least one embodiment, at least some of the services 3120 can be supported as part of the system (e.g., Figure 32The developed application may be tested locally (e.g., at the first facility, on data from the first facility) using an SDK of the system 3200). In at least one embodiment, because a DICOM object may contain anywhere from one to hundreds of images or other data types, and because the data varies, the developer may be responsible for managing (e.g., setting up constructs, building pre-processing into the application, etc.) the extraction and preparation of the input DICOM data. In at least one embodiment, once validated by the system 3200 (e.g., for accuracy, security, patient privacy, etc.), the application may be available in a container registry for selection and / or implementation by a user (e.g., a hospital, clinic, laboratory, healthcare provider, etc.) to perform one or more processing tasks on the data at the user's facility (e.g., the second facility).

[0368] In at least one embodiment, the developer can then share the application or container over the network for use by the system (e.g., Figure 32 3124). In at least one embodiment, completed and validated applications or containers can be stored in a container registry, and associated machine learning models can be stored in a model registry 3124. In at least one embodiment, a requesting entity (e.g., a user at a medical facility) providing an inference or image processing request can browse the container registry and / or model registry 3124 of applications, containers, datasets, machine learning models, etc., select a desired combination of elements to include in the data processing pipeline, and submit an imaging processing request. In at least one embodiment, the request can include the input data necessary to execute the request (and, in some examples, associated patient data), and / or can include a selection of one or more applications and / or machine learning models to be executed in processing the request. In at least one embodiment, the request can then be passed to one or more components of the deployment system 3106 (e.g., the cloud) to perform processing in the data processing pipeline. In at least one embodiment, processing by the deployment system 3106 can include referencing the selected elements (e.g., applications, containers, models, etc.) from the container registry and / or model registry 3124. In at least one embodiment, once the results are generated by the pipeline, the results can be returned to the user for reference (e.g., for viewing in a viewing application suite executed on a local, on-site workstation or terminal). In at least one embodiment, the radiologist can receive results from a data processing pipeline comprising any number of applications and / or containers, where the results can include abnormality detection in X-rays, CT scans, MRIs, etc.

[0369] In at least one embodiment, to assist in processing or executing applications or containers in the pipeline, services 3120 may be utilized. In at least one embodiment, services 3120 may include computing services, artificial intelligence (AI) services, visualization services, and / or other service types. In at least one embodiment, services 3120 may provide functionality that is common to one or more applications in software 3118, thereby abstracting functionality into services that can be called or utilized by applications. In at least one embodiment, the functionality provided by services 3120 may run dynamically and more efficiently, while also facilitating parallel processing of data by allowing applications to process data in parallel (e.g., using parallel computing platforms 3230 ( Figure 32 )) to scale well. In at least one embodiment, service 3120 can be shared between and among different applications, rather than requiring each application that shares the same functionality provided by service 3120 to have a corresponding instance of service 3120. In at least one embodiment, as a non-limiting example, the service may include an inference server or engine that can be used to perform detection or segmentation tasks. In at least one embodiment, a model training service may be included that can provide machine learning model training and / or retraining capabilities. In at least one embodiment, a data enhancement service may be further included that can provide GPU accelerated data (e.g., DICOM, RIS, CIS, REST compliant, RPC, raw, etc.) extraction, resizing, scaling and / or other enhancements. In at least one embodiment, a visualization service may be used that can add image rendering effects - such as ray tracing, rasterization, denoising, sharpening, etc. - to add realism to two-dimensional (2D) and / or three-dimensional (3D) models. In at least one embodiment, a virtual instrument service that provides beamforming, segmentation, reasoning, imaging and / or support for other applications within the pipeline of the virtual instrument may be included.

[0370] In at least one embodiment, where the service 3120 includes an AI service (e.g., an inference service), one or more machine learning models associated with an application for anomaly detection (e.g., tumor, growth abnormality, scarring, etc.) can be executed by calling (e.g., as an API call) the inference service (e.g., an inference server) to execute one or more machine learning models, or processing thereof, as part of the execution of the application. In at least one embodiment, where another application includes one or more machine learning models for a segmentation task, the application can call upon the inference service to execute the machine learning model for performing one or more of the processing operations associated with the segmentation task. In at least one embodiment, the software 3118 implementing the high-level processing and inference pipeline including the segmentation application and the anomaly detection application can be streamlined because each application can call the same inference service to perform one or more inference tasks.

[0371] In at least one embodiment, hardware 3122 may include a GPU, a CPU, a graphics card, an AI / deep learning system (e.g., an AI supercomputer such as NVIDIA's DGX), a cloud platform, or a combination thereof. In at least one embodiment, different types of hardware 3122 may be used to provide efficient, purpose-built support for software 3118 and services 3120 in deployment system 3106. In at least one embodiment, the use of GPU processing may be implemented for local processing (e.g., at facility 3102), within AI / deep learning systems, in cloud systems, and / or in other processing components of deployment system 3106 to improve efficiency, accuracy and efficacy (e.g., in real time) of image processing, image reconstruction, segmentation, MRI examinations, stroke or heart attack detection, image quality in rendering, and the like. In at least one embodiment, a facility may include imaging devices, genomics devices, sequencing devices, and / or other types of devices in the field that may utilize GPUs to generate imaging data representing a subject's anatomical structure. In at least one embodiment, as a non-limiting example, software 3118 and / or services 3120 may be optimized for GPU processing relative to deep learning, machine learning, and / or high-performance computing. In at least one embodiment, at least some of the computing environments of the deployment system 3106 and / or training system 3104 may be implemented in a data center using one or more supercomputers or high-performance computing systems with GPU-optimized software (e.g., a hardware and software combination of NVIDIA's DGX system). In at least one embodiment, the data center may be compliant with HIPAA regulations, such that the reception, processing, and transmission of imaging data and / or other patient data is handled securely with respect to the privacy of the patient data. In at least one embodiment, the hardware 3122 may include any number of GPUs that can be invoked to perform processing of the data in parallel, as described herein. In at least one embodiment, the cloud platform may also include GPU processing for GPU-optimized execution of deep learning tasks, machine learning tasks, or other computing tasks. In at least one embodiment, a cloud platform (e.g., NVIDIA's NGC) may be implemented using an AI / deep learning supercomputer and / or GPU-optimized software (e.g., provided on NVIDIA's DGX system) as a hardware abstraction and scaling platform. In at least one embodiment, the cloud platform may integrate an application container cluster system or orchestration system (e.g., Kubernetes) across multiple GPUs to achieve seamless scaling and load balancing.

[0372] Figure 32 is a system diagram of an example system 3200 for generating and deploying an imaging deployment pipeline according to at least one embodiment. In at least one embodiment, the system 3200 can be used to implement Figure 31In at least one embodiment, the system 3200 may include a training system 3104 and a deployment system 3106. In at least one embodiment, the training system 3104 and the deployment system 3106 may be implemented using software 3118, services 3120, and / or hardware 3122, as described herein.

[0373] In at least one embodiment, system 3200 (e.g., training system 3104 and / or deployment system 3106) can be implemented in a cloud computing environment (e.g., using cloud 3226). In at least one embodiment, system 3200 can be implemented locally relative to a healthcare provider facility, or as a combination of cloud computing resources and local computing resources. In at least one embodiment, in cloud computing implementations, patient data can be separated from or processed by one or more components of system 3200 that would render the processing non-compliant with HIPAA and / or other data handling and privacy regulations or laws. In at least one embodiment, access to APIs in cloud 3226 can be restricted to authorized users through established security measures or protocols. In at least one embodiment, the security protocols can include a web token that can be signed by an authentication service (e.g., AuthN, AuthZ, Gluecon, etc.) and can carry appropriate authorization. In at least one embodiment, the API of the virtual tool (described herein) or other instantiations of system 3200 can be restricted to a set of public IP addresses that have been vetted or authorized for interaction.

[0374] In at least one embodiment, the various components of the system 3200 can communicate with each other and with each other using any of a variety of different network types, including but not limited to a local area network (LAN) and / or a wide area network (WAN), via wired and / or wireless communication protocols. In at least one embodiment, communications between facilities and components of the system 3200 (e.g., for transmitting inference requests, for receiving results of inference requests, etc.) can be transmitted via a data bus, a wireless data protocol (Wi-Fi), a wired data protocol (e.g., Ethernet), etc.

[0375] In at least one embodiment, the training system 3104 can execute the training pipeline 3204 similar to that described herein with respect to Figure 31In at least one embodiment, where one or more machine learning models are to be used by a deployment system 3106 in a deployment pipeline 3210, a training pipeline 3204 may be used to train or retrain one or more (e.g., pre-traine...

Claims

1. A processor, comprising: One or more circuits for determining, using one or more neural networks, a reconstruction probability of a second view of one or more objects in one or more images based at least in part on a first view of the one or more objects, and generating a second view based on at least one image of the first view, the reconstruction probability of the second view, and a latent space. 2 . The processor of claim 1 , wherein the one or more circuits are further configured to perform instance segmentation to identify features of two or more objects in the one or more images.

3. The processor of claim 2, wherein the one or more neural networks comprises at least one variational autoencoder for encoding the features of the two or more objects into the latent space.

4. The processor of claim 3 , wherein the one or more neural networks comprises a generative network for generating the second view, the generative network accepting as input at least the latent space and a reconstruction probability of the second view.

5. The processor of claim 1 , wherein the one or more images correspond to one or more frames of video content, and wherein the one or more circuits are further configured to generate the second perspective using at least two passes, the one or more circuits being further configured to store information of two or more objects identified during a first pass to a cache for use in extrapolating image content of the two or more objects in the second perspective to be generated in a second pass.

6. A system comprising: One or more processors for determining, using one or more neural networks, a reconstruction probability of a second view of one or more objects in the one or more images based at least in part on the first view of the one or more objects, and generating the second view based on at least one image of the first view, the reconstruction probability of the second view, and a latent space. 7 . The system of claim 6 , wherein the one or more processors are further configured to perform instance segmentation to identify features of two or more objects in the one or more images.

8. The system of claim 7, wherein the one or more neural networks comprises at least one variational autoencoder for encoding the features of the two or more objects into the latent space.

9. The system of claim 8, wherein the one or more neural networks comprises a generative network for generating the second view, the generative network accepting as input at least the latent space and a reconstruction probability of the second view.

10. The system of claim 6, wherein the one or more images correspond to one or more frames of video content, and wherein the one or more processors are further configured to generate the second perspective using at least two passes, the one or more processors being further configured to store information of two or more objects identified during a first pass to a cache for use in extrapolating image content of the two or more objects in the second perspective to be generated in a second pass.

11. A method comprising: Determining, using one or more neural networks, a reconstruction probability of a second view of one or more objects in the one or more images based at least in part on the first view of the one or more objects, and generating the second view based on at least one image of the first view, the reconstruction probability of the second view, and a latent space.

12. The method according to claim 11, further comprising: Instance segmentation is performed to identify features of two or more objects in the one or more images.

13. The method of claim 12, wherein the one or more neural networks comprises at least one variational autoencoder for encoding the features of the two or more objects into the latent space.

14. The method of claim 13, wherein the one or more neural networks comprises a generative network for generating the second view, the generative network accepting as input at least the latent space and a reconstruction probability of the second view.

15. The method of claim 11 , wherein the one or more images correspond to one or more frames of video content, and the method further comprises: The second perspective is generated using at least two passes, and information of the two or more objects identified during the first pass is stored in a cache for use in extrapolating image content of the two or more objects in the second perspective to be generated in a second pass.

16. A machine-readable medium having stored thereon a set of instructions that, if executed by one or more processors, cause the one or more processors to at least: Determining, using one or more neural networks, a reconstruction probability of a second view of one or more objects in the one or more images based at least in part on the first view of the one or more objects, and generating the second view based on at least one image of the first view, the reconstruction probability of the second view, and a latent space.

17. The machine-readable medium of claim 16, wherein the instructions, if executed, further cause the one or more processors to: Instance segmentation is performed to identify features of two or more objects in the one or more images.

18. The machine-readable medium of claim 17, wherein the one or more neural networks comprises at least one variational autoencoder for encoding the features of the two or more objects into the latent space.

19. The machine-readable medium of claim 18, wherein the one or more neural networks comprises a generative network for generating the second view, the generative network accepting as input at least the latent space and a reconstruction probability of the second view.

20. The machine-readable medium of claim 16, wherein the one or more images correspond to one or more frames of video content, and wherein the instructions, if executed, further cause the one or more processors to: The second perspective is generated using at least two passes, and information of the two or more objects identified during the first pass is stored in a cache for use in extrapolating image content of the two or more objects in the second perspective to be generated in a second pass.

21. An image enhancement system comprising: one or more processors to determine, using one or more neural networks, a reconstruction probability of a second view of one or more objects in the one or more images based at least in part on the first view of the one or more objects, and generate a second view based on the at least one image of the first view, the reconstruction probability of the second view, and a latent space; as well as A memory is used to store network parameters of the one or more neural networks.

22. The image enhancement system of claim 21, wherein the one or more processors are further configured to perform instance segmentation to identify features of the one or more objects in the one or more images.

23. The image enhancement system of claim 22, wherein the one or more neural networks comprises at least one variational autoencoder for encoding the features of the one or more objects into the latent space.

24. The image enhancement system of claim 23, wherein the one or more neural networks comprises a generative network for generating the second view, the generative network accepting as input at least the latent space and a reconstruction probability of the second view.

25. The image enhancement system of claim 21 , wherein the one or more images correspond to one or more frames of video content, and wherein the one or more processors are further configured to generate the second perspective using at least two passes, the one or more processors being further configured to store information of the two or more objects identified during the first pass to a cache for use in extrapolating image content of the two or more objects in the second perspective to be generated in the second pass.

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