Display device and driving method of display device

Abstract

A display device and a driving method of the display device are provided. The display device includes a display unit including a pixel, an emission driver applying an emission control signal for allowing the pixel to emit light, and a signal controller receiving a data enable signal including an active period in which an image signal is input and a blank period, and outputting a control signal for controlling the emission driver so that an emission period of the pixel is changed in response to the blank period.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0109639 filed on August 28, 2020, and all benefits accruing therefrom, the contents of which are incorporated herein in their entirety by reference. TECHNICAL FIELD

[0002] Embodiments of the present application relate to a display apparatus and a driving method of a display apparatus. BACKGROUND

[0003] Generally, a display apparatus displays (or refreshes) an image at a constant frame frequency of 60 hertz (Hz) or more. However, a frame frequency rendered by a main processor (e.g., a graphics processing unit ("GPU") or a graphics card) that provides frame data to the display apparatus can not match a refresh frame frequency of the display apparatus. Due to the mismatch between the frame frequency of the main processor and the refresh frame frequency of the display apparatus, a tearing phenomenon in which a boundary line is generated in an image displayed on the display apparatus can occur.

[0004] A variable frame mode (e.g., an adaptive sync mode, a free sync mode, or a G sync mode) that provides frame data to a display apparatus at a variable frame frequency has been developed by changing a blank period per frame to prevent such a tearing phenomenon. A display apparatus supporting the variable frame mode can prevent the tearing phenomenon by displaying an image in synchronization with the variable frame frequency. SUMMARY

[0005] In a display apparatus operating in a variable frame mode, when an image is displayed at a high frame frequency and then an image is displayed at a low frequency, there is a problem in which a user can recognize a luminance difference.

[0006] Embodiments have endeavored to reduce a luminance deviation between frames displayed by a display apparatus when a frame frequency is changed.

[0007] Embodiments have endeavored to improve display quality of a display apparatus.

[0008] Embodiments of the present application provide a display apparatus including a display unit including a pixel, an emission driver that applies an emission control signal to cause the pixel to emit light, and a signal controller that determines a length of a blank period of a data enable signal other than an active period in which an image signal is input by receiving the data enable signal from an external graphic source, and generates a control signal for controlling the emission driver to cause the pixel to emit light during an emission period corresponding to the length of the blank period.

[0009] In embodiments, the signal controller can include a counter for determining the length of the blank period of the data enable signal.

[0010] In an embodiment, the counter can determine the length of the blank period using a main clock signal input from the external graphic source.

[0011] In an embodiment, the signal controller can further include a transmission period adjuster for generating a control signal for controlling a pulse width of the transmission control signal according to a change in the length of the blank period.

[0012] In an embodiment, the counter can output information about the length of the blank period to the transmission period adjuster.

[0013] In an embodiment, the transmission period adjuster can generate the control signal so that the pulse width of the transmission control signal changes according to the length of the blank period.

[0014] In an embodiment, the display apparatus can further include a memory including information about a transmission period corresponding to the length of the blank period.

[0015] In an embodiment, the transmission period adjuster can read information about a transmission period corresponding to the length of the blank period from the memory, and generate the control signal so that the pulse width of the transmission control signal changes based on the information about the transmission period.

[0016] In an embodiment, when the counter determines that the blank period of the current frame is longer than the blank period of the previous frame, a pixel that emits light by the transmission control signal having a changed pulse width in the next frame can have a non-emission period longer than the non-emission period in the current frame.

[0017] In an embodiment, the start of the transmission period of the next frame can be delayed or the end of the transmission period can be advanced.

[0018] An embodiment of the present application provides a driving method of a display apparatus, and the driving method includes receiving a data enable signal from an external graphic source, determining a length of a blank period of the data enable signal other than an active period in which an image signal is input from the external graphic source using the data enable signal, and generating a control signal for controlling a transmission driver for applying a transmission control signal so that a pixel included in a display unit emits light during a transmission period corresponding to the length of the blank period.

[0019] In an embodiment, determining the length of the blank period can include determining the length of the blank period using a main clock signal input from the external graphic source.

[0020] In an embodiment, generating the control signal can include generating the control signal so that a pulse width of the transmission control signal changes according to a change in the length of the blank period.

[0021] In an embodiment, the generating of the control signal can include reading information about the emission period from a memory in which information about a length of the blank period corresponding to the emission period is stored, and generating the control signal so that a pulse width of the emission control signal is changed based on the information about the emission period.

[0022] In an embodiment, the generating of the control signal can include, when it is determined that the blank period of the current frame is longer than the blank period of the previous frame, generating the control signal so that a pixel that emits light in the next frame by the emission control signal having the changed pulse width has a non-emission period longer than a non-emission period in the current frame.

[0023] In an embodiment, a start of the emission period of the next frame can be delayed or an end of the emission period can be advanced.

[0024] An embodiment of the present application provides a system including an application processor and a display apparatus, the application processor outputting a data enable signal having different blank periods according to a variable frame mode, the display apparatus including a display unit including a pixel and a signal controller for controlling the display unit so that a period in which the pixel emits light is different according to the blank periods.

[0025] In an embodiment, the signal controller can include a counter determining a length of the blank period, an emission period adjuster changing a pulse width of an emission control signal for controlling the display unit so that the period in which the pixel emits light is different according to a change in the length of the blank period, and a memory including information about the emission period according to the length of the blank period.

[0026] In an embodiment, when the counter determines that the blank period of the current frame is longer than the blank period of the previous frame, a pixel that emits light in the next frame by the emission control signal having the changed pulse width can have a non-emission period longer than a non-emission period in the current frame.

[0027] In an embodiment, a start of the emission period of the next frame can be delayed or an end of the emission period can be advanced.

[0028] According to an embodiment, there is an effect of reducing a flicker phenomenon of an image displayed by a display apparatus even when a frame frequency is changed.

[0029] According to an embodiment, there is an advantage in that display quality of a display apparatus can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0030] The above and other exemplary embodiments, advantages, and features of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

[0031] Figure 1 A block diagram showing a schematic configuration of a display device is shown.

[0032] Figure 2 A circuit diagram showing an embodiment of a pixel in the display device of Figure 1

[0033] Figures 3 to 5 A timing chart schematically showing drive timing of a scan signal and a emission control signal is shown.

[0034] Figure 6 A block diagram schematically showing an embodiment of some constituent elements of a signal controller is shown.

[0035] Figure 7 A timing chart schematically showing an embodiment of a change in a data enable signal according to a frequency during adaptive synchronous driving is shown.

[0036] Figures 8A to 8C A timing chart showing an embodiment of an emission control signal applied to an i-th emission control line according to a change in a data enable signal is shown.

[0037] Figure 9 A flowchart schematically showing an embodiment of a method of adjusting an emission period of a display device is shown. DETAILED DESCRIPTION

[0038] Embodiments of the present application will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown. As this described embodiments can be modified in various different ways, all not departing from the spirit or scope of the present application, the described embodiments are not to be construed as limiting the present application in all aspects.

[0039] For the sake of clarity, portions of the description that are not necessary to an understanding of the present application have been omitted and like or similar components are designated with like reference numerals throughout the description.

[0040] Further, since the dimensions and thicknesses of the constituent members shown in the drawings are arbitrarily given for the sake of better understanding and ease of description, the present application is not limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, and the like are exaggerated for the sake of clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for the sake of better understanding and ease of description.

[0041] ​It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. Also, in the description herein, the phrase "on" or "above" means positioned on or below the object, and does not necessarily mean positioned on the upper side of the object based on the direction of gravity.

[0042] Furthermore, the term "comprise" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0043] Furthermore, in the specification, the phrase "in plan view" means when the object is viewed from above, and the phrase "in cross-sectional view" means when a cross-section taken by vertically cutting the object is viewed from the side.

[0044] "About" or "approximately," as used herein, includes the recited value and means within the acceptable range of deviations for a particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the recited value.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0046] Figure 1 A block diagram showing an embodiment showing a schematic configuration of a display device 10 is shown. The display device 10 includes a display unit 100, a scan driver 110, a data driver 120, an emission driver 130, a power supply 140, and a signal controller 150. In an embodiment, the display device 10 can be connected to an application processor 160 or can include the application processor 160. Figure 1 The constituent elements shown in FIG. 1 are not essential to implement the display device, and thus the display device described in the present application can include more or less constituent elements than those listed above.

[0047] The display unit 100 includes a plurality of pixels connected with a corresponding one of a plurality of scan lines SL1 to SLn, a corresponding one of a plurality of data lines DL1 to DLm, and a corresponding one of a plurality of emission control lines EM1 to EMn. Here, m and n are natural numbers. Each of the pixels emits light according to a data signal transmitted to the corresponding pixel, whereby the display unit 100 can display an image.

[0048] The scan lines SL1 to SLn extend substantially in a row direction to be substantially parallel to each other. The emission control lines EM1 to EMn also extend substantially in the row direction to be substantially parallel to each other. The data lines DL1 to DLm extend substantially in a column direction to be substantially parallel to each other.

[0049] Each of the plurality of pixels receives a power supply voltage ELVDD and ELVSS and an initialization voltage Vint from the power supply 140.

[0050] Herein, the scan lines SLi-1 and SLi, the emission control line EMi, and the supply line of the initialization voltage Vint can be wirings located in the same layer, and the data line DLj and the supply lines of the power supply voltages ELVDD and ELVSS can be wirings located in the same layer. The scan lines SLi-1 and SLi, the emission control line EMi, the supply line of the initialization voltage Vint, the data line DLj, and the supply lines of the power supply voltages ELVDD and ELVSS can include the same material or different materials, and can be arranged in the same layer or different layers on the substrate.

[0051] The scan driver 110 is connected to the display unit 100 through the scan lines SL1 to SLn. The scan driver 110 generates a plurality of scan signals according to a control signal CONT2 to sequentially transmit the scan signals to corresponding ones of the scan lines SL1 to SLn, respectively. The control signal CONT2 is an operation control signal of the scan driver 110 generated and transmitted by the signal controller 150. The scan driver 110 sequentially drives the plurality of scan lines SL1 to SLn by sequentially supplying the scan signals of the on voltage or the off voltage under the control of the signal controller 150. According to the driving method, the scan driver 110 can be arranged at only one side of the display unit 100 or at opposite sides of the display unit 100.

[0052] The data driver 120 is connected to each pixel of the display unit 100 through the data lines DL1 to DLm. The data driver 120 receives an image data signal DATA and transmits a data signal corresponding to a corresponding one of the data lines DL1 to DLm according to a control signal CONT1. The control signal CONT1 is an operation control signal of the data driver 120 generated and transmitted by the signal controller 150.

[0053] The data driver 120 selects a gray voltage according to the image data signal DATA and transmits the selected gray voltage as a data signal to the data lines DL1 to DLm. In an embodiment, for example, the data driver 120 samples and holds the input image data signal DATA according to the control signal CONT1 and transmits a plurality of data signals to the data lines DL1 to DLm. The data driver 120 can apply a data signal having a predetermined voltage range to the data lines DL1 to DLm while the scan signal of an enable level is applied.

[0054] The emission driver 130 generates a plurality of emission control signals according to the control signal CONT3. The control signal CONT3 can include an emission start signal, a plurality of emission clock signals switched to an enable level at different times, a hold control signal, etc. The emission start signal is a signal for generating a first emission control signal for displaying an image of one frame. The emission clock signal included in the control signal CONT3 is a synchronization signal for applying an emission control signal to the emission control lines EM1 to EMn. The hold control signal is a signal that controls the emission driver 130 to continuously output an emission signal during low-frequency driving. The generation of the control signal CONT3 by the signal controller 150 will be described in detail below. Figure 6

[0055] The signal controller 150 receives an image signal IS input from an application processor (also referred to as an external graphics source) 160 (e.g., a graphics processing unit ("GPU") or a graphics card) and an input control signal for controlling the display of the image signal IS. The image signal IS can include luminance information divided by the gray scale of each pixel of the display unit 100.

[0056] The input control signal transmitted to the signal controller 150 includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal MCLK, and a data enable signal DE.

[0057] The signal controller 150 generates the control signals CONT1, CONT2, CONT3, and CONT4 and the image data signal DATA according to the image signal IS, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, the main clock signal MCLK, the data enable signal DE, etc. The signal controller 150 appropriately processes the image signal IS according to the operating conditions of the display unit 100 and the data driver 120 based on the input image signal IS and the input control signal. Specifically, the signal controller 150 can generate the image data signal DATA by performing an image processing process such as gamma correction and luminance compensation on the image signal IS.

[0058] ​In an embodiment, for example, the signal controller 150 generates a control signal CONT1 for controlling the operation of the data driver 120, and transmits the control signal CONT1 to the data driver 120 together with the image data signal DATA that has undergone the image processing process. In addition, the signal controller 150 transmits a control signal CONT2 for controlling the operation of the scan driver 110 to the scan driver 110. The signal controller 150 can also drive the emission driver 130 by transmitting a control signal CONT3 to the emission driver 130.

[0059] In addition, the signal controller 150 can control the driving of the power supply 140. The power supply 140 can supply a power supply voltage ELVDD and ELVSS for driving each of the pixels, and an initialization voltage Vint. In an embodiment, for example, the signal controller 150 can drive the power supply 140 by transmitting a control signal CONT4 to the power supply 140. The power supply 140 can be connected to a voltage supply line formed in the display unit 100.

[0060] Since the application processor 160 supplies an image signal (also referred to as input image data) IS to the display device 10 at a variable frame frequency by changing the blank period of each frame period, and the signal controller 150 supplies the image data signal DATA to the data driver 120 in synchronization with the variable frame frequency, the signal controller 150 can support a variable frame mode in which an image is displayed (or refreshed) at a variable frame frequency. The variable frame mode can also be referred to as an adaptive sync mode, a free sync mode, a G-sync mode, etc.

[0061] The period or frequency of rendering of the application processor 160 (e.g., a GPU or a graphics card) can be non-constant (especially when rendering game image data), and in the variable frame mode, the application processor 160 can supply input image data IS (i.e., frame data) to the display device 10 in synchronization with the non-constant period or frequency of such rendering. Each frame period includes an active period in which a data enable signal DE is triggered, and a blank period in which the data enable signal DE is not triggered, and the application processor 160 can change the length of the blank period to thereby supply frame data to the display device 10 at a variable frame frequency.

[0062] Next, a description will be made with reference to Figure 2 A pixel included in the display device 10 is described.

[0063] Figure 2 A circuit diagram showing an embodiment of a pixel PX(i, j) in the display device 10 of Figure 1

[0064] ​The pixel PX(i, j) includes a plurality of transistors T1, T2, T3, T4, T5, and T6, a capacitor Cst, and an organic light emitting diode OLED which are selectively connected to each of a scan line SLi to which a scan signal SL[i] is supplied, a scan line SLi-1 to which a scan signal SL[i-1] is supplied, an emission control line EMi to which an emission control signal EM[i] is supplied, a supply line of an initialization voltage Vint, a data line DLj to which a data signal Data is supplied, and a supply line of a power supply voltage ELVDD and ELVSS. Here, i and j can be natural numbers.

[0065] The gate of the first transistor T1 is connected to the drain of the third transistor T3, the drain of the fourth transistor T4, and the first electrode of the capacitor Cst at the first node N1, the source of the first transistor T1 is connected to the drain of the second transistor T2 and the drain of the fifth transistor T5, and the drain of the first transistor T1 is connected to the source of the third transistor T3 and the source of the sixth transistor T6.

[0066] The gate of the second transistor T2 is connected to the scan line SLi, the source of the second transistor T2 is connected to the data line DLj, and the drain of the second transistor T2 is connected to the source of the first transistor T1 at the second node N2.

[0067] The gate of the third transistor T3 is connected to the scan line SLi, the source of the third transistor T3 is connected to the drain of the first transistor T1 at the third node N3, and the drain of the third transistor T3 is connected to the gate of the first transistor T1 at the first node N1.

[0068] The gate of the fourth transistor T4 is connected to the scan line SLi-1, the source of the fourth transistor T4 is connected to the supply line of the initialization voltage Vint, and the drain of the fourth transistor T4 is connected to the gate of the first transistor T1 at the first node N1.

[0069] The gate of the fifth transistor T5 is connected to the emission control line EMi, the source of the fifth transistor T5 is connected to the supply line of the power supply voltage ELVDD, and the drain of the fifth transistor T5 is connected to the source of the first transistor T1 at the second node N2.

[0070] The gate of the sixth transistor T6 is connected to the emission control line EMi, the source of the sixth transistor T6 is connected to the drain of the first transistor T1 at the third node N3, and the drain of the sixth transistor T6 is connected to the first electrode of the organic light emitting diode OLED. The first transistor T1 is connected to the organic light emitting diode OLED through the sixth transistor T6.

[0071] The capacitor Cst has a first electrode connected to the gate of the first transistor T1 and the drain of the third transistor T3 at the first node N1, and a second electrode connected to the supply line of the power supply voltage ELVDD.

[0072] The organic light emitting diode OLED has a first electrode, a second electrode arranged on the first electrode, and an organic emission layer arranged between the first electrode and the second electrode. The first electrode of the organic light emitting diode OLED is connected to the drain of the sixth transistor T6, and its second electrode is connected to the supply line of the power supply voltage ELVSS.

[0073] In the above, it has been described that the pixel PX(i,j) includes six transistors T1, T2, T3, T4, T5, and T6 and one capacitor Cst. However, the present application is not limited thereto, and the pixel PX(i,j) can further include a transistor connected between the first electrode of the organic light emitting diode OLED and the supply line of the initialization voltage Vint and including a gate connected to the scan line SLi-1.

[0074] Reference will be made to Figures 3 to 5 An operation of a display device including the pixel having the above-described structure will be described.

[0075] Figures 3 to 5 A timing chart schematically showing drive timings of the scan signals and the emission control signal is shown.

[0076] The current scan line to be driven is the i-th scan line SLi, the scan signal applied to the i-th scan line SLi is SL[i], the scan line driven before the current scan line is the (i-1)-th scan line SLi-1, and the scan signal applied to the (i-1)-th scan line SLi-1 is SL[i-1].

[0077] Figure 3 A timing chart schematically showing drive timings of the scan signals SL[i-1] and SL[i] and the emission control signal EM[i] when the frame frequency is f1 is shown. Here, F1 which is a time span from t01 to t05 is one frame period, and P1 which is a time span from t03 to t04 is an emission period within one frame period.

[0078] As Figure 3As shown in the middle, in the time span from t01 to t02, the previous scan signal SL[i-1] has the enable level E, and the current scan signal SL[i] and the emission control signal EM[i] have the disable level D. The fourth transistor T4 is turned on by the previous scan signal SL[i-1] of the enable level E, and the first transistor T1, the second transistor T2, and the third transistor T3, and the fifth transistor T5 and the sixth transistor T6 are turned off by the current scan signal SL[i] and the emission control signal EM[i] of the disable level D. Accordingly, the voltage stored in the capacitor Cst (i.e., the gate voltage of the first transistor T1) is initialized.

[0079] Thereafter, in the time span from t02 to t03, the previous scan signal SL[i-1] and the emission control signal EM[i] have the disable level D, and the current scan signal SL[i] has the enable level E. The fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off by the previous scan signal SL[i-1] and the emission control signal EM[i] of the disable level D, and the second transistor T2 and the third transistor T3 are turned on by the current scan signal SL[i] of the enable level E, so that the first transistor T1 is connected as a diode. The nodes N1 and N3 are connected through the third transistor T3, and the data voltage VDATA applied to the corresponding jth data line DLj is input into the source of the first transistor T1. Since the first transistor T1 is connected as a diode, the gate voltage of the first transistor T1 is VDATA-VTH(T1), and the gate voltage is stored in the capacitor Cst. Herein, VTH(T1) is the threshold voltage of the first transistor T1.

[0080] Then, in the time span from t03 to t04, the previous scan signal SL[i-1] and the current scan signal SL[i] have the disable level D, and the time span from t03 to t04 is an emission period P1 in which the emission control signal EM[i] has the enable level E. The second transistor T2, the third transistor 3, and the fourth transistor T4 are turned off by the previous scan signal SL[i-1] and the current scan signal SL[i] of the disable level D, and the fifth transistor T5 and the sixth transistor T6 are turned on by the emission control signal EM[i] of the enable level E. A driving current is generated according to the voltage difference between the gate voltage of the first transistor T1 and the power voltage ELVDD, and is supplied to the organic light emitting diode OLED through the sixth transistor T6 to allow the organic light emitting diode OLED to emit light. During the emission period P1, the gate-source voltage Vgs of the first transistor T1 is held at VDATA+VTH(T1)-ELVDD through the capacitor Cst, and the driving current is (VDATA-ELVDD) 2is proportional. Accordingly, the drive current is determined independently of the threshold voltage VTH(T1) of the first transistor T1.

[0081] Finally, the time span from t04 to t05 is a period from the end of the emission period P1 until the start of the next frame, and the previous scan signal SL[i-1], the current scan signal SL[i], and the emission control signal EM[i] all have the disable level D. Accordingly, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all turned off. Here, it has been described that t04 is different from t05, but t04 can be the same as t05, and in this case, the scan signal for the next frame can start as soon as the emission period P1 ends.

[0082] A new frame starts from t05, and the above-described sequence from t01 to t05 can be repeated.

[0083] Figure 4 A timing chart schematically showing the drive timing of the scan signals SL[i-1] and SL[i] and the emission control signal EM[i] when the frame frequency is f2 is shown. Here, F2, which is the time span from t11 to t15, is one frame period, and P2, which is the time span from t13 to t14, is an emission period within one frame period.

[0084] The operation of the time span from t11 to t12 can be similar to the operation of the time span from t01 to t02 described above. The operation of the time span from t12 to t13 can be similar to the operation of the time span from t02 to t03 described above. The operation of the time span from t13 to t14 can be similar to the operation of the time span from t03 to t04 described above. The operation of the time span from t14 to t15 can be similar to the operation of the time span from t04 to t05 described above.

[0085] Figure 5 A timing chart schematically showing the drive timing of the scan signals SL[i-1] and SL[i] and the emission control signal EM[i] when the frame frequency is f3 is shown. Here, F3, which is the time span from t21 to t25, is one frame period, and P3, which is the time span from t23 to t24, is an emission period within one frame period.

[0086] The operation of the time span from t21 to t22 can be similar to the operation of the time span from t01 to t02 described above. The operation of the time span from t22 to t23 can be similar to the operation of the time span from t02 to t03 described above. The operation of the time span from t23 to t24 can be similar to the operation of the time span from t03 to t04 described above. The operation of the time span from t24 to t25 can be similar to the operation of the time span from t04 to t05 described above.

[0087] A comparison and description will be made of the timing chart shown in FIG. 10. Figures 3 to 5 The frame frequencies can satisfy f1 < f2 < f3. In this case, the time spans of one frame period can satisfy F1 > F2 > F3, and the emission periods can satisfy P1 > P2 > P3. As the frame frequencies become higher, more time is required to write data during the same time span. Accordingly, as the frame frequencies become higher, the emission periods become shorter and the brightness becomes lower. For this reason, when the frame frequencies of consecutive frames are rapidly changed, for example, when an image is displayed at a high frame frequency by adaptive synchronization and then an image is displayed at a lower frequency, there is a problem in which the brightness difference can be recognized by a user.

[0088] Figure 6 A block diagram showing an embodiment schematically showing some constituent elements of a signal controller is shown.

[0089] The signal controller 150 can include a counter 310, an emission period adjuster (also referred to as an emission span adjuster) 330, and a memory 350.

[0090] The counter 310 can receive a data enable signal DE and a main clock signal MCLK from the application processor 160 (refer to FIG. 1). Figure 1 ) The counter 310 can receive a data enable signal DE whose input frequency changes every frame period from the application processor 160.

[0091] When the data enable signal DE is received from the application processor 160, the counter 310 can determine the length of a blank period after the data enable signal DE reaches a disable level D and until the data enable signal DE is triggered. In addition, the counter 310 can detect the frame frequency from the time span between the active periods of the data enable signal DE. In this case, the counter 310 can determine the length of the blank period by counting a clock signal during the blank period of the data enable signal DE, but the present application is not limited thereto. The clock signal can be a main clock signal MCLK supplied from the application processor 160, can be an internal clock signal generated based on the main clock signal MCLK, or can be a clock signal generated by an oscillator included in the signal controller 150, but the present application is not limited thereto.

[0092] After determining the length of the blank period of the data enable signal DE, the counter 310 outputs a first signal S1 to the emission period adjuster 330. The first signal S1 can include information about the frame frequency and information about the length of the blank period of the data enable signal DE.

[0093] The emission period adjuster 330 can receive the first signal S1 from the counter 310, and can determine the non-emission period of the next frame according to the received first signal S1. The emission period adjuster 330 can determine the emission period of the pixel based on the second signal S2 received from the memory 350.

[0094] The emission period adjuster 330 can output a control signal CONT3 to the emission driver 130 (refer to Figure 1 ) so that the emission control signal has a disable level D during the determined non-emission period. In this case, the emission period adjuster 330 can output the control signal CONT3 that makes the non-emission period of the pixel in the next frame identical to the non-emission period of the previous frame. The non-emission period in which the emission control signal output from the emission driver 130 has the disable level D can be adjusted by the control signal CONT3.

[0095] That is, the emission period adjuster 330 can change the emission period of the pixel according to the change in the blank period of the data enable signal DE, and can allow the non-emission period of the pixel to be constant in each frame. Accordingly, the emission period adjuster 330 can adjust the brightness of the image by controlling the pulse width of the emission control signal in response to the brightness that fluctuates according to the change in the blank period, thereby preventing the user of the display apparatus 10 from visually recognizing flicker between frames.

[0096] The time in which the blank period of the frame period needs to be counted until the end of the blank period of the changed frame period after the frame frequency of the data enable signal DE is changed in order for the counter 310 to check the blank period of the data enable signal DE. Accordingly, the emission period adjuster 330 can adjust the emission period of the pixel after the frame frequency is changed with a delay of at least one frame, instead of adjusting the emission period of the pixel from the changed first frame after the frame frequency is changed.

[0097] The memory 350 can store information about the appropriate emission period according to the change of the frame frequency of the data enable signal DE. The memory 350 can store information about the appropriate emission period corresponding to the blank period of the data enable signal DE counted by the counter 310. The memory 350 can also store information about the emission period according to the value of the frame frequency changed between two frames. In an embodiment, for example, the memory 350 separately and stores information about the emission period in the case of changing from about 240 hertz (Hz) to about 60 Hz, and information about the emission period in the case of changing from about 120 Hz to about 60 Hz. The information can be stored in the memory 350 in the form of a plurality of look-up tables ("LUTs"). The length of the blank period can be divided into a plurality of periods, and information about the emission period corresponding to each of the periods can be stored in the LUTs. In an embodiment, for example, assuming that the blank count corresponds to the frame frequency, information about the emission period when the frame frequency is changed to f2 can be stored in the LUT corresponding to the period when the frame frequency is f2. In an embodiment, for example, information about the emission period according to the case where the frame frequency is changed from f3 to f2, the case where the frame frequency is changed from f1 to f2, etc. can be stored in the LUT corresponding to the period when the frame frequency is f2.

[0098] The memory 350 can output the second signal S2 to the emission period adjuster 330, and the second signal S2 can include information about the emission period according to the change of the length of the blank period, and information about the emission period according to the change of the frame frequency.

[0099] Figure 7 A timing chart schematically showing the change of the data enable signal according to the frequency during adaptive sync driving is shown.

[0100] When the image data is input at a constant frame frequency, each frame period includes an active period having a constant time length and a blank period. When the image data is input at a variable frame frequency, each frame period includes an active period having a constant time length regardless of the frame frequency and a blank period having a time length corresponding to the variable frame frequency.

[0101] As Figure 7As shown in FIG. 6, in the time span F1, the active period APa (t31 to t32) and the blank period BPa (t32 to t33) of the data enable signal DE are included in one frame period FPa. In the time span F2, the active period APb (t41 to t42) and the blank period BPb (t42 to t43) of the data enable signal DE are included in one frame period FPb. Further, in the time span F3, the active period APc (t51 to t52) and the blank period BPc (t52 to t53) of the data enable signal DE are included in one frame period FPc. Here, F1 is a time span with a frame frequency of fl, F2 is a time span with a frame frequency of f2, and F3 is a time span with a frame frequency of f3. Here, fl, f2, and f3 can satisfy fl > f2 > f3. That is, as the frame frequency becomes slower, the blank period of the data enable signal DE becomes longer. In an embodiment, for example, when fl is about 240 Hz, f2 is about 120 Hz, and f3 is about 60 Hz, the lengths of the blank periods can satisfy BPa < BPb < BPc.

[0102] Thus, when the data enable signal DE is input at a variable frame frequency, the blank period is variable, and therefore, unlike the case where an image is displayed at a constant frame frequency, the length of the blank period can differ for each frame. The time span in which the pixel emits light can also change according to the length difference of the blank period, and when the time span in which the pixel emits light differs for each frame, the flicker phenomenon can occur, thereby causing degradation of image quality.

[0103] Reference will now be made to Figures 8A to 8C The operation of the signal controller 150 for adjusting the length of the emission period between frames will be described.

[0104] Figures 8A to 8C A timing chart showing the emission control signal applied to the ith emission control line according to the change in the data enable signal DE is shown.

[0105] Figure 8AThe case where the frame frequency is changed from fl to f3 is shown. In the first frame period after the frame frequency is changed from fl to f3, the emission control signal EM[i] is changed to the disable level D at tal, and then the emission control signal EM[i] is changed to the enable level E at ta2. In addition, the emission control signal EM[i] is changed to the disable level D at ta3, and a new frame of the frame frequency f3 starts. Here, the time span for which the emission control signal EM[i] remains at the enable level E is Pa1. Conventionally, the emission control signal EM[i] is changed to the enable level E at ta4, and the emission control signal EM[i] remains at the enable level E until the emission control signal EM[i] is changed to the disable level D at ta7. The time span for which the emission control signal EM[i] remains at the enable level E until the emission control signal EM[i] is changed to the disable level D at ta7 is the same as the time span Pa1. Accordingly, there is a problem that there is a difference in luminance between frames when the frame frequency is changed.

[0106] However, in the embodiment of the present application, the emission control signal EM[i] is changed to the enable level E at ta4, and then changed to the disable level D at ta6. Here, the time span for which the emission control signal EM[i] remains at the enable level E is Pa2, and the length of Pa2 is shorter than the length of Pa1. That is, within the same time span, the difference in luminance between frames can be reduced by controlling the pulse width of the emission control signal EM[i] with the control signal CONT3 to reduce the difference between the length of the non-emission period before the change in the frame frequency and the length of the non-emission period after the change in the frame frequency.

[0107] In the above, it has been described that the emission control signal EM[i] is changed to the enable level E at ta4 and changed to the disable level D at ta6, but the emission control signal EM[i] can be changed to the enable level E at ta5 and changed to the disable level D at ta7. However, as described above, since the time is required to count the blank period of the frame period where the frame frequency is changed, the emission period can not be adjusted from the frame period where the frame frequency is changed from fl to f3, and there can be a delay of at least one frame.

[0108] Figure 8BThe case where the frame frequency is changed from f2 to f3 is shown. In the first frame period after the frame frequency is changed from f2 to f3, the emission control signal EM[i] is changed to the disable level D at tb1, and then the emission control signal EM[i] is changed to the enable level E at tb2. In addition, the emission control signal EM[i] is changed to the disable level D at tb3, and a new frame having the frame frequency of f3 starts. Here, the time span for which the emission control signal EM[i] remains at the enable level E is Pb1. Conventionally, the emission control signal EM[i] is changed to the enable level E at tb4, and the time span for which the emission control signal EM[i] remains at the enable level E until the emission control signal EM[i] is changed to the disable level D at tb7 is the same as the time span of Pb1.

[0109] However, in the embodiment of the present application, the emission control signal EM[i] is changed to the enable level E at tb4, and then changed to the disable level D at tb6. Here, the time span for which the emission control signal EM[i] remains at the enable level E is Pb2, and the length of Pb2 is shorter than the length of Pb1. Accordingly, the length of the non-emission period before the change in frame frequency and the length of the non-emission period after the change in frame frequency remain consistent within the same time span.

[0110] In the above, it has been described that the emission control signal EM[i] is changed to the enable level E at tb4 and changed to the disable level D at tb6, but the emission control signal EM[i] can be changed to the enable level E at tb5 and changed to the disable level D at tb7. However, as described above, since the time is required to count the blank period of the frame period in which the frame frequency is changed, the emission period can not be adjusted from the frame period in which the frame frequency is changed from f2 to f3, and there can be a delay of at least one frame.

[0111] Figure 8C The case where the frame frequency is changed from f1 to f2 is shown. In the first frame period after the frame frequency is changed from f1 to f2, the emission control signal EM[i] is changed to the disable level D at tc1, and then the emission control signal EM[i] is changed to the enable level E at tc2. In addition, the emission control signal EM[i] is changed to the disable level D at tc3, and a new frame having the frame frequency of f2 starts. Here, the time span for which the emission control signal EM[i] remains at the enable level E is Pc1. Conventionally, the emission control signal EM[i] is changed to the enable level E at tc4, and the time span for which the emission control signal EM[i] remains at the enable level E until the emission control signal EM[i] is changed to the disable level D at tc7 is the same as the time span of Pc1.

[0112] However, in an embodiment of the invention, the transmit control signal EM[i] is changed to the enable level E at tc4 and then to the disable level D at tc6. Here, the transmit control signal EM[i] remains at the enable level E for a time span of Pc2, and the length of Pc2 is shorter than the length of Pc1. Accordingly, the length of the non-transmit period before the frame frequency change and the length of the non-transmit period after the frame frequency change remain consistent within the same time span.

[0113] Above, it has been described that the transmit control signal EM[i] changes to the enable level E at tc4 and to the disable level D at tc6. However, the transmit control signal EM[i] can also change to the enable level E at tc5 and to the disable level D at tc7. However, as mentioned above, since it is necessary to count the blank periods of the frame period when the frame frequency changes, the transmit period may not be adjusted from the frame period when the frame frequency changes from f1 to f2, and there may be a delay of at least one frame.

[0114] like Figures 8A to 8C As shown, when the first, second, and third frames are consecutive frames and the frame frequencies of the second and third frames are lower than the frame frequency of the first frame—that is, when the blank period of the data enable signal DE during image signal input in the second and third frames is longer than the blank period of the data enable signal DE during image signal input in the first frame—the non-emission period of the third frame can be increased. Because the brightness difference between frames is reduced by decreasing the emission period, there is an effect of reducing flicker.

[0115] Figure 9 A flowchart illustrating an embodiment of a method for adjusting the emission period of a display device is shown.

[0116] Counter 310 receives a data enable signal DE (S901) from application processor 160. Counter 310 can also receive a master clock signal MCLK from application processor 160.

[0117] Counter 310 counts the blank periods of the received data enable signal DE (S902). The counting unit 310 can determine the length of the blank period by counting the clock signal. The clock signal can be the master clock signal MCLK supplied from the application processor 160, an internal clock signal generated based on the master clock signal MCLK, or a clock signal generated by an oscillator included in the signal controller 150.

[0118] The transmission time adjustment mechanism 330 determines the transmission time based on the counted blank time periods (S903). When the blank time period of the current frame is longer than the blank time period of the previous frame, the transmission time adjustment mechanism 330 can further reduce the transmission time period of the next frame compared with the transmission time period of the current frame.

[0119] The emission period adjuster 330 outputs a control signal to the emission driver 130 to have the determined emission period (S904). In this case, among the plurality of pixels, the time of emitting light of the previous frame and the time of emitting light of the next frame for the same time can be substantially the same.

[0120] The operations constituting the method according to the present application can be performed in a proper order, except for those explicitly stated or contradicted with the order. The present application is not necessarily limited to the order of the operations described. In the present application, the use of all examples or illustrative terms (e.g., etc.) is only for the detailed description of the present application, and thus the scope of the present application is not limited thereto. In addition, those of ordinary skill in the art can recognize that various modifications, combinations, and changes can be made within the scope of the claims or their equivalents.

[0121] While the present application has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the application is not to be limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device, comprising: The display unit includes pixels; A transmitter driver that applies a transmitter control signal to cause the pixel to emit light; as well as A signal controller determines the length of a blank period (excluding the effective period when the image signal is input) of the data enable signal by receiving a data enable signal from an external graphics source, and generates a control signal for controlling the emission driver so that the pixel emits light during an emission period corresponding to the length of the blank period. The signal controller includes a counter, which is used to determine the length of the blank period of the data enable signal. When the counter determines that the blank period of the current frame is longer than the blank period of the previous frame, the pixel that emits light in the next frame by means of an emission control signal with a changed pulse width has a non-emission period longer than the non-emission period in the current frame.

2. The display device as claimed in claim 1, wherein, The counter uses a master clock signal input from the external graphics source to determine the length of the blank period.

3. The display device as claimed in claim 2, wherein, The signal controller further includes a transmission period regulator for generating the control signal for controlling the pulse width of the transmission control signal according to the change in the length of the blank period.

4. The display device as claimed in claim 3, wherein, The counter outputs information related to the length of the blank period to the transmission period regulator.

5. The display device as claimed in claim 4, wherein, The transmission period regulator generates the control signal such that the pulse width of the transmission control signal changes according to the length of the blank period.

6. The display device as claimed in claim 4, further comprising: The memory includes information relating to the transmission period corresponding to the length of the blank period, wherein, The transmit time adjustment reads the information related to the transmit time corresponding to the length of the blank time from the memory, and generates the control signal such that the pulse width of the transmit control signal is changed based on the information related to the transmit time.

7. The display device as claimed in claim 1, wherein, The start of the transmission period in the next frame is delayed or the end of the transmission period in the next frame is brought forward.

8. A driving method for a display device, the driving method comprising: Receive data enable signals from external graphics sources; The data enable signal is used to determine the length of the blank period of the data enable signal, excluding the valid period of the image signal input from the external graphics source; as well as A control signal is generated to control the emission driver that applies the emission control signal, such that pixels included in the display unit emit light during an emission period corresponding to the length of the blank period. The generation of the control signal includes: when it is determined that the blank period of the current frame is longer than the blank period of the previous frame, generating the control signal such that the pixel that emits light in the next frame by means of an emission control signal with a changed pulse width has a non-emission period longer than the non-emission period in the current frame.

Images