Display Driver

Abstract

The present invention provides a display driver. In the present invention, the designation of the output timing in each of the first and k-th output channels of the display driver is received, a first delayed pulse signal is generated at the output timing of the first output channel, and a second delayed pulse signal is generated at the output timing of the k-th output channel. First to k-th first direction delayed shift signals are generated, in which the first delayed pulse signal appears after the delay added for each output channel from the first to the k-th output channel. First to k-th second direction delayed shift signals are generated, in which the second delayed pulse signal appears after the delay added for each output channel from the k-th output channel to the first output channel. From each of the first to k-th first direction delayed shift signals and each of the first to k-th second direction delayed shift signals, one with an earlier timing for the delayed pulse signal to appear is selected, and the signal selected for each output channel is used as the first to k-th output timing signal.

Description

Technical Field

[0001] The invention relates to a display driver for driving a display panel according to an image signal. Background Art

[0002] In a display panel such as a liquid crystal display panel that displays an image, a plurality of gate lines extending in the horizontal direction of a two-dimensional screen and a plurality of source lines extending in the vertical direction of the two-dimensional screen are arranged in a cross manner. Furthermore, the liquid crystal display panel is equipped with: a source driver that applies a grayscale display voltage corresponding to the brightness level of each pixel represented by an input image signal to each source line; and a gate driver that applies a gate signal for selecting a display line to be driven to the gate line.

[0003] As such a source driver, the following source driver has been proposed: a plurality of display data corresponding to one horizontal synchronization period is individually taken into each of N (N is an integer greater than 2) latches, and a driving voltage having a voltage value corresponding to the display data taken into each latch is applied to each source line (for example, refer to patent document 1).

[0004] In the source driver, N (N is an integer greater than 2) stages of flip-flops (called FFs) are provided to sequentially shift and take in a delayed pulse signal of a single pulse to the next stage in synchronization with a reference timing signal, and the output of each FF is individually supplied to N latches as an input signal. Thus, the timing at which each driving voltage is applied to each source line is staggered, thereby avoiding a state in which a current flowing into the source line group changes sharply at the same time, and suppressing noise generated in this state.

[0005] [Prior art literature]

[0006] [Patent Document]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2015-143780 Summary of the invention

[0008] [Problems to be solved by the invention]

[0009] In recent years, in display panels that are becoming larger and more precise, a plurality of source driver ICs, which are constructed by dividing a source driver into a plurality of integrated circuit (IC) chips, are provided on one end side of a source line group.

[0010] When driving such a display panel, since the gate line and the source line are long, the waveform of the gate signal and the drive voltage is blunted due to the wiring resistance accompanying the line length. In addition, the degree of blunting of the waveform varies depending on the position within the screen of the display panel. For example, at the center of the screen of the display panel, the line length from each driver is longer than that at the two ends of the screen, so the waveform of the gate signal and the drive voltage is blunted, that is, the delay time becomes longer. Therefore, the output timing of the appropriate drive voltage for the gate signal is different at the center of the screen of the display panel and at the end of the screen.

[0011] Therefore, it is considered to apply the technology of Patent Document 1 to delay the timing of applying the driving voltage to each source line stepwise by a predetermined unit delay amount toward the center of the screen of the display panel, thereby performing driving in accordance with the arrival timing of the gate signal.

[0012] However, when a display panel is driven by a plurality of source drivers, if the amount of deviation in output timing of drive voltages between adjacent output channels of adjacent source drivers increases, display unevenness may occur at the boundary between the adjacent output channels.

[0013] Therefore, in order to suppress such display unevenness, it is conceivable to perform adjustment in each source driver so as to reduce the delay time difference in the output timing of the drive voltage between the output channels.

[0014] However, in order to perform such adjustment, it is necessary to increase the frequency of the circuit that reduces the unit delay amount that determines the output timing of the driving voltage, which causes a problem of increasing the circuit scale.

[0015] In addition, by changing the unit delay amount, the output timing of the driving voltage in the last output channel will also change. Therefore, in order to reduce the delay time difference with respect to the output timing of the driving voltage in the last output channel of the source driver, it is also necessary to change the output timing in the first output channel of the source driver adjacent to the source driver, so there is a problem that the adjustment becomes complicated.

[0016] Therefore, an object of the present invention is to provide a display driver that can easily adjust output timing to suppress display unevenness without increasing the circuit scale when a display panel is driven by a plurality of display drivers.

[0017] [Technical means to solve the problem]

[0018] The display driver of the present invention has a first output channel to a k-th output channel that output a first pixel driving voltage to a k-th (k is an integer greater than 2) pixel driving voltage corresponding to the brightness level of each pixel represented by an image signal, respectively. The display driver has: an output timing control unit that generates a first output timing signal to a k-th output timing signal indicating the output timing in each of the first output channel to the k-th output channel; and an output unit that outputs the first pixel driving voltage to the k-th pixel driving voltage at the output timing indicated by each of the first output timing signal to the k-th output timing signal; and the output timing control unit has: a control signal generating unit that receives a designation of the output timing in each of the first output channel and the k-th output channel, generates a first delay pulse signal at the designated output timing of the first output channel, and generates a second delay pulse signal at the designated output timing of the k-th output channel; a first delay generating unit that receives the first delay pulse signal, generates a first delay pulse signal from the first output channel to the k-th output channel, and outputs the first pixel driving voltage to the k-th pixel driving voltage at the output timing indicated by each of the first output timing signal to the k-th output timing signal. a first output channel, each of which increases the delay of the unit delay time to generate a first first direction delayed shift signal to a kth first direction delayed shift signal of the first delayed pulse signal; a second delay generating unit, receiving the second delayed pulse signal, generating a first second direction delayed shift signal to a kth second direction delayed shift signal from the kth output channel to the first output channel, each of which increases the delay of the unit delay time to generate the second delayed pulse signal; and a delay selecting unit, for each of the first output channel to the kth output channel, selecting one of the signals corresponding to the same output channel, i.e., each of the first first direction delayed shift signal to the kth first direction delayed shift signal and each of the first second direction delayed shift signal to the kth second direction delayed shift signal, with an earlier timing of the occurrence of the delayed pulse signal, and outputting the selected signal as the first output timing signal to the kth output timing signal for each of the first output channel to the kth output channel.

[0019] [Effects of the Invention]

[0020] In the present invention, when adjusting the output timing of each of the first output channel to the kth output channel (k is an integer greater than 2) of the display driver, first, the designation of the output timing in the first output channel and the kth output channel is received. Secondly, a first delayed pulse signal is generated at the output timing of the designated first output channel, and a second delayed pulse signal is generated at the output timing of the designated kth output channel. Here, a first first direction delayed shift signal to a kth first direction delayed shift signal are generated, in which a first delayed pulse signal appears after a delay increased for each output channel from the first output channel to the kth output channel. Furthermore, a first second direction delayed shift signal to a kth second direction delayed shift signal are generated, in which a second delayed pulse signal appears after a delay increased for each output channel from the kth output channel to the first output channel. Secondly, from the signals corresponding to the same output channel, that is, each of the first first direction delayed shift signal to the kth first direction delayed shift signal and each of the first second direction delayed shift signal to the kth second direction delayed shift signal, one of the signals with an earlier timing of appearing the delayed pulse signal is selected. Then, each selected signal for the first output channel to the kth output channel is used as the first output timing signal to the kth output timing signal, and the first pixel driving voltage to the kth pixel driving voltage corresponding to each pixel is output according to the output timing of the first output timing signal to the kth output timing signal.

[0021] Therefore, when using multiple display drivers to drive the display panel, by specifying the output timing in each of the first output channel and the second output channel for each display driver, the following adjustment can be made: without shortening the unit delay time, the delay time difference in the output timing of the boundary portions of adjacent display drivers can be reduced.

[0022] Therefore, according to the present invention, when a display panel is driven by a plurality of display drivers, it is possible to easily adjust the output timing to suppress display unevenness without increasing the circuit scale. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 1 is a block diagram showing a schematic configuration of a display device 100 including a display driver according to the present invention.

[0024] Figure 2 4 is a block diagram showing an example of the internal structure of the driver IC 4a.

[0025] Figure 3 The diagram shows examples of three systems of delay characteristics DR based on rightward delay shift signal R1 to rightward delay shift signal Rk and delay characteristics DL1 to DL3 based on leftward delay shift signal L1 to leftward delay shift signal Lk.

[0026] Figure 4A : is a graph showing the output timing delay characteristics in the R shift mode.

[0027] Figure 4B : is a graph showing the output timing delay characteristics in the L shift mode.

[0028] Figure 4C : is a graph showing the output timing delay characteristics in the V shift mode.

[0029] Figure 5 This is a diagram showing an example of a delay form of the output timing adjusted according to the designation of the start timing setting data TA1 and the start timing setting data TA2.

[0030] Figure 6 1 is a diagram showing an example of a delay state of output timing in each of the driver IC 4 a and the driver IC 4 b after adjustment based on the start timing setting data TA1 and the start timing setting data TA2 .

[0031] Figure 7 2 is a circuit diagram showing an example of the internal configuration of the right-direction delay generating section 411 , the left-direction delay generating section 412 , and the delay selecting section 413 .

[0032] Figure 8 2 is a timing chart showing an example of the operations of the right-direction delay generating section 411 , the left-direction delay generating section 412 , and the delay selecting section 413 .

[0033] Fig. 9 2 is a circuit diagram showing another example of the internal structure of the right-direction delay generating section 411 and the left-direction delay generating section 412 .

[0034] Fig.10 : is a circuit diagram showing an example of the internal structure of the delay selection unit 413.

[0035] Fig.11 4 is a circuit diagram showing another example of the internal structure of the delay selection unit 413 .

[0036] Fig.12 1 is a circuit diagram showing a circuit that realizes the functions of the right-direction delay generating section 411 , the left-direction delay generating section 412 , and the delay selecting section 413 with a simplified configuration.

[0037] Explanation of symbols

[0038] 10: Display Panel

[0039] 20: Drive control unit

[0040] 40: Source driver

[0041] 41: Output timing control unit

[0042] 42: Data latch unit

[0043] 410: Control signal generating unit

[0044] 411: Right direction delay generation unit

[0045] 412: Left direction delay generation unit

[0046] 413: Delayed Selection Department DETAILED DESCRIPTION

[0047] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0048] Figure 1 1 is a diagram showing a schematic structure of a display device 100 including a display driver of the present invention. Figure 1 As shown, the display device 100 includes a drive control unit 20, a gate driver 30A and a gate driver 30B, a source driver 40, and a display panel 10. In addition, the source driver 40 includes a plurality of semiconductor IC (Integrated Circuit) chips having the same structure. Figure 1 In the illustrated embodiment, the source driver 40 includes five driver ICs 4a to 4e, each of which has k (k is an integer greater than 2) output channels obtained by dividing n (n is a natural number greater than 2) output channels 5 of the source driver 40.

[0049] The display panel 10 includes, for example, a liquid crystal or an organic electroluminescence (EL) panel. The display panel 10 includes m (m is an integer greater than or equal to 2) horizontal scanning lines S1 to Sm extending in the horizontal direction of the two-dimensional screen, and n data lines D1 to Dn extending in the vertical direction of the two-dimensional screen. Display units carrying pixels are formed at each intersection of the gate line and the source line.

[0050] The drive control unit 20 receives a video signal to be displayed, extracts a horizontal synchronization signal and a vertical synchronization signal from the video signal, and supplies the horizontal synchronization signal to the gate driver 30A and the gate driver 30B.

[0051] Furthermore, the drive control unit 20 generates, for each pixel, a series of pixel data PD representing the brightness level of the pixel using, for example, 8 bits, based on the video signal.

[0052] Furthermore, the drive control unit 20 supplies the following delay shift amount setting data SA1 and SA2, start timing setting data TA1 and TA2, and a series of image data signals DVS and pixel data PD including the synchronization signal CS and the reference clock signal CLK to the source driver 40.

[0053] The synchronization signal CS includes, for example, a horizontal synchronization signal.

[0054] The delay shift amount setting data SA1 is data for designating a unit delay time for increasing the delay to be applied to the output timing in a stepwise manner from the first output channel to the k-th output channel (also referred to as the right direction) for each of the driver ICs 4 a to 4 e.

[0055] The delay shift amount setting data SA2 is data for designating a unit delay time for increasing the delay to be applied to the output timing in a stepwise manner from the k-th output channel toward the first output channel (also referred to as the left direction) for each of the driver ICs 4a to 4e.

[0056] The start timing setting data TA1 is data for designating the output timing in the first output channel for each of the driver ICs 4 a to 4 e.

[0057] The start timing setting data TA2 is data for designating the output timing in the k-th output channel for each of the driver ICs 4 a to 4 e.

[0058] The gate driver 30A is connected to one end of each of the gate lines S1 to Sm, and the gate driver 30B is connected to the other end of each of the gate lines S1 to Sm. The gate driver 30A and the gate driver 30B generate gate pulses in synchronization with the horizontal synchronization signal, and sequentially apply the gate pulses to each of the gate lines S1 to Sm of the display panel 10.

[0059] The source driver 40 generates n pixel driving voltages G1 to Gn corresponding to the source lines D1 to Dn of the display panel 10 , respectively, based on the image data signal DVS, and outputs the n pixel driving voltages G1 to Gn to the source lines D1 to Dn.

[0060] Here, the driver IC 4a constituting the source driver 40 generates pixel driving voltages G1 to Gk corresponding to k source lines D1 to Dk among the source lines D1 to Dn of the display panel 10, and outputs them to the source lines D1 to Dk, respectively. The driver IC 4b generates pixel driving voltages Gk+1 to Gr corresponding to k source lines Dk+1 to Dr (r is 2·k) among the source lines D1 to Dn, and outputs them to the source lines Dk+1 to Dr, respectively. The driver IC 4c generates pixel driving voltages Gr+1 to Gy corresponding to k source lines Dr+1 to Dy (y is 3·k) among the source lines D1 to Dn, and outputs them to the source lines Dr+1 to Dy, respectively. The driver IC 4d generates pixel drive voltages Gy+1 to Gq corresponding to k source lines Dy+1 to Dq (q is 4·k) among the source lines D1 to Dn, and outputs them to the source lines Dy+1 to Dq, respectively. The driver IC 4e generates pixel drive voltages Gq+1 to Gn corresponding to k source lines Dq+1 to Dn among the source lines D1 to Dn, and outputs them to the source lines Dq+1 to Dn, respectively.

[0061] Figure 2 This is a block diagram showing the internal structure of the source driver by extracting the driver IC 4a from the driver ICs 4a to 4e.

[0062] like Figure 2 As shown, the driver IC 4 a includes a receiving section 40 , an output timing control section 41 , a data latch section 42 , and a digital analog (DA) amplification and output section 43 .

[0063] The receiving unit 40 receives the image data signal DVS, and extracts a series of pixel data PD, delay shift amount setting data SA1 and SA2, start timing setting data TA1 and TA2, and a synchronization signal CS from the image data signal DVS. The receiving unit 40 supplies the extracted delay shift amount setting data SA1 and SA2, start timing setting data TA1 and TA2, and synchronization signal CS to the output timing control unit 41, and supplies the extracted series of pixel data PD to the data latch unit 42.

[0064] The output timing control unit 41 receives the synchronization signal CS and the reference clock signal CLK, and output delay control data including delay shift amount setting data SA1 and SA2 , and start timing setting data TA1 and TA2 .

[0065] The output timing control unit 41 generates output timing signals NC1 to NCk indicating the output timing of each of the first output channel to the kth output channel based on the synchronization signal CS, the reference clock signal CLK, and the output delay control data (SA1, SA2, TA1, TA2). That is, when delaying the output timing in each output channel, the output timing control unit 41 generates output timing signals NC1 to NCk after the delay time is changed for each output channel. The output timing control unit 41 supplies the generated output timing signals NC1 to NCk to the data latch unit 42.

[0066] The data latch unit 42 latches k consecutive pixel data PD in the series of pixel data PD supplied from the receiving unit 40, and outputs them as pixel data V1 to pixel data Vk to the DA amplification output unit 43 at each output timing indicated by the output timing signal NC1 to the output timing signal NCk.

[0067] The DA amplifier output unit 43 converts the pixel data V1 to Vk into k grayscale voltages having analog voltage values ​​corresponding to the luminance levels they represent, and outputs voltages obtained by individually amplifying the k grayscale voltages as pixel driving voltages G1 to Gk.

[0068] Thus, the driver IC 4a outputs the pixel driving voltage G1 to the pixel driving voltage Gk at the output timing after changing the delay time for each output channel based on the output delay control data (SA1, SA2, TA1, TA2). The pixel driving voltage G1 to the pixel driving voltage Gk output from the driver IC 4a are applied to the source lines D1 to the source lines Dk of the display panel 10.

[0069] In addition, if Figure 2 As shown, the output timing control section 41 includes a control signal generating section 410 , a right direction delay generating section 411 , a left direction delay generating section 412 , and a delay selecting section 413 .

[0070] The control signal generating unit 410 generates various control signals for controlling the right direction delay generating unit 411 and the left direction delay generating unit 412 based on the output delay control data (SA1, SA2, TA1, TA2) in synchronization with the reference clock signal CLK and the synchronization signal CS. Furthermore, the control signal generating unit 410 generates a control signal for controlling the delay selecting unit 413 in synchronization with the synchronization signal CS.

[0071] The right-delayed generating unit 411 generates right-delayed shifted signals R1 to Rk, each of which is delayed by a unit delay time from the first output channel to the k-th output channel to generate a single delayed pulse signal.

[0072] Specifically, the right direction delay generating unit 411 generates the right direction delay shift signal R1 which generates a delayed pulse signal at the output timing specified by the start timing setting data TA1 based on the synchronization signal CS (horizontal synchronization signal). Furthermore, the right direction delay generating unit 411 generates the right direction delay shift signal R2 to the right direction delay shift signal Rk which generate delayed pulse signals by delaying each output channel by the unit delay time specified by the delay shift amount setting data SA1 from the first output channel to the k-th output channel.

[0073] The right-direction delay generating section 411 supplies the right-direction delay shift signal R1 to the right-direction delay shift signal Rk generated as described above to the delay selecting section 413 .

[0074] The left-direction delay generating unit 412 generates left-direction delay shift signals L1 to Lk based on various control signals supplied from the control signal generating unit 410, where each output channel is delayed by a unit delay time to generate a single delayed pulse signal from the k-th output channel to the first output channel.

[0075] Specifically, the left direction delay generating unit 412 generates a left direction delay shift signal Lk that generates a delayed pulse signal at the output timing specified by the start timing setting data TA2 based on the synchronization signal CS (horizontal synchronization signal). Furthermore, the left direction delay generating unit 412 generates a left direction delay shift signal Lk-1 to a left direction delay shift signal L1 that generates a delayed pulse signal by delaying each output channel by a unit delay time specified by the delay shift amount setting data SA2 from the kth output channel to the first output channel.

[0076] The left-direction delay generating section 412 supplies the left-direction delay shift signal L1 to the left-direction delay shift signal Lk generated as described above to the delay selecting section 413 .

[0077] The delay selection unit 413 selects, for each of the output channels, one of the signals corresponding to the same output channel, namely, the rightward delayed shift signals (R1 to Rk) and the leftward delayed shift signals (L1 to Lk), whichever has the earlier timing of the delayed pulse signal appearing. Furthermore, the delay selection unit 413 supplies the signal selected as described above to the data latch unit 42 as the output timing signals NC1 to NCk for each of the first to kth output channels.

[0078] For example, when the right direction delayed shift signal R1 and the left direction delayed shift signal L1 corresponding to the first output channel have an earlier timing of the delayed pulse signal appearing, the delay selection section 413 selects the right direction delayed shift signal R1. At this time, the delay selection section 413 supplies the selected right direction delayed shift signal R1 as the output timing signal NC1 to the data latch section 42. In addition, when the left direction delayed shift signal L2 and the right direction delayed shift signal R2 corresponding to the second output channel have an earlier timing of the delayed pulse signal appearing, the delay selection section 413 selects the left direction delayed shift signal L2. At this time, the delay selection section 413 supplies the selected left direction delayed shift signal L2 as the output timing signal NC2 to the data latch section 42.

[0079] Figure 3 It is a diagram showing an example of delay characteristics DR of a delay pulse based on rightward delayed shift signal R1 to rightward delayed shift signal Rk, and examples of three systems of delay characteristics DL1 to DL3 as delay characteristics of a delay pulse based on leftward delayed shift signal L1 to leftward delayed shift signal Lk.

[0080] The delay characteristic DL1 is a characteristic obtained when the start timing setting data TA2 specifies a timing later than the output timing of the k-th output channel in the delay characteristic DR. At this time, the right-direction delayed shift signal R(t) (t is an integer of 1 to k) corresponding to the delay characteristic DR appears earlier than the left-direction delayed shift signal L(t) corresponding to the delay characteristic DL1.

[0081] Therefore, when receiving the right-direction delayed shift signal R1 to the right-direction delayed shift signal Rk corresponding to the delay characteristic DR and the left-direction delayed shift signal L1 to the left-direction delayed shift signal Lk corresponding to the delay characteristic DL1, the delay selection unit 413 selects the right-direction delayed shift signal R1 to the right-direction delayed shift signal Rk and outputs them as the output timing signal NC1 to the output timing signal NCk, respectively. According to the output timing signal NC1 to the output timing signal NCk, as shown in FIG. Figure 4AAs shown, along the output timing delay characteristic (R shift mode) in which the delay time of the output timing increases from the first output channel to the kth output channel, the pixel driving voltages G1 to Gn corresponding to the first output channel to the kth output channel are output respectively.

[0082] The delay characteristic DL2 is a characteristic obtained when the start timing setting data TA2 is set in such a way that the output timing corresponding to the first output channel is earlier than the output timing specified by the start timing setting data TA1. At this time, the timing of the delayed pulse signal appears earlier than the left-direction delayed shift signal L(t) (t is an integer of 1 to k) corresponding to the delay characteristic DL2 and the right-direction delayed shift signal R(t) corresponding to the delay characteristic DR.

[0083] Therefore, when receiving the right-direction delayed shift signal R1 to the right-direction delayed shift signal Rk corresponding to the delay characteristic DR and the left-direction delayed shift signal L1 to the left-direction delayed shift signal Lk corresponding to the delay characteristic DL2, the delay selection unit 413 selects the left-direction delayed shift signal L1 to the left-direction delayed shift signal Lk and outputs them as the output timing signal NC1 to the output timing signal NCk, respectively. Figure 4B As shown, along the output timing delay characteristic (L shift mode) in which the delay time of the output timing from the kth output channel to the first output channel increases, the pixel driving voltages G1 to Gn corresponding to the first output channel to the kth output channel are output respectively.

[0084] The delay characteristic DL3 is a characteristic obtained when the start timing setting data TA2 is designated such that the left-direction delayed shift signal L1 is later than the right-direction delayed shift signal R1 and the left-direction delayed shift signal Lk is earlier than the right-direction delayed shift signal Rk.

[0085] like Figure 3 As shown, the timing of the delayed pulse signal appears earlier than the right-direction delayed shift signal R(u) (u is an integer from 1 to w) corresponding to the first output channel to the w-th output channel (w is an integer in the range of 2 to k-1) along the delay characteristic DR and the left-direction delayed shift signal L(u) in the first output channel to the w-th output channel along the delay characteristic DL3. In addition, the timing of the delayed pulse signal appears earlier than the left-direction delayed shift signal L(x) (x is an integer from w+1 to k) in the w+1-th output channel to the k-th output channel along the delay characteristic DL3 and the right-direction delayed shift signal R(x) in the w+1-th output channel to the k-th output channel along the delay characteristic DR.

[0086] Therefore, the delay selection unit 413 selects the right direction delayed shift signal R1 to the right direction delayed shift signal Rw and the left direction delayed shift signal Lw+1 to the left direction delayed shift signal Lk from the left direction delayed shift signal L1 to the left direction delayed shift signal Lk and the right direction delayed shift signal R1 to the right direction delayed shift signal Rk, and outputs them as the output timing signals NC1 to the output timing signals NCk. According to the output timing signals NC1 to the output timing signals NCk, as shown in FIG. Figure 4C As shown, along the w-th output channel as the boundary, the delay time applied at the output timing tends to change from increasing to decreasing output timing delay characteristics (V shift mode), and the pixel driving voltages G1 to Gn corresponding to the first output channel to the k-th output channel are output respectively.

[0087] Furthermore, in the V shift mode, by designating the start timing setting data TA2, the output timing in the k-th output channel can be adjusted without changing the unit delay time.

[0088] Figure 5 This is a diagram showing an example of a delay form of the output timing adjusted according to the designation of the start timing setting data TA1 and the start timing setting data TA2.

[0089] like Figure 5 As shown in FIG. 1 , when the output timing in the k-th output channel specified by the start timing setting data TA2 is set to “a”, the output timing in the k-th output channel is later than the output timing in the first output channel by a delay time ta. Figure 5 As shown in FIG. 1 , when the output timing in the k-th output channel specified by the start timing setting data TA2 is set to "b" which is later than "a", the output timing in the k-th output channel is later than the output timing in the first output channel by a delay time tb (ta<tb). Figure 5 As shown, the longer the delay time in the k-th output channel is, the closer the output channel, which is the boundary where the delay time applied from the first output channel to the k-th output channel at each output timing switches from an increasing tendency to a decreasing tendency, is to the k-th output channel side.

[0090] Figure 6 It means from Figure 1 The driver IC 4a and the driver IC 4b which are arranged adjacent to each other are extracted from the driver ICs 4a to 4e, and are diagrams showing an example of a delay form of output timing adjusted by the start timing setting data TA1 and the start timing setting data TA2.

[0091] exist Figure 6In the example shown, the driver IC 4a is supplied with the start timing setting data TA1 designating "a1" as the output timing in the first output channel, and the start timing setting data TA2 designating "a2" as the output timing in the k-th output channel. On the other hand, the driver IC 4b arranged adjacent to the driver IC 4a is supplied with the start timing setting data TA1 designating "a2" or a value close to "a2" as the output timing in the first output channel.

[0092] Therefore, according to the output timing control unit 41, by specifying the start timing setting data TA1 and the start timing setting data TA2, the delay time difference of the output timing between adjacent output channels of adjacent driver ICs (source drivers) can be adjusted to reduce the delay time without shortening the unit delay time.

[0093] Therefore, according to the present invention, it is possible to easily adjust the output timing while suppressing display unevenness without increasing the circuit scale.

[0094] The following, Figure 2 Specific structures of the right direction delay generating section 411, the left direction delay generating section 412, and the delay selecting section 413 included in the output timing control section 41 will be described.

[0095] Figure 7 2 is a circuit diagram showing an example of the internal configuration of the right-direction delay generating section 411 , the left-direction delay generating section 412 , and the delay selecting section 413 .

[0096] In addition, in adopting Figure 7 In the case of the structure shown, the control signal generating unit 410 generates the following delayed pulse signal LDR, delayed pulse signal LDL, reset signal RST, clock signal CLK1 and clock signal CLK2 based on the output delay control data (SA1, SA2, TA1, TA2), the reference clock signal CLK and the synchronization signal CS.

[0097] That is, the control signal generating unit 410 generates the following signal using the reference clock signal CLK: Figure 8 The clock signal CLK1 shown in FIG. 1 has a unit delay time specified by the delay shift amount setting data SA1 as one cycle. In addition, the control signal generating unit 410 generates the clock signal CLK1 using the reference clock signal CLK as shown in FIG. Figure 8 The clock signal CLK2 shown in FIG. 1 has a unit delay time specified by the delay shift amount setting data SA2 as one cycle.

[0098] In addition, Figure 8In the example shown, the cycles of the clock signals CLK1 and CLK2 are the same, but when the unit delay times designated by the delay shift amount setting data SA1 and SA2 are different from each other, the cycles of the clock signals CLK1 and CLK2 are also different from each other.

[0099] In addition, the control signal generating unit 410 generates the following according to the synchronization signal CS (horizontal synchronization signal): Figure 8 The reset signal RST is shown as a single pulse.

[0100] In addition, the control signal generating unit 410 is Figure 8 The output timing specified by the start timing setting data TA1 is based on the timing of the rising edge of the reset signal RST shown in FIG. Figure 8 The delayed pulse signal LDR is a single pulse as shown.

[0101] Furthermore, the control signal generating unit 410 is Figure 8 The output timing specified by the start timing setting data TA2 is based on the timing of the rising edge of the reset signal RST shown in FIG. Figure 8 The delayed pulse signal LDL is a single pulse.

[0102] The control signal generating section 410 supplies the clock signal CLK1 and the delay pulse signal LDR to the right delay generating section 411 and supplies the clock signal CLK2 and the delay pulse signal LDL to the left delay generating section 412. The control signal generating section 410 supplies the reset signal RST to the delay selecting section 413.

[0103] The right direction delay generating unit 411 includes the following shift registers: Figure 7 As shown, the first to kth delay circuits corresponding to the first to kth output channels are cascade-connected in the order of first to kth arrangement. The flip-flops DF1 to DFk receive the clock signal CLK1 using their respective clock terminals. The flip-flop DF1 receives the clock signal CLK1. Figure 8 The single pulse delayed pulse signal LDR shown in the figure is outputted at the timing of the clock signal CLK1 and supplied to the next stage flip-flop DF2. Similarly, the flip-flop DF2 to the flip-flop DFk respectively supply the delayed pulse signal LDR outputted by the previous stage flip-flop DF to the next stage flip-flop DF at the timing of the clock signal CLK1.

[0104] In the right-direction delay generating section 411 , output signals respectively outputted from the flip-flop DF1 to the flip-flop DFk are supplied to the delay selecting section 413 as the right-direction delay shift signal R1 to the right-direction delay shift signal Rk.

[0105] The left direction delay generating unit 412 includes the following shift registers: Figure 7 As shown, the first to kth delay circuits corresponding to the first to kth output channels are cascade-connected in the order of kth to first. The flip-flops DF1k to DF11 receive the clock signal CLK2 using their respective clock terminals. The flip-flop DF1k receives the clock signal CLK2. Figure 8 The single pulse delayed pulse signal LDL is outputted at the timing of the clock signal CLK2 and supplied to the next stage flip-flop DF1k-1. Similarly, the flip-flop DF1k-1 to the flip-flop DF11 respectively supply the delayed pulse signal LDL outputted by the previous stage flip-flop DF to the next stage flip-flop DF at the timing of the clock signal CLK2.

[0106] In the left-direction delay generating section 412 , output signals respectively outputted from the flip-flop DF11 to the flip-flop DF1 k are supplied to the delay selecting section 413 as the left-direction delay shift signal L1 to the left-direction delay shift signal Lk.

[0107] The delay selection unit 413 has delay selection circuits SE1 to SEk respectively corresponding to the first output channel to the kth output channel. The delay selection circuits SE1 to SEk respectively include the same circuit structure and receive the reset signal RST respectively. Furthermore, the delay selection circuits SE1 to SEk respectively receive a pair of right-direction delay shift signals R(f) (f is an integer from 1 to k) and a left-direction delay shift signal L(f) corresponding to their own output channels. For example, Figure 8 As shown, the delay selection circuit SE1 receives the right-direction delayed shift signal R1 and the left-direction delayed shift signal L1. In addition, the delay selection circuit SE2 receives the right-direction delayed shift signal R2 and the left-direction delayed shift signal L2.

[0108] like Figure 8 As shown, the delay selection circuits SE1 to SEk reset the output timing signals NC1 to NCk outputted by the delay selection circuits SE1 to SEk from logic level 0 to logic level 1 at the timing of the rising edge of the reset signal RST. Thereafter, the delay selection circuits SE1 to SEk respectively change the output timing signal NC(f) to logic level 0 at the timing when the delay pulse signal appears earlier in the right direction delay shift signal R(f) and the left direction delay shift signal L(f) received by the delay selection circuits SE1 to SEk.

[0109] For example, in Figure 8In the example shown, of the right-delayed shift signal R1 and the left-delayed shift signal L1, the right-delayed shift signal R1 has an earlier timing of appearing a delayed pulse signal. Figure 8 As shown, the delay selection circuit SE1 receiving the pair of rightward delayed shift signal R1 and leftward delayed shift signal L1 selects the rightward delayed shift signal R1 and changes the output timing signal NC1 from logic level 1 to logic level 0 at the timing of its rising edge.

[0110] In addition, in adopting Figure 7 When the circuit configuration shown is used as the right-direction delay generator 411, the left-direction delay generator 412, and the delay selector 413, Figure 8 The falling edge of each of the output timing signals NC1 to NCk is the output timing. Thus, the data latch unit 42 outputs the latched k pixel data PD at the timing of the trailing edge of each of the output timing signals NC1 to NCk.

[0111] Fig. 9 4 is a circuit diagram showing another example of the internal structure of the right-direction delay generating section 411 and the left-direction delay generating section 412. Fig. 9 In the example, the internal structure of the delay selection unit 413 is similar to Figure 7 The same as shown, so their description is omitted.

[0112] exist Fig. 9 In the structure shown in the figure, the delay circuit used as the right-direction delay generating unit 411 is replaced by Figure 7 Instead of the flip-flop DF1 to flip-flop DFk shown in FIG. 1 , an inverter circuit IV1 to an inverter circuit IVk including a pair of inverter elements connected in cascade to each other are used. In addition, as the delay circuit of the left-direction delay generating unit 412, a Figure 7 The flip-flop DF1k to flip-flop DF11 shown in the figure adopts the inverter circuit IV1k to inverter circuit IV11 including two-stage inverters in cascade connection. In addition, the inverter circuit IV1 to inverter circuit IVk and the inverter circuit IV1k to inverter circuit IV11 are delay variable elements whose element delay time required from receiving an input signal to outputting an output can be changed according to a delay control signal.

[0113] In addition, the control signal generating unit 410 supplies the delay control signal DC1 indicating the unit delay time specified by the delay shift amount setting data SA1 to the inverter circuit IV1 to the inverter circuit IVk instead of the clock signal CLK1. As a result, the inverter circuit IV1 to the inverter circuit IVk delay the delay pulse signal LDR supplied from the previous stage by the delay time indicated by the delay control signal DC1, and output it to the inverter circuit of the next stage.

[0114] In addition, the control signal generating section 410 supplies the delay control signal DC2 indicating the unit delay time specified by the delay shift amount setting data SA2 to the inverter circuit IV1k to the inverter circuit IV11 instead of the clock signal CLK2. As a result, the inverter circuit IV1k to the inverter circuit IV11 delay the delay pulse signal LDL supplied from the previous stage by the delay time indicated by the delay control signal DC2, and output it to the inverter circuit of the next stage.

[0115] Fig.10 It means realization Figure 8 The action shown, Figure 7 or Fig. 9 1 is a circuit diagram showing an example of the internal structure of the delay selection circuit SE1 to the delay selection circuit SEk.

[0116] like Fig.10 As shown, the delay selection circuits SE1 to SEk respectively include the same structure, namely, an OR gate 51 and a reset set (RS) flip-flop 52 .

[0117] The OR gate 51 receives a pair of right-direction delayed shift signals R(f) (f is an integer from 1 to k) and left-direction delayed shift signals L(f) corresponding to the same output channel, and supplies the result of the logical sum of the two to the reset terminal of the RS flip-flop 52. In addition, when at least one of the right-direction delayed shift signal R(f) and the left-direction delayed shift signal L(f) indicates a logic level 1, the OR gate 51 supplies a signal of a logic level 1 to prompt a reset to the reset terminal of the RS flip-flop 52.

[0118] In addition, the RS flip-flop 52 receives the reset signal RST at its set terminal. When the RS flip-flop 52 receives the reset signal RST of logic level 1 at its set terminal, it is in a set state and outputs a signal of logic level 1. On the other hand, when the RS flip-flop 52 receives the signal of logic level 1 at its reset terminal, it is in a reset state and outputs a signal of logic level 0.

[0119] The delay selection circuit SE1 to the delay selection circuit SEk output the signals output from the respective RS flip-flops 52 to the data latch section 42 as the output timing signals NC1 to the output timing signals NCk.

[0120] In addition, Fig.10 In the example shown, the logical AND result of the OR gate 51, that is, the output of the OR gate, is supplied to the reset terminal of the RS flip-flop 52, and the reset signal RST is supplied to the set terminal of the RS flip-flop 52. However, the output of the OR gate may be supplied to the set terminal, and the reset signal RST may be supplied to the reset terminal. In this case, the timing of the rising edge of each of the output timing signal NC1 to the output timing signal NCk becomes the output timing. In short, any configuration in which the output of the OR gate is supplied to one of the reset terminal and the set terminal of the RS flip-flop 52, and the reset signal RST is supplied to the other of the reset terminal and the set terminal of the RS flip-flop 52 may be sufficient.

[0121] Fig.11 It means realization Figure 8 The action shown, Figure 7 or Fig. 9 2 is a circuit diagram showing another example of the internal structure of the delay selection circuit SE1 to the delay selection circuit SEk.

[0122] In addition, when using Fig.11 When the circuit configuration shown in the figure is used as each of the delay selection circuits SE1 to SEk, the control signal generation unit 410 generates an inverted reset signal XRST which inverts the logic level of the reset signal RST, instead of Figure 8 The reset signal RST is shown.

[0123] like Fig.11 As shown, the delay selection circuits SE1 to SEk respectively include the same structure, namely, a p-channel Metal Oxide Semiconductor (MOS) transistor Q1, an n-channel MOS transistor Q2, and an n-channel MOS transistor Q3.

[0124] Transistor Q1 uses its gate to receive Figure 8 The inverted reset signal XRST is shown. The transistor Q1 is turned on during the period when the inverted reset signal XRST is at a logic level 0, and a current based on the power supply voltage VDD is sent to the node n1, thereby accumulating a charge (pre-charging) at the node n1. The transistor Q1 increases the voltage of the node n1 by the pre-charging, thereby reaching a logic level 1 state.

[0125] The transistor Q2 receives the right direction delayed shift signal R(f) of a pair of right direction delayed shift signals R(f) (f is an integer of 1 to k) and the left direction delayed shift signal L(f) corresponding to the same output channel through its gate. The transistor Q2 is turned on during the period when the right direction delayed shift signal R(f) is in the state of logic level 1, and discharges the charge accumulated in the node n1. Thus, the transistor Q2 makes the node n1 reach the state of logic level 0.

[0126] The transistor Q3 receives the left direction delayed shift signal L(f) of a pair of right direction delayed shift signal R(f) and left direction delayed shift signal L(f) corresponding to the same output channel through its gate. The transistor Q3 is turned on during the period when the left direction delayed shift signal L(f) is in the state of logic level 1, and discharges the charge accumulated in the node n1. Thus, the transistor Q3 makes the node n1 reach the state of logic level 0.

[0127] The delay selection circuit SE1 to the delay selection circuit SEk output the voltage of the respective node n1 to the data latch portion 42 as the output timing signal NC1 to the output timing signal NCk.

[0128] exist Fig.11 In the structure shown, Figure 8 During the period when the inverted reset signal XRST is at logic level 0, the node n1 of each of the delay selection circuits SE1 to SEk is precharged by the transistor Q1, and the node n1 is set to the state of logic level 1. As a result, the output timing signals NC1 to NCk corresponding to the states of the node n1 are respectively Figure 8 As shown, the right-delayed shift signal R(f) and the left-delayed shift signal L(f) are also set to the state of logic level 1. Thereafter, in the one of the right-delayed shift signal R(f) and the left-delayed shift signal L(f) that becomes the state of logic level 1 first, the transistor Q2 or the transistor Q3 discharges the charge accumulated in the node n1. As a result, the output timing signal NC changes from the state of logic level 1 to the state of logic level 0.

[0129] For example, Figure 8 As shown in FIG. 1 , among the right direction delayed shift signal R1 and the left direction delayed shift signal L1 corresponding to the first output channel, the right direction delayed shift signal R1 is first converted to the state of logic level 1. Therefore, Figure 8 As shown, by delaying the timing of the rising edge of the shift signal R1 in the right direction, the transistor Q2 of the delay selection circuit SE1 discharges the node n1, as shown in FIG. Figure 8 As shown, the output timing signal NC1 which is the output of the delay selection circuit SE1 changes to the state of logic level 0.

[0130] Fig.12 It means that Figure 2 The circuit diagram of the circuit shown is a circuit in which the functions of the right-direction delay generating section 411, the left-direction delay generating section 412 and the delay selecting section 413 are realized with a simplified structure.

[0131] Fig.12 The circuit shown has circuit blocks BC1 to BCk corresponding to the first to kth output channels, respectively, and each having the same circuit structure.

[0132] The circuit block BC1 to the circuit block BCk include an inverter IT, a p-channel MOS transistor U1, an n-channel MOS transistor U2, and an n-channel MOS transistor U3, respectively.

[0133] The transistor U1 of each circuit block BC1 to circuit block BCk receives the Figure 8 The inverted reset signal XRST is shown. When the inverted reset signal XRST is at a logic level 0, the transistor U1 becomes conductive, sends a current based on the power supply voltage VDD to the node nd, and accumulates charge (precharge) at the node nd. The transistor U1 increases the voltage of the node nd through the precharge, thereby reaching a logic level 1.

[0134] Among the circuit blocks BC1 to BCk, the transistor U2 of each circuit block BC except the circuit block BCk corresponding to the kth output channel receives the inverted output timing signal output from the circuit block BC corresponding to the output channel of the next stage by its own gate. The transistor U2 becomes conductive during the period when the inverted output timing signal is in the state of logic level 1, and discharges the charge accumulated in the node nd. Thus, the transistor U2 makes the node nd reach the state of logic level 0.

[0135] The transistor U2 of the circuit block BCk corresponding to the k-th output channel receives the delay pulse signal LDL based on the start timing setting data TA2 through its gate. The transistor U2 of the circuit block BCk becomes conductive during the period when the delay pulse signal LDL is in the state of logic level 1, and discharges the charge accumulated in the node nd. Thus, the transistor U2 makes the node nd reach the state of logic level 0.

[0136] Among the circuit blocks BC1 to BCk, the transistor U3 of the circuit block BC1 corresponding to the first output channel receives the delay pulse signal LDR based on the start timing setting data TA1 by its gate. The transistor U3 of the circuit block BC1 becomes conductive during the period when the delay pulse signal LDR is in the state of logic level 1, and discharges the charge accumulated in the node nd. Thus, the transistor U3 of the circuit block BC1 makes the node nd reach the state of logic level 0.

[0137] The inverter IT of the circuit block BC1 supplies a signal obtained by inverting the logic level of the node nd as the inverted output timing signal to the gate of the transistor U3 of the circuit block BC1 of the next stage.

[0138] The inverter IT of each of the circuit blocks BC1 to BCk, including BC2 to BCk-1, inverts the logic level of the node nd as the inverted output timing signal, and supplies it to the gate of the transistor U3 of each of the circuit blocks BC at the next stage and the gate of the transistor U2 of each of the circuit blocks BC at the previous stage.

[0139] The inverter IT of the circuit block BCk supplies a signal obtained by inverting the logic level of the node nd as the inverted output timing signal to the gate of the transistor U2 of the circuit block BCk-1 of the previous stage.

[0140] The transistor U3 of each circuit block BC2 to circuit block BCk receives the inverted output timing signal output from the circuit block BC of the previous stage, and becomes conductive during the period when the inverted output timing signal is in the state of logic level 1, so as to discharge (discharge) the charge accumulated in the node nd. Thus, the transistor U3 of each circuit block BC2 to circuit block BCk makes the node nd reach the state of logic level 0.

[0141] The circuit block BC1 to the circuit block BCk output the voltage of each node nd to the data latch portion 42 as the output timing signal NC1 to the output timing signal NCk.

[0142] exist Fig.12 In the structure shown, Figure 8 As shown, first, according to the inverted reset signal XRST of logic level 0, the transistor U1 of each circuit block BC1 to circuit block BCk precharges the node nd. Figure 8 As shown, the output timing signals NC1 to NCk are all in the state of logic level 1.

[0143] Then, when Figure 8 When the delayed pulse signal LDR shown in FIG. 1 is supplied to the gate of the transistor U3 of the circuit block BC1, the node nd of the circuit block BC1 is discharged. Figure 8As shown in FIG. 1 , the output timing signal NC1 changes to a logic level 0. As a result, the inverter IT of the circuit block BC1 supplies an inverted output timing signal of a logic level 1 to the gate of the transistor U3 of the next-stage circuit block BC2. Then, the node nd of the circuit block BC2 is discharged through the transistor U3 of the circuit block BC2, as shown in FIG. Figure 8 As shown, the output timing signal NC2 changes to a logic level 0.

[0144] In addition, during this period, Figure 8 When the delayed pulse signal LDL shown in FIG. 1 is supplied to the gate of the transistor U2 of the circuit block BCk, the node nd of the circuit block BCk is discharged, as shown in FIG. Figure 8 As shown in FIG. 1 , the output timing signal NCk changes to a logic level 0. As a result, the inverter IT of the circuit block BCk supplies an inverted output timing signal of a logic level 1 to the gate of the transistor U2 of the circuit block BCk-1 of the previous stage. Then, the node nd of the circuit block BCk-1 is discharged through the transistor U2 of the circuit block BCk-1, as shown in FIG. Figure 8 As shown, the output timing signal NCk-1 changes to a logic level 0.

[0145] As mentioned above, in the use of Fig.12 When the structure shown in the figure is used as the right direction delay generating unit 411, the left direction delay generating unit 412 and the delay selecting unit 413, it is also possible to realize Figure 3 to Figure 6 and Figure 8 Action shown.

[0146] In addition, Figure 2 In the example shown, the output timing of each of the output channels of the pixel driving voltage G1 to the pixel driving voltage Gk is adjusted by outputting k pixel data PD latched by the data latch unit 42 at the output timing of the output timing signals NC1 to the output timing signal NCk, but the pixel driving voltage G1 to the pixel driving voltage Gk may also be output at the output timing of the output timing signals NC1 to the output timing signal NCk.

[0147] In short, the display driver (eg, 4a to 4e) of the present invention may be any driver as long as it has the following output timing control unit and output unit.

[0148] The output timing control unit (41) generates a first output timing signal to a kth output timing signal (NC1 to NCk) indicating the output timing in each of the first output channel to the kth output channel. The output units (42, 43) respectively output a first pixel driving voltage to a kth pixel driving voltage (G1 to Gk) at the output timing indicated by each of the first output timing signal to the kth output timing signal.

[0149] Furthermore, the output timing control unit (41) includes the following control signal generating unit, a first delay generating unit, a second delay generating unit, and a delay selecting unit.

[0150] The control signal generating unit receives the designation of the output timing of each of the first output channel and the k-th output channel (TA1, TA2), and generates a first delayed pulse signal (LDR) at the designated output timing of the first output channel. Furthermore, it generates a second delayed pulse signal (LDL) at the designated output timing of the k-th output channel.

[0151] The first delay generating unit (411) receives the first delayed pulse signal and generates a first first direction delayed shift signal to a kth first direction delayed shift signal (R1 to Rk) which increases the delay of a unit delay time from the first output channel to the kth output channel to generate a first delayed pulse signal.

[0152] The second delay generating unit (412) receives the second delayed pulse signal and generates a first second direction delayed shift signal to a kth second direction delayed shift signal (L1 to Lk) which generates a second delayed pulse signal by increasing the delay of a unit delay time from the kth output channel to the first output channel.

[0153] The delay selection unit (413) selects, for each of the first to kth output channels, one of the signals corresponding to the same output channel, i.e., each of the first to kth first direction delayed shift signals and each of the first to kth second direction delayed shift signals, one of which has an earlier timing of appearing a delayed pulse signal, and outputs the selected signal for each of the first to kth output channels as the first to kth output timing signals (NC1 to NCk).

Claims

1. A display driver having first to k-th output channels for outputting first to k-th pixel driving voltages respectively corresponding to the brightness levels of respective pixels represented by an image signal, wherein k is an integer greater than or equal to 2, Features have: an output timing control unit that generates first to k-th output timing signals indicating output timings in each of the first to k-th output channels; and an output unit that outputs the first to k-th pixel driving voltages at the output timings indicated by the first to k-th output timing signals, respectively; The output timing control unit comprises: a control signal generating unit receiving a designation of an output timing in each of the first output channel and the k-th output channel, generating a first delayed pulse signal at the designated output timing of the first output channel, and generating a second delayed pulse signal at the designated output timing of the k-th output channel; A first delay generating unit receives the first delay pulse signal and generates first to k-th first direction delay shift signals, which are the first delay pulse signal, from the first output channel to the k-th output channel, where each output channel increases the delay of the first delay pulse signal by a unit delay time. A second delay generating unit receives the second delay pulse signal and generates a first second direction delay shift signal to a kth second direction delay shift signal, wherein the second delay pulse signal appears after each output channel increases the delay of a unit delay time from the kth output channel to the first output channel; and The delay selection unit selects, for each of the first to k-th output channels, one of the signals corresponding to the same output channel, i.e., each of the first to k-th first-direction delayed shift signals and each of the first to k-th second-direction delayed shift signals, which has an earlier timing of appearing the delayed pulse signal, and outputs the selected signal as the first to k-th output timing signals for each of the first to k-th output channels.

2. The display driver according to claim 1, It is characterized in that The first delay generating unit includes a first delay circuit group in which first to k-th delay circuits corresponding to the first to k-th output channels are cascade-connected in a first to k-th arrangement order, and is configured to input the first delay pulse signal to the first delay circuit of the first delay circuit group, and use the respective outputs of the first to k-th delay circuits of the first delay circuit group as the first first-direction delayed shift signal to the k-th first-direction delayed shift signal, and The second delay generating unit includes a second delay circuit group in which the first delay circuit to the kth delay circuit corresponding to the first output channel to the kth output channel are cascade-connected in the order of kth to first, and is configured to input the second delayed pulse signal to the kth delay circuit of the second delay circuit group, and use the outputs of the first delay circuit to the kth delay circuit of the second delay circuit group as the first second direction delayed shift signal to the kth second direction delayed shift signal.

3. The display driver according to claim 2, It is characterized in that The delay circuits respectively included in the first delay circuit group and the second delay circuit group are triggers, The first delay circuit group includes a first shift register, wherein the first shift register is configured such that first to k-th triggers corresponding to the first to k-th output channels are cascade-connected in the order of the first to k-th triggers, and the first delay pulse signal is input to the first trigger, and The second delay circuit group includes a second shift register, which is configured such that the first to kth triggers corresponding to the first to kth output channels are cascade-connected in the order of the kth to first triggers, and the second delay pulse signal is input to the kth trigger.

4. The display driver according to claim 2, It is characterized in that The delay circuits included in the first delay circuit group and the second delay circuit group are inverter circuits including a pair of inverter elements connected in cascade to each other. The first delay circuit group is composed of first to kth inverter circuits corresponding to the first to kth output channels, which are cascade-connected in the order of first to kth arrangement, and the first delay pulse signal is input to the first inverter circuit, and The second delay circuit group is configured such that the first to kth inverter circuits corresponding to the first to kth output channels are cascade-connected in the order of kth to first, and the second delay pulse signal is input to the kth inverter circuit.

5. The display driver according to any one of claims 2 to 4, It is characterized in that The control signal generating unit generates a reset signal corresponding to a horizontal synchronization signal in the video signal. The delay selection unit includes first to k-th delay selection circuits corresponding to the first to k-th output channels, respectively, and The first delay selection circuit to the kth delay selection circuit respectively include: an OR gate receiving outputs of the delay circuits in the first delay circuit group and the second delay circuit group corresponding to the same output channel from the first delay circuit to the kth delay circuit in the first delay circuit group and the outputs of the delay circuits in the second delay circuit group; and A reset-set flip-flop receives one of the reset signal and the output of the OR gate via a set terminal and receives the other via a reset terminal, wherein The signals outputted from the reset-set flip-flops of the first to k-th delay selection circuits are outputted as the first to k-th output timing signals.

6. The display driver according to any one of claims 2 to 4, It is characterized in that The control signal generating unit generates a reset signal corresponding to a horizontal synchronization signal in the video signal. The delay selection unit includes first to k-th delay selection circuits corresponding to the first to k-th output channels, respectively, and The first delay selection circuit to the kth delay selection circuit respectively include: First node; a first transistor, precharging the first node according to the reset signal; a second transistor that discharges the first node according to an output of one of a pair of the delay circuits corresponding to the same output channel among the first to k-th delay circuits included in the first delay circuit group and the first to k-th delay circuits included in the second delay circuit group; and a third transistor that discharges the first node according to the output of the other of the pair of delay circuits, wherein The signals generated in the first nodes of the first to k-th delay selection circuits are output as the first to k-th output timing signals.

7. The display driver according to claim 1, It is characterized in that The control signal generating unit generates a reset signal corresponding to a horizontal synchronization signal in the video signal. The output timing control unit, the first delay generating unit, the second delay generating unit, and the delay selecting unit include a structure in which first to k-th circuit blocks corresponding to the first to k-th output channels are cascade-connected, respectively, and The first to kth circuit blocks respectively include: First node; a first p-channel transistor, precharging the first node according to the reset signal; A second n-channel transistor and a third n-channel transistor discharge the first node; and An inverter is used to invert the signal of the first node, wherein The second transistor included in each of the first to k-1th circuit blocks discharges the first node according to the output of the inverter included in the subsequent circuit block. The third transistor included in each of the second to k-th circuit blocks discharges the first node according to the output of the inverter included in the circuit block at the previous stage, The third transistor included in the first circuit block discharges the first node according to the first delayed pulse signal, The second transistor included in the kth circuit block discharges the first node according to the second delayed pulse signal, and The signals generated in the first nodes included in each of the second to k-th circuit blocks are output as the first to k-th output timing signals.

8. The display driver according to claim 3, It is characterized in that The control signal generating unit receives the designation of a first unit delay time and a second unit delay time, generates a first clock signal having a period corresponding to the first unit delay time, and supplies the first clock signal to the clock terminals of the first to k-th triggers of the first delay circuit group, and generates a second clock signal having a period corresponding to the second unit delay time, and supplies the second clock signal to the clock terminals of the first to k-th triggers of the second delay circuit group.

9. The display driver according to claim 4, It is characterized in that The first to k-th inverter circuits of each of the first delay circuit group and the second delay circuit group can change the output delay time based on a delay control signal, and The control signal generating unit receives the designation of a first unit delay time and a second unit delay time, supplies a first delay control signal indicating the designated first unit delay time to each of the first to k-th inverting circuits of the first delay circuit group, and supplies a second delay control signal indicating the designated second unit delay time to each of the first to k-th inverting circuits of the second delay circuit group.

Images