Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The forming method includes: providing a substrate including a target layer for forming a target pattern; forming discrete core layers on the target layer; forming dummy sidewalls on sidewalls of the core layers; forming a filling layer on the target layer exposed by the core layers and the dummy sidewalls; removing a part of the height of the dummy sidewalls, and the remaining dummy sidewalls, the filling layer and the core layers enclose a trench; filling a mask sidewall in the trench; after forming the mask sidewall, removing the core layers and the filling layer; using the mask sidewall as a mask to pattern the target layer to form a target pattern. Embodiments of the present invention are beneficial to improving the accuracy of pattern transfer, and further improving the pattern accuracy (e.g., critical dimension accuracy) and topography quality of the target pattern.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] Lithography technology is a commonly used patterning method and is the most critical production technology in semiconductor manufacturing processes. As the semiconductor process nodes continue to decrease, the Self-Aligned Double Patterning (SADP) method has become a favored patterning method in recent years. This method can increase the density of patterns formed on a substrate, further reduce the pitch between two adjacent patterns, so that the lithography process can overcome the limit of lithography resolution.

[0003] As the critical dimension (CD) of patterns continues to decrease, the Self-Aligned Quadruple Patterning (SAQP) method has emerged. The density of patterns formed on a substrate by the self-aligned double patterning method is twice the density of patterns formed on the substrate by the lithography process, that is, a 1 / 2 minimum pitch can be obtained. Without changing the current lithography technology (i.e., the size of the lithography window remains unchanged), the density of patterns formed on the substrate by the self-aligned quadruple patterning method is four times the density of patterns formed on the substrate by the lithography process, that is, a 1 / 4 minimum pitch can be obtained. Thus, the density of semiconductor integrated circuits can be greatly improved, the feature size of patterns can be reduced, and further the device performance can be improved.

[0004] However, the current pattern transfer accuracy is low. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to improving the pattern transfer accuracy.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate including a target layer for forming a target pattern; forming discrete core layers on the target layer; forming dummy sidewalls on sidewalls of the core layers; forming a filling layer on the target layer exposed by the core layers and the dummy sidewalls; removing a part of the height of the dummy sidewalls, and the remaining dummy sidewalls, the filling layer, and the core layers enclose a trench; filling a mask sidewall in the trench; after forming the mask sidewall, removing the core layers and the filling layer; using the mask sidewall as a mask to pattern the target layer to form a target pattern.

[0007] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate including a target layer for forming a target pattern; a core layer separated from the target layer; a sidewall structure layer located on the sidewalls of the core layer, the sidewall structure layer including a dummy sidewall and a mask sidewall located on the dummy sidewall, wherein the mask sidewall is used as a mask for patterning the target layer; and a filling layer located on the target layer exposed by the core layer and the sidewall structure layer.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the method for forming the semiconductor structure provided by the embodiment of the present invention, after forming the dummy sidewall, a filling layer is first formed on the substrate exposed by the core layer and the dummy sidewall; a part of the height of the dummy sidewall is removed to form a trench; a mask sidewall is filled in the trench; in the step of forming the dummy sidewall, the sidewall of the dummy sidewall has a certain inclination, and there is an easy problem of bottom footing at the bottom of the dummy sidewall. The closer to the bottom of the dummy sidewall, the larger the lateral dimension of the dummy sidewall, and the greater the deviation between the lateral dimension of the dummy sidewall and the design dimension. The closer to the top of the dummy sidewall, the smaller the deviation between the lateral dimension of the dummy sidewall and the design dimension. After forming the trench by removing a part of the height of the dummy sidewall and forming a mask sidewall in the trench, compared with the lateral dimension of the dummy sidewall, the deviation between the lateral dimension of the mask sidewall and the design dimension is smaller. Therefore, in the process of patterning the target layer with the mask sidewall as a mask, it is beneficial to improve the accuracy of pattern transfer, reduce the deviation between the critical dimension of the target pattern and the design dimension, and further improve the pattern accuracy of the target pattern (for example: critical dimension accuracy), and it is also beneficial to improve the problem of pitch walking, which correspondingly helps to increase the process window of subsequent processes, improve the process yield, and the performance of the semiconductor structure. Description of the Drawings

[0010] Figures 1 to 4 is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0011] Figures 5 to 15 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present invention. Detailed Embodiments

[0012] As can be seen from the background art, SADP and SAQP are widely used in the patterning process. However, currently, the pattern transfer accuracy of the SADP or SAQP process is low, and the quality of the formed target pattern is poor. The reason for the low pattern transfer accuracy is analyzed in combination with a method for forming a semiconductor structure.

[0013] Reference Figures 1 to 4 shows a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0014] Reference Figure 1 provides a substrate 1; a discrete core layer 2 is formed on the substrate 1.

[0015] Reference Figure 2 a spacer 3 is formed on the sidewall of the core layer 2.

[0016] Reference Figure 3 the core layer 2 is removed.

[0017] Reference Figure 4 using the spacer 3 as a mask, the substrate 1 is patterned to form a target pattern 4.

[0018] In the formation method, the spacer 3 is used as a mask for patterning the substrate 1, and the morphology and dimensions of the spacer 3 are crucial for the effect of pattern transfer. However, during the formation process of the spacer 3, the spacer 3 is prone to defects such as bottom footing, and moreover, the sidewall of the spacer 3 is not completely perpendicular to the surface of the substrate 1. The sidewall of the spacer 3 usually has a certain inclination. The closer to the bottom of the spacer 3, the larger the lateral dimension of the spacer 3, and the greater the deviation between the lateral dimension of the spacer 3 and the designed dimension. This results in poor pattern transfer accuracy, and further leads to poor pattern accuracy and morphology quality of the target pattern 4. The morphology quality and critical dimensions of the target pattern 4 are difficult to meet the design requirements, and it is also prone to problems such as pitchwalking.

[0019] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate including a target layer for forming a target pattern; forming a discrete core layer on the target layer; forming a pseudo-spacer on the sidewall of the core layer; forming a filling layer on the target layer exposed by the core layer and the pseudo-spacer; removing a part of the height of the pseudo-spacer, and the remaining pseudo-spacer, the filling layer and the core layer enclose a trench; filling a mask spacer in the trench; after forming the mask spacer, removing the core layer and the filling layer; using the mask spacer as a mask, patterning the target layer to form a target pattern.

[0020] In the method for forming a semiconductor structure provided by an embodiment of the present invention, after forming a dummy sidewall, a filling layer is first formed on the core layer and the substrate exposed by the dummy sidewall; a part of the height of the dummy sidewall is removed to form a trench; a mask sidewall is filled in the trench; in the step of forming the dummy sidewall, the sidewall of the dummy sidewall has a certain inclination, and there is an easy problem of bottom footing at the bottom of the dummy sidewall. The closer to the bottom of the dummy sidewall, the larger the lateral dimension of the dummy sidewall, and the larger the deviation between the lateral dimension of the dummy sidewall and the design dimension. The closer to the top of the dummy sidewall, the smaller the deviation between the lateral dimension of the dummy sidewall and the design dimension. After forming a trench by removing a part of the height of the dummy sidewall and forming a mask sidewall in the trench, compared with the lateral dimension of the dummy sidewall, the deviation between the lateral dimension of the mask sidewall and the design dimension is smaller. Therefore, in the process of patterning a target layer with the mask sidewall as a mask pattern, it is beneficial to improve the accuracy of pattern transfer, reduce the deviation between the critical dimension of the target pattern and the design dimension, and further improve the pattern accuracy of the target pattern (for example: critical dimension accuracy), and it is also beneficial to improve the problem of pitch walking, which correspondingly helps to increase the process window of subsequent processes, improve the yield of the process and the performance of the semiconductor structure.

[0021] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0022] Figures 5 to 15 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

[0023] Refer to Figure 5 , a substrate is provided, including a target layer 100 for forming a target pattern.

[0024] The substrate is used to provide a platform for the process. The target layer 100 is a film layer to be patterned to form a target pattern.

[0025] In this embodiment, the target layer 100 is an initial substrate. Subsequently, the initial substrate is patterned to form a substrate and fins protruding from the substrate. Correspondingly, the target pattern is the fins. The fins are used to form fin field effect transistors (FinFETs).

[0026] In this embodiment, the material of the initial substrate is silicon. In some other embodiments, the material of the initial substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the initial substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. In still some other embodiments, the initial substrate can also include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, and then the second semiconductor layer is patterned to form fins, and the first semiconductor layer is retained for use as the substrate.

[0027] In other embodiments, the target pattern can also be patterns such as a gate structure, an interconnect trench in the back-end process, a channel stack in a gate-all-around (GAA) transistor, or a hard mask (HM) layer. According to the target pattern formed according to actual needs, the material of the target layer can also be other corresponding materials.

[0028] In this embodiment, the substrate further includes an adhesion layer 101 and a hard mask material layer 102 stacked in sequence on the target layer 100.

[0029] The adhesion layer 101 is used to improve the adhesion between the hard mask material layer 102 and the target layer 100 and reduce the stress generated between the film layers. In this embodiment, the material of the adhesion layer 101 is silicon oxide.

[0030] After forming the mask sidewall, the hard mask material layer 102 is first patterned using the mask sidewall as a mask pattern to form a hard mask layer. Even if the mask sidewall is damaged during the process of patterning the target layer 100, the target layer 100 can still be patterned using the hard mask layer as a mask subsequently, which is beneficial to improving the process stability of patterning the target layer 100 and correspondingly improving the accuracy of pattern transfer. In addition, the subsequent processes of forming the core layer, removing the core layer, and filling the layer on the target layer 100 all include etching processes, and the hard mask material layer 102 can also define the etching stop position in these etching processes to avoid etching damage to the film layer below it, thereby reducing the probability of the problem of inconsistent heights on the top surface of the film layer to be etched below it and correspondingly improving the etching uniformity of patterning the target layer 100 subsequently.

[0031] The material of the hard mask material layer 102 includes one or more of silicon nitride, titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon oxynitride. In this embodiment, the material of the hard mask material layer 102 is silicon nitride.

[0032] It should be noted that in this embodiment, the forming method further includes: forming an etching buffer layer 110 on the target layer 100. Specifically, the etching buffer layer 110 is formed on the hard mask material layer 102.

[0033] In this embodiment, the subsequent steps further include: forming discrete core layers on the target layer 100; forming sidewall films conformally covering the core layers and the target layer 100, and the sidewall films located on the sidewalls of the core layers are used as pseudo sidewalls; forming a filling layer on the exposed sidewall films of the core layers and the pseudo sidewalls; removing a part of the height of the pseudo sidewalls to form trenches; filling mask sidewalls in the trenches; removing the core layers and the filling layer; using the mask sidewalls as masks to pattern the target layer to form target patterns.

[0034] By forming the etch buffer layer 110, the sidewall films are formed on the etch buffer layer 110. Thus, before subsequent patterning of the target layer 100, the sidewall films, the etch buffer layer 110, and the pseudo sidewalls can also be etched using the mask sidewalls as masks; after removing the filling layer and the core layers, one side of the mask sidewalls exposes the sidewall films, and the other side exposes the substrate surface. The etch buffer layer 110 is used to reduce the influence of the film height difference on both sides of the mask sidewalls on the etching of the sidewall films and the pseudo sidewalls, so as to avoid the problem of inconsistent etching depth, which is beneficial to preventing damage to the film layers below the etch buffer layer 110, and correspondingly improving the process effect of subsequent patterning of the target layer 100. Moreover, the pattern of the mask sidewalls can also be transferred to the pseudo sidewalls, the sidewall films, and the etch buffer layer 110. When there are bottom foot defects or low sidewall perpendicularity at the bottom of the pseudo sidewalls, it is beneficial to etch and remove the bottom defects of the pseudo sidewalls to prevent the pattern defects of the pseudo sidewalls from having an adverse effect on the patterning of the target layer 100, making the sidewall perpendicularity of the etched pseudo sidewalls, sidewall films, and etch buffer layer 110 relatively high, thereby improving the pattern transfer accuracy.

[0035] In this embodiment, the etch selectivity between the etch buffer layer 110 and the pseudo sidewalls is from 1:2 to 2:1, and the etching properties of the etch buffer layer 110 and the pseudo sidewalls are similar, so as to ensure that in a subsequent step, the sidewall films, the pseudo sidewalls, and the etch buffer layer 110 can be etched using the mask sidewalls as masks, which is beneficial to reducing the difficulty of etching the sidewall films, the pseudo sidewalls, and the etch buffer layer 110 using the mask sidewalls as masks, and correspondingly improving the sidewall perpendicularity at the bottom of the pseudo sidewalls.

[0036] As an example, the etch selectivity between the etch buffer layer 110 and the pseudo sidewalls is 1:1.1.

[0037] According to the material of the subsequent pseudo sidewalls, the material of the etch buffer layer 110 includes silicon oxide, silicon, silicon carbide, silicon oxynitride, silicon carbonitride, or silicon carbon oxynitride. In this embodiment, the material of the etch buffer layer 110 is silicon oxide.

[0038] It should be noted that the thickness of the etching buffer layer 110 should not be too small or too large. If the thickness of the etching buffer layer 110 is too small, it is likely that the effect of the etching buffer layer 110 in reducing the height difference of the film layers on both sides of the mask sidewall on etching the sidewall film and the pseudo-sidewall is not obvious; if the thickness of the etching buffer layer 110 is too large, the time required for subsequent etching of the pseudo-sidewall, the sidewall film, and the etching buffer layer 110 using the mask sidewall as a mask is too long, which is likely to increase the additional process time. Therefore, in this embodiment, along the direction perpendicular to the substrate surface, the thickness of the sidewall film is the reference thickness, and the thickness of the etching buffer layer 110 is 3 to 8 times the reference thickness.

[0039] In this embodiment, the etching buffer layer 110 is formed by a deposition process. The deposition process can be an atomic layer deposition process, a chemical vapor deposition process, etc.

[0040] Continue to refer to Figure 5 , and discrete core layers 120 are formed on the target layer 100.

[0041] The core layer 120 is used to provide a supporting role for the subsequent formation of the pseudo-sidewall. Specifically, the core layer 120 is discrete on the etching buffer layer 110.

[0042] Subsequently, the core layer 120 will also be removed. Therefore, the core layer 120 is made of a material that is easy to remove, and the material of the core layer 120 has an etching selectivity with respect to the materials of the etching buffer layer 110, and the subsequent pseudo-sidewall and the mask sidewall, which is conducive to reducing the damage to other film layers during the process of removing the core layer 120 and reducing the difficulty of removing the core layer 120. The material of the core layer 120 includes one or more of amorphous silicon, silicon nitride, silicon oxide, and amorphous carbon. In this embodiment, the material of the core layer 120 is amorphous silicon.

[0043] The core layer 120 can be formed by a process combining deposition and etching, and the core layer 120 can also be formed by a patterning process such as SAQP or SADP, so that the core layers 120 have a smaller pitch and size.

[0044] Refer to Figure 6 , and a pseudo-sidewall 130 is formed on the sidewall of the core layer 120.

[0045] The portion of the pseudo-sidewall 130 near the top is used to occupy a spatial position for the subsequent formation of the mask sidewall.

[0046] Specifically, the pseudo-sidewall 130 is formed on the etching buffer layer 110.

[0047] In this embodiment, the dummy sidewall 130 is made of a material with etching properties similar to those of the etching buffer layer 110. Specifically, the etching selectivity ratio between the etching buffer layer 110 and the dummy sidewall 130 is from 1:2 to 2:1. Moreover, the material of the dummy sidewall 130 also has etching selectivity with respect to the material of the core layer 120. The material of the dummy sidewall 130 includes materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon, aluminum oxide, titanium nitride, or titanium oxide.

[0048] In this embodiment, the material of the dummy sidewall 130 is the same as that of the etching buffer layer 110, which is beneficial to further reducing the process difficulty of etching the dummy sidewall 130, the sidewall film, and the etching buffer layer 110 using the mask sidewall as a mask in the same subsequent step, and improving process compatibility.

[0049] In this embodiment, in the step of forming the dummy sidewall 130, the height of the dummy sidewall 130 is the overall height H1.

[0050] In this embodiment, the step of forming the dummy sidewall 130 includes: forming a conformal sidewall film 125 covering the core layer 120 and the target layer 100, and the sidewall film 125 located on the sidewall of the core layer 120 is used as the dummy sidewall 130.

[0051] In this embodiment, the sidewall film 125 is formed by atomic layer deposition. The atomic layer deposition process has high step coverage ability, thereby improving the coverage ability of the sidewall film 125 on the top surface and sidewalls of the core layer 120, as well as on the etching buffer layer 110. Correspondingly, it is beneficial to improve the thickness uniformity of the sidewall film 125, and at the same time, it is also beneficial to improve the sidewall perpendicularity of the dummy sidewall 130.

[0052] In this embodiment, the method for forming the semiconductor structure further includes: removing the sidewall film 125 located on the top surface of the core layer 120, so as to expose the top of the core layer 120 for subsequent removal of the core layer 120, and at the same time, it can also expose the top surface of the dummy sidewall 130 located on the sidewall of the core layer 120, so as to facilitate subsequent removal of a part of the height of the dummy sidewall 130 through the exposed top surface of the dummy sidewall 130.

[0053] Reference Figures 7 to 9 , a filling layer 140 is formed on the exposed target layer 100 of the core layer 120 and the dummy sidewall 130.

[0054] Subsequently, a part of the height of the dummy sidewall 130 is removed, and the remaining dummy sidewall 130, the filling layer 140, and the core layer 120 enclose a trench. The filling layer 140 is used to provide support for forming a mask sidewall in the trench subsequently.

[0055] Subsequently, the filling layer 140 will also be removed. Therefore, the filling layer 140 is made of a material that is easy to remove. The material of the filling layer 140 includes one or more of amorphous silicon, silicon nitride, silicon oxide, and amorphous carbon. In this embodiment, the material of the filling layer 140 is the same as that of the core layer 120, and the material of the filling layer 140 is amorphous silicon, which not only helps to avoid introducing new material types to improve process compatibility and reduce process risks, but also enables the removal of the core layer and the filling layer in the same step after the formation of the mask sidewall, which is beneficial to simplifying the process steps.

[0056] The method for forming the semiconductor structure further includes: removing the sidewall film 125 on the top surface of the core layer 120, thereby exposing the top of the core layer 120 to facilitate the subsequent removal of the core layer 120. In this embodiment, in the step of forming the filling layer 140, removing the sidewall film 125 on the top surface of the core layer 120 is beneficial to integrating the formation of the filling layer 140 with the removal of the sidewall film 125 on the top surface of the core layer 120, thereby simplifying the process and improving process compatibility.

[0057] In this embodiment, the step of forming the filling layer 140 includes: as Figure 7 shown, forming a filling material layer 135 covering the sidewall film 125; as Figure 8 shown, using the sidewall film 125 on the top surface of the core layer 120 as the stop position, planarizing the filling material layer 135; as Figure 9 shown, after planarizing the filling material layer 135, removing the filling material layer 135 higher than the top surface of the core layer 120 to form the filling layer 140. Among them, in the step of removing the filling material layer 135 higher than the top surface of the core layer 120, the sidewall film 125 on the top surface of the core layer 120 is removed.

[0058] In this embodiment, the process for forming the filling material layer 135 includes one or more of spin coating process, chemical vapor deposition process, and atomic layer deposition process. As an example, a chemical vapor deposition (CVD) process is used to form the filling material layer 135. The chemical vapor deposition process has high filling ability, which is beneficial to improving the filling quality of the filling material layer 135 between the sidewalls 130, reducing the probability of defects in the filling material layer 135, and the cost of the chemical vapor deposition process is low.

[0059] In this embodiment, taking the sidewall film 125 on the top surface of the core layer 120 as the stop position, the filling material layer 135 is planarized, which is beneficial to reducing the difficulty of planarizing the filling material layer 135, and further beneficial to improving the flatness of the top surface of the planarized filling material layer 135. Specifically, the process of planarizing the filling material layer 135 includes a chemical mechanical polishing process.

[0060] In this embodiment, an etching process is used to remove the filling material layer 135 above the top surface of the core layer 120 and the sidewall film 125 on the top surface of the core layer 120. Specifically, the etching process can be a dry etching process. The dry etching process has high etching accuracy and etching efficiency.

[0061] In other embodiments, it is also possible to remove the sidewall film on the top surface of the core layer and the target layer after forming the pseudo sidewall and before forming the filling layer. Correspondingly, an anisotropic etching process is used to remove the sidewall film on the top surface of the core layer and the target layer. Specifically, the anisotropic etching process can be an anisotropic dry etching process.

[0062] Correspondingly, in this embodiment, the steps of forming the filling layer include: forming a filling material layer covering the core layer and the pseudo sidewall on the substrate; planarizing the filling material layer with the top surface of the pseudo sidewall as the stop position to form the filling layer.

[0063] Reference Figure 10 , a part of the height of the pseudo sidewall 130 is removed, and the remaining pseudo sidewall 130, the filling layer 140 and the core layer 120 enclose a trench 300.

[0064] The trench 300 is used to provide a spatial position for forming a mask sidewall subsequently.

[0065] After removing a part of the height of the pseudo sidewall 130, the remaining pseudo sidewall 130 at the bottom of the trench 300 serves to support the subsequent mask sidewall, so that after the subsequent removal of the filling layer 140 and the core layer 120, the mask sidewall on the remaining pseudo sidewall 130 is not prone to collapse or tilt.

[0066] In the step of forming the dummy sidewall 130, the sidewall of the dummy sidewall 130 has a certain inclination. There is an easy problem of bottom footing at the bottom of the dummy sidewall 130. The closer to the bottom of the dummy sidewall 130, the larger the lateral dimension of the dummy sidewall 130, and the greater the deviation between the lateral dimension of the dummy sidewall 130 and the design dimension. By removing a part of the height of the dummy sidewall 130, after forming a mask sidewall in the trench 300, the lateral dimension of the mask sidewall is smaller than that of the dummy sidewall 130, correspondingly reducing the deviation between the mask sidewall and the design dimension. Further, after patterning the target layer 100 to form a target pattern subsequently, the deviation between the target pattern and the design dimension is smaller. Therefore, this embodiment is beneficial to reducing the influence of the sidewall inclination angle of the dummy sidewall 130 on the critical dimension of the target pattern, beneficial to improving the accuracy and quality of pattern transfer, further improving the pattern accuracy (e.g., critical dimension accuracy) and topography quality of the target pattern, and also beneficial to improving the problem of pitch walking.

[0067] Therefore, in the step of removing a part of the height of the dummy sidewall 130, the remaining height H2 of the dummy sidewall 130 should not be too small or too large. The closer to the bottom of the dummy sidewall 130, the greater the deviation between the lateral dimension of the dummy sidewall 130 and the design dimension. If the remaining height H2 of the dummy sidewall 130 is too small, the removed height of the dummy sidewall 130 is too large, which easily results in an insignificant reduction effect of the lateral dimension of the trench 300 compared with the lateral dimension of the dummy sidewall 130. Further, it is easy to result in an insignificant effect on reducing the deviation between the lateral dimension of the mask sidewall and the design dimension. Moreover, it is easy to cause the subsequent mask sidewall to be too high, and after removing the filling layer 140 and the core layer 120, it is easy to increase the risk of the mask sidewall tilting or collapsing; if the remaining height H2 of the dummy sidewall 130 is too large, the removed height of the dummy sidewall 130 is too small, and the depth of the trench 300 is correspondingly too small, which easily causes the subsequent mask sidewall to be too low, and further causes the mask sidewall to be easily removed during the subsequent patterning of the target layer 100, correspondingly reducing the effect of patterning the target layer 100 with the mask sidewall as a mask. For this reason, in this embodiment, in the step of removing a part of the height of the dummy sidewall 130, 50% to 75% of the height of the dummy sidewall 130 is removed. That is to say, the remaining height H2 of the dummy sidewall 130 is 25% to 50% of the overall height H1. For example, the remaining height H2 of the dummy sidewall 130 is one-third of the overall height H1.

[0068] In this embodiment, during the process of removing a part of the height of the dummy sidewall 130, since there is an etching selectivity between the dummy sidewall 130 and the core layer 120 or the filling layer 140, therefore, in the direction parallel to the substrate and perpendicular to the sidewall of the dummy sidewall 130, the core layer 120 and the filling layer 140 can define the stopping position of etching, which is beneficial to reducing the process difficulty of removing a part of the height of the dummy sidewall 130, so that this embodiment can flexibly select the process of etching the dummy sidewall 130.

[0069] Specifically, in this embodiment, in the step of removing a part of the height of the dummy sidewall 130, the etching selectivity between the dummy sidewall 130 and the core layer 120 or the filling layer 140 is at least 50:1, so that the process of removing a part of the height of the dummy sidewall 130 is not likely to cause mis-etching of the core layer 120 or the filling layer 140, thereby preventing the opening size of the trench 300 from being enlarged, correspondingly ensuring that the deviation between the critical dimension of the subsequent mask sidewall and the designed dimension is small, and also being beneficial to ensuring the profile quality of the trench 300.

[0070] In this embodiment, the process of removing a part of the height of the dummy sidewall 130 is an isotropic etching process. In the direction perpendicular to the sidewall of the core layer 120, the thickness of the dummy sidewall 130 is highly consistent, and the top area of the dummy sidewall 130 exposed in each region is highly consistent. Therefore, during the process of etching the dummy sidewall 130 by using the isotropic etching process, the removal height of the dummy sidewall 130 is also highly consistent, and using the isotropic etching process is also beneficial to reducing the damage to other film layers. For example, it reduces the probability of mis-etching the core layer 120 or the filling layer 140, so as to avoid enlarging the opening size of the trench 300, and correspondingly ensures that the deviation between the opening size of the trench 300 and the designed dimension is small. Specifically, the isotropic etching process includes one or two processes of dry etching and wet etching. As an example, the material of the dummy sidewall 130 is silicon oxide, and the wet etching process is used to remove a part of the height of the dummy sidewall 130, and the etching solution of the wet etching process is a hydrofluoric acid solution.

[0071] Reference Figures 11 to 12 , a mask sidewall 150 is filled in the trench 300.

[0072] The mask sidewall 150 is used as a mask for the subsequent patterned target layer 100.

[0073] As can be seen from the foregoing, the deviation between the opening size and the design size of the trench 300 is small. Correspondingly, after the mask sidewall 150 is formed in the trench 300, compared with the lateral dimension of the dummy sidewall 130, the deviation between the lateral dimension of the mask sidewall 150 and the design size is smaller. Therefore, during the process of patterning the target layer 100 with the mask sidewall 150 as the mask, it is beneficial to improve the accuracy of pattern transfer, reduce the deviation between the critical dimension of the target pattern and the design size, thereby improving the pattern accuracy (e.g., critical dimension accuracy) and topography quality of the target pattern, and also beneficial to improving the problem of pitch walking. Correspondingly, it is beneficial to increase the process window of subsequent processes, improve the yield of the process, and the performance of the semiconductor structure.

[0074] In this embodiment, the material of the mask sidewall 150 is different from any one of the materials of the dummy sidewall 130, the filling layer 140, and the core layer 120, so as to ensure that the mask sidewall 150 has an etching selectivity with respect to any one of the dummy sidewall 130, the filling layer 140, and the core layer 120. Furthermore, it is ensured that the probability of incorrect etching of the mask sidewall 150 during the subsequent process of removing the filling layer 140 and the core layer 120 is low, and the mask effect of using the mask sidewall 150 for patterning the target layer 100 is ensured.

[0075] The material of the mask sidewall 150 includes one or more of silicon nitride, silicon oxide, titanium nitride, titanium oxide, and titanium. As an example, the material of the mask sidewall 150 is silicon nitride.

[0076] In this embodiment, the step of forming the mask sidewall 150 includes: as Figure 11 shown, filling the mask sidewall material 145 in the trench 300, and the mask sidewall material 145 also covers the top surfaces of the filling layer 140 and the core layer 120; as Figure 12 shown, removing the mask sidewall material 145 that is higher than the top surfaces of the filling layer 140 and the core layer 120 to form the mask sidewall 150.

[0077] In this embodiment, the process of forming the mask sidewall material 145 includes an atomic layer deposition process. The atomic layer deposition process has a high gap filling ability, so it is easy to fill the trench 300 with the mask sidewall material 145. Moreover, the film layer formed by the atomic layer deposition process has the characteristic of high density, which is beneficial to improving the density of the mask sidewall, and correspondingly improving the pattern transfer effect of subsequent patterning the target layer 100 with the mask sidewall as the mask.

[0078] In this embodiment, an etching process is used to remove the mask sidewall material 145 that is higher than the top surfaces of the filling layer 140 and the core layer 120; the etching process includes a dry etching process. The dry etching process has high etching accuracy and etching efficiency.

[0079] In this embodiment, after the mask sidewall 150 is formed, the dummy sidewall 130 and the mask sidewall 150 located on the dummy sidewall 130 form a sidewall structure layer 200, and the sidewall structure layer 200 is located on the sidewall of the core layer 120.

[0080] Reference Figure 13 , after the mask sidewall 150 is formed, the core layer 120 and the filling layer 140 are removed.

[0081] Removing the core layer 120 and the filling layer 140 facilitates etching the dummy sidewall 130 with the mask sidewall 150 as a mask, and subsequently patterning the target layer 100 with the mask sidewall 150 as a mask.

[0082] In this embodiment, the process for removing the core layer 120 and the filling layer 140 includes one or both of a dry etching process and a wet etching process.

[0083] After the filling layer 140 and the core layer 120 are removed, one side of the mask sidewall 150 exposes the sidewall film 125, and the other side exposes the substrate surface.

[0084] Continuing to refer to Figure 13 , in this embodiment, before patterning the target layer 100, the forming method further includes: etching the dummy sidewall 130 with the mask sidewall 150 as a mask.

[0085] As can be seen from the foregoing, compared with the lateral dimension of the dummy sidewall 130, the deviation between the lateral dimension of the mask sidewall 150 and the design dimension is smaller. Therefore, by etching the dummy sidewall 130 with the mask sidewall 150 as a mask, it is beneficial to reduce the difference between the lateral dimension of the remaining dummy sidewall 130 and the design dimension, and it is also beneficial to prevent the bottom defects of the remaining dummy sidewall 130 from affecting the patterning of the target layer 100, thereby being beneficial to improving the pattern transfer accuracy of patterning the target layer 100 with the mask sidewall 150 as a mask.

[0086] In this embodiment, using the mask sidewall 150 as a mask, the dummy sidewall 130, the sidewall film 125, and the etch buffer layer 110 are etched. The etch buffer layer 110 can reduce the influence of the film height difference on both sides of the mask sidewall 150 on the etching of the sidewall film 125 and the dummy sidewall 130, so as to avoid the problem of inconsistent etching depth, which is beneficial to preventing damage to the film layer below the etch buffer layer 110, and correspondingly improving the process effect of the subsequent patterned target layer 100. Moreover, it can also transfer the pattern of the mask sidewall 150 to the dummy sidewall 130, the sidewall film 125, and the etch buffer layer 110, which is beneficial to etching and removing the bottom defects of the dummy sidewall 130 to prevent the pattern defects of the dummy sidewall 130 from having an adverse impact on the patterned target layer 100.

[0087] In this embodiment, an anisotropic dry etching process is used. Using the mask sidewall 150 as a mask, the dummy sidewall 130, the sidewall film 125, and the etch buffer layer 110 are etched. The anisotropic dry etching process has anisotropic etching characteristics, which is not only beneficial to improving the etching accuracy and pattern transfer accuracy, but also beneficial to reducing the probability of lateral misetching of the dummy sidewall 130 below the mask sidewall 150, thereby ensuring the support of the dummy sidewall 130 for the mask sidewall 150, and further improving the process stability of the subsequent patterned target layer 100.

[0088] Combined with reference Figure 14 , in this embodiment, the substrate further includes a dicing area (not labeled), and the method for forming the semiconductor structure further includes: after etching the dummy sidewall 130 using the mask sidewall 150 as a mask and before patterning the target layer 100, removing the mask sidewall 150 located in the dicing area.

[0089] Removing the mask sidewall 150 located in the dicing area, so that in the subsequent process of patterning the target layer 100 using the mask sidewall 150 as a mask, no pseudo-target patterns (such as pseudo-fins, etc.) will be formed. Correspondingly, there is no need to perform the step of removing the pseudo-target patterns subsequently. Moreover, removing the mask sidewall 150 located in the dicing area correspondingly makes the remaining mask sidewalls 150 have different spacings. When forming the target patterns, the target patterns also have different spacings, thereby making the spacing between the target patterns meet the design requirements.

[0090] Reference Figure 15 , using the mask sidewall 150 as a mask, pattern the target layer 100 to form target patterns.

[0091] As described above, compared with the lateral dimension of the pseudo sidewall 130, the deviation between the lateral dimension of the mask sidewall 150 and the design dimension is smaller, and the pattern accuracy of the mask sidewall 150 is high. Therefore, during the process of patterning the target layer 100 with the mask sidewall 150 as the mask pattern, it is beneficial to improve the accuracy of pattern transfer, reduce the deviation between the critical dimension of the target pattern and the design dimension, correspondingly improve the patterning effect of the target layer 100, and further improve the pattern accuracy (e.g., critical dimension accuracy) and topography quality of the target pattern. It is also beneficial to improve the problem of pitch swing, correspondingly beneficial to increase the process window of subsequent processes, improve the process yield, and the performance of the semiconductor structure.

[0092] In this embodiment, the target layer 100 is an initial substrate. Therefore, the initial substrate is patterned with the mask sidewall 150 as the mask to form the substrate 180 and the fin portion 170 protruding from the substrate 180. Correspondingly, the target pattern is the fin portion 170. The fin portion 170 is used to form a fin field-effect transistor (FinFET). The pattern quality and dimensional accuracy of the fin portion 170 formed in this embodiment are high, which is beneficial to improving the performance of the FinFET.

[0093] In other embodiments, the target pattern may also be a gate structure, an interconnect trench in the back-end process, a channel stack or a hard mask layer in a fully-depleted surround gate transistor, etc. When the target pattern is other patterns, this embodiment is also beneficial to improving the pattern quality and dimensional accuracy of the target pattern, and correspondingly can also improve the performance of the device.

[0094] In this embodiment, before patterning the target layer 100, the hard mask material layer 102 and the adhesion layer 101 are patterned in sequence with the mask sidewall 150 as the mask, and the remaining hard mask material layer 102 is used as the hard mask layer 160. Therefore, even if the mask sidewall 150 is damaged during the process of patterning the target layer 100, the hard mask layer 160 can continue to be used as the mask for patterning the target layer 100, which is beneficial to improving the accuracy and stability of pattern transfer.

[0095] Correspondingly, the present invention also provides a semiconductor structure. Refer to Figure 12 , which shows a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.

[0096] The semiconductor structure includes: a substrate including a target layer 100 for forming a target pattern; a core layer 120 separated from the target layer 100; a sidewall structure layer 200 located on the sidewalls of the core layer 120, the sidewall structure layer 200 including a pseudo sidewall 130 and a mask sidewall 150 located on the pseudo sidewall 130, wherein the mask sidewall 150 is used as a mask for patterning the target layer 100; and a filling layer 140 located on the target layer 100 exposed by the core layer 120 and the sidewall structure layer 200.

[0097] The sidewall structure layer 200 includes a pseudo-sidewall 130 and a mask sidewall 150 located on the pseudo-sidewall 130. The mask sidewall 150 is used as a mask for the patterned core layer 120. The mask sidewall 150 is located on the pseudo-sidewall 130. The sidewall of the sidewall structure layer 200 has a certain inclination. The closer to the bottom of the sidewall structure layer 200, the larger the lateral dimension of the sidewall structure layer 200, and the larger the deviation between the lateral dimension of the sidewall structure layer 200 and the design dimension. The closer to the top of the sidewall structure layer 200, the smaller the deviation between the lateral dimension of the sidewall structure layer 200 and the design dimension. Therefore, compared with the lateral dimension of the pseudo-sidewall 130, the deviation between the lateral dimension of the mask sidewall 150 and the design dimension is smaller and the pattern accuracy is higher. In the process of patterning the target layer 100 with the mask sidewall 150 as a mask, it is beneficial to improve the accuracy of pattern transfer, reduce the deviation between the critical dimension of the target pattern and the design dimension, correspondingly improve the patterning effect of the patterned target layer 100, and further improve the pattern accuracy (e.g., critical dimension accuracy) and topography quality of the target pattern. It is also beneficial to improve the problem of pitch walking, correspondingly beneficial to increase the process window of subsequent processes, improve the process yield, and the performance of semiconductor structures.

[0098] The substrate is used to provide a platform for the process.

[0099] The target layer 100 is a film layer to be patterned to form a target pattern.

[0100] In this embodiment, the target layer 100 is an initial substrate. Subsequently, the initial substrate is patterned to form a substrate and fins protruding from the substrate. Correspondingly, the target pattern is the fins. The fins are used to form fin field-effect transistors (FinFETs).

[0101] In this embodiment, the material of the initial substrate is silicon. In some other embodiments, the material of the initial substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the initial substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. In still some other embodiments, the initial substrate can also include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer. Subsequently, the second semiconductor layer is patterned to form fins, and the first semiconductor layer is retained for use as a substrate.

[0102] In other embodiments, the target pattern may also be a pattern such as a gate structure, an interconnect trench in the back-end process, a channel stack in a gate-all-around (GAA) transistor, or a hard mask (HM) layer. According to the target pattern formed according to actual needs, the material of the target layer may also be other corresponding materials.

[0103] In this embodiment, the substrate further includes an adhesion layer 101 and a hard mask material layer 102 that are sequentially stacked on the target layer 100.

[0104] The adhesion layer 101 is used to improve the adhesion between the hard mask material layer 102 and the target layer 100 and reduce the stress generated between the film layers. In this embodiment, the material of the adhesion layer 101 is silicon oxide.

[0105] Subsequently, the hard mask material layer 102 is patterned using the mask sidewall 150 as a mask pattern to form a hard mask layer. Even if the mask sidewall 150 is damaged during the process of patterning the target layer 100, the target layer 100 can still be patterned using the hard mask layer as a mask subsequently, which is beneficial to improving the process stability of patterning the target layer 100 and correspondingly improving the accuracy of pattern transfer. In addition, the processes of forming the core layer 120, subsequently removing the core layer 120, and filling the filling layer 140 all include etching processes. The hard mask material layer 102 can also define an etch stop position in these etching processes to prevent etching damage to the film layer below it, thereby reducing the probability of the top surface of the film layer to be etched below having a height inconsistency problem and correspondingly improving the etching uniformity of patterning the target layer 100 subsequently.

[0106] The material of the hard mask material layer 102 includes one or more of silicon nitride, titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon oxynitride. In this embodiment, the material of the hard mask material layer 102 is silicon nitride.

[0107] The core layer 120 is used to provide a supporting role for forming the pseudo sidewall 130 and the mask sidewall 150.

[0108] Subsequently, the core layer 120 will be removed. Therefore, the core layer 120 is a material that is easy to remove, and the material of the core layer 120 has an etching selectivity with respect to the pseudo sidewall 130 and the mask sidewall 150, which is beneficial to reducing the damage to other film layers during the process of removing the core layer 120 and reducing the removal difficulty of removing the core layer 120. The material of the core layer 120 includes one or several of amorphous silicon, silicon nitride, silicon oxide, and amorphous carbon. In this embodiment, the material of the core layer 120 is amorphous silicon.

[0109] The sidewall structure layer 200 is composed of a pseudo sidewall 130 and a mask sidewall 150 located on the pseudo sidewall 130.

[0110] The dummy sidewall 130 is not used as a mask for the patterned target layer 100. Subsequently, the dummy sidewall 130 will be etched using the mask sidewall 150 as a mask, which helps prevent the bottom defects and lateral dimensions of the dummy sidewall 130 from having an adverse effect on the patterned target layer 100, thereby improving the accuracy of pattern transfer. Moreover, after the filling layer 140 and the core layer 120 are removed subsequently, the dummy sidewall 130 is located at the bottom of the mask sidewall 150 and also serves to support the mask sidewall 150.

[0111] In this embodiment, the dummy sidewall 130 is made of a material that has an etching selectivity with respect to the materials of the core layer 120, the filling layer 140, and the mask sidewall 150. The material of the dummy sidewall 130 includes materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon, aluminum oxide, titanium nitride, or titanium oxide.

[0112] In this embodiment, the material of the dummy sidewall 130 is silicon oxide.

[0113] The sidewall structure layer 200 is located on the sidewalls of the core layer 120, and the top surface of the sidewall structure layer 200 is flush with the top surface of the core layer 120.

[0114] The height of the dummy sidewall 130 should not be too small or too large. The closer to the bottom of the sidewall structure layer 200, the lower the verticality of the sidewall of the sidewall structure layer 200 and the quality of the cross-sectional morphology. If the height of the dummy sidewall 130 is too small, the height of the mask sidewall 150 is too large, and the mask sidewall 150 is too close to the bottom of the sidewall structure layer 200, which is likely to result in an insignificant reduction effect on the deviation between the lateral dimension of the mask sidewall 150 and the designed dimension. Moreover, when the height of the mask sidewall 150 is too large, after the filling layer 140 and the core layer 120 are removed subsequently, the probability of the mask sidewall 150 tilting or collapsing is likely to increase. If the height of the dummy sidewall 130 is too large, the height of the mask sidewall 150 is correspondingly too small, which may cause the mask sidewall 150 to be easily worn and removed during the subsequent patterning of the target layer 100, and correspondingly, the process effect of the subsequent patterned target layer 100 is likely to be reduced. Therefore, in this embodiment, the height of the dummy sidewall 130 is 25% to 50% of the height of the sidewall structure layer 200. For example, the height of the dummy sidewall 130 is one-third of the height of the sidewall structure layer 200.

[0115] The mask sidewall 150 is used as a mask for the patterned target layer 100. As can be seen from the foregoing, compared with the lateral dimension of the dummy sidewall 130, the deviation between the lateral dimension of the mask sidewall 150 and the design dimension is smaller. During the process of patterning the target layer 100 with the mask sidewall 150 as the mask, it is beneficial to improve the accuracy and quality of pattern transfer, thereby improving the pattern accuracy (e.g., critical dimension accuracy) and topography quality of the target pattern, and is also beneficial to improving the problem of pitchwalking, which correspondingly helps to increase the process window of subsequent processes, improve the process yield, and the performance of the semiconductor structure.

[0116] Therefore, the material of the mask sidewall 150 is different from that of any one of the dummy sidewall 130, the filling layer 140, and the core layer 120, so as to ensure that the mask sidewall 150 has an etching selectivity with respect to any one of the dummy sidewall 130, the filling layer 140, and the core layer 120. Furthermore, it is ensured that the probability of incorrect etching of the mask sidewall 150 during the subsequent process of removing the filling layer 140 and the core layer 120 is low, and the mask effect of the mask sidewall 150 for etching the dummy sidewall 130 and patterning the target layer 100 is ensured.

[0117] The material of the mask sidewall 150 includes one or more of silicon nitride, silicon oxide, titanium nitride, titanium oxide, and titanium. As an example, the material of the mask sidewall 150 is silicon nitride.

[0118] In this embodiment, the semiconductor structure further includes: a sidewall film 125, which is located between the filling layer 140 and the target layer 100 and is connected to the bottom of the dummy sidewall 130.

[0119] The sidewall film 125 is retained in the semiconductor structure because during the formation process of the semiconductor structure, in the step of forming the filling layer 140, the sidewall film 125 located on the top surface of the core layer 120 is removed. Therefore, the sidewall film 125 located on the target layer 100 is covered by the filling layer 140 and thus retained in the semiconductor structure.

[0120] In this embodiment, the sidewall film 125 and the dummy sidewall 130 are of an integral structure, and the material of the sidewall film 125 is the same as that of the dummy sidewall 130.

[0121] The filling layer 140 is used to provide a supporting role during the process of forming the mask sidewall 150.

[0122] Subsequently, the filling layer 140 will be removed. Therefore, the filling layer 140 is made of a material that is easy to be removed. The material of the filling layer 140 includes one or more of amorphous silicon, silicon nitride, silicon oxide, and amorphous carbon. In this embodiment, the material of the filling layer 140 is the same as that of the core layer 120, and the material of the filling layer 140 is amorphous silicon, which not only helps to avoid introducing new material types to improve process compatibility and reduce process risks, but also enables the removal of the core layer and the filling layer in the same step after the formation of the mask sidewall, which is beneficial to simplifying the process steps.

[0123] In this embodiment, the filling layer 140 is located on the sidewall film 125.

[0124] In this embodiment, the semiconductor structure further includes: an etching buffer layer 110, which is located between the core layer 120 and the target layer 100, between the sidewall structure layer 200 and the target layer 100, and between the sidewall film 125 and the target layer 100.

[0125] The sidewall film 125 is located on the etching buffer layer 110. Thus, before the subsequent patterning of the target layer 100, the sidewall film 125, the etching buffer layer 110, and the dummy sidewall 130 can be etched using the mask sidewall 150 as a mask; after removing the filling layer 140 and the core layer 120, one side of the mask sidewall 150 exposes the sidewall film 120, and the other side exposes the substrate surface. The etching buffer layer 110 is used to reduce the influence of the film height difference on both sides of the mask sidewall 150 on the etching of the sidewall film 125 and the dummy sidewall 130, so as to avoid the problem of inconsistent etching depth, which is beneficial to preventing damage to the film layer located below the etching buffer layer 110, and correspondingly improving the process effect of the subsequent patterning of the target layer 100. Moreover, it can also transfer the pattern of the mask sidewall 150 to the dummy sidewall 130, the sidewall film 125, and the etching buffer layer 110. When there are bottom foot defects or low sidewall perpendicularity at the bottom of the dummy sidewall 130, it is beneficial to etch and remove the bottom defects of the dummy sidewall 130 to prevent the pattern defects of the dummy sidewall 130 from having an adverse impact on the patterning of the target layer 100, making the sidewall perpendicularity of the etched dummy sidewall 130, sidewall film 125, and etching buffer layer 110 relatively high, thereby improving the pattern transfer accuracy.

[0126] In this embodiment, the etching selectivity between the etching buffer layer 110 and the dummy sidewall is 1:2 to 2:1. The etching properties of the etching buffer layer 110 and the dummy sidewall 130 are similar, so as to ensure that in a subsequent step, with the mask sidewall 150 as a mask, the sidewall film 125, the dummy sidewall, and the etching buffer layer 110 can be etched, which is beneficial to reducing the difficulty of etching the sidewall film 125, the dummy sidewall 130, and the etching buffer layer 110 with the mask sidewall 150 as a mask, and correspondingly improving the sidewall perpendicularity at the bottom of the dummy sidewall 130.

[0127] As an example, the etching selectivity between the etching buffer layer 110 and the dummy sidewall 130 is 1:1.1. In this embodiment, a material with etching properties similar to those of the dummy sidewall 130 is selected for the etching buffer layer 110. Moreover, the material of the etching buffer layer 110 also has etching selectivity with respect to the material of the core layer 120 or the filling layer 140. The material of the etching buffer layer 110 includes silicon oxide, silicon, silicon carbide, silicon oxynitride, silicon carbonitride, or silicon carbon oxynitride.

[0128] In this embodiment, the materials of the etching buffer layer 110 and the dummy sidewall 130 are the same, and the material of the etching buffer layer 110 is silicon oxide, which is beneficial to further reducing the process difficulty of etching the dummy sidewall 130, the sidewall film 125, and the etching buffer layer 110 with the mask sidewall 150 as a mask in a subsequent step and improving process compatibility.

[0129] It should be noted that the thickness of the etching buffer layer 110 should not be too small or too large. If the thickness of the etching buffer layer 110 is too small, it is likely that the effect of the etching buffer layer 110 in reducing the influence of the film height difference on both sides of the mask sidewall 150 on the etching of the sidewall film 125 and the dummy sidewall is not obvious; if the thickness of the etching buffer layer 110 is too large, the time required for etching the dummy sidewall 130, the sidewall film 125, and the etching buffer layer 110 with the mask sidewall 150 as a mask in the subsequent step is too long, which is likely to increase the additional process time. For this reason, in this embodiment, along the direction perpendicular to the substrate surface, the thickness of the sidewall film 125 is the reference thickness, and the thickness of the etching buffer layer 110 is 3 to 8 times the reference thickness.

[0130] The semiconductor structure can be formed by the formation method described in the foregoing embodiment or by other formation methods. For a specific description of the semiconductor structure in this embodiment, reference can be made to the corresponding description in the foregoing embodiment, and details are not repeated herein.

[0131] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate including a target layer for forming a target pattern; Forming discrete core layers on the target layer; Forming pseudo sidewalls on the sidewalls of the core layers; Forming a filling layer on the target layer exposed by the core layers and the pseudo sidewalls; Removing a part of the height of the pseudo sidewalls, and the remaining pseudo sidewalls, the filling layer and the core layers enclose a trench; Filling a mask sidewall in the trench; After forming the mask sidewall, removing the core layers and the filling layer; Using the mask sidewall as a mask to pattern the target layer to form a target pattern.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The step of forming the mask sidewall includes: filling a mask sidewall material in the trench, and the mask sidewall material also covers the top surfaces of the filling layer and the core layers; Removing the mask sidewall material higher than the top surfaces of the filling layer and the core layers to form the mask sidewall.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The process of forming the mask sidewall material includes an atomic layer deposition process.

4. The method for forming a semiconductor structure according to claim 2, characterized in that, Adopting an etching process to remove the mask sidewall material higher than the top surfaces of the filling layer and the core layers; the etching process includes a dry etching process.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, In the step of removing a part of the height of the pseudo sidewalls, removing 50% to 75% of the height of the pseudo sidewalls.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, The process of removing a part of the height of the pseudo sidewalls includes one or both of a dry etching process and a wet etching process.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, The etching selectivity between the pseudo sidewalls and the filling layer is at least 50:1; The etching selectivity between the pseudo sidewalls and the core layers is at least 50:

1.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, The step of forming the pseudo sidewalls includes: forming a conformal sidewall film covering the core layers and the target layer, and the sidewall film on the sidewalls of the core layers is used as the pseudo sidewalls; The step of forming the filling layer includes: forming a filling material layer covering the sidewall film; using the top of the sidewall film on the top surface of the core layer as a stop position to planarize the filling material layer; after planarizing the filling material layer, removing the filling material layer higher than the top surface of the core layer to form the filling layer; The method for forming the semiconductor structure further includes: in the step of removing the filling material layer higher than the top surface of the core layer, removing the sidewall film on the top surface of the core layer; Using the mask sidewall as a mask to etch the pseudo sidewalls and the sidewall film.

9. The method for forming a semiconductor structure according to claim 8, characterized in that, After providing the substrate and before forming the core layers, the method for forming the semiconductor structure further includes: forming an etching buffer layer on the target layer; The sidewall film is formed on the etching buffer layer; The method for forming the semiconductor structure further includes: before patterning the target layer using the mask sidewall as a mask, etching the sidewall film, the etching buffer layer and the pseudo sidewalls using the mask sidewall as a mask.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The etching selectivity between the etching buffer layer and the pseudo sidewalls is 1:2 to 2:

1.

11. The method for forming a semiconductor structure according to claim 9, characterized in that, The material of the pseudo sidewalls is the same as the material of the etching buffer layer.

12. The method for forming a semiconductor structure as claimed in claim 9, wherein, In the step of forming the sidewall film, along the direction perpendicular to the surface of the substrate, the thickness of the sidewall film is a reference thickness; in the step of forming the etching buffer layer, the thickness of the etching buffer layer is 3 to 8 times the reference thickness.

13. The method for forming a semiconductor structure as claimed in claim 1, wherein, The steps of forming the pseudo sidewall include: forming a conformal sidewall film covering the core layer and the target layer, and the sidewall film on the sidewall of the core layer is used as the pseudo sidewall; The method for forming the semiconductor structure further includes: after forming the pseudo sidewall and before forming the filling layer, removing the sidewall film on the top surface of the core layer and the target layer; The steps of forming the filling layer include: forming a filling material layer covering the core layer and the pseudo sidewall on the substrate; planarizing the filling material layer with the top surface of the pseudo sidewall as the stop position to form the filling layer.

14. The method for forming a semiconductor structure as claimed in claim 1, wherein, The material of the mask sidewall includes one or more of silicon nitride, silicon oxide, titanium nitride, titanium oxide, and titanium.

15. A semiconductor structure, wherein, Including: A substrate, including a target layer for forming a target pattern; A core layer, separated on the target layer; A sidewall structure layer, located on the sidewall of the core layer, the sidewall structure layer includes a pseudo sidewall and a mask sidewall on the pseudo sidewall, wherein the mask sidewall is used as a mask for patterning the target layer; A filling layer, located on the target layer exposed by the core layer and the sidewall structure layer, and the material of the filling layer is the same as that of the core layer.

16. The semiconductor structure as claimed in claim 15, wherein, The height of the pseudo sidewall is 25% to 50% of the height of the sidewall structure layer.

17. The semiconductor structure as claimed in claim 15, wherein, The material of the mask sidewall is different from any one of the materials of the pseudo sidewall, the filling layer, and the core layer.

18. The semiconductor structure as claimed in claim 15, wherein, The material of the mask sidewall includes one or more of silicon nitride, silicon oxide, titanium nitride, titanium oxide, and titanium.

19. The semiconductor structure as claimed in claim 15, wherein, The material of the filling layer includes one or several of amorphous silicon, silicon nitride, silicon oxide, and amorphous carbon.

20. The semiconductor structure as claimed in claim 15, wherein, The semiconductor structure further includes: a sidewall film, located between the filling layer and the target layer and connected to the bottom of the pseudo sidewall; an etch buffer layer, located between the core layer and the target layer, between the sidewall structure layer and the target layer, and between the sidewall film and the target layer.

21. The semiconductor structure as claimed in claim 20, wherein, The etch selectivity between the etch buffer layer and the pseudo sidewall is 1:2 to 2:

1.

22. The semiconductor structure as claimed in claim 20, wherein, The material of the etch buffer layer is the same as that of the pseudo sidewall.

23. The semiconductor structure as claimed in claim 20, wherein, In the direction perpendicular to the surface of the substrate, the thickness of the sidewall film is a reference thickness; in the step of forming the etch buffer layer, the thickness of the etch buffer layer is 3 to 8 times the reference thickness.

24. The semiconductor structure as claimed in claim 20, wherein, The material of the pseudo sidewall includes silicon oxide, silicon nitride, silicon oxynitride, silicon, aluminum oxide, titanium nitride, or titanium oxide; the material of the etch buffer layer includes silicon oxide, silicon, silicon carbide, silicon oxynitride, silicon oxycarbide, or silicon carbonitride.

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