Semiconductor structure and method of forming a semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, the structure comprising: a substrate; a gate structure on the substrate; a sidewall structure on the sidewall of the gate structure; a dielectric layer on the substrate, the dielectric layer on the sidewall of the sidewall structure, and the top surface of the dielectric layer higher than the top surface of the sidewall structure and the top surface of the gate structure, and the top surface of the dielectric layer is a convex arc surface. The performance of the semiconductor structure is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming a semiconductor structure. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. As a result of this growth, the functionality, speed, and capacity of ICs have generally increased while costs have generally decreased. This growth can be attributed to advances in various integrated circuit fabrication processes including metallization, chemical-mechanical polishing, and lithography processes. In the course of IC evolution, functionality density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be fabricated) has generally decreased. This scaling of the components has generally been dictated by Moore's Law, which states that density (i.e., the number of components) doubles approximately every 18 months.

[0003] In some IC designs, as technology nodes shrink, one advantage that is realized is that metal gates are used to replace the typical poly-silicon gates to improve device performance, while the size of the components is reduced. One process to form metal gates is known as a replacement gate or "gate-last" process, in which the metal gate is fabricated "last," which allows for a reduction in the number of subsequent processes, including high temperature processing that must be performed after the gate is formed.

[0004] However, there are still some problems in the process of forming metal gates by the existing "gate-last" process. SUMMARY

[0005] The present application solves the technical problem of providing a semiconductor structure and a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] To solve the above technical problem, the present application provides a semiconductor structure, comprising: a substrate; a gate structure on the substrate; a sidewall structure on the sidewall of the gate structure; a dielectric layer on the substrate, the dielectric layer is on the sidewall of the sidewall structure, and the top surface of the dielectric layer is higher than the top surface of the sidewall structure and the top surface of the gate structure, and the top surface of the dielectric layer is a convex arc surface.

[0007] Optionally, the height of the convex arc surface ranges from 5 nm to 10 nm.

[0008] Optionally, the material of the sidewall structure comprises a dielectric material, and the dielectric material comprises silicon nitride.

[0009] Optionally, the material of the dielectric layer comprises a dielectric material, and the dielectric material comprises silicon oxide.

[0010] Optionally, the substrate comprises a first region and a second region, and the device density of the first region is greater than the device density of the second region.

[0011] Optionally, the interval of the adjacent gate structures on the first area ranges from 1nm to 30nm; the interval of the adjacent gate structures on the second area is greater than 30nm.

[0012] Optionally, the height of the sidewall structure ranges from 20nm to 30nm.

[0013] Optionally, the gate structure comprises a gate dielectric layer and a gate electrode layer on the gate dielectric layer.

[0014] Optionally, the material of the gate dielectric layer comprises silicon oxide; the material of the gate electrode layer comprises silicon.

[0015] Optionally, the gate structure further comprises a work function layer between the gate dielectric layer and the gate electrode layer.

[0016] Optionally, the material of the gate dielectric layer comprises a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, the high dielectric constant material comprises hafnium oxide or aluminum oxide; the material of the gate electrode layer comprises a metal, the metal comprises tungsten; the material of the work function layer comprises an N-type work function material or a P-type work function material, the N-type work function material comprises titanium aluminum, and the P-type work function material comprises titanium nitride or tantalum nitride.

[0017] The technical scheme of the present application further provides a semiconductor structure, comprising: a substrate; a gate structure on the substrate; a sidewall structure on the sidewall of the gate structure; a bottom dielectric layer on the substrate, the bottom dielectric layer is on the sidewall of the sidewall structure, and the top surface of the bottom dielectric layer is flush with the top surface of the gate structure.

[0018] Optionally, the material of the sidewall structure comprises a dielectric material, and the dielectric material comprises silicon nitride.

[0019] Optionally, the material of the bottom dielectric layer comprises a dielectric material, and the dielectric material comprises silicon oxide.

[0020] Optionally, the substrate comprises a first area and a second area, and the device density of the first area is greater than that of the second area.

[0021] Optionally, the interval of the adjacent gate structures on the first area ranges from 1nm to 30nm; the interval of the adjacent gate structures on the second area is greater than 30nm.

[0022] Optionally, the height of the sidewall structure ranges from 20nm to 30nm.

[0023] Optionally, the gate structure comprises a gate dielectric layer and a gate electrode layer on the gate dielectric layer.

[0024] Optionally, the material of the gate dielectric layer comprises silicon oxide; the material of the gate electrode layer comprises silicon.

[0025] Optionally, the gate structure further comprises a work function layer between the gate dielectric layer and the gate layer.

[0026] Optionally, the material of the gate dielectric layer comprises a high dielectric constant material, the high dielectric constant material has a dielectric constant greater than 3.9, the high dielectric constant material comprises hafnium oxide or aluminum oxide; the material of the gate layer comprises a metal, the metal comprises tungsten; the material of the work function layer comprises an N-type work function material or a P-type work function material, the N-type work function material comprises titanium aluminum, and the P-type work function material comprises titanium nitride or tantalum nitride.

[0027] Correspondingly, the present application also provides a forming method of a semiconductor structure, comprising: providing a substrate; forming an initial dummy gate structure and an initial sidewall structure on the sidewall of the initial dummy gate structure on the substrate; forming an initial dielectric layer on the substrate, the initial dielectric layer being on the sidewall of the initial sidewall structure; removing part of the initial dummy gate structure to form a dummy gate structure, the dummy gate structure exposing part of the initial sidewall structure; removing the initial sidewall structure exposed by the dummy gate structure to form a sidewall structure; removing part of the initial dielectric layer exposed by the dummy gate structure to form a dielectric layer, the top surface of the sidewall structure being lower than the top surface of the dielectric layer, and the top surface of the dielectric layer being a convex arc surface; after forming the sidewall structure, removing the dummy gate structure to form a gate opening in the dielectric layer; forming a gate structure in the gate opening, the top surface of the gate structure being lower than or flush with the top surface of the sidewall structure.

[0028] Optionally, the height range of the convex arc surface is 5 nm to 10 nm.

[0029] Optionally, part of the initial dielectric layer is removed to form the dielectric layer while the initial sidewall structure is removed.

[0030] Optionally, the process of removing the initial sidewall structure exposed by the dummy gate structure comprises a dry etching process.

[0031] Optionally, the dry etching process comprises a SiCoNi process, and the gas of the SiCoNi process comprises a mixed gas of nitrogen trifluoride and hydrogen.

[0032] Optionally, the etching rate of the SiCoNi process on the initial sidewall structure is greater than the etching rate on the initial dielectric layer.

[0033] Optionally, the forming method of the gate structure comprises: forming a gate structure material layer in the gate opening and on the dielectric layer; planarizing the gate structure material layer and the dielectric layer until the top surface of the sidewall structure is exposed to form a gate structure and an underlying dielectric layer.

[0034] Optionally, the planarization process of the gate structure material layer and the dielectric layer includes a chemical mechanical polishing process.

[0035] Optionally, the process of removing part of the initial dummy gate structure includes a dry etching process.

[0036] Optionally, the process of removing the dummy gate structure includes a wet etching process.

[0037] Optionally, the material of the initial side wall structure is different from the etching rate of the material of the initial dielectric layer.

[0038] Optionally, the material of the initial side wall structure includes a dielectric material, and the dielectric material includes silicon nitride.

[0039] Optionally, the material of the initial dielectric layer includes a dielectric material, and the dielectric material includes silicon oxide.

[0040] Optionally, the substrate includes a first region and a second region, and the device density of the first region is greater than the device density of the second region.

[0041] Optionally, the distance between adjacent gate structures on the first region ranges from 1 nm to 30 nm, and the distance between adjacent gate structures on the second region is greater than 30 nm.

[0042] Optionally, the height of the initial side wall structure ranges from 80 nm to 100 nm.

[0043] Optionally, the height of the side wall structure ranges from 20 nm to 30 nm.

[0044] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0045] In the semiconductor structure in the technical scheme of the present application, the top surface of the dielectric layer is higher than the top surface of the side wall structure and the top surface of the gate structure, and the top surface of the dielectric layer is a convex arc surface. Therefore, when the gate structure is formed, because the top surface of the side wall structure is lower than the top surface of the dielectric layer, and the top surface of the dielectric layer is a convex arc surface, the process conditions of the planarization process of the gate structure material can be reduced, thereby reducing the difference in etching rate of the side wall structure and the dielectric layer caused by the planarization process of the gate structure material, so that the subsequent formed side wall structure and the underlying dielectric layer have a height difference, and the performance of the formed semiconductor structure is more uniform.

[0046] The method for forming the semiconductor structure in the technical solution removes part of the initial dummy gate structure, removes the initial side wall structure exposed by the dummy gate structure, and removes part of the initial dielectric layer, so that the top surface of the formed side wall structure is lower than the top surface of the dielectric layer, and the height of the side wall structure is the height of the subsequently formed gate structure. Therefore, when the gate structure is subsequently formed in the gate opening, the process conditions of the planarization gate structure material process can be reduced because the top surface of the side wall structure is lower than the top surface of the dielectric layer, so that the difference in etching rate of the side wall structure and the dielectric layer caused by the planarization gate structure material process is reduced, the subsequently formed side wall structure and the bottom dielectric layer have a height difference, and the performance of the formed semiconductor structure is more uniform.

[0047] Further, the process of removing the initial side wall structure includes a SiCoNi process, which can remove part of the initial dielectric layer while removing the initial side wall structure, so that the height of the formed dielectric layer is reduced, the process conditions required by the planarization process in the process of forming the gate structure can be reduced, the polishing effect is uniform when the planarization process stops on the side wall structure, the difference in etching selectivity of the side wall structure and the dielectric layer caused by the large planarization process conditions is reduced, the subsequently formed side wall structure and the bottom dielectric layer have a height difference, and the performance of the formed semiconductor structure is more uniform.

[0048] Further, the process of removing the initial side wall structure includes a SiCoNi process, which can remove part of the initial dielectric layer while removing the initial side wall structure, so that the height of the formed dielectric layer is reduced, the process conditions required by the planarization process in the process of forming the gate structure can be reduced, the polishing effect is uniform when the planarization process stops on the side wall structure, the difference in etching selectivity of the side wall structure and the dielectric layer caused by the large planarization process conditions is reduced, the subsequently formed side wall structure and the bottom dielectric layer have a height difference, and the performance of the formed semiconductor structure is more uniform. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 is a cross-sectional structure schematic diagram of a semiconductor structure in an embodiment;

[0050] Figures 2 to 6 is a cross-sectional structure schematic diagram of a semiconductor structure forming process in an embodiment of the application. DETAILED DESCRIPTION

[0051] As described in the background, the existing "gate last" process for forming a metal gate still has some problems. Now, specific embodiments will be analyzed and described.

[0052] Figure 1Figure 1 is a schematic diagram of a cross-sectional structure of a semiconductor structure in an embodiment.

[0053] Referring to Figure 1 , comprising: a substrate 100, the substrate 100 comprising a first region I and a second region II; a first gate structure 101 on the first region I and a first sidewall 102 on the sidewall of the first gate structure 101; a second gate structure 103 on the second region II and a second sidewall 104 on the sidewall of the second gate structure 103; a dielectric layer 105 on the first region I and the second region II, the dielectric layer 105 on the sidewall of the first gate structure 101 and the sidewall of the second gate structure 103.

[0054] In the semiconductor structure, the device density on the first region I is greater than the device density on the second region II, so that the surface area of the dielectric layer 105 on the first region I is less than the surface area of the dielectric layer 105 on the second region II, and the surface area of the first sidewall 102 on the first region I is greater than the surface area of the second sidewall 104 on the second region II. The material of the first sidewall 102 and the second sidewall 104 is different from the material of the dielectric layer 105, the material of the first sidewall 102 and the second sidewall 104 is generally silicon nitride, and the material of the dielectric layer 105 is generally silicon oxide. The silicon nitride material of the first sidewall 102 and the second sidewall 104 is harder and has a smaller grinding speed.

[0055] The first gate structure 101 and the second gate structure 103 are metal gates. In the process of forming the first gate structure 101 and the second gate structure 103 by using a back gate process, a dummy gate structure (not shown) and an initial dielectric layer (not shown) on the sidewall of the dummy gate structure are first formed on the substrate, then the dummy gate structure is removed to form a gate opening (not shown) in the initial dielectric layer, then a gate structure material layer (not shown) is formed in the gate opening and on the initial dielectric layer, and finally a chemical mechanical polishing process is used to planarize the gate structure material layer until the surface of the initial dielectric layer, the surface of the first sidewall 102 and the surface of the second sidewall 104 are exposed, forming the first gate structure 101, the second gate structure 103 and the dielectric layer 105.

[0056] However, in the process of polishing the gate structure material layer by using the chemical mechanical polishing process, the first side wall 102 and the second side wall 104 are also usually polished to a certain height to reach the required height of the gate structure, and the silicon oxide material of the dielectric layer 105 is relatively easy to be polished, and the silicon nitride material of the first side wall 102 and the second side wall 104 is difficult to be polished, and thus a large polishing amount is required. Since the surface area of the dielectric layer 105 in the first region I is smaller than the surface area of the dielectric layer 105 in the second region II, the contact area of the polishing material of the chemical mechanical polishing process with the dielectric layer 105 in the second region II is larger, and thus the polishing degree of the dielectric layer 105 in the second region II is larger than the polishing degree of the dielectric layer 105 in the first region I under the same chemical mechanical polishing process conditions. Meanwhile, the polishing degree of the first side wall 102 and the second side wall 104 is smaller, so that the surface of the dielectric layer 105 in the second region II has the second groove 108, and the surface of the dielectric layer 105 in the first region I has the first groove 107, and the depth of the first groove 107 is smaller than the depth of the second groove 108, which makes the dielectric layer 105 in the first region I and the dielectric layer 105 in the second region II have a height difference, and the first side wall 102 and the second side wall 104 have a height difference with the dielectric layer 105.

[0057] Therefore, when subsequent back-end-of-line processes are performed on the first region I and the second region II, the dielectric layer 105 in the first region I and the dielectric layer 105 in the second region II have a height difference, and the first side wall 102 and the second side wall 104 have a height difference with the dielectric layer 105, which affects the process accuracy and further affects the performance of the semiconductor structure.

[0058] In order to solve the above problems, the technical scheme of the present application provides a semiconductor structure and a forming method of the semiconductor structure. After part of the initial dummy gate structure is removed, the initial side wall structure exposed by the dummy gate structure is removed, and part of the initial dielectric layer is removed, so that the top surface of the formed side wall structure is lower than the top surface of the dielectric layer, and the height of the side wall structure is the height of the subsequently formed gate structure. Therefore, when the gate structure is subsequently formed in the gate opening, since the top surface of the side wall structure is lower than the top surface of the dielectric layer, the process conditions of the planarization gate structure material process can be reduced, so as to reduce the case that the subsequently formed side wall structure and the bottom dielectric layer have a height difference caused by the different etching rates of the side wall structure and the dielectric layer in the process of planarizing the gate structure material, and the performance of the formed semiconductor structure is more uniform.

[0059] In order to make the above-mentioned objects, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings.

[0060] Figures 2 to 6 is a cross-sectional view of a semiconductor structure formation process in an embodiment of the present application.

[0061] Referring to Figure 2 , a substrate 200 is provided.

[0062] The substrate 200 includes a first region I and a second region II, the device density of the first region I is greater than that of the second region II.

[0063] In the embodiment, the material of the substrate 200 is silicon.

[0064] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0065] Continuously referring to Figure 2 , an initial dummy gate structure 201 and an initial side wall structure 202 on the sidewall of the initial dummy gate structure 201 are formed on the substrate 200.

[0066] The initial dummy gate structure 201 includes a dummy gate dielectric layer (not shown) and a dummy gate electrode layer (not shown) on the dummy gate dielectric layer.

[0067] The forming method of the initial dummy gate structure 201 includes: forming a dummy gate dielectric material layer (not shown) on the substrate 200; forming a dummy gate material layer (not shown) on the dummy gate dielectric material layer; forming a patterned mask layer (not shown) on the dummy gate material layer; etching the dummy gate material layer and the dummy gate dielectric material layer with the patterned mask layer as a mask until the surface of the substrate 200 is exposed, thereby forming the initial dummy gate structure 201.

[0068] The material of the dummy gate dielectric layer includes silicon oxide or low-K (K is less than 3.9) material; the material of the dummy gate electrode layer includes polysilicon.

[0069] The forming method of the initial side wall structure 202 includes: forming a side wall material layer (not shown) on the surface of the substrate 200, the top surface and the sidewall surface of the initial dummy gate structure 201; etching back the side wall material layer until the surface of the substrate 200 is exposed, thereby forming the initial side wall structure 202 on the sidewall of the initial dummy gate structure 201.

[0070] The material of the initial sidewall structure 202 includes a dielectric material, which includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, and silicon carbon oxynitride. In this embodiment, the material of the initial sidewall structure 202 includes silicon nitride.

[0071] In this embodiment, the height of the initial dummy gate structure 201 ranges from 80 nm to 100 nm. The height of the initial dummy gate structure 201 is relatively high, so that when part of the initial sidewall structure 202 is removed later and the height of the sidewall formed after the removal is used as the height of the subsequently formed gate structure, the height of the gate structure can be within a controllable preset range.

[0072] In this embodiment, the distance between adjacent initial dummy gate structures 201 on the first region I ranges from 1 nm to 30 nm, and the distance between adjacent initial dummy gate structures 201 on the second region II is greater than 30 nm.

[0073] Please continue to refer to Figure 2 An initial dielectric layer 203 is formed on the substrate 200, and the initial dielectric layer 203 is located on the sidewall of the initial sidewall structure 202.

[0074] The forming method of the initial dielectric layer 203 includes: forming a dielectric material layer (not shown) on the substrate 200, on the top surface of the initial dummy gate structure 201, and on the sidewall of the initial sidewall structure 202; and planarizing the dielectric material layer until the top surface of the initial dummy gate structure 201 is exposed, thereby forming the initial dielectric layer 203.

[0075] The material of the initial dielectric layer 203 is different from the material of the initial sidewall structure 202, so that when part of the initial sidewall structure 202 is removed later, the etching rate of the removal process on the initial sidewall structure 202 is greater than the etching rate of the removal process on the initial dielectric layer 203, so that the etching degree of the removal process on the initial dielectric layer 203 is smaller.

[0076] The material of the initial dielectric layer 203 includes a dielectric material, which includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, and silicon carbon oxynitride. The process of forming the dielectric material layer includes a chemical vapor deposition process, a heat treatment process, or an atomic layer deposition process.

[0077] In this embodiment, the material of the initial dielectric layer 203 includes silicon oxide, and the process of forming the dielectric material layer includes a chemical vapor deposition process, which can quickly form a dielectric material layer with a relatively thick thickness and a dense structure.

[0078] Please refer to Figure 3, removing part of the initial dummy gate structure 201 to form a dummy gate structure 204, which exposes part of the initial side wall structure 202.

[0079] The process of removing part of the initial dummy gate structure 201 includes one or more of a combination of a wet etching process and a dry etching process. In this embodiment, the process of removing part of the initial dummy gate structure 201 includes a dry etching process, which can accurately control the height of the removed initial dummy gate structure 201, so that the height of the formed dummy gate structure 204 is within a predetermined range.

[0080] In this embodiment, the height of the dummy gate structure 204 ranges from 20 nanometers to 40 nanometers.

[0081] The height range of the dummy gate structure 204 is also the height range of the subsequently formed side wall structure and the height range of the subsequently formed gate structure.

[0082] Please refer to Figure 4 , removing the initial side wall structure 202 exposed by the dummy gate structure 204 to form a side wall structure 205, the top surface of the side wall structure 205 being lower than the top surface of the initial dielectric layer 203.

[0083] The top surface of the side wall structure 205 is lower than the top surface of the initial dielectric layer 203, and the height of the side wall structure 205 is the height of the subsequently formed gate structure, so that when the gate structure is subsequently formed in the gate opening, the process conditions of the planarization gate structure material process can be reduced due to the top surface of the side wall structure 205 being lower than the top surface of the initial dielectric layer 203, thereby reducing the case that the subsequently formed side wall structure 205 and the bottom dielectric layer have a height difference due to the different etching rates of the side wall structure 205 and the initial dielectric layer 203 caused by the process of planarizing the gate structure material, so that the performance of the semiconductor structure formed is more uniform.

[0084] In this embodiment, the initial side wall structure 202 is removed, and at the same time, part of the initial dielectric layer 203 is also removed to form a dielectric layer 206; the top surface of the side wall structure 205 is lower than the top surface of the dielectric layer 206.

[0085] The initial side wall structure 202 is removed, and part of the initial medium layer 203 is also removed, so that the height of the medium layer 206 formed is reduced, and the process condition of the planarization process in the process of forming the gate structure can be reduced, so that the polishing effect is uniform when the planarization process stops on the side wall structure 205, and the case that the side wall structure 205 has a height difference with the underlying medium layer due to the larger etching selectivity of the side wall structure 205 and the medium layer 206 when the planarization process condition is large is reduced, so that the performance of the semiconductor structure formed is more uniform.

[0086] In other embodiments, part of the initial medium layer can not be removed.

[0087] In the embodiment, the top surface of the medium layer 206 is a convex arc surface. The top surface of the medium layer 206 is a convex arc surface, so that the process condition of the planarization process in the process of forming the gate structure can be reduced, so that the polishing effect is uniform when the planarization process stops on the side wall structure 205, and the case that the side wall structure 205 has a height difference with the underlying medium layer due to the larger etching selectivity of the side wall structure 205 and the medium layer 206 when the planarization process condition is large is reduced, so that the performance of the semiconductor structure formed is more uniform.

[0088] In the embodiment, the height of the convex arc surface is h, and the height h ranges from 5 nm to 10 nm.

[0089] In other embodiments, the top surface of the medium layer can not be formed as a convex arc surface.

[0090] The process of removing the initial side wall structure 202 exposed by the dummy gate structure 204 includes one or more combinations of a wet etching process and a dry etching process.

[0091] In the embodiment, the process of removing the initial side wall structure 202 exposed by the dummy gate structure 204 includes a dry etching process, which can accurately control the height of the initial side wall structure 202 removed, so that the height of the side wall structure 205 formed ranges within a preset range.

[0092] In the embodiment, the dry etching process includes a SiCoNi process, and the gas of the SiCoNi process includes a mixed gas of nitrogen trifluoride and hydrogen.

[0093] The SiCoNi process has a higher etching rate on the initial sidewall structure 202 than on the initial dielectric layer 203. Thus, the SiCoNi process can remove part of the initial dielectric layer 203 while removing the initial sidewall structure 202 exposed by the dummy gate structure 204, forming the dielectric layer 206, and the top surface of the dielectric layer 206 is a convex arc surface. The process conditions of the planarization process in the subsequent formation of the gate structure process can be reduced, thereby reducing the case that the subsequently formed sidewall structure 205 has a height difference with the underlying dielectric layer due to the different etching rates of the sidewall structure 205 and the initial dielectric layer 203 caused by the process of planarizing the gate structure material, so that the performance of the formed semiconductor structure is more uniform.

[0094] Please refer to Figure 5 After forming the sidewall structure 205, the dummy gate structure 204 is removed to form a gate opening 207 in the dielectric layer 206.

[0095] The process of removing the dummy gate structure 204 includes one or a combination of wet etching process and dry etching process. In the present embodiment, the process of removing the dummy gate structure 204 includes a wet etching process, which can remove the dummy gate structure 204 at the bottom of the gate opening 207 completely, avoiding the case that incomplete removal of the dummy gate structure 204 affects the performance of the subsequently formed gate structure.

[0096] Please refer to Figure 6 The gate structure 208 is formed in the gate opening 207, and the top surface of the gate structure 208 is lower than or flush with the top surface of the sidewall structure 205.

[0097] The gate structure 208 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) on the gate dielectric layer. In the present embodiment, the gate structure further includes a work function layer (not shown) between the gate dielectric layer and the gate electrode layer.

[0098] The material of the gate dielectric layer includes a high dielectric constant material with a dielectric constant greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate electrode layer includes a metal, and the metal includes tungsten; the material of the work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0099] The forming method of the gate structure 208 comprises: forming a gate structure material layer (not shown) in the gate opening 207 and on the dielectric layer 206; planarizing the gate structure material layer and the dielectric layer 206 until the top surface of the side wall structure 205 is exposed, forming the gate structure 208 and the bottom dielectric layer 207 on the sidewall of the gate structure 208.

[0100] In the embodiment, the top plane of the bottom dielectric layer 207 is flush with the top plane of the gate structure 208.

[0101] The material of the side wall structure 205 is different from that of the dielectric layer 206, so that the side wall structure 205 can be used as a stop layer for planarizing the gate structure material layer and the dielectric layer 206.

[0102] The planarizing process of the gate structure material layer and the dielectric layer 206 comprises a chemical mechanical polishing process.

[0103] Since the top surface of the side wall structure 205 is lower than the top surface of the dielectric layer 206, the grinding amount of the chemical mechanical polishing process for planarizing the gate structure material layer can be reduced, so that the subsequent height difference between the side wall structure 205 and the bottom dielectric layer 207 caused by the different etching rates of the side wall structure 205 and the initial dielectric layer 203 during the planarizing process of the gate structure material layer is reduced, and the performance of the semiconductor structure is more uniform.

[0104] In addition, the removal of the initial side wall structure 202 also removes part of the initial dielectric layer 203, so that the height of the formed dielectric layer 206 is reduced, the grinding amount of the chemical mechanical polishing process for planarizing the gate structure material layer can be reduced, the polishing effect is uniform when the planarizing process stops on the side wall structure 205, and the subsequent height difference between the side wall structure 205 and the bottom dielectric layer 207 caused by the larger etching selectivity of the side wall structure 205 and the dielectric layer 206 under the large process condition of the planarizing process is reduced, and the performance of the semiconductor structure is more uniform.

[0105] Further, the top surface of the dielectric layer 206 is a convex arc surface, so that the grinding amount of the chemical mechanical polishing process for planarizing the gate structure material layer can be reduced, the polishing effect is uniform when the planarizing process stops on the side wall structure 205, and the subsequent height difference between the side wall structure 205 and the bottom dielectric layer 207 caused by the larger etching selectivity of the side wall structure 205 and the dielectric layer 206 under the large process condition of the planarizing process is reduced, and the performance of the semiconductor structure is more uniform.

[0106] Correspondingly, the embodiment of the present application also provides a semiconductor structure, please continue to refer to Figure 4 , comprising:

[0107] a substrate 200;

[0108] a gate structure 204 on the substrate 200;

[0109] a sidewall structure 205 on the sidewall of the gate structure 204;

[0110] a dielectric layer 206 on the substrate 200, the dielectric layer 206 is on the sidewall of the sidewall structure 205, and the top surface of the dielectric layer 206 is higher than the top surface of the sidewall structure 205 and the top surface of the gate structure 204, and the top surface of the dielectric layer 206 is a convex arc surface.

[0111] In this embodiment, the convex arc surface has a height ranging from 5nm to 10nm.

[0112] In this embodiment, the material of the sidewall structure 205 includes a dielectric material, and the dielectric material includes silicon nitride.

[0113] In this embodiment, the material of the dielectric layer 206 includes a dielectric material, and the dielectric material includes silicon oxide.

[0114] In this embodiment, the substrate 200 includes a first region I and a second region II, and the device density of the first region I is greater than that of the second region II.

[0115] In this embodiment, the distance between adjacent gate structures 204 on the first region I ranges from 1nm to 30nm, and the distance between adjacent gate structures 204 on the second region II is greater than 30nm.

[0116] In this embodiment, the height of the sidewall structure 205 ranges from 20nm to 30nm.

[0117] In this embodiment, the gate structure 204 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) on the gate dielectric layer.

[0118] In this embodiment, the material of the gate dielectric layer includes silicon oxide, and the material of the gate electrode layer includes silicon.

[0119] In other embodiments, the gate structure further includes a work function layer between the gate dielectric layer and the gate electrode layer.

[0120] In other embodiments, the material of the gate dielectric layer includes a high dielectric constant material having a dielectric constant greater than 3.9, the high dielectric constant material including hafnium oxide or aluminum oxide; the material of the gate electrode layer includes a metal, the metal including tungsten; the material of the work function layer includes an N-type work function material or a P-type work function material, the N-type work function material including titanium aluminum, the P-type work function material including titanium nitride or tantalum nitride.

[0121] The semiconductor structure, the top surface of the dielectric layer 206 is higher than the top surface of the sidewall structure 205 and the top surface of the gate structure 204, and the top surface of the dielectric layer 206 is a convex arc surface. Thus, when forming the gate structure 204, since the top surface of the sidewall structure 205 is lower than the top surface of the dielectric layer 206, and the top surface of the dielectric layer 206 is a convex arc surface, the process conditions of the planarization gate structure material process can be reduced, thereby reducing the difference in etching rate of the sidewall structure 205 and the dielectric layer 206 caused by the planarization gate structure material process, resulting in the subsequent formation of the sidewall structure and the underlying dielectric layer having a height difference, so that the performance of the semiconductor structure formed is more uniform.

[0122] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the scope of protection of the present application should be limited by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized by, The application relates to a substrate, which comprises a first area and a second area, the device density of the first area being greater than that of the second area. The substrate comprises a dummy gate structure, a sidewall structure on the sidewall of the dummy gate structure, a dielectric layer on the substrate, the dielectric layer being on the sidewall of the sidewall structure, and the top surface of the dielectric layer being higher than the top surfaces of the sidewall structure and the dummy gate structure, the sidewall structure and the dummy gate structure exposing part of the sidewall surface of the dielectric layer, and the top surface of the dielectric layer being a convex arc surface. The convex height of the arc surface ranges from 5nm to 10nm. The material of the sidewall structure comprises a dielectric material, and the dielectric material comprises silicon nitride. The material of the dielectric layer comprises a dielectric material, and the dielectric material comprises silicon oxide.

2. The semiconductor structure of claim 1, wherein, The distance between adjacent dummy gate structures on the first area ranges from 1nm to 30nm, and the distance between adjacent dummy gate structures on the second area is greater than 30nm.

3. The semiconductor structure of claim 1, wherein, The height of the sidewall structure ranges from 20nm to 30nm.

4. The semiconductor structure of claim 1, wherein, The dummy gate structure comprises a dummy gate dielectric layer and a dummy gate electrode layer on the dummy gate dielectric layer.

5. The semiconductor structure of claim 1, wherein, The material of the dummy gate dielectric layer comprises silicon oxide, and the material of the dummy gate electrode layer comprises polysilicon.

6. The semiconductor structure of claim 1, wherein, The application also relates to a method for manufacturing a substrate, which comprises a first area and a second area, the device density of the first area being greater than that of the second area.

7. The semiconductor structure of claim 1, wherein, The method comprises the following steps: providing a substrate; forming an initial dummy gate structure and an initial sidewall structure on the sidewall of the initial dummy gate structure on the substrate; forming an initial dielectric layer on the substrate, the initial dielectric layer being on the sidewall of the initial sidewall structure; removing part of the initial dummy gate structure to form a dummy gate structure, the dummy gate structure exposing part of the initial sidewall structure; removing the initial sidewall structure exposed by the dummy gate structure to form a sidewall structure; removing part of the initial dielectric layer exposed by the dummy gate structure to form a dielectric layer while the initial sidewall structure is removed, the top surface of the sidewall structure being lower than the top surface of the dielectric layer, the sidewall structure and the dummy gate structure exposing part of the sidewall surface of the dielectric layer, and the top surface of the dielectric layer being a convex arc surface; removing the dummy gate structure after the sidewall structure is formed to form a gate opening in the dielectric layer; and forming a gate structure in the gate opening, the top surface of the gate structure being lower than or flush with the top surface of the sidewall structure.

8. The semiconductor structure of claim 7, wherein, The convex height of the arc surface ranges from 5nm to 10nm.

9. A method of forming a semiconductor structure, comprising: The process for removing the initial sidewall structure exposed by the dummy gate structure comprises a dry etching process. The dry etching process comprises a SiCoNi process, and the gas of the SiCoNi process comprises a mixed gas of nitrogen trifluoride and hydrogen. The etching rate of the SiCoNi process to the initial sidewall structure is greater than the etching rate of the SiCoNi process to the initial dielectric layer. The method for forming the gate structure comprises the following steps: forming a gate structure material layer in the gate opening and on the dielectric layer; and planarizing the gate structure material layer and the dielectric layer until the top surface of the sidewall structure is exposed to form a gate structure and a bottom dielectric layer. The process for planarizing the gate structure material layer and the dielectric layer comprises a chemical mechanical polishing process. ​ ​ ​ ​ 10. The method of forming a semiconductor structure of claim 9, wherein, ​ 11. The method for forming a semiconductor structure as described in claim 9, characterized in that, ​ 12. The method of forming a semiconductor structure of claim 11, wherein, ​ 13. The method of forming a semiconductor structure of claim 12, wherein, ​ 14. The method of forming a semiconductor structure of claim 9, wherein, ​ 15. The method of forming a semiconductor structure of claim 14, wherein, ​ 16. The method of forming a semiconductor structure of claim 9, wherein, The process of removing part of the initial dummy gate structure includes a dry etching process.

17. The method of forming a semiconductor structure of claim 9, wherein, The process of removing the dummy gate structure includes a wet etching process.

18. The method of forming a semiconductor structure of claim 9, wherein, The material of the initial side wall structure is different from the etching rate of the material of the initial dielectric layer.

19. The method of forming a semiconductor structure of claim 18, wherein, The material of the initial side wall structure includes a dielectric material including silicon nitride.

20. The method of forming a semiconductor structure of claim 18, wherein, The material of the initial dielectric layer includes a dielectric material including silicon oxide.

21. The method of forming a semiconductor structure of claim 9, wherein, The pitch of the adjacent gate structures on the first region ranges from 1 nanometer to 30 nanometers; the pitch of the adjacent gate structures on the second region ranges from greater than 30 nanometers.

22. The method of forming a semiconductor structure of claim 9, wherein, The height of the initial side wall structure ranges from 80 nanometers to 100 nanometers.

23. The method of forming a semiconductor structure of claim 9, wherein, The height of the side wall structure ranges from 20 nanometers to 30 nanometers.

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