Silicon carbide trench structure, method of manufacturing the same, and semiconductor device

Abstract

The application discloses a silicon carbide trench structure, a manufacturing method thereof and a semiconductor device, wherein the manufacturing method of the silicon carbide trench structure comprises the following steps: forming a first mask layer on a surface of a silicon carbide substrate; forming a photoresist layer with a preset pattern on the first mask layer; performing first etching on the first mask layer to form an opening by taking the photoresist layer as a mask, and the opening exposes the surface of the silicon carbide substrate; and performing second etching on the surface of the silicon carbide substrate exposed by the opening by taking the first mask layer after etching as a mask to form a trench; wherein the etching gas used in the process condition of the second etching comprises a mixture of chlorine and fluorocarbon gas or boron chloride gas. The boron chloride gas or the fluorocarbon gas has a protection effect on the side wall of the trench, can form a trench structure with a vertical side wall and a smooth bottom, and can increase the depth-width ratio of the silicon carbide trench.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and more particularly to a silicon carbide trench structure, a manufacturing method thereof and a semiconductor device. BACKGROUND

[0002] As a third-generation wide-bandgap semiconductor material, SiC material has a series of advantages such as wide band gap, high thermal conductivity, high breakdown electric field strength, large saturated electron drift velocity and ability to withstand extreme environmental changes, which makes SiC material have great application potential in high temperature, high frequency, high power, optoelectronics and radiation resistance. Therefore, at present, silicon carbide material is mainly applied to the preparation of electronic devices. Field effect transistor is a typical electronic device, which can realize signal amplification, switching and other functions and avoid sparking, and is widely used in microwave communication, power grid and other fields. The gate is an important part of the field effect transistor. Compared with the traditional planar gate structure, the trench gate has stronger control ability to the channel. Therefore, how to obtain a trench structure in silicon carbide material is a key process step in the preparation of silicon carbide field effect transistor at present.

[0003] However, the silicon carbide material also has the characteristic of high hardness, which is only second to diamond. The bond energy of SiC material is large, and the chemical properties are very stable. The wet chemical etching at room temperature cannot realize the etching of SiC, so the commonly used etching method of SiC is dry etching. The main researched reaction gases for etching silicon carbide are SF6, CF4, HBr, Cl2, Ar, O2, etc. However, in various etching methods, micro-trench effect generally occurs, which affects the performance of the device. The main reason for the occurrence of micro-trench effect is that the Bias power is high, which causes the plasma to rebound on the sidewall and form a micro-trench at the bottom, so the protection of the sidewall needs to be strengthened. However, if the sidewall protection is too heavy, the bottom etching will shrink and the steepness of the sidewall will be poor. On the other hand, if the bottom of the trench is flat, the sharp tip morphology will easily cause tip discharge. Taking MOS field effect transistor as an example, tip discharge breaks down the gate, which leads to device failure. Therefore, how to obtain a trench structure with vertical sidewall and smooth bottom in silicon carbide etching is an important challenge. SUMMARY

[0004] The purpose of the present application is to provide a silicon carbide trench structure, a manufacturing method thereof and a semiconductor device, which can obtain a trench structure with vertical sidewall and smooth bottom.

[0005] In order to achieve the above purpose, the present application provides a manufacturing method of a silicon carbide trench structure, which comprises the following steps:

[0006] forming a first mask layer on the surface of the silicon carbide substrate;

[0007] forming a photoresist layer with a preset pattern on the first mask layer;

[0008] Using a photoresist layer as a mask, the first mask layer is etched to form an opening, which exposes the surface of the silicon carbide substrate.

[0009] Using the etched first mask layer as a mask, a second etching is performed on the surface of the silicon carbide substrate exposed by the opening to form trenches; wherein, the etching gas used in the process conditions of the second etching includes: a mixture of chlorine and fluorocarbon gases or boron chloride gas.

[0010] In an optional embodiment, the etching gas includes BCl3, Ar, SF6, and O2.

[0011] In an optional embodiment, the volumetric flow rate ratio of BCl3 to SF6 is 0.5 to 1.5; and / or, the volumetric flow rate ratio of O2 to SF6 is 1 to 3.

[0012] In an optional embodiment, the etching gas includes: Cl2, C4F8, Ar, SF6, and O2.

[0013] In an optional embodiment, the volumetric flow rate ratio of O2 to C4F8 is 0.3 to 1; and / or, the volumetric flow rate ratio of O2 to Cl2 is 1 to 2.

[0014] In an optional embodiment, the process conditions for the second etching include a power range of 500W to 1500W for the lower electrode.

[0015] In an optional embodiment, the process conditions for the second etching include: the chamber pressure of the reaction chamber is in the range of 1 to 50 mTorr, the power of the lower electrode is in the range of 500 to 1500 W, the flow rate of BCl3 is in the range of 10 to 1000 sccm, the flow rate of Ar is in the range of 10 to 1000 sccm, the flow rate of SF6 is in the range of 10 to 1000 sccm, and the flow rate of O2 is in the range of 10 to 1000 sccm.

[0016] In an optional embodiment, the process conditions for the second etching include: the chamber pressure range of the reaction chamber is 1 to 50 mTorr, the power range of the lower electrode is 500 to 1500 W, the flow rate of Cl2 is 10 to 1000 sccm, the flow rate of C4F8 is 10 to 1000 sccm, the flow rate of SF6 is 10 to 1000 sccm, and the flow rate of O2 is 10 to 1000 sccm.

[0017] In an optional embodiment, the first mask layer is a silicon dioxide layer.

[0018] The present invention also provides a silicon carbide trench structure, which is formed by etching using the above method. The sidewalls of the formed trench are vertical, the bottom wall is arc-shaped, and the connection between the sidewalls and the bottom wall is transitioned by rounded corners.

[0019] The present invention also provides a semiconductor device comprising the above-described silicon carbide trench structure.

[0020] The beneficial effects of this invention are as follows:

[0021] The boron chloride gas or fluorocarbon gas of the present invention provides protection for the trench sidewalls, can form a trench structure with vertical sidewalls and a smooth bottom, and can increase the depth-to-width ratio of the silicon carbide trench.

[0022] The present invention has other features and advantages, which will be apparent from or will be set forth in detail in the accompanying drawings and the following detailed description, which together serve to explain the particular principles of the invention. Attached Figure Description

[0023] The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of exemplary embodiments of the invention in conjunction with the accompanying drawings.

[0024] Figure 1 A flowchart illustrating a method for manufacturing a silicon carbide trench structure according to an embodiment of the present invention is shown.

[0025] Figure 2 A silicon carbide trench structure according to an embodiment of the present invention is shown.

[0026] Figure 3 The effect of the ratio of BCl3, SF6 and O2 gases on the process results is shown according to an embodiment of the present invention.

[0027] Figure 4 The effect of the SF6 / BCl3 and O2 / SF6 gas ratios on process results is shown according to an embodiment of the present invention.

[0028] Figures 5 to 17 The diagram shows structural schematics corresponding to different steps in a method for manufacturing a trench MOSFET device according to an embodiment of the present invention. Detailed Implementation

[0029] The invention will now be described in more detail. While preferred embodiments are provided, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0030] One embodiment of the present invention provides a method for manufacturing a silicon carbide trench structure. Figure 1 A flowchart illustrating the steps of this method is shown. Please refer to it.Figure 1 The method includes:

[0031] A first mask layer is formed on the surface of a silicon carbide substrate;

[0032] A photoresist layer with a preset pattern is formed on the first mask layer;

[0033] Using the first photoresist layer as a mask, the first mask layer is etched to form an opening, which exposes the surface of the silicon carbide substrate.

[0034] Using the first etched mask layer as a mask, a second etching is performed on the exposed surface of the silicon carbide substrate to form trenches; wherein, the etching gas used in the second etching process conditions includes: a mixture of chlorine and fluorine-based gases or boron chloride gas.

[0035] In this embodiment, boron chloride gas or fluorocarbon gas provides protection for the trench sidewalls, forming a trench structure with vertical sidewalls and a smooth bottom, and can increase the depth-to-width ratio of the silicon carbide trench.

[0036] The method is described below with two specific examples.

[0037] Example 1

[0038] The first step is to clean the silicon carbide substrate using standard RCA wet chemical cleaning technology to obtain a clean silicon carbide substrate.

[0039] The second step involves placing the cleaned silicon carbide substrate into a deposition apparatus and growing a first mask layer using PECVD. The first mask layer can be silicon dioxide with a thickness of 0.5–10 micrometers, preferably 3 micrometers. The cavity pressure ranges from 20 to 200 Pa, the plasma power ranges from 50 to 500 W, the SiH4 flow rate ranges from 5 to 150 sccm, the N2O flow rate ranges from 100 to 5000 sccm, the N2 flow rate ranges from 100 to 5000 sccm, the growth temperature ranges from 100 to 500 °C, and the growth time is selected based on the thickness and growth rate. For example, under the above preferred conditions, growing a preferred thickness of 3 micrometers requires 8700 s.

[0040] The third step is to spin-coat a photoresist layer on the surface of the silicon carbide substrate, with a thickness of 0.5 to 10 micrometers, preferably 5 micrometers.

[0041] The fourth step is exposure and development. The photomask is designed and processed in advance as needed. The exposure time is preferably 6 seconds, with a value range of 3 to 20 seconds. The development time is preferably 75 seconds, with a value range of 45 to 120 seconds. The fixing time is preferably 120 seconds, with a value range of 60 to 300 seconds, so that the photoresist forms a preset pattern.

[0042] The fifth step involves using a plasma etching machine and a photoresist layer as a mask to perform the first etching on the silicon dioxide mask layer, forming an opening that exposes the surface of the silicon carbide substrate. The process conditions are as follows: cavity pressure range 1–30 mTorr, upper electrode power range 600–3000 W, lower electrode power range 50–500 W, argon flow rate range 10–100 sccm, CF4 flow rate range 10–100 sccm (other fluorocarbon gases such as C4F8 and CHF3 can also be used), and substrate coolant temperature range -15–10°C.

[0043] Step 6, etching the silicon carbide substrate: Using the etched first mask layer (silicon dioxide) as a mask, a second etching is performed on the exposed surface of the silicon carbide substrate to form trenches. The etching gases used in the second etching process include a mixture of chlorine and fluorine-based gases or boron chloride gas. In this embodiment, etching gases BCl3, Ar, SF6, and O2 are introduced into the reaction chamber. The chamber pressure ranges from 1 to 50 mTorr, the power of the lower electrode ranges from 500 to 1500 W, the BCl3 flow rate ranges from 10 to 1000 sccm, the Ar flow rate ranges from 10 to 1000 sccm, the SF6 flow rate ranges from 10 to 1000 sccm, and the O2 flow rate ranges from 10 to 1000 sccm. Specific preferred etching process formulations are shown in Table 1.

[0044] Table 1

[0045]

[0046] Example 2

[0047] The first 5 steps of this example are the same as those in Example 1, and will not be repeated here.

[0048] Step 6, etching the silicon carbide substrate: Etching gases Cl2, C4F8, Ar, SF6, and O2 are introduced into the reaction chamber. The chamber pressure ranges from 1 to 50 mTorr, the power of the lower electrode ranges from 500 to 1500 W, the Cl2 flow rate ranges from 10 to 1000 sccm, the C4F8 flow rate ranges from 10 to 1000 sccm, the SF6 flow rate ranges from 10 to 1000 sccm, and the O2 flow rate ranges from 10 to 1000 sccm.

[0049] Existing methods for etching silicon carbide substrates (corresponding to step six in both examples) include:

[0050] 1. The combination of SF6, O2, and HBr forms a trench with a flat (non-rounded) bottom. The right-angled shape is prone to tip discharge, which can break down the dielectric layer and cause device failure.

[0051] 2. Cl2+O2+N2: The trench sidewall angle formed by this combination is relatively oblique, which is not suitable for high aspect ratio silicon carbide etching.

[0052] 3. High-temperature annealing under an argon atmosphere after dry etching can produce silicon carbide trench morphology with rounded corners at both the top and bottom. However, this technique requires an additional horizontal furnace annealing step, which increases the cost.

[0053] In the two examples above, the use of BCl3 gas or a mixture of Cl2 and C4F8 gas provides protection for the trench sidewalls, enabling the formation of trench structures with vertical sidewalls and smooth bottoms, and increasing the aspect ratio of the silicon carbide trenches. This invention, through an optimized etching formula, directly achieves a bottom-trench-free surface with good roughness via ICP etching.

[0054] In the two examples above, the trench depth is 3 micrometers and the width is 0.5 micrometers, resulting in a depth-to-width ratio of 6:1. The bottom corner radius is greater than 0.2 micrometers. In existing technologies, when the mask layer is silicon dioxide, the trench depth-to-width ratio is generally 2:1. Although metal mask layers can increase the trench depth-to-width ratio, most semiconductor devices do not use metal masks due to metal particle contamination.

[0055] The reaction equation related to the mechanism by which a mixture of Cl2 and C4F8 gases can etch silicon carbide substrates and form trench sidewall protection is as follows:

[0056] Silicon carbide etching:

[0057] SiC + 2Cl₂ + O₂ → SiCl₄↑ + CO₂↑

[0058] Carbon-fluorine plasma formation:

[0059] CxFy→CF3*+CF2*+CF*+F*+e-+photon

[0060] Formation of fluoropolymers:

[0061] CFn→{CF2}n↓

[0062] Fluoropolymers are formed on the sidewalls of the trench, thus protecting the sidewalls.

[0063] The reaction equation related to the mechanism by which BCl3 gas can form protective trench sidewalls is as follows:

[0064] BCl3→BClx*+Cl-

[0065] BClx ions are adsorbed on the trench sidewalls, protecting them, while SF6, O2, and Ar act as etching agents for silicon carbide.

[0066] Furthermore, in the two examples above, the power range of the lower electrode is 500–1500W, preferably 850W, while the power of the lower electrode in existing technologies is generally below 500W. Due to the difference in potential energy between the chemical reactions of silicon and carbon, the etching rate of silicon is greater than that of carbon (existing technologies suppress the etching rate of silicon). By increasing the power of the lower electrode, this effect can be eliminated, making the etching rates of both materials closer, thereby increasing the overall etching rate of silicon carbide and shortening the process time. In the two examples above, WPH (wafer throughput per hour) > 7.

[0067] refer to Figure 3 and Figure 4 , Figure 3 The horizontal axis represents the SF6 ratio, and the vertical axis represents the BCl3 ratio. Figure 4 The horizontal axis represents the O2 / SF6 ratio, and the vertical axis represents the SF6 / BCl3 ratio. R14, R16, R11, etc., in the figure represent different process parameter sets (parameters include temperature, pressure, time, etc.). Through repeated experiments, the inventors discovered that both excessively high and low SF6 flow rates affect the trench morphology. When the SF6 ratio is too low, a V-shaped morphology (larger at the top and smaller at the bottom) is formed. When the SF6 ratio is too high, excessive erosion occurs, causing damage or even etching through adjacent patterns. Conversely, excessively high or low BCl3 gas ratios can cause damage or pattern erosion. When the O2 ratio is too high, the sidewall protection is excessive, causing plasma rebound on the sidewalls and resulting in anomalies at the trench bottom. When the O2 ratio is too low, the sidewall protection is insufficient, and adjacent patterns are etched through. Excessively high or low BCl3 and Cl2 ratios can also cause damage or pattern erosion. SF6, O2, and BCl3 gases all play important roles, while using a mixture of four gases (Ar, SF6, O2, and BCl3) or five gases (Ar, SF6, O2, Cl2, and C4F8) for silicon carbide etching is significantly different from existing technologies.

[0068] Since Ar simply acts as a physical bombardment agent, changes in Ar flow rate have little impact on the process. Therefore, in Example 1, the preferred ratio of BCl3 to SF6 volumetric flow rates is 0.5–1.5, and the ratio of O2 to SF6 volumetric flow rates is 1–3. In Example 2, the preferred ratio of O2 to C4F8 volumetric flow rates is 0.3–1, and the ratio of O2 to Cl2 volumetric flow rates is 1–2. By selecting appropriate gas ratios, well-formed trenches are etched.

[0069] An embodiment of the present invention provides a silicon carbide trench structure, which is manufactured by the above-described manufacturing method. The trench has vertical sidewalls, an arc-shaped bottom wall, and the connection between the sidewalls and the bottom wall is transitioned by rounded corners. Figure 2The diagram shows the structure of the trench, which is 2.13 micrometers deep, 518 nanometers wide at the bottom, and 542 nanometers wide at the top. It is evident that the trench sidewalls are perpendicular to the bottom surface (the sidewalls are not tilted), exhibiting a high aspect ratio. The transition between the sidewalls and the bottom is smooth, preventing tip discharge.

[0070] One embodiment of the present invention provides a semiconductor device including the aforementioned silicon carbide trench structure, such as a trench MOSFET device, and a grating structure, particularly a diffraction grating structure. For a diffraction grating structure, where light enters and exits perpendicularly to the plane of the paper, an aspect ratio of 6:1 is required; otherwise, the area available for light diffraction is very small, resulting in poor performance and affecting practical application.

[0071] refer to Figures 5 to 17 Briefly describe the manufacturing method of trench MOSFET devices, refer to Figure 5 First, a silicon carbide substrate 10 is provided, on which source and drain regions (not shown in the figure) are formed. (Reference) Figure 6 A first mask layer (silicon dioxide layer 11) is deposited on a silicon carbide substrate 10 using a CVD process. (Reference) Figure 7 A photoresist layer 12 is formed on the silicon dioxide layer 11, and a pattern is pre-set in the photoresist layer 12 using a photolithography process. (Reference) Figure 8 Using the photoresist layer 12 after photolithography as a mask, an opening is formed in the silicon dioxide layer 11 exposed by the photoresist pattern through a first etching process, exposing the surface of the silicon carbide substrate 10. (Reference) Figure 9 After forming the opening, the photoresist layer is removed. (Reference) Figure 10 Using the silicon dioxide layer 11 after the opening is formed as a mask, a second etching is performed on the surface of the silicon carbide substrate 10 exposed by the opening to form trenches. The method for forming trenches in the silicon carbide substrate described above is the same as in Example 1 or 2, and will not be repeated here. (See also...) Figure 11 Gate oxide 13 is formed on the sidewalls of the trench. (Reference) Figure 12 and Figure 13 A polysilicon layer 14 is formed on a silicon carbide substrate using a CVD process. The polysilicon layer outside the trench region is removed, and the polysilicon in the trench forms the gate electrode. (Reference) Figure 14 A silicon dioxide layer 15 was formed on a silicon carbide substrate using a CVD process. (Reference) Figure 15 Vias are formed by etching in the silicon dioxide layer 15, extending to the source and gate electrodes. (Reference) Figure 16 A metal wiring layer 16 is formed in the via and on the upper surface of the silicon dioxide layer 15. (Reference) Figure 17A passivation layer 17 is formed on the metal wiring layer 16, exposing a portion of the metal wiring layer 16 for subsequent process steps to bring out the electrical characteristics of the source and gate. The silicon carbide substrate 10 is thinned on the back side, and a conductive layer 18 is formed on the back side of the silicon carbide substrate 10 to bring out the electrical characteristics of the drain. Shorting the gate and drain allows for the formation of a high-current rectifier. The MOSFET device formed using this method has smooth transitions between the trench sidewalls and bottom wall, preventing tip discharge that could break down the gate and ensuring device reliability.

[0072] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method for manufacturing a silicon carbide trench structure, characterized in that, include: A first mask layer is formed on the surface of a silicon carbide substrate; A photoresist layer with a preset pattern is formed on the first mask layer; Using a photoresist layer as a mask, the first mask layer is etched to form an opening, which exposes the surface of the silicon carbide substrate. Using the etched first mask layer as a mask, a second etching is performed on the surface of the silicon carbide substrate exposed by the opening to form trenches; wherein, the etching gas used in the second etching process conditions includes: BCl3, Ar, SF6 and O2, and the volumetric flow rate ratio of BCl3 and SF6 is 0.5 to 1.5, or the etching gas includes: Cl2, C4F8, Ar, SF6 and O2, and the volumetric flow rate ratio of O2 and C4F8 is 0.3 to 1.

2. The method for manufacturing the silicon carbide trench structure according to claim 1, characterized in that, When the etching gas includes BCl3, Ar, SF6 and O2, the volumetric flow rate ratio of O2 to SF6 is 1 to 3.

3. The method for manufacturing the silicon carbide trench structure according to claim 1, characterized in that, When the etching gas includes Cl2, C4F8, Ar, SF6 and O2, the volumetric flow rate ratio of O2 to Cl2 is 1 to 2.

4. The method for manufacturing the silicon carbide trench structure according to claim 1, characterized in that, The second etching process conditions include a power range of 500W to 1500W for the lower electrode.

5. The method for manufacturing the silicon carbide trench structure according to claim 1, characterized in that, The process conditions for the second etching include: a chamber pressure range of 1–50 mTorr, a power range of 500–1500 W for the lower electrode, a flow rate range of 10–1000 sccm for BCl3, a flow rate range of 10–1000 sccm for Ar, a flow rate range of 10–1000 sccm for SF6, and a flow rate range of 10–1000 sccm for O2.

6. The method for manufacturing the silicon carbide trench structure according to claim 1, characterized in that, The process conditions for the second etching include: a chamber pressure range of 1–50 mTorr, a power range of 500–1500 W for the lower electrode, a flow rate range of 10–1000 sccm for Cl2, a flow rate range of 10–1000 sccm for C4F8, a flow rate range of 10–1000 sccm for SF6, and a flow rate range of 10–1000 sccm for O2.

7. The method for manufacturing a silicon carbide trench structure according to claim 1, characterized in that, The first mask layer is a silicon dioxide layer.

8. A silicon carbide trench structure, characterized in that, The trench is formed by etching using the method described in any one of claims 1-7, wherein the sidewalls of the formed trench are vertical, the bottom wall is arc-shaped, and the connection between the sidewalls and the bottom wall is transitioned by rounded corners.

9. A semiconductor device, characterized in that, It includes the silicon carbide trench structure as described in claim 8.

Images