Method for improving the alignment passing rate of epitaxially grown wafers

Abstract

The present invention discloses a method for improving the alignment pass rate of epitaxially grown wafers, which includes the following steps: Step 1, obtain the original layout; Step 2, lithography for precise alignment requires placing lithography alignment marks in the original layout; Step 3, leave the lithography alignment marks on the wafer by etching; Step 4, perform epitaxial growth on the wafer engraved with the lithography alignment marks to generate an epitaxial growth pattern. Due to the characteristics of crystal growth along the crystal growth direction unique to the epitaxial process, the lithography alignment marks will have drifted and deformed patterns. By utilizing the characteristics of the adjustable focal length of the vision imaging lens and the fixed growth direction and drift direction characteristics of the epitaxial growth pattern, filter out the clutter and interference patterns formed by the lithography alignment marks after epitaxial growth, and obtain the relatively sharp-cornered alignment mark signal of the lithography alignment marks before epitaxial growth. The present invention can filter out the clutter and interference patterns formed by the lithography alignment marks after epitaxial growth.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for improving the alignment passing rate of epitaxial growth wafers. Background Art

[0002] The BCD process is a monolithic integration process technology, which was first developed successfully by STMicroelectronics in 1986. This technology can fabricate three types of devices, namely bipolar devices, CMOS, and DMOS, on the same chip, and is called the BCD process. With the further development of integrated circuit technology, the BCD process has become the mainstream manufacturing technology for PICs. The BCD process combines the advantages of bipolar devices with high transconductance and strong load driving ability, and CMOS with high integration and low power consumption, making them complement each other and give full play to their respective advantages. At the same time, DMOS can operate in the switching mode with extremely low power consumption, and can transfer high power to the load without an expensive packaging and cooling system. Low power consumption is one of the main advantages of the BCD process. The BCD process can significantly reduce power consumption, improve system performance, save the packaging cost of the circuit, and has better reliability.

[0003] The BCD process needs to integrate bipolar devices, CMOS devices, and DMOS devices onto the same chip, and must borrow the epitaxial process. Based on the principle of epitaxial growth, the normal alignment pattern will undergo morphological changes and drifts, resulting in an increased probability of subsequent lithography alignment layer failure. Summary of the Invention

[0004] In view of the above situation, in order to overcome the defects of the prior art, the present invention provides a method for improving the alignment passing rate of epitaxial growth wafers.

[0005] The present invention solves the above technical problems through the following technical solutions: A method for improving the alignment passing rate of epitaxial growth wafers, characterized in that it includes the following steps:

[0006] Step 1, obtaining the original layout;

[0007] Step 2, placing lithography alignment marks in the original layout for precise lithography alignment;

[0008] Step 3, leaving the lithography alignment marks on the wafer by etching;

[0009] Step 4: Epitaxial growth is performed on the wafer engraved with the photolithography alignment mark to generate an epitaxial growth pattern. The photolithography alignment mark will drift and deform due to the unique characteristics of epitaxial growth in the epitaxial process. By utilizing the adjustable focal length of the visual imaging lens and the fixed growth direction and drift direction characteristics of the epitaxial growth pattern, the focal length of the visual imaging is adjusted to change the imaging pattern from a clear pattern to a blurred pattern, and the noise and interference pattern formed by the photolithography alignment mark after epitaxial growth are filtered out, and the relatively sharp alignment mark signal of the photolithography alignment mark before epitaxial growth is obtained.

[0010] Preferably, the original layout in step 1 is obtained through layout design software.

[0011] Preferably, the photolithography alignment marks include at least one group of coarse alignment marks and one group of fine alignment marks.

[0012] Preferably, in step 2, a photolithography alignment lens is used to place a photolithography alignment mark.

[0013] Preferably, the wafer in step 4 is epitaxially grown in an epitaxial furnace.

[0014] Preferably, the epitaxial furnace adopts high-frequency induction heating.

[0015] Preferably, the wafer in step 4 is epitaxially grown using a vapor phase epitaxy process.

[0016] The positive progress of the present invention is that: the present invention adjusts the focal length of the visual imaging by utilizing the characteristics of the visual imaging lens that can adjust the focal length and the fixed growth direction and drift direction of the epitaxial growth pattern, thereby changing the imaging pattern from a clear pattern to a blurred pattern. In this way, the epitaxial growth pattern is penetrated, the noise and interference patterns formed by the lithography alignment mark after the epitaxial growth are filtered out, and the more angular alignment mark signal of the lithography alignment mark before the epitaxial growth is obtained, thereby increasing the epitaxial wafer alignment pass rate from 50% to 100%. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the structure of the coarse alignment mark in the present invention.

[0018] Figure 2 Schematic diagram of the structure of the precise alignment mark in the present invention.

[0019] Figure 3 This is a schematic diagram of the structure of generating an etched pattern by photolithography alignment marks in the present invention.

[0020] Figure 4 Schematic diagram of the structure of the mark image at normal focal length.

[0021] Figure 5 It is a schematic diagram of a mark image under focus adjustment according to the present invention.

[0022] Figure 6 The present invention is a flow chart of a method for improving the alignment pass rate of epitaxially grown wafers. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0024] like Figure 6 As shown, the method for improving the alignment pass rate of epitaxially grown wafers of the present invention comprises the following steps:

[0025] Step 1: Get the original layout. The original layout can be obtained through layout design software, which is convenient to obtain and use.

[0026] Step 2: Place photolithography alignment marks on the original layout for precise alignment. Place photolithography alignment marks on the original layout. The photolithography alignment marks include at least one set of coarse alignment marks and one set of fine alignment marks. Figure 1 As shown, the precise alignment marks are as follows Figure 2 As shown; it is not limited to the above-mentioned lithography alignment mark; the coarse alignment mark gives a rough position information to facilitate the execution of fine alignment, and the coarse alignment and fine alignment mutually confirm the alignment accuracy. Figure 1 and Figure 2 The O in represents the alignment center of the original layout.

[0027] Step 3: Leave the photolithography alignment mark on the wafer by etching. The final etching pattern is as follows: Figure 3 As shown, the edges and corners of the pattern are relatively clear. Under normal focusing conditions, the photolithography alignment mark will not change under the visual imaging effect and some more complex signals will not appear. Using the alignment mark pattern at this stage, under normal circumstances, there is no risk of photolithography alignment failure.

[0028] Step 4: Epitaxial growth is performed on the wafer with the lithography alignment marks to generate epitaxial growth patterns. Due to the unique characteristics of epitaxial growth in the epitaxial process, the lithography alignment marks will have drifting patterns and deformed patterns. The drifting patterns and deformed patterns will generate more interference signals and noise in the visual imaging effect, interfering with the normal lithography alignment process to position the wafer, resulting in the failure of the positioning process. The wafer will be rejected in the lithography alignment process. Figure 4As shown, under normal focusing conditions, the drift pattern and deformation pattern of the lithography alignment mark pattern can be captured by visual imaging; such as Figure 5 As shown, by utilizing the characteristics of the adjustable focal length of the visual imaging lens and the fixed growth direction, drift direction, etc. of the epitaxial growth pattern, the focal length of the visual imaging is adjusted to change the imaging pattern from a clear pattern to a blurred pattern. Through this method, the epitaxial growth pattern is used to filter out the clutter and interference patterns (i.e., the drifted patterns and deformed patterns) formed by the lithography alignment marks after epitaxial growth, and the relatively sharp alignment mark signal (i.e., the coarse pre-alignment mark) of the lithography alignment mark before epitaxial growth is obtained. In this way, the alignment pass rate of the epitaxial wafer can be increased from 50% to 100%.

[0029] In step two, a lithography alignment lens is used to place the lithography alignment mark to improve the readiness and facilitate correspondence with the lithography machine.

[0030] The wafer in step four is subjected to epitaxial growth in an epitaxial furnace, with stable furnace temperature and good repeatability.

[0031] The epitaxial furnace adopts high-frequency induction heating, without the need for warm-up time, which speeds up the epitaxial growth rate.

[0032] The wafer in step four is epitaxially grown using the vapor phase epitaxy process, which can ensure the control of resistivity.

[0033] The above specific implementation manners are the preferred embodiments of the present invention and cannot limit the present invention. Any other changes or other equivalent replacement methods that do not deviate from the technical solution of the present invention are included in the protection scope of the present invention.

Claims

1. A method for improving the alignment pass rate of epitaxially grown wafers, characterized in that: It includes the following steps: Step 1: Get the original layout; Step 2: Precise photolithography alignment requires placing photolithography alignment marks on the original layout; Step 3: Leave the photolithography alignment mark on the wafer by etching; The lithography alignment marks have sharp edges and corners. Under normal focusing conditions, the drift and deformation of the lithography alignment marks can be captured by visual imaging. Step 4: Epitaxial growth is performed on the wafer engraved with the photolithography alignment mark to generate an epitaxial growth pattern. The photolithography alignment mark will drift and deform due to the unique characteristics of epitaxial growth in the epitaxial process. By utilizing the adjustable focal length of the visual imaging lens and the fixed growth direction and drift direction characteristics of the epitaxial growth pattern, the focal length of the visual imaging is adjusted to change the imaging pattern from a clear pattern to a blurred pattern, and the noise and interference pattern formed by the photolithography alignment mark after epitaxial growth are filtered out, and the relatively sharp alignment mark signal of the photolithography alignment mark before epitaxial growth is obtained.

2. The method for improving the alignment pass rate of epitaxially grown wafers according to claim 1, wherein: The original layout in step 1 is obtained through layout design software.

3. The method for improving the alignment pass rate of epitaxially grown wafers according to claim 1, wherein: The photolithography alignment marks include at least one group of coarse alignment marks and one group of fine alignment marks.

4. The method for improving the alignment pass rate of epitaxially grown wafers according to claim 1, wherein: In the step 2, a photolithography alignment lens is used to place a photolithography alignment mark.

5. The method for improving the alignment pass rate of epitaxially grown wafers according to claim 1, wherein: The wafer in step 4 is epitaxially grown in an epitaxial furnace.

6. The method for improving the alignment pass rate of epitaxially grown wafers according to claim 5, wherein: The epitaxial furnace adopts a high-frequency induction heating method.

7. The method for improving the alignment pass rate of epitaxially grown wafers according to claim 1, wherein: The wafer in step 4 is epitaxially grown using a vapor phase epitaxy process.

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