Method for improving the profile after filling the interlayer dielectric layer in an embedded flash memory structure

Abstract

The present invention discloses a method for improving the profile of an interlayer dielectric layer after filling in an embedded flash memory structure. The method comprises the following steps: Step 1: reducing the height of the flash memory cell; Step 2: adjusting the profile of the flash memory cell shoulder by wet etching, so that the profile of the ILD layer after HDP filling is smoother, facilitating subsequent TEOS filling. The present invention makes the flash memory cell shoulder smoother, and the smoother shoulder also makes the profile of the ILD layer after HDP filling smoother and less concave, facilitating subsequent TEOS filling and preventing the formation of voids. The longer the wet etching time, the smoother the profile after HDP filling.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a method for improving the profile of an interlayer dielectric layer after filling in an embedded flash memory structure. Background Art

[0002] In embedded flash memory structures, after the ILD (interlayer dielectric) layer is filled with oxide using high-density plasma (HDP), a layer of TEOS (tetraethyl orthosilicate) is deposited using plasma-enhanced CVD (PECVD). The profile of the flash memory cell affects the profile of the interlayer dielectric layer after filling. The high aspect ratio and protruding cell shoulders make the profile after ILD HDP filling unfavorable for TEOS filling, resulting in voids at the interface between TEOS and HDP, leading to bit line bridges. Summary of the Invention

[0003] In view of the above situation, in order to overcome the defects of the prior art, the present invention provides a method for improving the profile of an interlayer dielectric layer after filling in an embedded flash memory structure.

[0004] The present invention solves the above technical problems through the following technical solutions: a method for improving the profile of an interlayer dielectric layer after filling in an embedded flash memory structure, characterized in that it comprises the following steps:

[0005] Step 1: lowering the height of the flash memory unit;

[0006] Step 2: Adjust the profile of the flash memory cell shoulder by wet etching to make the profile smoother after HDP filling, which is conducive to TEOS filling.

[0007] Preferably, the first step is to adjust the chemical mechanical polishing process conditions for forming the word line pattern, thereby reducing the height of the flash memory cell.

[0008] Preferably, after reducing the height of the flash memory cells in step 1, the aspect ratio between the flash memory cells is reduced, which is beneficial for filling the ILD layer with oxide using a high-density plasma method.

[0009] Preferably, in step 2, after adjusting the profile of the flash memory cell shoulder by wet etching, the profile of the flash memory cell shoulder is smooth. The smooth shoulder of the flash memory cell makes the profile of the ILD layer smooth after HDP filling, which is beneficial to the subsequent PECVD deposited TEOS filling.

[0010] Preferably, the wet etching time is sixty seconds to eighty seconds.

[0011] The positive improvement effect of the present invention is that the present invention makes the shoulders of the flash memory unit smoother, and the smooth shoulders make the contour after HDP filling smoother and not too concave, which is beneficial to the filling of TEOS and prevents the generation of voids. The longer the wet etching time (60-80S), the smoother the contour after HDP filling. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The present invention is a flow chart of a method for improving the profile of an interlayer dielectric layer in an embedded flash memory structure after filling.

[0013] Figure 2 This is a schematic diagram of adjusting the profile of the flash memory cell shoulder using a wet etching method according to the present invention.

[0014] Figure 3 Schematic diagram of the outline structure of the interlayer dielectric layer after high-density plasma filling. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0016] like Figure 1 As shown, the method for improving the profile of the interlayer dielectric layer after filling in the embedded flash memory structure of the present invention includes the following steps:

[0017] Step 1: Lowering the height of the flash memory cell. Specifically, the WLCMP (Chemical Mechanical Polish) process conditions used to form the wordline pattern are adjusted to reduce the cell height. The height of the wordline reflects the cell height. After wordline polysilicon (poly) deposition, CMP (Chemical Mechanical Polish) is used to polish away excess polysilicon and flatten the wordline. Adjusting the WLCMP process conditions reduces the cell height and adjusts the cell shoulder profile. After the height of the flash memory cell is reduced, the interlayer dielectric layer is filled with oxide using a high-density plasma (ILD HDP) method. The aspect ratio between the flash memory cells is reduced, which is conducive to ILD HDP filling. However, excessive CMP polishing in this step will damage the offset spacer dielectric layer structure, and the polishing will contact three materials: oxide, SiN (silicon nitride), and polysilicon (poly). Due to the different polishing rates of the three materials, while the height of the word line is reduced, the oxide polishing rate is faster, and there will be a protrusion at the junction of oxide and silicon nitride at the shoulder of the flash memory cell. When the ILD layer is subsequently filled with HDP, the existence of the protruding shoulder causes the contour of the HDP to be severely concave after filling. The subsequent ILD TEOS filling will produce a void at the junction of TESO and HDP, resulting in a CT bridge.

[0018] Step 2: Adjust the outline of the flash memory cell shoulder by WET (wet etching) to make the outline smoother after HDP filling (such as Figure 2 After the HDP filling aspect ratio is reduced by chemical mechanical polishing to form the word line pattern, after the SiN (silicon nitride) of the flash memory cell is removed, WET etching is added to adjust the profile of the flash memory cell shoulder, making the flash memory cell shoulder smoother. The smooth shoulder makes the profile after HDP filling smoother and less concave (as shown in the figure). Figure 3 (as shown), which facilitates subsequent PECVD-deposited TEOS filling. A further layer of TEOS (tetraethyl orthosilicate) is deposited via PECVD (plasma-enhanced CVD) to facilitate TEOS filling and prevent void formation. A longer wet etch time results in a smoother profile after HDP filling. A wet etch time of 60 to 80 seconds (preferably 70 seconds) results in a smoother profile after HDP filling.

[0019] The above specific implementation manner is a preferred embodiment of the present invention and does not limit the present invention. Any other changes or other equivalent replacement methods that do not deviate from the technical solution of the present invention are included in the protection scope of the present invention.

Claims

1. A method for improving the profile of an interlayer dielectric layer after filling in an embedded flash memory structure, characterized in that: It includes the following steps: Step 1: After word line polysilicon is deposited, the chemical mechanical polishing process conditions for forming the word line pattern are adjusted to remove excess polysilicon and flatten the surface by chemical mechanical polishing to reduce the height of the flash memory cell. Step 2: Adjust the profile of the flash memory cell shoulder by wet etching; In step three, a high-density plasma method is used to fill oxide between the flash memory cells, and then a layer of TEOS is deposited by PECVD.

2. The method for improving the profile of an interlayer dielectric layer after filling in an embedded flash memory structure according to claim 1, wherein: The wet etching time is 60 to 80 seconds.

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