Method for forming a transistor structure

Abstract

A method for forming first and second transistor structures, wherein the first and second transistor structures are spaced apart by an insulating wall, comprising: forming first and second semiconductor layer stacks on a semiconductor layer of a substrate, each layer stack including a sacrificial layer and a channel layer in a bottom-up direction, wherein the layer stacks are spaced apart by trenches extending into the semiconductor layer substrate, and the trenches are filled with an insulating wall material to form an insulating wall; processing the layer stacks to form first and second transistor structures in first and second device regions, respectively, the processing including forming source regions and drain regions and forming gate stacks; further comprising, before processing: removing the sacrificial layer of each layer stack by etching to form corresponding cavities under the channel layers of the first and second layer stacks on either side of the insulating wall, the channel layers being supported by the insulating wall; depositing a bottom insulating material in the cavities; after processing, the bottom insulating material forms a bottom insulating layer under the source regions, drain regions, and channel regions on either side of the insulating wall.

Description

Technical Field

[0001] The inventive concept relates to a method for forming a transistor structure. Background Art

[0002] Modern semiconductor integrated circuit technology includes horizontal-channel transistors, where a FinFET having a gate spanning a fin-shaped semiconductor channel portion is an example. Other examples include horizontal or lateral nanowire FETs (NWFETs) and nanosheet FETs (NSHFETs). These transistor structures typically include a source, a drain, a channel including one or more nanowire or nanosheet channel portions extending horizontally (i.e., along the substrate), and a gate stack. In a gate-all-around (GAA) design, the channel portions may extend through the gate stack such that the gate stack surrounds one or more of these channel portions all around.

[0003] A "forksheet" device is a design that allows for providing an n-type NSHFET and a p-type NSHFET adjacent to each other, each controlled by a fork-shaped gate structure and separated by an insulating wall. Before gate patterning, an insulating wall may be formed between the p-type device region and the n-type device region. This wall may separate the p-gate trench from the n-gate trench, allowing for a closer n-to-p spacing.

[0004] In horizontal-channel transistor structures (e.g., NWFETs, NSHFETs, and forksheets), electrical insulation (e.g., "bottom insulation") may be desired to mitigate charge carrier leakage from, for example, the source, drain, or channel into the underlying semiconductor substrate. However, existing processing techniques may be relatively complex and challenging to apply at more aggressive device dimensions. Summary of the Invention

[0005] An object of the inventive concept is to provide an improved method that allows for providing electrical insulation under a horizontal-channel transistor structure. Additional and alternative objects may be understood from the following.

[0006] According to an aspect of the inventive concept, there is provided a method for forming a first transistor structure and a second transistor structure in a first device region and a second device region of a substrate, respectively, each transistor structure including a source region, a drain region, a channel region extending between the source region and the drain region in a first direction along the substrate, and a gate stack at the channel region, wherein the first transistor structure and the second transistor structure are spaced apart by an insulating wall extending in the first direction in a second direction along the substrate transverse to the first direction, and the method includes:

[0007] A first semiconductor layer stack in the first device region and a second semiconductor layer stack in the second device region are formed on the semiconductor layer of the substrate. Each layer stack includes a sacrificial layer and a channel layer in a bottom-up direction. The layer stacks are separated by trenches extending into the semiconductor layer of the substrate, and the trenches are filled with insulating wall material to form the insulating wall; and

[0008] The layer stacks are processed to form the first transistor structure and the second transistor structure in the first device region and the second device region respectively. The processing includes forming the source regions and the drain regions and forming the gate stacks;

[0009] The method further includes, before the processing:

[0010] The sacrificial layer of each layer stack is removed by etching, so as to form corresponding cavities under the channel layers of the first layer stack and the second layer stack on either side of the insulating wall. The channel layers are supported by the insulating wall; and

[0011] Bottom insulating material is deposited in the cavities;

[0012] Wherein, after the processing of the layer stacks for forming the first transistor structure and the second transistor structure, the bottom insulating material forms a bottom insulating layer under the source region, the drain region and the channel region on either side of the insulating wall.

[0013] According to the method of the present invention, the sacrificial layer under these channel layers can be "replaced" by a bottom insulating layer, which is used to electrically insulate the semiconductor layer from the channel regions of the first transistor structure and the second transistor structure and the source regions and the drain regions.

[0014] Since this replacement process is performed before the formation of the source / drain regions and the gate stack, these bottom insulating layers can extend continuously under the source region, the drain region and the channel region. In addition, the method is compatible with the source / drain and gate stack formation processes (such as source / drain epitaxy and replacement metal gate (RMG) processes) conventionally used in advanced technology nodes. The related advantage is that each of these bottom insulating layers can extend continuously under multiple pairs of the first transistor structure and the second transistor structure formed along the insulating wall.

[0015] The replacement process is facilitated by the insulating wall extending into the semiconductor layer of the lower layer of the substrate. Thus, the height of the insulating wall (and correspondingly the depth of the trench) can exceed the height of the layer stack above the (upper surface of the) semiconductor layer of the substrate. Thus, the base portion of the insulating wall can be anchored in the semiconductor layer of the lower layer. Thus, when the sacrificial layer is removed, the insulating wall can act as a support structure for the remaining layers of the layer stack (e.g., the channel layer). Consequently, the remaining layers can be suspended above the cavities by the insulating wall.

[0016] The insulating wall can additionally confer advantages corresponding to those of the fin device, e.g., providing physical and electrical isolation between these transistor structures and the corresponding gate stacks. More specifically, the insulating wall can simplify gate stack patterning and enable reduced sensitivity to mask edge placement error (EPE), since the gate stacks can be self-aligned with the respective channel regions of the transistor structures. For complementary transistor pairs, where the first device region can be an n-type device region and the second device region can be a p-type device region, this can provide further advantages during work function metal (WFM) fill and etchback in the RMG process. Additionally, the insulating wall can reduce the risk of source / drain merging of these transistor structures, e.g., during n- and p-type epitaxy.

[0017] The channel regions of these transistor structures extend in a first direction along the substrate. The first direction and the second direction can be considered "horizontal" directions (or equivalently "lateral" directions). Thus, the first and second (horizontal) directions should be understood herein as the respective directions / orientations along / parallel to the main extension plane or main surface of the substrate or the semiconductor layer of the substrate.

[0018] The terms "bottom-up" or "vertical" can be used to refer to the direction / orientation orthogonal to the main extension plane, main surface of the substrate supporting these transistor structures. Meanwhile, terms such as "above", "on", "top", "upward" and "below", "under", "bottom", "beneath", "downward" can be used to refer to relative positions as viewed along the vertical direction, and thus do not imply an absolute orientation of the substrate.

[0019] The sacrificial layers and the channel layers are layers of different semiconductor materials, where the sacrificial layers can be selectively removed with respect to the channel layers. That is, the sacrificial layers can be selectively removed with respect to the channel layers by selectively etching the material of the sacrificial layers (the sacrificial material) with respect to the material of the channel layers (the channel material). Thus, the sacrificial layers / materials can be removed in an etching process that preserves the channel layer / material. That is, the selective removal of the sacrificial layers can include etching the sacrificial material at a greater rate than the channel material.

[0020] These sacrificial layers and these channel layers can correspondingly be, for example, semiconductor layers epitaxially grown (e.g., epitaxially) of a sacrificial material and a channel material. This enables high-quality material layers with a favorable degree of control over composition and dimensions.

[0021] These sacrificial layers and these channel layers can be layers including Si, where these sacrificial layers have a greater Ge content than these channel layers. These sacrificial layers and these channel layers can each be SiGe layers. Alternatively, these sacrificial layers can be SiGe layers, and these channel layers can be formed of Si layers. These sacrificial layers can be formed of Si 1-y Ge y and these channel layers can be formed of Si 1-z Ge z where y > z. The lower or zero Ge content in these channel layers (i.e., y > z ≥ 0) can facilitate selective processing (e.g., removal) of these sacrificial layers. The Ge content of these sacrificial layers can advantageously be at least 20% greater than the Ge content of these channel layers (i.e., y ≥ z + 0.2).

[0022] Removing the sacrificial layer of each layer stack can include etching these sacrificial layers of these layer stacks simultaneously from a side facing away from the insulating wall (i.e., the corresponding side of these layer stacks).

[0023] The bottom insulating material can be conformally deposited on these layer stacks with a certain thickness such that the cavities are filled with the bottom insulating material, and then the method can include removing the bottom insulating material from these layer stacks above the level of these cavities. The bottom insulating material can thus form a liner layer covering these layer stacks. Conformal deposition enables the bottom insulating material to be deposited within these cavities. Deposition can be stopped when these cavities are closed or "pinched-off" by the bottom insulating material or afterwards.

[0024] After depositing the bottom insulating material, a second insulating material (e.g., an oxide such as silicon oxide) can be deposited. The second insulating material can cover these layer stacks and the bottom insulating material on these layer stacks. Afterwards, a simultaneous etchback of the second insulating material and the bottom insulating material in a top-down direction can be performed to expose these layer stacks above the level of these cavities. The upper portion of these layer stacks (i.e., above these cavities) can thus be exposed from the bottom insulating material (e.g., liner) and the second insulating material, while the bottom insulating material is retained within these cavities. The etched-back second insulating material can remain as an insulating layer embedded in the lower portion of these layer stacks. The insulating layer can be retained to form a shallow trench isolation (STI) adjacent to these transistor structures.

[0025] This method can be advantageously used to form a stacked nanosheet transistor structure including a nanosheet channel portion (e.g., a "forked-sheet" FET structure). However, the method is not limited to transistor structures including a stack of nanosheet channel portions, but is generally applicable to forming transistor structures including one or more channel layer portions such as nanowires or nanosheets, e.g., a field-effect transistor (FET) structure.

[0026] In a method for forming a first transistor structure and a second transistor structure each including a plurality of channel layer portions, these sacrificial layers can be referred to as "first" sacrificial layers, and each layer stack can include the first sacrificial layer, a plurality of channel layers, and a plurality of "second" sacrificial layers. These "first" sacrificial layers can be referred to as "bottom" sacrificial layers, and these "second" sacrificial layers can be referred to as "upper" sacrificial layers. These second sacrificial layers can be alternating with these channel layers. These channel layers can be formed of a material (channel material) different from these first sacrificial layers and these second sacrificial layers. The method can include: selectively removing the first sacrificial layer of each layer stack for these second sacrificial layers and these channel layers. Subsequent processing of these layer stacks (except for the formation of source and drain and the formation of the gate stack) can include forming released channel layer portions by selectively etching these second sacrificial layers for these channel layers. These gate stacks can then be formed along these channel layer portions.

[0027] In other words, these first sacrificial layers can be removed in a first etching process such that these second sacrificial layers and these channel layers are retained. Second sacrificial layer portions can be removed in a second etching process such that these channel layer portions are retained.

[0028] These channel layer portions in corresponding device regions can form the channel regions of the corresponding transistor structures. These channel layer portions can be spaced apart by gaps or spaces, i.e., thus being "released".

[0029] Each gate stack can partially enclose these channel portions of the transistor structure. These gate stacks can be formed between (i.e., in the gaps) and along these released channel portions in corresponding device regions. In other words, these channel layer portions can extend through the corresponding gate stacks.

[0030] Depending on the configuration of these layer stacks, each gate stack can be formed along at least two sides and in any case at most three sides of the channel layer portion. The presence of this insulating wall can block the formation of the gate stack along the sidewall surfaces of these channel portions facing the trench / insulating wall.

[0031] There are different ways for selectively removing these first sacrificial layers for these second sacrificial layers:

[0032] According to the first approach, these first sacrificial layers can be formed of a first sacrificial material. These second sacrificial layers can be formed of a second sacrificial material (different from the first sacrificial material). These channel layers can be formed of a channel material (different from the first sacrificial material and the second sacrificial material). Thus, these first sacrificial layers can be selectively removed with respect to these second sacrificial layers and these channel layers by selectively etching the first sacrificial material with respect to the second sacrificial material and the channel material. Therefore, the first sacrificial layer / material can be removed during an etching process that preserves the second sacrificial layer / material and the channel layer / material. That is, the selective removal of these first sacrificial layers can include etching the first sacrificial material at a rate greater than that of the second sacrificial material and the channel material. By way of example, the selective etching of material “A” (e.g., the first sacrificial material) relative to material “B” (e.g., the second sacrificial material) can be 10:1 or greater. That is, the removal rate of material “A” can be at least an order of magnitude greater than the removal rate of material “B”.

[0033] In each layer stack, the bottommost second sacrificial layer can be formed on the first sacrificial layer. Thus, each layer stack can include a repeating sequence of the first / bottom sacrificial layer and the second / upper sacrificial layer on the first / bottom sacrificial layer and the channel layer on the second / upper sacrificial layer. Therefore, a gap or space can also be formed below the bottommost channel layer portion in each device region (i.e., between these bottom insulating layers and these bottommost channel layer portions). This configuration enables these gate stacks to also be formed along three sides of these bottommost channel layer portions.

[0034] The first sacrificial material can be Si 1-x Ge x , the second sacrificial material can be Si 1-y Ge y , and the channel material can be Si 1-z Ge z , where x > y > z. A higher Ge content in these first sacrificial layers than in these second sacrificial layers and these channel layers can facilitate the selective processing (e.g., etching) of these first sacrificial layers. Correspondingly, a higher Ge content in these second sacrificial layers than in these channel layers can facilitate the selective processing (e.g., etching) of these second sacrificial layers. The Ge content of these first sacrificial layers can advantageously be at least 20% greater than the Ge content of these first sacrificial layers (i.e., x ≥ y + 0.2). The Ge content of these second sacrificial layers can advantageously be at least 20% greater than the Ge content of these channel layers (i.e., y ≥ z + 0.2). These channel layers can be Si layers (i.e., z = 0).

[0035] According to an alternative second approach, each first sacrificial layer may include a lower thickness portion and an upper thickness portion, and the bottommost channel layer is formed on the upper thickness portion. The method may further include: forming a spacer layer on sidewall surfaces of the first layer stack and the second layer stack facing away from the insulating wall, the spacer layer covering sidewall surfaces of the channel layers and the second sacrificial layers; and at least exposing the lower thickness portion of the first sacrificial layers, and wherein the first sacrificial layers are selectively removed for the second sacrificial layers by etching the first sacrificial layers using the spacer layer as an etching mask.

[0036] Thus, the first sacrificial layers can be removed during an etching process that preserves the second sacrificial layers. That is, the selective removal of the first sacrificial layers can include etching the first sacrificial material while masking the second sacrificial layers. If a selective etching process for the materials of the first sacrificial layers and the second sacrificial layers is not available, then using a spacer layer (e.g., a sidewall spacer layer) as an etching mask facilitates the selective removal of the first sacrificial layers even if the first sacrificial layers and the second sacrificial layers are formed of the same material (i.e., the first sacrificial material and the second sacrificial material are the same material).

[0037] The lower thickness portion of each first sacrificial layer may have a greater width than the upper thickness portion such that an upper surface of the lower thickness portion is exposed adjacent to the upper thickness portion. Forming the spacer layer may include:

[0038] conformally depositing spacer material over the first layer stack and the second layer stack; and

[0039] etching back the deposited spacer material in a top-down direction such that the upper surfaces of the lower thickness portions are exposed and the spacer layer remains on the sidewall surfaces of the first layer stack and the second layer stack.

[0040] This can facilitate forming a spacer layer with a desired extension, i.e., masking the channel layers and sidewall surface portions of the second sacrificial layers and exposing at least a portion of the first sacrificial layers.

[0041] The first sacrificial layers and the second sacrificial layers may be formed of Si 1-y Ge y and the channel layers may be formed of Si 1-z Ge z where y > z. As discussed above, a higher Ge content in these sacrificial layers than in these channel layers can facilitate selective processing (e.g., etching) of these sacrificial layers.

[0042] According to an aspect of the method of the present invention, forming the layer stacks may include:

[0043] Epitaxially grow a sacrificial material layer and a channel material layer, and

[0044] pattern the epitaxially grown sacrificial material layer and channel material layer to form the trench and the first layer stack and the second layer stack.

[0045] As discussed above, the epitaxially grown layer can be a layer including Si, wherein the (multiple) sacrificial material has a greater Ge content than the channel material.

[0046] Each layer stack can be patterned to form an elongated (e.g., fin-shaped) layer stack extending along the first direction. These layer stacks can protrude above the semiconductor layer of the substrate (e.g., in the vertical direction).

[0047] Each layer stack can be patterned such that the channel layers form channel nanowires or channel nanosheets.

[0048] The method can include forming the trench and filling the trench with the insulating wall material before forming the first layer stack and the second layer stack. Sequentially forming the trench and these layer stacks can facilitate forming the trench to extend into the semiconductor layer of the substrate. In addition, the insulating wall material can mask the trench when forming these layer stacks.

[0049] Processing of these layer stacks can further include:

[0050] forming a sacrificial gate extending across these layer stacks and the insulating wall;

[0051] etching these layer stacks on either side of the sacrificial gate;

[0052] forming corresponding source regions and drain regions of the first transistor structure and the second transistor structure on either side of the sacrificial gate by epitaxy, wherein these source regions and these drain regions are formed above the bottom insulating layer; and

[0053] replacing the sacrificial gate with the gate stack after forming these source regions and these drain regions.

[0054] Thus, these gate stacks can be formed during the RMG process. During the formation of these source regions and these drain regions (e.g., including layer stack etching and epitaxy), the sacrificial gate can act as a mask. Thus, these source / drain regions can be formed in a self-aligned manner with respect to these gate stacks / channel regions, where the insulating wall can act as a separator between the gate stacks of the first transistor structure and the second transistor structure. In addition, the insulating wall can facilitate defining the source / drain epitaxy of the first transistor structure to the first device region and the source / drain epitaxy of the first transistor structure to the second device region.

[0055] Etching of these layer stacks can include etching back these layer stacks on each side of the sacrificial gate and stopping on the bottom insulating layer.

[0056] The method can further include: after the epitaxy, depositing a capping material that covers these source regions and these drain regions and surrounds the sacrificial gate; and

[0057] removing the sacrificial gate to expose the first layer stack and the second layer stack in the first gate trench and the second gate trench, respectively, where the first gate trench and the second gate trench are separated by the insulating wall;

[0058] wherein, these gate stacks can then be formed in the first gate trench and the second gate trench.

[0059] This facilitates the formation of gate stacks of different compositions for the first transistor structure and the second transistor structure.

[0060] The first transistor structure can be, for example, a p-type transistor structure, and the second transistor structure can be an n-type transistor structure.

[0061] Forming these gate stacks can include: depositing a p-type work function metal (WFM) in the first gate trench and the second gate trench along the channel regions of the first nanosheet transistor structure and the second nanosheet transistor structure;

[0062] forming a trench mask over the first gate trench, and etching away the p-type WFM in the second gate trench by etching while the trench mask and the insulating wall act as an etch mask for the p-type WFM in the first gate trench; and

[0063] subsequently depositing an n-type WFM in at least the second gate trench along the channel region of the second nanosheet transistor structure.

[0064] The insulating wall facilitates the selective removal of the p-type WFM from the channel region of the second transistor structure because the insulating wall can act as a lateral etch stop that resists lateral over-etching of the p-type WFM at the first channel portion. Additionally, the insulating wall can physically and electrically separate the p-type WFM and the n-type WFM. The n-type WFM can then be deposited in at least the second gate trench and optionally also in the first gate trench over the p-type WFM.

[0065] After removing the sacrificial gate and before forming the gate stacks, a released channel layer portion is formed by etching portions of the second sacrificial layer that are exposed in the first gate trench and the second gate trench, the etching being selective to the channel layers. Thus, a released channel layer portion can be formed in the gate trenches. Brief Description of the Drawings

[0066] The above and additional objects, features, and advantages of the inventive concept will be better understood from the following illustrative and non-limiting detailed description made with reference to the accompanying drawings. In the drawings, like reference numerals will be used for like elements unless otherwise stated.

[0067] Figure 1 is a flowchart of a method for forming a first transistor structure and a second transistor structure.

[0068] Figures 2 to 12 illustrates method steps for forming a nanosheet FET structure, where the bottom insulating layer is formed according to a first manner.

[0069] Figures 13 to 17 illustrates method steps for forming the bottom insulating layer according to a second manner. Detailed Description of the Embodiments

[0070] Figure 1 is a flowchart of a method 10 for forming a first transistor structure and a second transistor structure (e.g., a first FET structure and a second FET structure).

[0071] Method 10 includes step S12, which includes forming a first semiconductor layer stack, a second semiconductor layer stack, and an insulating wall. The layer stacks are on a semiconductor layer of a substrate. The first stack can be formed in a first device region (e.g., a p-type device region) of the substrate, and the second stack can be formed in a second device region (e.g., an n-type device region) of the substrate. The first stack and the second stack can have the same composition and include a bottom sacrificial layer and a channel layer located above the bottom sacrificial layer. The layer stacks are separated by trenches extending into the semiconductor layer substrate. The trenches are filled with an insulating wall material to form the insulating wall.

[0072] Method 10 further includes step S14, which includes etching to remove the bottom sacrificial layer of each layer stack, thereby forming corresponding cavities on either side of the insulating wall below the channel layer. Through the insulating wall, the remaining layers of the layer stack can be supported above the cavities.

[0073] Method 10 further includes step S16, which includes depositing bottom insulating material in the cavities formed on each side of the insulating wall in step S14. Thus, through steps S14 and S16, the bottom sacrificial layer can be replaced by the bottom insulating material, that is, selectively for the channel layer. The bottom insulating material can form bottom insulating layers on each side of the insulating wall. The bottom insulating layers can continuously extend below the source region and the drain region and the channel region of the transistor structures to be formed on either side of the insulating wall. Different ways for selectively replacing the bottom sacrificial layer below the channel layer will be disclosed hereinafter.

[0074] After forming the bottom insulating layer, the method can continue with the processing of the layer stack as indicated, so as to form the first transistor structure and the second transistor structure. In Figure 1 this, the processing is indicated as "processing block" 20, and as shown, it can include: forming source regions and drain regions for the first semiconductor structure and the second semiconductor structure (step S22); and forming gate stacks for the first transistor structure and the second transistor structure (step S24).

[0075] Processing block 20 can further include a certain number of additional processing steps as indicated by the dashed box, which depends, for example, on the composition of the layer structure, the type of transistor structure to be formed, etc. For example, processing block 20 can include the formation of sacrificial gates, the release of channel layer portions, the formation of replacement metal gates, and various masking and etching steps, as can be illustrated hereinafter.

[0076] The bottom sacrificial layer has a different composition from the channel layer, that is, it is formed of a material different from the channel layer. Therefore, an etching process selective to the material of the sacrificial layer (i.e., etching the material of the bottom sacrificial layer at a greater rate than the material of the channel layer (and optionally additional layers of the layer stack)) can be employed to selectively remove the bottom sacrificial layer for the channel layer. Any suitable dry etching process or wet etching process, or a combination of a dry etching process and a wet etching process can be employed. According to an example, the bottom sacrificial layer can be an epitaxial layer of a SiGe alloy (e.g., having a Ge content of 20%-35%), and the channel layer can be an epitaxial layer of Si. The bottom sacrificial material can more generally be epitaxially grown Si 1-y Ge y and the channel material can be epitaxially grown Si 1-z Ge z, where y > z ≥ 0. By way of example, in a layer stack including Si 1-y Ge y layers and Si 1-z Ge z layers (where y ≥ z + 0.2), HCl-based dry etching can provide an etching rate of Si 1-y Ge y layers that exceeds the etching rate of Si 1-z Ge z layers by at least one order of magnitude. Another example is wet etching with an ammonia peroxide mixture (APM). As can be understood, a larger difference in Ge content can increase the relative etching rate of the bottom sacrificial material with respect to the channel material. At the same time, the larger difference may affect the material quality of the channel layer, and a suitable composition may thus typically involve a trade-off between the relative etching rate on the one hand and the channel material quality on the other hand.

[0077] Although this method is suitable for layer stacks including a sacrificial layer having a higher Ge content than the channel layer, the method is not limited thereto, and the reverse relationship is also possible. More generally, it is contemplated that the method is applicable to any semiconductor layer stack including sacrificial layers and channel layers of different compositions, such that selective removal of the sacrificial layer is allowed.

[0078] The layer stacks may each include a bottom sacrificial layer and a single channel layer on the bottom sacrificial layer, thus allowing the formation of a transistor structure including a single channel layer portion on a bottom insulating layer. Alternatively, the layer stacks may each include an alternating sequence of channel layers and upper / second sacrificial layers above the bottom / first sacrificial layer. Such a configuration allows the formation of a transistor structure having corresponding channel regions that include a certain number of vertically distributed channel layer portions, the number corresponding to the number of channel layers in each layer stack. In this case, removal of the bottom / first sacrificial layer of each layer stack can be selective with respect to both the upper / second sacrificial layer and the channel layer, to allow selective replacement of the bottom sacrificial layer with a bottom insulating material. If the bottom sacrificial layer is formed of a material different from both the upper sacrificial layer and the channel layer, the bottom sacrificial layer can be selectively removed by etching. For example, the bottom sacrificial layer may be formed of Si 1-x Ge x formed, the second sacrificial layer may be formed of Si 1-y Ge y formed, and the channel layer may be formed of Si 1-z Ge z formed, where x > y > z, for example, x ≥ y + 0.2 and y ≥ z + 0.2. If the bottom sacrificial layer and the upper sacrificial layer are formed of the same material (e.g., Si 1-y Ge y ) but different from the channel layer (e.g., Si 1-zGe z , for example, formed by y≥z + 0.2), the bottom sacrificial layer can be selectively removed by masking the sacrificial layer and the channel layer during etching. In any case, process block 20 can further include forming a released channel layer portion by selectively etching the second sacrificial layer for the channel layer.

[0079] As part of step S12, a layer stack (e.g., including a bottom sacrificial layer, an upper sacrificial layer, and a channel layer) can be formed by epitaxially growing a sacrificial material layer and a channel material layer. The (bottom / first) sacrificial material layer can be grown first on the semiconductor layer of the substrate. Thereafter, an alternating sequence of the channel material layer and the (upper / second) sacrificial material can be grown sequentially. Chemical vapor deposition (CVD) processes or any other conventional suitable deposition methods can be used.

[0080] The substrate can be of a conventional type, e.g., a substrate suitable for complementary metal oxide semiconductor (CMOS) processing and including (as the topmost layer) a semiconductor layer of a composition that allows a layer stack to be formed thereon. Substrate 100 can be, for example, a semiconductor bulk substrate, such as a Si substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate. Other examples include semiconductor-on-insulator (SOI) type substrates, such as a Si-on-insulator substrate, a Ge-on-insulator substrate, or a SiGe-on-insulator substrate.

[0081] In step S12, the epitaxially grown sacrificial material layer and channel material layer can be further patterned to form trenches (which will be filled with an insulating wall material) and a first layer stack and a second layer stack. The patterning can include etching the epitaxially grown material layers while masking the regions where the layer stack is to be formed. Single or multiple patterning techniques can be employed, e.g., self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), or some other conventional self-aligned multiple patterning (SAMP) techniques. The layer stack can be patterned to form a fin-shaped layer stack, including, for example, a channel layer in the form of channel nanosheets (i.e., a nanosheet-shaped channel layer), thereby allowing the formation of a nanosheet-based transistor structure. By way of example, the nanosheets can have a width in the range of 10 nm to 30 nm (e.g., as seen across the length of the channel region) and a thickness in the range of 3 nm to 10 nm. The layer stack can also be patterned such that the channel layer forms a nanowire-shaped layer. By way of example, the nanowires can have a thickness similar to that of the example nanosheets, yet with a smaller width, e.g., 3 nm to 10 nm.

[0082] Now reference will be made to Figures 2 to 12Disclosed is a method for forming a nanosheet FET structure, wherein the bottom insulating layer is formed according to a first manner. However, the method is not limited to transistor structures including stacks of nanosheet channel portions, but is generally applicable to forming FET-type transistor structures including one or more channel layer portions such as nanowires or nanosheets.

[0083] Figure 2 A portion of the semiconductor layer of the substrate is shown in cross-section, commonly designated 100 in the figure and hereinafter referred to as the "substrate layer" for brevity. In Figure 2 it, the directions X and Y respectively indicate a first horizontal direction and a second horizontal direction (along the substrate layer 100). The direction Z indicates a vertical or bottom-up direction (orthogonal to the substrate layer 100). The cross-section is taken along the YZ plane.

[0084] The method includes forming a first semiconductor layer stack 102 and a second semiconductor layer stack 104 on the substrate layer 100, the layer stacks 102, 104 being spaced apart by a trench 107 filled with an insulating material along the Y direction to form an insulating wall 108 (e.g., Figure 1 step S12 of method 10). The trench 107 can be formed to extend along an intended boundary between a first device region 118 and a second device region 120. The first device region 118 and the second device region 120 can be regions in which a p-type device and an n-type device are to be formed, respectively. Thus, the position of the trench 107 can determine the position of the PN boundary between the first transistor structure and the second transistor structure to be formed. The trench 107 can be formed, for example, to have a width in the range of 5 nm to 20 nm.

[0085] The following description will relate to the processing of a pair of layer stacks 102, 104. However, as indicated in the figure, a certain number of such pairs can be formed on the substrate layer 100 and processed in parallel. As can be understood, the substrate layer 100 can typically exhibit a much larger lateral / horizontal extent than that shown, extending beyond the cross-section shown. It can further be noted that the relative dimensions of the shown structure (e.g., the relative thickness of the layers) are only schematic and can be different from the physical device structure for the sake of clarity of illustration.

[0086] The layer stacks 102, 104 can be formed as fin-like structures elongated in the X direction. As shown, each layer stack 102, 104 can include, in a bottom-up direction, a bottom / first sacrificial layer 110, and an alternating sequence of an upper / second sacrificial layer 112 and a channel layer 114. Figure 2The number of the upper sacrificial layer 112 and the channel layer 114 shown is only an example, and a greater or smaller number of the upper sacrificial layer 112 and the channel layer 114 may be changed. The same reference numerals are used to designate the sacrificial layers 110, 112 and the channel layer 114 in the first layer stack 102 and the second layer stack 104. However, it should be understood that each layer stack 102, 104 may include corresponding sacrificial layer 114 and channel layer 116 on either side of the insulating wall 108.

[0087] As Figure 2 indicated, the bottom sacrificial layer 110, the upper sacrificial layer 112 and the channel layer 114 may form a nanosheet. As shown, the topmost upper sacrificial layer 112b may optionally be formed to have a greater thickness so as to extend the height of the insulating wall 112b above the topmost channel layer 114b. However, the following description also generally applies to other layer stack configurations, for example, layer stacks including sacrificial layers having a greater thickness than the channel layers formed as nanosheets (such that the vertical spacing of the channel layers can be increased), and layer stacks including sacrificial layers and channel layers formed as nanowires (such that a nanowire transistor structure can be formed). As another example, the thickness of the bottom sacrificial layer 110 may generally be adapted to correspond to the desired thickness of the bottom insulating layer to be formed.

[0088] The bottommost second sacrificial layer 112a may be formed on (i.e., adjacent to) the bottom sacrificial layer 110. This enables the formation of a gate stack that also extends under the channel layer portion of the bottommost channel layer 114a. However, if such a gate stack configuration is not desired, the bottommost channel layer 114 may also be formed on the bottom sacrificial layer 110. As further shown in the figure, the topmost channel layer 114b of each layer stack 102, 104 is formed under the topmost sacrificial layer 112b. This enables the formation of a gate stack that also extends above the channel layer portion of the topmost channel layer 114b. However, if such a gate stack configuration is not desired, the sacrificial layer on the topmost channel layer 114b may also be omitted.

[0089] The bottom sacrificial layer 110 may be formed of a first sacrificial material, the upper sacrificial layer 112 may be formed of a second sacrificial material, and the channel layer may be formed of a channel material. Any of the above-discussed examples of materials are possible. For example, the first sacrificial material may be Si 0.35 Ge 0.65 , the second sacrificial material may be Si 0.65 Ge 0.35 , and the channel material may be Si.

[0090] The layer stacks 102, 104 and the trench 107 can be formed by patterning epitaxially grown material layer stacks as discussed above. Various options are possible for forming the layer stacks 102, 104 and the trench 107: The trench 107 can be patterned in the material layer stack using a first set of etch masks and then filled with an insulating wall material to form an insulating wall 108 therein. Subsequently, the layer stacks 102, 104 can be patterned on either side of the insulating wall using a second set of etch masks. Alternatively, a preliminary layer stack can first be patterned in the material layer stack using a first set of etch masks. Subsequently, the trench 107 can be patterned in the preliminary layer stack using a second set of etch masks to divide it into a first layer stack 102 and a second layer stack 104. Thereafter, the trench can be filled with an insulating wall material to form an insulating wall 108 therein. The reference numeral 116 indicates the portion of the etch mask (e.g., a material based on oxide, nitride or carbide) remaining on the layer stacks 102, 104 after patterning.

[0091] In either case, the insulating wall material can be conformally deposited before being etched isotropically or anisotropically (i.e., in a top-down direction) to remove the deposited insulating material outside the trench 107. The insulating wall material can be deposited with a thickness such that the insulating wall material deposited at the respective sidewalls of the trench 107 combines to "close" and thus fill the trench 107. By etching, the insulating material can be removed outside the trench 107 but retained in the "closed" trench 107. As can be appreciated, the insulating wall material filling the trench 107 can be subjected to etch-back (top-down), the amount of etch-back corresponding to the thickness of the conformally deposited insulating material outside the trench 107 (assuming isotropic etch stop when the insulating material has been removed outside the trench 107). The insulating wall material can be, for example, a material comprising nitride or oxide, advantageously a high-k material such as, for example, SiN, SiCO, SiCN or SiOCN deposited by ALD or CVD.

[0092] As Figure 2 shown, the trench 107 can be formed to extend into the substrate layer 110. The trench 107 can thus be formed to have a depth h1 that exceeds the height h2 of the layer stacks 102, 104 above the substrate layer 110. Thus, the base portion of the insulating wall 108 can be embedded in the substrate layer 110. This can impart structural stability, thereby reducing the risk of collapse of the layer stacks 102, 104 when the bottom sacrificial layer 110 is removed, as discussed below.

[0093] In Figure 3 which, etching has been carried out (e.g., Figure 1Step S14) of method 10 removes the bottom sacrificial layer 110 of each layer stack 102, 104. Thereby, corresponding cavities 122 have been formed on either side of the insulating wall 108 below the channel layer 114a at the very bottom of the layer stacks 102, 104. Since the first sacrificial material (i.e., the material of the bottom sacrificial layer 110) is different from the second sacrificial material and the channel material, the bottom sacrificial layer 110 can be removed by a selective etching process. As shown, the removal of the bottom sacrificial layer 110 of each layer stack 102, 104 can include etching the sacrificial layer 110 of the layer stacks 102, 104 simultaneously from the corresponding sides of the layer stacks 102, 104 that face away from the insulating wall 108.

[0094] In Figure 4 , a bottom insulating material 124 is deposited in the cavity 122 (e.g., Figure 1 step S16) of method 10. As shown, the bottom insulating material can be conformally deposited on the layer stacks 102, 104 with a certain thickness such that the cavity 122 is filled with the bottom insulating material. The bottom insulating material 124 can be selected, for example, from the examples mentioned for the insulating wall material.

[0095] Figure 5 And Figure 6 shows how the bottom insulating material 124 can subsequently be removed from the layer stacks 102, 104 above the level of the cavity 122.

[0096] In Figure 5 , a second insulating material 126 has been deposited to cover the layer stacks 102, 104 and the bottom insulating material 124 on these layer stacks. The second insulating material 126 can be an oxide, such as silicon oxide deposited, for example, by CVD (e.g., by flowable CVD (FCVD)).

[0097] In Figure 6 , the second insulating material and the bottom insulating material 124 have been etched back simultaneously in a top - down direction to expose the layer stacks 102, 104 above the level of the cavity 122. For example, a wet etching process can be used to etch the second insulating material (e.g., silicon oxide) and the bottom insulating material 124 (e.g., SiN). Before the etch - back, chemical - mechanical polishing (CMP) can be applied to provide the second insulating material 126 with a flat upper surface and perform its initial thickness reduction. The CMP can be continued so as to also remove the remaining mask portion (e.g., Figure 2 the mask portion 116 shown in

[0098] As Figure 6As shown, the bottom insulating material 124 remains in the cavity 122 after etch-back and can thus form the bottom insulating layer. In Figure 6 , the etch-back has stopped slightly above the level of the recess 122, consistent with the level of the bottommost sacrificial layer 112a. However, this is only an example, and the etch-back can further continue, for example, to a level that falls within the cavity 122, because the layers of the layer stack 102, 104 that are held above the cavity 122 can shield the bottom insulating material 124 deposited in the cavity 122. The (etched-back) second insulating material 126 can form part of a shallow trench isolation (STI) region between the paired first FET structure and the second FET structure.

[0099] The method can then continue with the processing of the layer stack 102, 104 to form the first nanosheet transistor structure and the second nanosheet transistor structure (e.g., Figure 1 processing block 20 of method 10).

[0100] In Figure 7 , a sacrificial gate 130 (also referred to as a dummy gate) has been formed to extend across the layer stack 102, 104 and the insulating wall 108. The sacrificial gate 130 can thus extend uninterruptedly between the first device region 118 and the second device region 120. A certain number of sacrificial gates 130 can be formed to extend in parallel across the layer stack 102, 104, as shown in an additional cross-sectional view taken along the XZ plane Figure 8 . Figure 8 Only a cross-section through one of the layer stacks 102, 104 may be shown. However, since the layer stacks 102, 104 are identical, Figure 8 it can be considered to represent a view of either the layer stack 102, 104 or any of the device regions 118, 120.

[0101] The sacrificial gate 130 can be formed in a manner known per se in the art, i.e., by patterning a layer of, for example, amorphous Si (e.g., using SADP or SAQP). The part of the mask (e.g., a hard mask material) used for patterning can be retained as a gate cap 132 on the sacrificial gate 130. As further shown in Figure 7 , the gate spacer 134 can be formed along the sidewalls of the sacrificial gate 130, for example, by conformal gate spacer layer deposition (e.g., SiC or SiBCN deposited by ALD) followed by (top-down) anisotropic etching.

[0102] The sacrificial gate 130 (or the sacrificial gate structure including the sacrificial gate 130, the gate cap 132, and the gate spacer 134) defines the positions of the corresponding channel regions of the first and second transistor structures to be formed through its overlap with the first layer stack 102 and the second layer stack 104. The positions of the corresponding source and drain regions are correspondingly defined on either side of the corresponding channel region (i.e., the regions not covered by the sacrificial gate 130 / sacrificial gate structure).

[0103] In Figure 9 , the layer stacks 102, 104 have been etched back on either side of the sacrificial gate 130, thereby forming a "cut" or "recessed" region. Subsequently, the corresponding source region 136 and drain region 138 have been epitaxially grown on either side of the sacrificial gate 130 (i.e., in the recessed region).

[0104] During the etch back, the sacrificial gate structure 130, 132, 134 can act as an etch mask. As shown, the etch back can continue until the upper surface has been recessed to the level of the bottom insulating layer 124 and then stopped. Thereby, both the channel material and the second sacrificial material can be removed before forming the source region 136 and the drain region 138. Dry etching such as RIE can be used to anisotropically etch the first stack 112 and the second stack 114 in the recessed region where the source / drain regions 136, 138 are to be formed. The dry etching can be adapted to anisotropically etch the first stack 112 and the second stack 114 in a top-down direction such that undercutting of the sacrificial gate 122 is avoided or at least minimized.

[0105] The source region 136 and the drain region 138 can thus be formed above the bottom insulating layer 124. Each source region 136 and drain region 138 can be formed as an epitaxially grown semiconductor body. The source / drain 130 can be grown on the exposed end surface / sidewall surface of the channel layer 114 exposed during the etch back. As can be understood, the choice of semiconductor material can take the channel material into account. For example, Si selective area epitaxy can be performed on a Si channel layer. The source region 136 and the drain region 138 can be doped according to the desired conduction type, for example, by in-situ doping. However, ion implantation doping or diffusion doping can also be employed. As an example, the source region 136 and the drain region 138 in the first device region 118 can be doped with a p-type dopant (to form a p-type nanosheet transistor structure). The source region 136 and the drain region 138 in the second device region 120 can be doped with an n-type dopant (to form an n-type nanosheet transistor structure). The n-doped region and the p-doped region can be formed sequentially such that n epitaxy is performed while masking the p-doped region and vice versa. Advantageously, the insulating wall 120 can facilitate the separation between the n-type source / drain region and the p-type source / drain region.

[0106] As further shown in the figure, the method may further include the step of forming a so-called "inner spacer" 137. The inner spacer may cover the end surface 137 of the upper sacrificial layer 112 facing the recessed region. The inner spacer 137 may be formed after forming the recessed region and before forming the source region 136 and the drain region 138. The inner spacer may be formed in a manner known per se in the field of NWFETs / NSHFETs. For example, the formation of the inner spacer cavity may be continued by selective lateral (horizontal) etching of the end surface of the upper sacrificial layer 112 with respect to the channel layer 114; conformal spacer material deposition (e.g., SiN, SiCO, or some other suitable low-k ALD dielectric); subsequent etching of the spacer material such that the spacer material remains only in the inner spacer cavity to form the inner spacer.

[0107] Figures 10 to 12 Subsequent process steps for replacing the sacrificial gate 130 with replacement metal gate stacks 146, 148 and additional process steps for forming the "released" channel portion are shown.

[0108] In Figure 10 a cover material has been deposited to cover the source region 136 and the drain region 138 and surround the sacrificial gate 130.

[0109] The cover material 140 may be an insulating material, such as, for example, an oxide (e.g., silicon oxide) deposited, planarized, and recessed by CMP and / or etching or another gap-filling dielectric material. CMP and / or etching may be continued to also remove the gate cap 132, thereby exposing the upper surface of the sacrificial gate 130. The sacrificial gate 122 may then be removed to expose the first layer stack 102 in the first gate trench 142 in the first region 118 and the second layer stack 104 in the corresponding second gate trench 144 in the second region 120. As shown, the gate spacers 134 may be retained during this process. As can be appreciated, the first gate trench 142 and the second gate trench 144 will be separated by the insulating wall 108.

[0110] In Figure 11 a portion of the upper sacrificial layer 112 has been removed by etching in the first gate trench 142 and the second gate trench 144. Figure 11The resulting “released” channel layer portions, commonly labeled 114a, are shown. For example, these channel layer portions each have the shape of a nanosheet. The channel layer portions 114a include a bottommost channel layer portion 114aa and a topmost channel layer portion 114ab. As shown, the upper and lower surfaces of the channel portions 114a can be exposed within the first gate trench 142, the second gate trench 144, and the second gate trench. The channel layer portions 114a form part of the respective channel regions of the first transistor structure and the second transistor structure. The channel region including the channel layer portions 114a extends between the source region 136 and the drain region 138 in the X direction. Since the second sacrificial material (i.e., the material of the upper sacrificial layer 112) is different from the channel material, the upper sacrificial layer 112 can be removed by a selective etching process. For example, a dry etching based on HCl can be used. However, other suitable etching processes that allow selective etching of SiGe relative to Si (e.g., wet etching processes) are known per se in the art and can also be used for this purpose.

[0111] As can be seen from the figure, the channel portions 114a are “partially released” in the sense that their upper and lower surfaces and outer sidewall surfaces are laid bare, while their inner sidewall surfaces (i.e., facing the insulating wall 108) are not laid bare but are adjacent to (and thus covered by) the insulating wall 108.

[0112] Figure 12 is shown in connection with Figure 2 the same cross-section (i.e., along the YZ plane and extending through the first gate trench 142 and the second gate trench 144). As Figure 12 shown, the first FET structure 150 is formed in the first device region 118, and the second FET structure 152 is formed in the second device region 120. Gate stacks 146, 148 (including replacement metal gates) of the first FET structure 150 and the second FET structure 152 have been formed in the first gate trench 142 and the second gate trench 144, respectively. The gate stacks 146, 148 have a fork-like shape with a certain number of prongs that extend along and between the channel layer portions 114a.

[0113] Although shown as a single structure, each gate stack 142, 144 may have a composite structure that includes: a gate dielectric layer (e.g., a high-k dielectric such as HfO2, HfSiO, LaO, AlO, or ZrO) on the channel portion 114a; one or more effective work function metal (WFM) layers on the gate dielectric layer (e.g., an n-type WFM such as TiAl or TiAlC in the second device region 120 / second gate trench 144, and a p-type WFM such as TiN or TaN covered by an n-type WFM in the first device region 118 / first gate trench 142); and optionally, gate fill metal (e.g., W, Al, Co, or Ru). The WFM layers may be conformally deposited, for example, by ALD. The gate fill metal may be deposited, for example, by CVD or PVD.

[0114] More specifically, forming the gate stack may include depositing a gate dielectric layer in the first gate trench 142 and the second gate trench 144. Subsequently, a p-type WFM (or n-type WFM) may be deposited in the first gate trench 142 and the second gate trench 144. After the deposition of the p-type (or n-type) WFM, an etch-back may be performed in a top-down direction, where the p-type (or n-type) WFM is recessed to a level below, at, or slightly above the upper surface of the insulating wall 108. A mask layer may be deposited (e.g., SoC or other organic spin-on) and etched (e.g., by dry etching) to a target level. Then, the etched mask layer may be used as a mask while removing the p-type (or n-type) WFM on the surface above the target level (e.g., the surface outside the gate trenches 142, 144) by, for example, isotropic etching (e.g., wet metal etching).

[0115] Subsequently, a trench mask may be formed above the first (or second) gate trench 142, where the p-type (or n-type) WFM in the second (or first) gate trench 144 may be removed by etching while the trench mask and the insulating wall 108 act as an etch mask for the p-type (or n-type) WFM in the first (or second) gate trench 142.

[0116] Subsequently, an n-type (or p-type) WFM may be deposited in at least the second (or first) gate trench 144 (optionally in both the first gate trench 142 and the second gate trench 144).

[0117] Subsequently, gate fill metal may be deposited to fill the remaining space in the first gate trench 142 and the second gate trench 144. The gate fill metal may be etched back (top-down) to obtain the final gate stacks 146, 148 of a desired height. In Figure 12In the figure, etch-back has been performed such that the gate stacks 146 and 148 form electrically-disconnected gate stacks separated by the insulating wall 108. However, the etch-back can also be limited such that the gate stacks 146, 148 remain connected across the insulating wall 108. Thus, the gate stacks 146, 148 can specify electrically-connected portions of a common gate stack. This can be a configuration suitable for, for example, a CMOS inverter.

[0118] The method can proceed with contact formation (for the gate stacks 146, 148 and the source / drain regions 136, 138) and wiring layer formation, as is known per se in the art, to incorporate the transistor structure into a functional circuit.

[0119] Now reference will be made to Figures 13 to 17 Disclosed is a method for forming a nanosheet FET structure, wherein the bottom insulating layer is formed according to a second manner. Similar to the above first manner, the second manner is disclosed with reference to a nanosheet FET structure, but generally applicable to forming an FET-type transistor structure including one or more channel layer portions such as nanowires or nanosheets.

[0120] The second manner proceeds in a manner similar to the first manner, however, it differs in that it eliminates the need for a bottom sacrificial layer that is different in material from the upper sacrificial layer. In other words, the same material can be used for the bottom sacrificial layer and the upper sacrificial layer.

[0121] Figure 13 Similar to Figure 2 Shown are a first semiconductor layer stack 202 and a second semiconductor layer stack 204, which are similar to the layer stacks 102, 104, but differ in that there is no bottom sacrificial layer 110 of the first sacrificial material. Instead, the bottom sacrificial layer 220 is formed of the same sacrificial material as the upper sacrificial layer 112. The sacrificial layer 112 (including the bottom sacrificial layer 220) can be formed of a sacrificial material, and the channel layer 114 can be formed of a channel material. Example materials discussed for the method of combination Figure 1 can be used, for example, the sacrificial material can be Si 0.65 Ge 0.35 and the channel material can be Si.

[0122] The bottom sacrificial layer 220 includes a lower thickness portion 220a and an upper thickness portion 220b, and the bottommost channel layer 114a is formed on the upper thickness portion.

[0123] The lower thickness portion 220a has a greater width (i.e., along the Y direction) than the upper thickness portion 220b. Accordingly, the upper surface of the lower thickness portion 220a is adjacent to and exposed beyond the upper thickness portion 220b, and in other words, laterally protrudes outside the upper thickness portion 220b. Such a possible profile of the bottom sacrificial layer 220 can be obtained, for example, as follows. Layers of sacrificial material and channel material can be alternately epitaxially grown to form a stack of material layers on the substrate layer 100. The bottommost sacrificial material layer can be formed to have a greater thickness than the subsequently grown channel material layers and sacrificial material layers. Then a first etch mask (e.g., the mask portion 116 in Figure 13 ) can be used to pattern the stack of material layers to form “preliminary” stacks 202, 204, including etching the stack of material layers and stopping at a level within the bottommost sacrificial layer. Thereby, the upper portions 220b of the stacks 202, 204 and the dimensions of the higher level layers can be defined. Thereafter, the preliminary stacks 202, 204 can be covered by a second etch mask with a width that (along the Y direction) exceeds the width of the preliminary stacks 102, 104. The second etch mask is formed, for example, by a SoC patterned using lithography and etching. Then further patterning of the bottommost sacrificial layer can be performed using the second etch mask. The etching can stop on the substrate layer 100 or, as shown in Figure 13 , extend into the substrate layer 100. By the further patterning, the (wider) dimensions of the lower portion 220a of the bottom sacrificial layer 220 can be defined. The second etch mask can then be removed. The trench 107 can be formed before or after the start of forming the stacks 202, 204 as discussed for the first approach and filled with an insulating wall material.

[0124] Figures 14 to 15 Shows the formation of a spacer layer 222 that covers the “outer” sidewall surfaces of the first stack 202 and the second stack 204 facing away from the insulating wall 108 and exposes their horizontally oriented surfaces, including the upper surface of the lower thickness portion 220a of the bottom sacrificial layer 220. Forming the spacer layer can include conformally depositing a spacer material over the first stack structure 202 and the second stack structure 204. The spacer material can be an oxide-based, nitride-based, or carbide-based material, such as, for example, SiO2, SiN, SiCO, SiCN, or SiOCN deposited by ALD. The spacer material can then be anisotropically etched (top-down) to remove the spacer material from the horizontally oriented surfaces and thus expose these horizontally oriented surfaces, which include the upper surface of the lower thickness portion 220b.

[0125] In Figure 16In [description], the bottom sacrificial layer 220 has been selectively removed for the upper sacrificial layer 112 and the channel layer 114 by etching the exposed upper surface of the lower thickness portion 220a while using the spacer layer 222 as an etch mask (e.g., Figure 1 step S14 of method 10). Despite the presence of the spacer layer 222, an etching process selective for the sacrificial material over the channel material can also be advantageously used to counteract an attack on the bottommost channel layer 114a.

[0126] In Figure 17 [description], a bottom insulating material 124 has been deposited in the cavity 224 (e.g., Figure 1 step S16 of method 10). Similar to that described in connection with Figures 4 to 6 [description], the bottom insulating material 124 can be conformally deposited and then etchbacked together with the second insulating material 126 such that the bottom insulating material 124 is removed from the layer stack 202, 204 above the level of the recess 224. The method can then continue as discussed above in connection with Figure 7 [description] and proceed forward (e.g., Figure 1 processing block 20 of method 10).

[0127] Above, the inventive concept has been described mainly with reference to a limited number of examples. However, as will be readily understood by those skilled in the art, other examples besides those disclosed above are equally possible within the scope of the inventive concept defined by the appended claims.

Claims

1. A method for forming a first transistor structure and a second transistor structure in a first device region and a second device region of a substrate, respectively, each transistor structure including a source region, a drain region, a channel region extending between the source region and the drain region in a first direction along the substrate, and a gate stack at the channel region, wherein, The first transistor structure and the second transistor structure are spaced apart by an insulating wall extending in the first direction in a second direction along the substrate transverse to the first direction, and the method includes: Forming a first semiconductor layer stack in the first device region and a second semiconductor layer stack in the second device region on the semiconductor layer of the substrate, each semiconductor layer stack including a first sacrificial layer, a plurality of channel layers, and a plurality of second sacrificial layers in a bottom-up direction, the second sacrificial layers alternating with the channel layers, and the channel layers being formed of a material different from the first sacrificial layer and the second sacrificial layers, wherein each first sacrificial layer includes a lower thickness portion and an upper thickness portion, and the bottommost channel layer is formed on the upper thickness portion, wherein the semiconductor layer stacks are spaced apart by trenches extending into the semiconductor layer of the substrate, and the trenches are filled with insulating wall material to form the insulating wall; and Processing the semiconductor layer stacks to form the first transistor structure and the second transistor structure in the first device region and the second device region, respectively, the processing including forming released channel layer portions by selectively etching the second sacrificial layers for the channel layers, forming the source regions and the drain regions, and forming the gate stacks along the channel layer portions; The method further includes, before the processing: Forming a spacer layer on sidewall surfaces of the first semiconductor layer stack and the second semiconductor layer stack facing away from the insulating wall, the spacer layer covering sidewall surfaces of the channel layers and the second sacrificial layers; and at least exposing the lower thickness portion of the first sacrificial layer; Removing the first sacrificial layer of each semiconductor layer stack by etching, thereby forming corresponding cavities under the channel layers of the first semiconductor layer stack and the second semiconductor layer stack on either side of the insulating wall, the channel layers being supported by the insulating wall, wherein the first sacrificial layer of each semiconductor layer stack is selectively removed for the second sacrificial layers by etching the first sacrificial layer using the spacer layer as an etching mask; and Depositing bottom insulating material in the cavities; Wherein, after the processing, the bottom insulating material forms a bottom insulating layer under the source region, the drain region, and the channel region on either side of the insulating wall.

2. The method according to claim 1, including conformally depositing the bottom insulating material on the semiconductor layer stacks with a certain thickness such that the cavities are filled with the bottom insulating material, and then removing the bottom insulating material from the semiconductor layer stacks above the level of the cavities.

3. The method according to claim 2, further including depositing a second insulating material, the second insulating material covering the semiconductor layer stacks and the bottom insulating material on the semiconductor layer stacks, and then simultaneously etching back the second insulating material and the bottom insulating material in a top-down direction to expose the semiconductor layer stacks above the level of the cavities.

4. The method according to claim 1, wherein The first sacrificial layers are formed of a first sacrificial material, the second sacrificial layers are formed of a second sacrificial material, and the channel layers are formed of a channel material, wherein the first sacrificial layers are selectively removed from the second sacrificial layers and the channel layers by selectively etching the first sacrificial material.

5. The method according to claim 4, wherein, In each semiconductor layer stack, a bottommost second sacrificial layer is formed on the first sacrificial layer.

6. The method according to claim 4, wherein The first sacrificial material is Si 1-x Ge x , the second sacrificial material is Si 1-y Ge y , and the channel material is Si 1-z Ge z , where x > y > z.

7. The method according to claim 1, wherein, The lower thickness portion of each first sacrificial layer has a greater width than the upper thickness portion, such that an upper surface of the lower thickness portion is exposed adjacent to the upper thickness portion, wherein forming the spacer layer comprises: conformally depositing a spacer material over the first semiconductor layer stack and the second semiconductor layer stack; and The deposited spacer material is etched back in a top-down direction such that upper surfaces of the lower thickness portions are exposed and the spacer layer remains on sidewall surfaces of the first semiconductor layer stack and the second semiconductor layer stack.

8. The method according to claim 1, wherein The first sacrificial layer and the second sacrificial layer are made of Si 1-y Ge y formed, and these channel layers are made of Si 1-z Ge z formed, where y > z.

9. The method according to claim 1, wherein Forming these semiconductor layer stacks includes: epitaxially growing a sacrificial material layer and a channel material layer, and The epitaxially grown sacrificial material layer and the channel material layer are patterned to form the trench and the first semiconductor layer stack and the second semiconductor layer stack.

10. The method according to claim 9, wherein, The method includes forming the trench and filling the trench with the insulating wall material before forming the semiconductor first layer stack and the semiconductor second layer stack.

11. The method according to any one of claims 1 to 3, wherein, The processing of these semiconductor layer stacks further includes: forming a sacrificial gate extending across the semiconductor layer stack and the insulating wall; etching the semiconductor layer stacks on either side of the sacrificial gate; forming respective source and drain regions of the first and second transistor structures on either side of the sacrificial gate by epitaxy, wherein the source and drain regions are formed above the bottom insulating layer; and The sacrificial gate is replaced by the gate stacks after forming the source regions and the drain regions.

12. The method according to claim 11, further comprising: After said epitaxy, depositing a capping material covering the source and drain regions and surrounding the sacrificial gate; as well as removing the sacrificial gate to expose the first semiconductor layer stack and the second semiconductor layer stack in the first gate trench and the second gate trench, respectively, the first gate trench and the second gate trench being separated by the insulating wall; The gate stacks are then formed in the first gate trench and the second gate trench.

13. The method according to claim 12 further includes forming released channel layer portions by etching portions of the second sacrificial layers exposed in the first gate trench and the second gate trench after removing the sacrificial gate and before forming the gate stacks, wherein the etching is selective to the channel layers.

14. The method according to any one of claims 1 to 3, wherein, Removing the sacrificial layer of each semiconductor layer stack comprises simultaneously etching the sacrificial layers of the semiconductor layer stacks from a side facing away from the insulating wall.

15. A method for forming a first transistor structure and a second transistor structure in a first device region and a second device region of a substrate, respectively, each transistor structure including a source region, a drain region, a channel region extending between the source region and the drain region in a first direction along the substrate, and a gate stack at the channel region, wherein, The first transistor structure and the second transistor structure are spaced apart by an insulating wall extending in the first direction in a second direction along the substrate transverse to the first direction, and the method includes: Forming a first semiconductor layer stack in the first device region and a second semiconductor layer stack in the second device region on the semiconductor layer of the substrate, each semiconductor layer stack including a first sacrificial layer, a plurality of channel layers, and a plurality of second sacrificial layers in a bottom-up direction, the second sacrificial layers alternating with the channel layers, and the channel layers being formed of a material different from the first sacrificial layer and the second sacrificial layers, wherein each first sacrificial layer includes a lower thickness portion and an upper thickness portion, the bottommost channel layer being formed on the upper thickness portion, wherein the lower thickness portion of each first sacrificial layer has a greater width than the upper thickness portion such that the upper surface of the lower thickness portion is exposed adjacent to the upper thickness portion, and wherein the semiconductor layer stacks are spaced apart by trenches extending into the semiconductor layer of the substrate, the trenches being filled with insulating wall material to form the insulating wall; and Processing the semiconductor layer stacks to form the first transistor structure and the second transistor structure in the first device region and the second device region, respectively, the processing including forming released channel layer portions by selectively etching the second sacrificial layers for the channel layers, forming the source regions and the drain regions, and forming the gate stacks along the channel layer portions; The method further includes, prior to the processing: Forming a spacer layer on sidewall surfaces of the first semiconductor layer stack and the second semiconductor layer stack facing away from the insulating wall, the spacer layer covering sidewall surfaces of the channel layers and the second sacrificial layers; and at least exposing the lower thickness portion of the first sacrificial layer, wherein forming the spacer layer includes conformally depositing spacer material over the first semiconductor layer stack and the second semiconductor layer stack, and etching back the deposited spacer material in a top-down direction such that the upper surface of the lower thickness portions is exposed and the spacer layer remains on the sidewall surfaces of the first semiconductor layer stack and the second semiconductor layer stack; Removing the first sacrificial layer of each semiconductor layer stack by etching to form corresponding cavities below the channel layers of the first semiconductor layer stack and the second semiconductor layer stack on either side of the insulating wall, the channel layers being supported by the insulating wall, wherein the first sacrificial layer of each semiconductor layer stack is selectively removed for the second sacrificial layers and the channel layers by etching the first sacrificial layer while using the spacer layer as an etch mask; and Depositing bottom insulating material in the cavities; Wherein, after the processing, the bottom insulating material forms a bottom insulating layer below the source region, the drain region, and the channel region on either side of the insulating wall.

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