Gallium nitride wide bandgap power module packaging structure and packaging method

Abstract

The present invention provides a GaN wide bandgap power module packaging structure, comprising: a packaging substrate, a packaging tube shell and a GaN wide bandgap power module; the frame of the packaging tube shell surrounds the packaging substrate to form a receiving groove; the power module is arranged in the receiving groove to form a low-inductance symmetrical commutation and control circuit structure; the GaN wide bandgap power module comprises a backing plate having a metal layer and at least two GaN chip groups symmetrically bonded to the metal layer, a plurality of spring pins, symmetrical busbar power terminals, a plurality of capacitors and a drive control board arranged above the backing plate; the backing plate is bonded to the substrate; the GaN chip group is symmetrically bonded to the middle of the metal layer; a plurality of spring pins are arranged on both sides of the GaN chip group; each GaN chip group is connected to the symmetrical busbar power terminal and the spring pin through the metal layer; and is electrically connected to the drive control board through the spring pins; a plurality of capacitors are symmetrically bonded to the two circumferential edge sides of the metal layer to form a low-inductance power loop.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a gallium nitride wide bandgap power module packaging structure and packaging method. Background Art

[0002] Wide bandgap power semiconductors have broad prospects in high-power applications. Due to the advantages of their own power semiconductor devices such as fast switching speed, low switching loss, and high current density, they can achieve high energy conversion efficiency, high switching frequency, more compact size, and more flexible switching control. They are ideal power devices to meet the needs of broader energy conversion and energy transmission applications in the future, and can be applied to new energy fields such as electric vehicles, electric aircraft, rail transit, smart grids, and industrial applications.

[0003] Gallium nitride (GaN) power semiconductor chips offer fast current and voltage change rates, high switching frequencies, high current density, high operating temperature, and high energy conversion efficiency, promising promising applications in future energy conversion and transmission. Currently, GaN devices are typically used in high-frequency switching applications like high-frequency communications and relatively low-power applications like power chargers. However, with the rapid development of power semiconductor device manufacturing and packaging technologies, as well as packaging materials, GaN holds great promise for medium- and high-power applications, such as main power inverters for electric vehicles.

[0004] Wide-bandgap power products place higher demands on packaging layout and high-temperature materials. The device's current and thermal characteristics are difficult to replicate within existing standard packages. Conventional packaging designs currently on the market cannot meet the packaging layout, current, and thermal requirements of high-power semiconductor devices with high switching frequencies, high power densities, and high integration.

[0005] Therefore, there is an urgent need for a new packaging structure and packaging method for gallium nitride (GaN) wide bandgap power semiconductor modules. Summary of the Invention

[0006] In view of this, an object of the present invention is to provide a GaN wide bandgap power module packaging structure and packaging method to solve the aforementioned problems.

[0007] To achieve the above objectives, the present invention provides a GaN wide bandgap power module packaging structure, comprising: a packaging substrate, a packaging tube shell, and a GaN wide bandgap power module; the packaging tube shell has a frame surrounding the packaging substrate to form a receiving groove; the wide bandgap power module is disposed in the receiving groove to form a low-inductance symmetrical commutation and control circuit structure;

[0008] The GaN wide bandgap power module includes a backing plate having a metal layer and at least two GaN chip groups symmetrically bonded to the metal layer, a plurality of spring pins, a symmetrical busbar power terminal, a plurality of capacitors, and a drive control board arranged above the backing plate; the backing plate is bonded to the substrate; at least two GaN chip groups are symmetrically bonded to the middle of the metal layer; a plurality of spring pins are arranged on both sides of the GaN chip group; each GaN chip group is connected to the symmetrical busbar power terminal and the spring pin through the metal layer; each GaN chip group is electrically connected to the drive control board through the spring pin to form a buffer circuit; the plurality of capacitors are symmetrically bonded to the two circumferential edge sides of the metal layer to form a low-inductance power loop; the top of the symmetrical busbar power terminal is arranged above the packaging tube shell and extends out of the packaging tube shell.

[0009] In one embodiment, the top of the symmetrical busbar power terminal extends out of the packaging tube shell, and the bottom pin is bonded to the liner; the symmetrical busbar power terminal includes a DC busbar power terminal and an AC busbar power terminal relatively arranged at both ends of the liner; the DC busbar power terminal includes a positive DC busbar power terminal and a negative DC busbar power terminal, and the middle part of the negative DC busbar power terminal cooperates with the middle part of the positive DC busbar power terminal to form an overlapping coupling structure, so that the stray inductance is reduced when the DC busbar power terminal conducts currents in different directions.

[0010] In one embodiment, the DC busbar power terminal includes a connecting portion and two main bodies symmetrically arranged on both sides of the connecting portion; the main body includes an external power connecting portion, a first bent portion, a second bent portion, and a bottom pin; two ends of the second bent portion are respectively connected to the main body and the first bent portion;

[0011] The two ends of the first bent portion are respectively connected to the external power connection portion and the bottom pin, and the shape of the first bent portion is adapted to the shape of the packaging tube shell, so that the external power connection portion extends out of the packaging tube shell, and the bottom pin is bonded to the backing plate; the bottom pin is a forked shape; the two ends of the second bent portion are respectively connected to the first bent portion and the connection portion, so that the main body is vertically connected to the connection portion.

[0012] In one embodiment, the negative DC busbar power terminal includes an external main current connection portion, a negative DC first bend portion, a negative DC second bend portion, a negative DC third bend portion and a negative DC bottom pin that are vertically connected in sequence;

[0013] The shape of the negative DC first bend portion is adapted to the shape of the packaging tube shell, so that the external main current connection portion extends out of the packaging tube shell; the negative DC second bend portion cooperates with the connection portion to form an overlapping coupling structure, and the middle portion of the negative DC second bend portion has a fork; the negative DC bottom pin is provided with two, symmetrically arranged on both sides of the fork of the negative DC second bend portion; the negative DC bottom pin is forked.

[0014] In one embodiment, the AC busbar power terminal includes an AC connecting portion, an AC bending portion, and two AC bottom pins arranged in reverse symmetry, which are vertically connected in sequence;

[0015] The AC bending portion includes a first AC bending portion and a second AC bending portion vertically connected in sequence. The shape of the first AC bending portion is adapted to the shape of the packaging tube shell so that the AC connecting portion extends out of the packaging tube shell; the middle and edge of the second AC bending portion are respectively provided with a spring pin avoidance groove group, each including two symmetrically arranged slot structures to form a low-interference current.

[0016] In one embodiment, the drive control board is provided with a plurality of series combinations of resistors and capacitors on a surface away from the liner; the plurality of series combinations are respectively provided in parallel with the plurality of chips in the gallium nitride chipset; the positive and negative electrodes of the plurality of series combinations are respectively connected to the drain and source electrodes of the plurality of chips via spring pins to form an RC snubber buffer circuit to reduce electromagnetic interference of the gallium nitride chipset.

[0017] In one embodiment, the metal layer includes a first metal layer region and a second metal layer region disposed on the same side of the gallium nitride chipset; the first metal layer region and the second metal layer region are disposed opposite to each other and spaced apart;

[0018] The first metal layer region includes a long strip-shaped main region and two enlarged end portions extending from both ends of the long strip-shaped main region toward the second metal layer region; the gate of the gallium nitride chipset is connected to the two enlarged end portions, and the enlarged end portions are connected to the drive control board via spring pins disposed in the middle of the long strip-shaped main region; the second metal layer region is long strip-shaped, the source of the gallium nitride chipset is connected to both ends of the second metal layer region along the length direction, and the second metal layer region is connected to the drive control board via spring pins disposed in the middle of the long strip-shaped main region, thereby forming a Kelvin Contact control loop for the gallium nitride chipset.

[0019] In one embodiment, the metal layer region further includes four third metal layer regions, which are symmetrically arranged on both sides of the two enlarged end portions; and magnetic beads are arranged between the enlarged end portions and the third metal layer regions.

[0020] In one embodiment, the spring pin includes a semi-annular bottom end and a long strip connected to the semi-annular bottom end.

[0021] An embodiment of the present invention further provides a wide bandgap power module packaging method, comprising:

[0022] According to the wide bandgap power module to be packaged, a liner, a plurality of spring pins, a symmetrical busbar power terminal and a drive control board are prepared; the liner is provided with a metal layer;

[0023] Sequentially bonding the gallium nitride chipset to the middle of the backing plate, bonding the gallium nitride chipset to the metal layer of the backing plate through wire bonding, and bonding the plurality of spring pins to both sides of the gallium nitride chipset;

[0024] symmetrically bonding a plurality of capacitors to two circumferential edge sides of the metal layer of the liner;

[0025] Sequentially bonding the obtained liner to the substrate, gluing the frame of the package shell to the edge of the package substrate, so that the frame of the package shell surrounds the package substrate;

[0026] The symmetrical power busbar terminals are ultrasonically bonded to the liner in sequence, with the tops of the symmetrical power busbar terminals positioned above and extending out of the package shell. The PCB control board is soldered to the upper ends of the spring pins to form a low-inductance symmetrical commutation and control circuit structure and a buffer circuit.

[0027] Fill the package with insulating glue and cure it.

[0028] As can be seen from the above description, the gallium nitride wide bandgap power module packaging structure and packaging method provided by the present invention adopt a symmetrically structured backing plate, symmetrically bonded to at least two gallium nitride chip groups, multiple spring pins, symmetrical busbar power terminals and multiple capacitors on the metal layer of the backing plate, and through the spring pins and the backing plate; and the multiple capacitors are symmetrically arranged in two edge areas of the metal layer of the backing plate that are perpendicular to the setting direction of the symmetrical power busbar terminals, thereby realizing a low-inductance symmetrical commutation structure, greatly reducing the parasitic inductance of the power module when performing large current energy exchange. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1This is a schematic structural diagram of the overall module package of an embodiment of the present invention;

[0031] Figure 2 This is a schematic structural diagram of the combination of a ceramic liner, busbar, chip, spring pins, etc. according to an embodiment of the present invention;

[0032] Figure 3 This is a schematic structural diagram of the resistors, capacitors, and spring pins at the bottom of the driver circuit board according to an embodiment of the present invention;

[0033] Figure 4 This is a schematic diagram of the layout of the ceramic liner according to an embodiment of the present invention;

[0034] Figure 5 Schematic diagram of the structure of the positive and DC busbars in an embodiment of the present invention;

[0035] Figure 6 This is a schematic structural diagram of a negative DC busbar according to an embodiment of the present invention;

[0036] Figure 7 This is a schematic structural diagram of an AC busbar according to an embodiment of the present invention;

[0037] Figure 8 This is a schematic structural diagram of a spring pin according to an embodiment of the present invention;

[0038] Figure 9 This is a flow chart of a module packaging method according to an embodiment of the present invention;

[0039] Among them, the package substrate 1, the package tube shell 2, the liner 4, the capacitor 41, the gallium nitride chipset 47, the spring pin 40, the drive control board 5, the positive DC busbar power terminal 31, the negative DC busbar power terminal 32, the connecting portion 315, the external power connecting portion 310, the external power connection through-hole 311, the first sub-bending portion 312, the second sub-bending portion 313, the third sub-bending portion 316, the second bending portion 314, the bottom pin 317, the external main current connecting portion 320, the external main current connection through-hole 321, the negative DC first bending portion 322, the negative DC second bending portion 323, the negative DC third bending portion 325, the negative DC bottom pin 327, the AC busbar power terminal 33, the AC connecting portion 330, the AC connection through-hole 331, the AC bottom pin 339, the first AC bending portion 332, the second AC bending portion 333, the third AC bending portion 337, First spring pin avoidance groove 334, second spring pin avoidance groove 336, third spring pin avoidance groove 335, middle part 450 of the first metal layer area, enlarged end 451, middle part 460 of the second metal layer area, end 461 of the second metal layer area, third metal layer area 452, fourth metal layer area 42, end 420 of the fourth metal layer area close to the sixth metal layer area, fifth metal layer area 43, end 430 of the fifth metal layer area, sixth metal layer area 44, end 440 of the sixth metal layer area close to the chip bonding area, chip bonding area 470, insulating solder resist 471, seventh metal layer area 481, eighth metal layer area 480, solder resist layer 482, ninth metal layer area 435, tenth metal layer area 434, drive control board resistor 51, drive control board capacitor 52, semi-annular bottom 400, and strip 401. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0041] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present invention should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0042] The inventors of the present invention discovered during their long-term research on GaN wide bandgap power chips that the traditional packaging structure design currently on the market cannot fully utilize the advantages of GaN wide bandgap power chips, and cannot fully reflect the unique characteristics of GaN wide bandgap power modules compared to traditional silicon-based power devices, such as high dv / dt rate when the current is turned on, high di / dt when the current is turned off, high switching frequency, high electromagnetic interference harmonic components, and high requirements for parasitic parameters such as inductance and capacitance. In the packaging process, in order to achieve electrical connection between the liner, chip, and pins, and the module packaging requires electrodes to be led out through the power terminals, these leads will increase the parasitic inductance of the loop.

[0043] The inventors of this invention propose a novel low-inductance symmetrical commutation layout structure, built-in noise-reducing capacitors, and internally integrated drive circuits to achieve uniform low inductance across the gate-source control terminals of multiple chips, thereby reducing electromagnetic interference. High-mechanical-strength ceramic materials and thick copper linings are used to achieve high reliability and efficient heat dissipation. The packaging architecture and implementation methods for wide-bandgap semiconductor power devices, utilizing a novel sintering process, fully leverage the advantages and characteristics of wide-bandgap devices, including high-temperature operation, high switching frequency, high heat dissipation, and low electromagnetic interference (EMI). The module's internal lining structure, power terminal structure, and gate control all adopt a completely symmetrical structure, and built-in capacitors are used to effectively reduce the inductance of the main current. A structure connecting the drive control board to spring pins forms a Kelvin contact at the control terminal, effectively reducing the control inductance of the gate-source loop and optimally meeting the packaging requirements of GaN power chips with high current switching rates. To meet the demands of high-power electric drive applications such as electric vehicles, ferrite beads are added to the control and main circuits to suppress and reduce high-frequency signals in the control and main current circuits, effectively reducing electromagnetic interference (EMI) generated by power devices. This increases the system's switching frequency while also reducing the most significant source of EMI in the entire system. A power busbar terminal technology combining symmetry and low structural stress with ultrasonic welding (USW) technology improves the long-term reliability of the power module in high-vibration and high-temperature shock scenarios such as electric vehicles.

[0044] See also Figure 1 and Figure 2 An embodiment of the present invention provides a GaN wide bandgap power module packaging structure, comprising: a packaging substrate 1, a packaging tube shell 2, and a GaN wide bandgap power module; the packaging tube shell 2 has a frame surrounding the packaging substrate 1 to form a receiving groove; the wide bandgap power module is disposed in the receiving groove to form a low-inductance symmetrical commutation circuit structure and a low-inductance symmetrical control circuit structure;

[0045] The GaN wide bandgap power module comprises a substrate 4 having a metal layer and at least two GaN chip groups 47 symmetrically bonded on the metal layer, a plurality of spring pins 40, a symmetrical busbar power terminal, a plurality of capacitors 41, and a drive control board 5 arranged above the substrate 4; the substrate 4 is bonded to the packaging substrate 1; at least two GaN chip groups 47 are symmetrically bonded to the middle of the metal layer of the substrate 4; a plurality of the spring pins 40 are arranged on both sides of the GaN chip group; each GaN chip group is bonded to the opposite The symmetrical busbar power terminals and the spring pins 40 are connected through the metal layer on the backing plate 4; each gallium nitride chipset is electrically connected to the drive control board 5 through the spring pins 40 to form a buffer circuit; the multiple capacitors 41 are symmetrically bonded to the two edge areas of the metal layer of the backing plate 4 that are perpendicular to the setting direction of the busbar power terminals (i.e., the two circumferential edge sides of the metal layer) to form low inductance; the top of the symmetrical busbar power terminal is set above the packaging tube shell 2 and extends out of the packaging tube shell 2.

[0046] The gallium nitride wide bandgap power module packaging structure provided by the embodiment of the present invention adopts a symmetrically structured backing plate 4, at least two gallium nitride chip groups symmetrically bonded to the metal layer of the backing plate 4, multiple spring pins 40, symmetrical busbar power terminals and multiple capacitors 41, and a drive control board 5 electrically connected to the backing plate 4 through the spring pins 40; and the multiple capacitors 41 are symmetrically arranged in two circumferential edge areas of the metal layer of the backing plate 4, realizing a low-inductance symmetrical commutation structure, greatly reducing the parasitic inductance of the power module when performing large current energy exchange.

[0047] In one embodiment, a heat sink is further included and is disposed at the bottom of the substrate to further reduce electromagnetic interference of the GaN wide bandgap power module.

[0048] The package substrate 1 is a metal substrate, such as an aluminum substrate, a copper substrate, or an iron substrate. The package substrate 1 can have various shapes, such as a plate. Substrate fastening holes 10 can be provided on the package substrate 1. Specifically, the substrate fastening holes 10 can be provided at the four ends of the package substrate 1. Specifically, the substrate fastening holes 10 can be through holes or holes. Providing substrate fastening holes 10 at the four ends of the package substrate 1 facilitates packaging.

[0049] The liner 4 is made of ceramic. It can be a ceramic liner with high voltage insulation, high heat dissipation efficiency, and high thermal-mechanical reliability. For example, it can be a ceramic liner made of at least one of aluminum oxide Al2O3, aluminum nitride AlN, silicon nitride SiN, and the like. The upper and lower surfaces of the ceramic liner 4 are both provided with a metal layer for conducting electricity. The lower surface of the liner 4 is bonded to the substrate, for example, by welding or silver sintering. The metal layer on the upper surface of the liner 4 performs functions such as conduction and control by taking into account factors such as electromagnetic current sharing.

[0050] The bottom pins of the symmetrical busbar power terminals are bonded to the metal layer of the liner 4, the middle portion is supported by the package tube shell 2, and the top portion extends outward from the package tube shell 2. The symmetrical busbar power terminals include DC busbar power terminals and AC busbar power terminals arranged at opposite ends of the liner 4.

[0051] The DC busbar power terminals include a positive DC busbar power terminal 31 and a negative DC busbar power terminal 32. The middle portion of the negative DC busbar power terminal 32 cooperates with the middle portion of the positive DC busbar power terminal 31 to form an overlapping coupling structure, thereby reducing stray inductance when the DC busbar power terminals conduct currents in different directions.

[0052] See also Figure 5 The positive DC busbar power terminal 31 includes a connecting portion 315 and two main bodies symmetrically arranged on either side of the connecting portion 315. The main body includes an external power connection portion 310, a first bend portion, a second bend portion 314, and a bottom pin 317. The two ends of the second bend portion 314 are respectively connected to the main body and the connecting portion 315, so that the main body and the connecting portion 315 are perpendicularly connected. In other words, the two ends of the connecting portion 315 are respectively connected to the first bend portions of the two main bodies through the second bend portion 314, thereby balancing the current on both sides. This allows the magnetic field of the current flowing through the positive DC busbar power terminal 31 to couple with the inductance of the negative DC busbar power terminal 32 and the metal layer of the liner 4, thereby reducing the overall inductance.

[0053] The external power connection portion 310 defines an external power connection through hole 311 for connecting to an external main conductive busbar terminal.

[0054] The first bent portion's two ends along its length (i.e., its two ends in its height) are respectively connected to the external power connection portion 310 and the bottom pin 317. The first bent portion abuts against the package case 2, and its shape matches that of the package case 2, allowing the external power connection portion 310 to extend outside the package case 2. The bottom pin 317 is bonded to the backing plate 4.

[0055] The first bend portion includes three sub-bends: a first sub-bend portion 312, a second sub-bend portion 313, and a third sub-bend portion 316. The external power connection portion 310, the first sub-bend portion 312, the second sub-bend portion 313, the third sub-bend portion 316, and the bottom pin 317 are connected vertically in sequence. The height and position of the first sub-bend portion 312, the second sub-bend portion 313, and the third sub-bend portion 316 are calculated through simulation to match the height and shape of the package 2, thereby alleviating stress on the bottom pin 317 during ultrasonic bonding and actual operation.

[0056] The bottom pin 317 is in a bifurcated shape to increase the contact area between the positive DC busbar power terminal 31 and the metal layer of the ceramic liner 4 , thereby improving heat dissipation and the current carrying capacity of the positive DC busbar power terminal 31 .

[0057] See also Figure 6 The negative DC busbar power terminal 32 includes an external main current connection portion 320, a negative DC first bending portion 322, a negative DC second bending portion 323, a negative DC third bending portion 325 and a negative DC bottom pin 327 which are vertically connected in sequence.

[0058] The external main current connection portion 320 defines an external main current connection through-hole 321 for connecting to an external main conductive busbar terminal. The negative DC first bend 322, negative DC second bend 323, and negative DC third bend 325 are optimized buffer structures. Their height and position were calculated through simulation to match the height and shape of the package 2 and mitigate structural stress and electromagnetic forces generated by high current.

[0059] The negative DC first bend portion 322 is positioned against the package tube case 2, so that the external main current connection portion 320 extends out of the package tube case 2. The negative DC second bend portion 323 cooperates with the connection portion 315 of the positive DC busbar power terminal 31 to form an overlapping coupling structure to reduce the overall inductance.

[0060] In one embodiment, a middle portion of the negative DC second bent portion 323 has a fork to divide the current path of the entire negative DC busbar power terminal 32 into two parts.

[0061] Correspondingly, two negative DC bottom pins 327 are provided, symmetrically arranged on either side of the bifurcation of the negative DC second bend 323 to form two negative DC paths. The bifurcated shape of the negative DC bottom pins 327 separates the two negative DC paths into two pins, increasing the contact area between the negative DC busbar power terminal 32 and the metal layer of the liner 4, improving heat dissipation and the current carrying capacity of the negative DC busbar power terminal 32.

[0062] See also Figure 7The AC busbar power terminal 33 includes an AC connecting portion 330, an AC bending portion, and two AC bottom pins 339 that are vertically connected in sequence. The AC connecting portion is provided with an AC connecting through-hole 331 for connecting to an external AC power source.

[0063] The AC bend portion includes a first AC bend portion 332, a second AC bend portion 333, and a third AC bend portion 337, which are connected vertically in sequence. These first, second, and third AC bend portions 332, 333, and 337 serve as optimized buffer structures to mitigate structural stress and the electromagnetic force generated by high current. Their height and position were calculated through simulation to match the height and shape of the package 2, mitigating stress on the AC bottom pin 339 during ultrasonic bonding and actual operation.

[0064] The shape of the first AC bend 332 matches the shape of the package tube shell 2, allowing the AC connection portion 330 to extend outside the package tube shell 2. Spring pin avoidance slot groups are defined in the middle and along the edges of the second AC bend 333. Each spring pin avoidance slot group includes two symmetrically arranged slot structures to generate a low-interference current. It can be understood that the spring pin avoidance slot group includes a first spring pin avoidance slot 334 and a second spring pin avoidance slot 336 defined in the middle of the second AC bend 333. The spring pin avoidance slot group also includes two third spring pin avoidance slots 335 defined along the edges of the second AC bend 333. The slot widths and lengths of the first spring pin avoidance slot 334, the second spring pin avoidance slot 336 and the two third spring pin avoidance slots 335 are obtained through optimization and calculation, so as to be perpendicular to the current flowing through the spring pins 40 while maximizing the high current carrying capacity, thereby minimizing the mutual interference between the AC busbar power terminal current and the direct current of the spring pins 40.

[0065] Two third AC bends 337 are provided, symmetrically positioned opposite each other at either end of the second AC bend 333. Two AC bottom pins 339 are perpendicularly connected to the two third AC bends 337, dividing the AC current into two current paths. Each AC bottom pin 339 is designed in a bifurcated shape, separating the two AC paths into two pins, thereby improving the current-carrying and electrical conductivity of the AC busbar power terminals and the metal layer on the upper surface of the ceramic liner 4.

[0066] See also Figure 2The plurality of GaN chip groups 47 may be two or four. In one embodiment, there are two GaN chip groups 47, and the two GaN chip groups 47 are symmetrically ultrasonically bonded to the center of the metal layer. In one embodiment, the number of GaN chip groups 47 is multiple, and the plurality of GaN chip groups 47 are connected in parallel. Adjacent GaN chip groups 47 are symmetrically arranged and connected by chip bonding wires to reduce oscillation and electromagnetic interference caused by the potential difference caused by large current in the parallel GaN chip groups 47.

[0067] Each GaN chipset 47 includes multiple GaN chips connected in parallel. Adjacent chips are connected via chip bonding wires to reduce oscillations and electromagnetic interference caused by potential differences between the parallel chips due to large currents. The number of chips can be two or three. Each chip has an internal resistor. The GaN chipset 47 constitutes the module's switch.

[0068] It should be noted that the chips are connected to each other via chip bonding wires, the chips are connected to the metal layer via backing board bonding wires, and the chips are connected to the symmetrical busbar power terminals and spring pins 40 via metal layers.

[0069] See also Figure 2 and Figure 4 The metal layer includes multiple GaN chip set bonding areas. That is, the metal layer is provided with the same number of GaN chip set bonding areas as the number of GaN chip sets 47. The GaN chip set bonding area includes four sequentially connected chip bonding areas 470. A slot-shaped gap is provided between two adjacent chip bonding areas to form an insulating solder resist 471, facilitating chip bonding via soldering or silver sintering.

[0070] The metal layer also includes a first metal layer region 45 and a second metal layer region 46, respectively, disposed on the same side of the GaN chip assembly bonding region. The first metal layer region 45 and the second metal layer region 46 are disposed opposite each other and spaced apart. In other words, the first metal layer region 45 and the second metal layer region 46 are disposed on the same side of the chip bonding region 470. Each chip bonding region 470 is provided with a first metal layer region 45 and a second metal layer region 46 on one side.

[0071] The first metal layer region 45 includes a long, rectangular main body region and two enlarged end portions 451 extending from both ends of the long, rectangular main body region toward the second metal layer region 46. A spring pin 40 is disposed in the central portion 450 of the long, rectangular main body region. The gate of the gallium nitride chipset 47 is connected to the two enlarged end portions 451 via substrate bonding wires. The enlarged end portions 451 are connected to the driver control board 5 via the spring pin 40 disposed in the central portion 450 of the long, rectangular main body region.

[0072] The second metal layer region 46 is in the shape of an elongated strip, with a spring pin 40 disposed in the middle 460 of the second metal layer region 46. The source of the gallium nitride chipset 47 is connected to both ends 461 of the second metal layer region 46 along its length via substrate bonding wires. The second metal layer region 46 is connected to the driver control board 5 via a spring pin 40 disposed in the middle of the main body of the elongated strip 401.

[0073] The gate of the gallium nitride chipset 47 is connected to the two enlarged end portions 451 of the first metal layer region 45 via substrate bonding wires, and the middle portion 450 of the first metal layer region 45 is connected to the drive control board 5 via spring pins 40; the source of the gallium nitride chipset 47 is connected to the two ends 461 of the second metal layer region 46 along the length direction via substrate 4 bonding wires, and the middle portion 460 of the second metal layer region 46 is connected to the drive control board 5 via spring pins 40, thereby forming a Kelvin Contact control loop for the gallium nitride chipset 47.

[0074] In another embodiment, the metal layer region further includes four third metal layer regions 452. These four third metal layer regions 452 are symmetrically arranged on either side of the two enlarged ends 451. The gates of the four chips in the gallium nitride chipset 47 are connected to the four third metal layer regions 452 via liner bonding wires, thereby providing fully symmetrical and balanced control of the four parallel chips. The gate control terminal connection can be a symmetrical bridge cascade connection.

[0075] In one embodiment, a magnetic bead is disposed between the enlarged end portion 451 and the third metal layer region 452 to suppress high-frequency components in the control signal. The magnetic bead may be a ferrite bead having a suitable resistance and can be soldered to both sides of the third metal layer region 452.

[0076] In the aforementioned Kelvin Contact control circuit, two spring pins 40, located in the middle of the first metal layer region 45 and the second metal layer region 46, respectively, achieve balanced control of the four GaN power chips in the GaN chipset 47. The gate-source layout in this control circuit accommodates the extremely fast switching speeds of the GaN chips, ensuring low control loop parasitics and balanced parasitics from the control signal to the chip. Combined with the magnetic bead placed between the enlarged end 451 and the third metal layer region 452, potential oscillations at the control end can be reduced, thereby minimizing electromagnetic interference.

[0077] The metal layer is further provided with a fourth metal layer region 42 , a fifth metal layer region 43 , a sixth metal layer region 44 , a seventh metal layer region 481 , an eighth metal layer region 480 , a ninth metal layer region 435 , and a tenth metal layer region 434 .

[0078] The fourth metal layer region 42 is disposed on the circumferential edge of the backing plate 4, and an opening is provided at one end of the fourth metal layer region 42. That is, the fourth metal layer region 42 is disposed on all four edges of the backing plate 4, and an opening is provided on one edge of the backing plate 4. The sixth metal layer region 44 is disposed in the opening region and extends from the edge with the opening toward the chip bonding region 470. The first metal layer region 45 and the second metal layer region 46 are disposed in the gap between the sixth metal layer region 44 and the chip bonding region 470.

[0079] The positive DC busbar power terminal 31 is bonded to the fourth metal layer region 42 at two ends 420 near the sixth metal layer region 44. The negative DC busbar power terminal 32 is bonded to the sixth metal layer region 44 in a region parallel to the two ends 420 of the fourth metal layer region, so that the center of the negative DC busbar power terminal 32 mates with the center of the positive DC busbar power terminal 31 to form an overlapping coupling structure. Four spring pin 40 bonding areas are also provided on one side of the sixth metal layer region 44 near the first metal layer region 45.

[0080] Multiple capacitors 41 are symmetrically arranged. The number of capacitors 41 can be 4, with two in each group. The two groups of capacitors 41 are symmetrically arranged in the area near the two pins of the positive DC power bus terminal 31. Each group of capacitors 41 is respectively arranged across the end 440 of the sixth metal layer area 44 near the chip bonding area 470 and the portion of the fourth metal layer area 42 adjacent to the end 440. Among them, the capacitor 41 is a decoupling capacitor with a suitable capacitance value. It is bonded to the area near the two pins of the DC power bus terminal through a welding process such as ultrasonic bonding. The decoupling capacitor cooperates with the external large-capacity DC capacitor to provide a lower inductance commutation circuit for high-frequency current energy, effectively suppressing high-frequency oscillations that may occur during the conversion process of the gallium nitride chipset 47 (i.e., the current switch). Among them, the DC low-frequency energy conversion is mainly completed by the external DC capacitor connected to the DC power bus terminal.

[0081] Seventh metal layer region 481, eighth metal layer region 480, ninth metal layer region 435, and tenth metal layer region 434 are all disposed on the other side of chip bonding region 470, that is, on the side of chip bonding region 470 away from second metal layer region 46. Furthermore, seventh metal layer region 481, eighth metal layer region 480, ninth metal layer region 435, tenth metal layer region 434, and fifth metal layer region 43 are disposed sequentially away from chip bonding region 470.

[0082] The seventh metal layer region 481 and the eighth metal layer region 480 are spaced apart from each other, with a solder resist layer 482 disposed between them. The top surfaces of the four chips in the gallium nitride chipset 47 are bonded to the seventh metal layer region 481 via bonding wires or metal ribbons. A magnetic bead is disposed between the eighth metal layer region 480 and the ninth metal layer region 435 to suppress the high-frequency components of the main current flowing through the chip. The magnetic bead can be a ferrite bead, which can be soldered and has a suitable resistance value.

[0083] The tenth metal layer region 434 is used to dispose spring pins 40. Moreover, the number of spring pins 40 provided here is four, which is consistent with the number of chips in the gallium nitride chipset 47, both being four.

[0084] Two fifth metal layer regions 43 are provided and spaced apart from each other. Two ends of the fifth metal layer region 43 away from the tenth metal layer region 434 are respectively used to provide two bottom pins 317 of the AC busbar power terminal.

[0085] The wide-bandgap power module features a dual-switch half-bridge structure. During operation of the module's top-side switch, current from the positive DC busbar power terminal 31 flows along the fourth metal layer region 42 around the liner 4, through the gallium nitride chipset 47 near the AC busbar power terminal 33, and then through the two ends 430 of the fifth metal layer region 43 to the AC busbar power terminal 34, forming a symmetrical top-side current. During operation of the bottom-side switch, external current flows from the AC busbar power terminal 33, through the two ends 430 of the fifth metal layer region 43, through the gallium nitride chipset 47 near the DC busbar power terminal, through the sixth metal layer region 44, and finally through the negative DC busbar power terminal 32, forming a symmetrical bottom-side current.

[0086] It should be noted that multiple spring pin 40 setting areas are provided on the lining plate 4, which are respectively arranged on the side of the sixth metal layer area 44 close to the first metal layer area 45, the middle 450 of the first metal layer area 45, the middle 460 of the second metal layer area 46, the tenth metal layer area 434 and the side of the fourth metal layer area 42 close to the AC busbar power terminal 33.

[0087] See also Figure 3 The drive control board 5 is provided with a series combination of multiple drive control board resistors 51 and drive control board capacitors 52 on a surface away from the backing plate 4. These series combinations are connected in parallel with the multiple chips in the gallium nitride chipset 47. The drive control board 5 also has multiple connection holes, which are located in a one-to-one correspondence with the locations of the spring pins 40 on the backing plate 4. The tops of the multiple spring pins 40 are each provided with a connection hole to electrically connect the drive control board 5 to the backing plate 4.

[0088] The positive and negative electrodes of multiple series combinations are connected to the drain and source of multiple chips respectively through spring pins 40 to form an RC Snubber buffer circuit. This RC Snubber buffer circuit can reduce the electromagnetic interference caused by the high dV / dt that the chip has to withstand during the turn-on phase. The resistance value of the drive control board resistor 51 and the capacitance value of the drive control board capacitor 52 need to be calculated and selected to appropriate values, so as to realize an effective RC-Snubber buffer circuit for GaN chips with fast switching rates, reduce electromagnetic interference, and thus protect the safe operation of the chip. At the same time, the heat generated by the RC Snubber buffer circuit during operation can be effectively dissipated through multiple spring pins 40.

[0089] The drive control board resistors 51 and capacitors 52 can be combined in two different ways, corresponding to different locations of the GaN chipset 47. That is, the drive control board resistors 51 and capacitors 52 are combined in different ways for the GaN chipset 47 located near the DC busbar power terminals and near the AC busbar power terminals 33. One way is for each drive control board resistor 51 to correspond to two drive control board capacitors 52, and the other way is for each drive control board resistor 51 to correspond to one drive control board capacitor 52.

[0090] See also Figure 8 The spring pin 40 includes a semi-annular bottom end 400 and a long strip 401 connected to the semi-annular bottom end 400. The semi-annular bottom end 400 is ultrasonically welded to the corresponding area on the lining plate 4, and the long strip 401 passes through the drive control board 5 arranged above the lining plate 4 and extends out of the drive control board 5. The top of the long strip 401 is welded to the connecting through hole of the drive control board 5 for electrical conductivity, forming the ability to conduct high-frequency signals or drive currents. The semi-annular structure of the bottom end 400 can keep the spring pin 40 standing steadily on the flat metal layer, playing a certain stress buffering role. Compared with the commonly used two-part pressure pin structure press-fit, this spring pin 40 has a simple structure and low cost, and can achieve high-reliability bonding through simple processes such as welding or ultrasonic bonding.

[0091] The gallium nitride wide bandgap power module packaging structure provided by the embodiment of the present invention has a fully symmetrical internal structure, including a liner structure, a busbar structure, a gate control structure, etc., which form a completely balanced symmetry between the main current symmetry and the control loop parasitic parameters in the structural design. At the same time, the DC positive and negative busbar power terminals inside the module are directly and symmetrically bonded to the internal absorption capacitor 14, forming an extremely low inductance for the high-frequency component of the main current flowing through the module. Compared with the module structure without built-in capacitor 14, the main current loop inductance is reduced by 50%. The busbar power terminal pins are bonded using a high-reliability ultrasonic bonding USW process. Through the layered pin design, the overall pin bonding area is increased, the heat dissipation and current carrying capacity of the busbar power terminal are improved, and the vibration resistance and high and low temperature impact reliability of this module are improved. A PCB drive control board is integrated on the upper part of the module package, and a control drive circuit is provided on the PCB drive control board to reduce the gate loop distance and meet the needs of fast switching of wide bandgap power chips such as GaN. A Kelvin contact method is used to achieve a symmetrical gate structure from the control signal input to the chip, effectively achieving efficient current sharing control for high-speed, high-current multi-chip applications. Ferrite beads and RC-snubber buffer circuits are used in the control and main circuits, respectively, to mitigate switching oscillations and reduce electromagnetic interference. A DC capacitor and resistor are connected in parallel to the main current terminal of each power chip to form a snubber buffer circuit. This filters out potential high-frequency energy components from each chip and reduces these high-frequency components through an RC snubber, thereby reducing electromagnetic interference across the entire module. A new, simple spring pin 40 terminal is used to connect to the drive control board 5. Heat dissipated by the high-frequency snubber is effectively conducted through the elongated end 402 of the spring pin 40, effectively reducing electromagnetic interference from the module.

[0092] See also Figure 9 The embodiment of the present invention further provides a wide bandgap power module packaging method, comprising:

[0093] S100, preparing a liner, a plurality of spring pins, a symmetrical busbar power terminal and a drive control board according to the wide bandgap power module to be packaged; the liner is provided with a metal layer.

[0094] Symmetrical busbar power terminals include a positive DC busbar power terminal, a negative DC busbar power terminal, and an AC busbar power terminal. The AC busbar power terminal features a spring pin avoidance slot set, consisting of two symmetrically arranged slots. The slots' positions and dimensions match those of the corresponding spring pins.

[0095] S200 , sequentially bonding the gallium nitride chipset to the middle of the backing plate, bonding the gallium nitride chipset to the metal layer of the backing plate through wire bonding, and bonding the plurality of spring pins to both sides of the gallium nitride chipset.

[0096] The method for bonding the GaN chipset to the backing plate metal layer via wires is as follows: one end of the wire is connected to the upper surface electrode of the GaN chipset via ultrasonic bonding, and the other end of the wire is connected to the corresponding metal layer of the backing plate via ultrasonic bonding. In practice, the number and thickness of the wires can be selected based on the area of ​​the chip electrodes and the amount of current flowing through them, and are not specifically limited here. The wires can be backing plate bonding wires.

[0097] S300 , symmetrically bonding a plurality of capacitors to two circumferential edge sides of the metal layer of the liner.

[0098] S400 , sequentially bonding the obtained liner to the substrate, gluing the frame of the package shell to the edge of the package substrate, so that the frame of the package shell surrounds the package substrate.

[0099] The package shell is bonded to the edge of the package substrate by a sealant, and the size of the package shell is based on being able to completely cover the circuit structure on the package substrate.

[0100] S500, ultrasonically bond the symmetrical power busbar terminals to the liner in sequence, and arrange the top of the symmetrical power busbar terminals above the packaging tube shell and extend out of the packaging tube shell, and weld the PCB control board to the upper end of the spring pin to form a low-inductance symmetrical commutation and control circuit structure and a commutation buffer circuit.

[0101] S600: Pouring insulation glue into the package shell and curing it.

[0102] The potting compound can be silicone gel, which is poured into the housing by dispensing and then left to stand for 24 hours to allow the silicone gel to solidify.

[0103] The packaging method provided in the embodiment of the present invention is used to prepare the aforementioned packaging structure and has the structure and corresponding effects in the corresponding specific embodiment, which will not be described in detail here.

[0104] It should be understood by those skilled in the art that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Within the scope of the present invention, the above embodiments or technical features in different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity.

[0105] Additionally, to simplify the description and discussion, and to avoid obscuring the present invention, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided figures. Furthermore, devices may be shown in block diagram form to avoid obscuring the present invention, recognizing that the implementation details of these block diagram devices are highly dependent on the platform on which the present invention is implemented (i.e., such details should be well within the purview of those skilled in the art). While specific details (e.g., circuitry) are set forth to describe exemplary embodiments of the present invention, it will be apparent to those skilled in the art that the present invention can be implemented without or with variations in these specific details. Accordingly, the descriptions should be considered illustrative rather than restrictive.

[0106] While the invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description.

[0107] The embodiments of the present invention are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A GaN wide bandgap power module packaging structure, characterized in that: include: Package substrates, package shells and GaN wide bandgap power modules; The frame of the packaging tube shell surrounds the packaging substrate to form a receiving groove; The GaN wide bandgap power module is arranged in the receiving slot to form a low-inductance symmetrical commutation and control circuit structure; The GaN wide bandgap power module comprises a substrate having a metal layer and at least two GaN chipsets symmetrically bonded to the metal layer, a plurality of spring pins, a symmetrical busbar power terminal, a plurality of capacitors, and a drive control board arranged above the substrate; the substrate is bonded to the packaging substrate; at least two GaN chipsets are symmetrically bonded to the middle of the metal layer; a plurality of spring pins are arranged on both sides of the GaN chipset; each GaN chipset is connected to the symmetrical busbar power terminal and the spring pins through the metal layer; each GaN chipset is electrically connected to the drive control board through the spring pins to form a buffer circuit; the plurality of capacitors are symmetrically bonded to the two circumferential edge sides of the metal layer to form a low-inductance power loop; the top of the symmetrical busbar power terminal is arranged above the packaging tube shell and extends out of the packaging tube shell; The symmetrical busbar power terminal includes a DC busbar power terminal and an AC busbar power terminal relatively arranged at both ends of the lining plate; the DC busbar power terminal includes a positive DC busbar power terminal and a negative DC busbar power terminal, and the middle part of the negative DC busbar power terminal cooperates with the middle part of the positive DC busbar power terminal to form an overlapping coupling structure, so that the DC busbar power terminal reduces stray inductance when conducting currents in different directions. The DC busbar power terminal includes a connecting portion and two main bodies symmetrically arranged on both sides of the connecting portion, and the negative DC busbar power terminal includes an external main current connecting portion, a negative DC first bending portion, a negative DC second bending portion, and a negative DC third bending portion vertically connected in sequence. The folded portion and the negative DC bottom pin; the negative DC second folded portion cooperates with the connecting portion to form an overlapping coupling structure; the AC busbar power terminal includes an AC connecting portion, an AC folded portion and two AC bottom pins arranged symmetrically in reverse order; the middle and edge of the second AC folded portion are respectively provided with a spring pin avoidance groove group, each including two symmetrically arranged slot structures to form a low-interference current, driving the control board away from the surface of the liner to set multiple series combinations of resistors and capacitors; multiple series combinations are respectively arranged in parallel with multiple chips in the gallium nitride chipset; the positive and negative electrodes of the multiple series combinations are respectively connected to the drain and source of the multiple chips through spring pins to form an RC A snubber buffer circuit is provided to reduce electromagnetic interference from a gallium nitride chipset. The metal layer includes a first metal layer region and a second metal layer region disposed on the same side of the gallium nitride chipset. The first and second metal layer regions are disposed opposite each other and spaced apart. The first metal layer region includes an elongated main body region and two enlarged end portions extending from opposite ends of the elongated main body region toward the second metal layer region. The gate of the gallium nitride chipset is connected to the two enlarged end portions, which are connected to a drive control board via spring pins disposed in the center of the elongated main body region. The second metal layer region is elongated in shape. The source of the gallium nitride chipset is connected to both ends of the second metal layer region along its length. The second metal layer region is connected to the drive control board via spring pins disposed in the center of the elongated main body region, forming a Kelvin contact control circuit for the gallium nitride chipset. The metal layer region also includes four third metal layer regions, symmetrically disposed on either side of the two enlarged end portions. Magnetic beads are disposed between the enlarged end portions and the third metal layer regions.

2. The GaN wide bandgap power module packaging structure according to claim 1, characterized in that: The top of the symmetrical busbar power terminal extends out of the packaging tube shell, and the bottom pin is bonded to the lining plate; the symmetrical busbar power terminal includes a DC busbar power terminal and an AC busbar power terminal relatively arranged at both ends of the lining plate; the DC busbar power terminal includes a positive DC busbar power terminal and a negative DC busbar power terminal, and the middle part of the negative DC busbar power terminal cooperates with the middle part of the positive DC busbar power terminal to form an overlapping coupling structure, so that the stray inductance is reduced when the DC busbar power terminal conducts currents in different directions.

3. The GaN wide bandgap power module packaging structure according to claim 2, characterized in that: The DC busbar power terminal includes a connecting portion and two main bodies symmetrically arranged on both sides of the connecting portion; the main body includes an external power connecting portion, a first bending portion, a second bending portion and a bottom pin; the two ends of the second bending portion are respectively connected to the main body and the first bending portion; The two ends of the first bent portion are respectively connected to the external power connection portion and the bottom pin, and the shape of the first bent portion is adapted to the shape of the packaging tube shell, so that the external power connection portion extends out of the packaging tube shell, and the bottom pin is bonded to the backing plate; the bottom pin is a forked shape; the two ends of the second bent portion are respectively connected to the first bent portion and the connection portion, so that the main body is vertically connected to the connection portion.

4. The GaN wide bandgap power module packaging structure according to claim 3, characterized in that: The negative DC busbar power terminal includes an external main current connection portion, a negative DC first bend portion, a negative DC second bend portion, a negative DC third bend portion and a negative DC bottom pin which are vertically connected in sequence; The shape of the negative DC first bend portion is adapted to the shape of the packaging tube shell, so that the external main current connection portion extends out of the packaging tube shell; the negative DC second bend portion cooperates with the connection portion to form an overlapping coupling structure, and the middle portion of the negative DC second bend portion has a fork; the negative DC bottom pin is provided with two, symmetrically arranged on both sides of the fork of the negative DC second bend portion; the negative DC bottom pin is forked.

5. The GaN wide bandgap power module packaging structure according to claim 2, characterized in that: The AC busbar power terminal comprises an AC connecting portion, an AC bending portion and two AC bottom pins arranged in opposite directions and symmetrically in sequence; The AC bending portion includes a first AC bending portion and a second AC bending portion vertically connected in sequence. The shape of the first AC bending portion is adapted to the shape of the packaging tube shell so that the AC connecting portion extends out of the packaging tube shell; the middle and edge of the second AC bending portion are respectively provided with a spring pin avoidance groove group, each including two symmetrically arranged slot structures to form a low-interference current.

6. The GaN wide bandgap power module packaging structure according to claim 1, characterized in that: The spring pin includes a semi-annular bottom end and a long strip connected to the semi-annular bottom end.

7. A wide bandgap power module packaging method, characterized in that: include: According to the wide bandgap power module to be packaged, a liner, a plurality of spring pins, a symmetrical busbar power terminal and a drive control board are prepared; the liner is provided with a metal layer; The symmetrical busbar power terminal includes a DC busbar power terminal and an AC busbar power terminal relatively arranged at both ends of the liner; the DC busbar power terminal includes a positive DC busbar power terminal and a negative DC busbar power terminal, and the middle portion of the negative DC busbar power terminal cooperates with the middle portion of the positive DC busbar power terminal to form an overlapping coupling structure, so that the stray inductance is reduced when the DC busbar power terminal conducts currents in different directions. The DC busbar power terminal includes a connecting portion and two main bodies symmetrically arranged on both sides of the connecting portion. The negative DC busbar power terminal includes an external main current connecting portion, a negative DC first bending portion, a negative DC second bending portion, a negative DC third bending portion, and a negative DC bottom pin that are vertically connected in sequence; The negative DC second bend cooperates with the connection portion to form an overlapping coupling structure; the AC busbar power terminal includes an AC connection portion, an AC bend portion, and two AC bottom pins arranged symmetrically in opposite directions, which are connected in sequence vertically; the middle and edge of the second AC bend portion are respectively provided with a spring pin avoidance groove group, each including two symmetrically arranged slot structures to form a low-interference current, and the drive control board is provided with multiple series combinations of resistors and capacitors away from the surface of the liner; the multiple series combinations are respectively arranged in parallel with the multiple chips in the gallium nitride chipset; the positive and negative electrodes of the multiple series combinations are respectively connected to the drain and source electrodes of the multiple chips through spring pins to form an RC snubber. A buffer circuit is provided to reduce electromagnetic interference from the GaN chipset. The metal layer includes a first metal layer region and a second metal layer region disposed on the same side of the GaN chipset. The first and second metal layer regions are disposed opposite each other and spaced apart. The first metal layer region includes an elongated main body region and two enlarged end portions extending from opposite ends of the elongated main body region toward the second metal layer region. The gate of the GaN chipset is connected to the two enlarged end portions, which are connected to the drive control board via spring pins disposed in the center of the elongated main body region. The second metal layer region is elongated in shape, and the source of the GaN chipset is connected to both ends of the second metal layer region along its length. The second metal layer region is connected to the drive control board via spring pins disposed in the center of the elongated main body region to form a Kelvin contact control circuit for the GaN chipset. The metal layer region also includes four third metal layer regions, symmetrically disposed on either side of the two enlarged end portions. Magnetic beads are disposed between the enlarged end portions and the third metal layer regions. Sequentially bonding the gallium nitride chipset to the middle of the backing plate, bonding the gallium nitride chipset to the metal layer of the backing plate through wire bonding, and bonding the plurality of spring pins to both sides of the gallium nitride chipset; symmetrically bonding a plurality of capacitors to two circumferential edge sides of the metal layer of the liner; sequentially bonding the obtained liner to the substrate and gluing the frame of the package shell to the edge of the package substrate, so that the frame of the package shell surrounds the package substrate; The symmetrical power busbar terminals are ultrasonically bonded to the liner in sequence, with the tops of the symmetrical power busbar terminals positioned above and extending out of the package shell. The PCB control board is soldered to the upper ends of the spring pins to form a low-inductance symmetrical control circuit structure and a commutation buffer circuit. Fill the package with insulating glue and cure it.

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