Semiconductor module

Abstract

A semiconductor module capable of reducing switching loss of a semiconductor switching element is provided. The semiconductor module includes a semiconductor chip in which a switching element and a control terminal connected to a control electrode of the switching element are provided, a first resistance between the control electrode and the control terminal has a positive temperature coefficient, and a second resistance connected to the control terminal has a negative temperature coefficient, and a temperature coefficient of a resultant resistance of the resistances connected to the control terminal is 0 or less.

Description

Technical Field

[0001] This invention relates to semiconductor modules. Background Technology

[0002] In semiconductor switching elements, structures designed to minimize the influence of ambient temperature on switching characteristics are known. For example, Patent Document 1 discloses a semiconductor switching element that uses a temperature-dependent resistive element with a negative temperature coefficient as the gate resistor.

[0003] With this structure, even if the ambient temperature rises, the resistance value of the gate resistor can be reduced accordingly to correspond to the temperature rise.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 5-18127 Summary of the Invention

[0007] The technical problem that the invention aims to solve

[0008] However, in the technology disclosed in Patent Document 1, the temperature coefficient of the external resistance of the semiconductor switching element is chosen to be negative, without considering the temperature coefficient of the internal resistance from the gate electrode of the semiconductor switching element itself to the terminal connected to the external resistance. Therefore, even when the temperature coefficient of the external resistance is negative, the actual gate resistance of the semiconductor switching element (the combined resistance of the internal and external resistances) may still be positive due to the influence of the temperature coefficient of the internal resistance. In this case, the switching losses of the semiconductor switching element will increase.

[0009] The purpose of this invention is to provide a semiconductor module that can reduce the switching losses of semiconductor switching elements.

[0010] Technical means for solving technical problems

[0011] An invention for achieving the above objective is a semiconductor module comprising: a semiconductor chip having a switching element and a control terminal connected to a control electrode of the switching element, wherein a first resistance between the control electrode and the control terminal has a positive temperature coefficient; and a second resistor connected to the control terminal and having a negative temperature coefficient, wherein the combined resistance of the resistors connected to the control terminal has a temperature coefficient below 0.

[0012] Invention Effects

[0013] According to the present invention, a semiconductor module that can reduce the switching losses of semiconductor switching elements can be provided. Attached Figure Description

[0014] Figure 1 This is a diagram illustrating an example of the structure of semiconductor module 1.

[0015] Figure 2 This is a diagram showing the equivalent circuit of semiconductor module 1.

[0016] Figure 3 This is a schematic diagram illustrating the temperature characteristics of the first resistor, the second resistor, and the combined resistor.

[0017] Figure 4 This is a schematic diagram illustrating the temperature characteristics of the first resistor, the second resistor, and the combined resistor.

[0018] Figure 5 This is a schematic diagram illustrating the relationship between temperature and switching losses when a switching element is turned on.

[0019] Figure 6 This is a schematic diagram illustrating the relationship between the maximum permissible carrier frequency and the maximum permissible current of a switching element.

[0020] Figure 7 This is a diagram illustrating an example of the temperature changes of the first and second resistors.

[0021] Figure 8 This is a diagram illustrating an example of the structure of semiconductor module 2.

[0022] Figure 9 This is a diagram showing the equivalent circuit of semiconductor module 2.

[0023] Figure 10 This is a diagram showing a modified example of the structure of semiconductor module 2.

[0024] Figure 11 This is a diagram illustrating an example of the structure of semiconductor module 3.

[0025] Figure 12 This is a diagram showing the equivalent circuit of semiconductor module 3. Detailed Implementation

[0026] The following points will be understood from the description in this instruction manual and the accompanying drawings.

[0027] ==Implementation Method 1==

[0028] <Structure of a Semiconductor Module>

[0029] Figure 1This is a diagram illustrating an example of the structure of the semiconductor module 1 according to this embodiment. The semiconductor module 1 includes an insulating plate 10, a first conductive pattern 11, a second conductive pattern 12, a semiconductor chip 13, a second resistor R2, a first terminal 14, a second terminal 15, a third terminal 16, and a housing 17.

[0030] The insulating plate 10 is made of, for example, ceramic, resin, etc. A first conductive pattern 11 and a second conductive pattern 12 are formed on the surface of the insulating plate 10, and are generally rectangular patterns made of, for example, copper, aluminum, or alloys containing them.

[0031] A semiconductor chip 13 is provided on the first conductive pattern 11. At least a second resistor R2 is provided on the second conductive pattern 12. Here, the semiconductor chip 13, on which the first resistor R1 is formed (described later), and the second resistor R2 are disposed at a predetermined distance d from each other.

[0032] A semiconductor chip 13 is disposed on the first conductive pattern 11. The semiconductor chip 13 is a chip using a substrate of Si, SiC, or GaN. In this embodiment, the semiconductor chip 13 is a chip using a Si substrate. A switching element 130 is provided in the semiconductor chip 13.

[0033] The switching element 130 is an IGBT, a MOS transistor, or a bipolar transistor. In this embodiment, the switching element 130 uses an N-type MOS transistor.

[0034] The front side of the semiconductor chip 13 has a gate terminal 131 and a source terminal 132 of the switching element 130. The back side of the semiconductor chip 13 has a drain terminal (not shown) of the switching element 130. The gate terminal 131, the source terminal 132, and the drain terminal of the semiconductor chip 13 are respectively connected to the gate electrode GE, the source electrode SE, and the drain electrode DE of the switching element 130, which is a MOSFET.

[0035] As described above, in this embodiment, the switching element 130 is a MOSFET. However, when the switching element 130 is an IGBT, the "source" in this embodiment corresponds to the "emitter" and the "drain" corresponds to the "collector". Furthermore, when the switching element 130 is a bipolar transistor, the "gate" in this embodiment corresponds to the "base", the "source" corresponds to the "emitter", and the "drain" corresponds to the "collector".

[0036] Furthermore, in this embodiment, "gate terminal" is equivalent to "control terminal", "source terminal" is equivalent to "ground side terminal", and "drain terminal" is equivalent to "power supply side terminal". In this embodiment, "gate electrode" is equivalent to "control electrode", "source electrode" is equivalent to "ground side electrode", and "drain electrode" is equivalent to "power supply side electrode".

[0037] In this embodiment, a MOSFET containing a parasitic diode is used as the switching element 130. However, if a component without a parasitic diode (such as an IGBT) is used, a return diode may be connected to the switching element 130.

[0038] A resistor with a positive temperature coefficient (hereinafter referred to as "first resistor R1") is formed between the gate electrode GE and the gate terminal 131, the details of which will be explained later. That is, the resistance value of the first resistor R1 increases with increasing temperature. The first resistor R1 is a built-in resistor formed in the semiconductor chip 13. In order to form the first resistor R1 with a positive temperature coefficient, the semiconductor chip 13 has a resistive wiring that connects the gate electrode GE and the gate terminal 131. As the material for such resistive wiring, materials such as metals and polysilicon can be used.

[0039] A second resistor R2 is disposed on the second conductive pattern 12. One end R2a of the second resistor R2 is connected to the gate terminal 131 of the semiconductor chip 13 via a wiring component, and the other end R2b is connected to the first terminal 14 via a wiring component. The wiring component can be made of any conductive material, such as aluminum or copper wires or lead frames. In the following description, "connection" can refer to an electrical connection or a connection via a diode or resistor.

[0040] The second resistor R2 has a negative temperature coefficient. That is, the resistance of the second resistor R2 decreases as the temperature increases. For example, ceramic can be used as the material for the second resistor R2 with a negative temperature coefficient.

[0041] One end of the first terminal 14 is connected inside the housing 17 to the other end R2b of the second resistor R2 via a wiring member. The other end of the first terminal 14 extends outside the housing 17. The other end of the first terminal 14 is connected to an external drive device (not shown). One end of the second terminal 15 is connected inside the housing 17 to the source terminal 132 of the switching element 130 via a wiring member. The other end of the second terminal 15 extends outside the housing 17. The other end of the second terminal 15 is connected to an external device (not shown). One end of the third terminal 16 is connected inside the housing 17 to the first conductor pattern 11 via a wiring member. The first conductor pattern 11 is bonded to the drain terminal of the switching element 130 via a bonding material such as solder. The other end of the third terminal 16 extends outside the housing 17. The other end of the third terminal 16 is connected to an external device (not shown).

[0042] The housing 17 is formed of resin or the like, and houses the insulating plate 10, the first conductive pattern 11, the second conductive pattern 12, the semiconductor chip 13, and the second resistor R2. In this embodiment, the housing 17... Figure 1The top view shown is of a generally rectangular box-shaped member with an opening on the front. In the housing 17 of this embodiment, a first terminal 14 extends from one side of the housing 17. In addition, a second terminal 15 and a third terminal 16 extend from the opposite side of the aforementioned one side of the housing 17.

[0043] <Temperature characteristics of resistance>

[0044] Here, the temperature characteristics of the first resistor R1, the second resistor R2, and the resistor connected to the gate terminal 131 are explained. The "resistance connected to the gate terminal 131" refers to the resistance between the gate electrode GE and the first terminal 14, which will be referred to as the "combined resistance" below. Figure 1 In semiconductor module 1, the combined resistor is the combined resistor of the first resistor R1 and the second resistor R2 connected in series.

[0045] Figure 2 This is a diagram showing the equivalent circuit of semiconductor module 1. The first resistor R1 and the second resistor R2 are connected in series. That is, the combined resistance of the first resistor R1 and the second resistor R2 is the sum of the resistance values ​​of the first resistor R1 and the second resistor R2.

[0046] Figure 3 and Figure 4 This is a schematic diagram illustrating two different cases of the temperature characteristics of the first resistor R1, the second resistor R2, and the combined resistor. Figure 3 and Figure 4 In the diagram, the temperature characteristics of the first resistor R1 are represented by a dashed line, the temperature characteristics of the second resistor R2 are represented by a dashed line, and the temperature characteristics of the combined resistor are represented by a solid line.

[0047] In this embodiment, the temperature coefficient of the combined resistance of the first resistor R1 and the second resistor R2 is designed to be 0 or less. That is, the resistance value of the combined resistance remains constant or decreases as the temperature rises. Furthermore, the temperature coefficient of this combined resistance can be 0 or less, at least within the operating range of the semiconductor module 1. In this embodiment, the operating range is defined as a temperature above T0 and below T1. Temperature T0 can be a value set according to the specifications of the semiconductor module 1 (e.g., -40°C). Temperature T1 can be the maximum bonding temperature (e.g., 175°C). Figure 3 and Figure 4 In this diagram, the temperature characteristics of the first resistor R1, the second resistor R2, and the combined resistor are simply represented by a straight line, but this is not the only method. Their temperature characteristics can also be curves. That is to say, within the operating range, the temperature coefficient of the combined resistor only needs to be below 0, and can be varied according to the temperature range below 0.

[0048] Figure 3This indicates that the temperature coefficient of the combined resistance is 0, meaning the combined resistance will not change with temperature. Figure 4 This indicates that the temperature coefficient of the combined resistance is negative, meaning that the combined resistance decreases as the temperature increases.

[0049] <Switching Characteristics>

[0050] Here, the switching characteristics of the switching element 130 in semiconductor module 1 will be explained. Figure 5 This is a schematic diagram illustrating the relationship between temperature and switching losses when switching element 130 is turned on. Figure 6 This is a schematic diagram illustrating the relationship between the maximum permissible carrier frequency and the maximum permissible current of the switching element 130. Figure 5 and Figure 6 In the diagram, solid lines represent semiconductor module 1 of this embodiment, while dashed lines represent conventional semiconductor modules whose synthesized resistance has a positive temperature coefficient.

[0051] like Figure 5 As shown, the combined resistor of existing semiconductor modules has a positive temperature coefficient, so its resistance increases with rising temperature. In contrast, the combined resistor of semiconductor module 1 has a temperature coefficient below 0, so its resistance decreases with rising temperature. Therefore, compared to existing semiconductor modules, semiconductor module 1 can suppress the increasing switching losses that occur with rising temperature during conduction. Figure 5 The text describes the switching losses when the switching element 130 is turned on, but the same applies when it is turned off.

[0052] Furthermore, compared to existing semiconductor modules, semiconductor module 1 increases the upper limit of its temperature specification. Therefore, as... Figure 6 As shown, both the maximum permissible carrier frequency and the maximum permissible current of semiconductor module 1 can be set higher than those of existing semiconductor modules. Here, "maximum permissible carrier frequency" refers to the maximum frequency at which the switching element 130 can be turned on and off. "Maximum permissible current" refers to the maximum current value that can flow from the source electrode to the drain electrode within the rated junction temperature range of the switching element 130.

[0053] In addition, the semiconductor module 1 of this embodiment can suppress the oscillation phenomenon that is prone to occur during operation at low temperatures, such as when the operation starts or when the operation is at a low current. On this basis, it can reduce the loss during stable operation under high current, which is prone to causing great losses.

[0054] <Layout of Conductive Patterns>

[0055] Here, the layout of the first conductive pattern 11 and the second conductive pattern 12 will be described. As described above, the semiconductor chip 13 on which the first resistor R1 is formed and the second resistor R2 are disposed at a predetermined distance d apart from each other.

[0056] The setting of the interval between the first conductive pattern 11 and the second conductive pattern 12 will be described in detail below. The interval between the first conductive pattern 11 and the second conductive pattern 12 is set based on the temperature changes of the first resistor R1 and the second resistor R2 respectively when the semiconductor device using the semiconductor module 1 is operating.

[0057] Figure 7 This is a diagram illustrating an example of the temperature changes of the first resistor R1 and the second resistor R2 over the operating time of the semiconductor module 1. The example described here is based on the case where the semiconductor module 1 drives a load (not shown) based on a PWM signal input to the first terminal 14.

[0058] Figure 7 In the process, before time t0, semiconductor module 1 operates stably based on a PWM signal with a specified duty cycle (e.g., 50%), and the temperatures of the first resistor R1 and the second resistor R2 remain constant. As the switching element 130 heats up, the temperature of the first resistor R1 becomes higher than that of the second resistor R2. Time t0 is the moment when the operating state of semiconductor module 1 switches. Specifically, it is the timing at which the duty cycle of the PWM signal (e.g., 60%) is increased to increase the power supplied to the load. Thus, as the operating state of semiconductor module 1 switches, the switching element 130 heats up more, and the temperature of the first resistor R1 (the temperature of semiconductor chip 13) begins to rise.

[0059] Then, the heat generated by the switching element 130 diffuses. Time t1 is the moment when the heat diffused from the switching element 130 reaches the second resistor R2, causing the temperature of the second resistor R2 to begin to rise. By setting the semiconductor chip 13, on which the first resistor R1 is formed, and the second resistor R2 apart from each other by a predetermined distance d, the temperature rise of the second resistor R2 is delayed by a predetermined time t after the temperature rise of the first resistor R1 begins. a Let's start again.

[0060] Subsequently, at time t2, the temperatures of the first conductive pattern 11 and the second conductive pattern 12 in semiconductor module 1 remain constant. Similarly, as the switching element 130 heats up, the temperature of the first resistor R1 is higher than the temperature of the second resistor R2.

[0061] Furthermore, even when the duty cycle of the PWM signal remains constant, the temperature of the first conductive pattern 11, where the semiconductor chip 13 is located, may sometimes rise, for example, when the load state transitions to a light load state. In this embodiment, the second resistor R2 is positioned at a predetermined distance d from the semiconductor chip 13 where the first resistor R1 is formed, so that the temperature rise of the second resistor R2 occurs after a predetermined time t has elapsed since the temperature rise of the semiconductor chip 13. a It happened again.

[0062] Therefore, in the above situation, after a specified time t after time t0... a During this period, only the temperature of the first resistor R1 rises, while the temperature of the second resistor R2 remains almost unchanged. Therefore, the resistance value of the combined resistor increases, which delays the on and off states of the switching element 130.

[0063] Existing semiconductor modules may experience oscillations when their operating states change or when the load suddenly shifts to a light load state. In this embodiment, the oscillation phenomenon can be suppressed because the resistance value of the synthesized resistor increases in such cases.

[0064] Here, the specified time t a The time can be, for example, more than 1 second and less than 120 seconds. This is because if the time is too short, the oscillation phenomenon cannot be suppressed, and if it is too long, the loss will increase. Therefore, the specified distance d can be, for example, more than 0.5 mm and less than 60 mm. In addition, the temperature of the second resistor R2 remaining almost constant means, for example, that the temperature rise of the second resistor R2 is within 10% of the temperature rise of the semiconductor chip 13. By setting it within 10%, the resistance rise of the first resistor R1 can be dominated, and the oscillation phenomenon can be suppressed.

[0065] ==Implementation Method 2==

[0066] Figure 8 This is a diagram illustrating an example of the structure of the semiconductor module 2 in this embodiment. Figure 9 This is a diagram showing the equivalent circuit of semiconductor module 2. Semiconductor module 2 differs from semiconductor module 1 in that it also includes a third resistor R3 and a first diode D1. Figure 8 and Figure 9 In the diagram, all the labels except for the third resistor R3 and the first diode D1 are the same as... Figure 1 and Figure 2 The same.

[0067] The third resistor R3 is disposed on the second conductive pattern 12. The third resistor R3 is disposed between the gate terminal 131 connected to one end R2a of the second resistor R2 and the first terminal 14 connected to the other end R2b of the second resistor R2, and is connected in parallel with the second resistor R2. The semiconductor chip 13 on which the first resistor R1 is formed is disposed at a predetermined distance d from the second resistor R2 and the third resistor R3.

[0068] The third resistor R3 has a negative temperature coefficient. The material for the third resistor R3, which also has a negative temperature coefficient, can be, for example, ceramic, similar to the second resistor R2.

[0069] A first diode D1 is disposed on the second conductive pattern 12. The first diode D1 is located between the gate terminal 131 connected to one end R2a of the second resistor R2 and the first terminal 14 connected to the other end R2b of the second resistor R2, and is connected in series with a third resistor R3. In this embodiment, the cathode of the first diode D1 is connected to the gate terminal 131 side, and the anode is connected to the first terminal 14 side. More specifically, the first diode D1, the third resistor R3, and the first terminal 14 are connected sequentially from the gate terminal 131.

[0070] Therefore, the combined resistance during conduction is less than the combined resistance during cutoff, thus enabling faster switching speed. Furthermore, even though the resistance values ​​of the second resistor R2 and the third resistor R3 decrease with increasing temperature, no current flows through the second resistor R2 during cutoff, thus suppressing surge voltage during cutoff.

[0071] As a variation, such as Figure 10 As shown, the connection relationship between the anode and cathode of the first diode D1 can be reversed compared to the semiconductor module 2 of this embodiment. That is, the cathode of the first diode D1 is connected to the first terminal 14 side, and the anode is connected to the gate terminal 131 side. With such a structure, the combined resistance when cut off is less than the combined resistance when turned on.

[0072] ==Implementation Method 3==

[0073] Figure 11 This is a diagram illustrating an example of the structure of the semiconductor module 3 in this embodiment. Figure 12 This is a diagram showing the equivalent circuit of semiconductor module 3. Semiconductor module 3 differs from semiconductor module 2 in that it also includes a second diode D2. Figure 11 and Figure 12 In the diagram, all the labels except for the second diode D2 are the same as... Figure 8 and Figure 9 The same.

[0074] The second diode D2 is disposed on the second conductive pattern 12. The second diode D2 is located between the gate terminal 131 and the first terminal 14, connected in series with the second terminal R2, and connected in reverse parallel with the first diode D1. More specifically, the second diode D2, the second resistor R2, and the first terminal 14 are connected sequentially from the gate terminal 131. The semiconductor chip 13, on which the first resistor R1 is formed, is disposed at a predetermined distance d from the second resistor R2 and the third resistor R3.

[0075] Therefore, the combined resistance during conduction and the combined resistance during cutoff can be easily set to desired values. Specifically, the combined resistance during conduction is the resistance value of the second resistor R2. The combined resistance during cutoff is the resistance value of the third resistor R3.

[0076] ==Summary==

[0077] The semiconductor modules 1, 2, and 3 of embodiments 1 to 3 include: a semiconductor chip 13, which has a switching element 130 and a control terminal connected to a control electrode of the switching element 130, a first resistor R1 between the control electrode and the control terminal having a positive temperature coefficient; and a second resistor R2, which is connected to the control terminal and has a negative temperature coefficient, and the combined resistance of the resistors connected to the control terminal has a temperature coefficient of 0 or less.

[0078] Therefore, the combined resistance of the resistors connected to the control terminals decreases as the temperature rises. This reduces the switching losses of the switching element 130.

[0079] Furthermore, in semiconductor modules 1, 2, and 3 of embodiments 1 to 3, the temperature coefficient of the synthesized resistor is at least 0 or less within the operating range of semiconductor modules 1, 2, and 3. This allows for a reduction in the switching losses of the switching element 130 within the operating range of semiconductor modules 1, 2, and 3.

[0080] Additionally, the semiconductor modules 2 and 3 in embodiments 2 and 3 include: a third resistor R3, which is disposed between a control terminal connected to one end of the second resistor R2 and a first terminal 14 connected to the other end of the second resistor R2, and is connected in parallel with the second resistor R2, and has a negative temperature coefficient; and a first diode D1, which is disposed between the control terminal and the other end of the second resistor R2, and is connected in series with the third resistor R3.

[0081] Therefore, the combined resistance during conduction is less than the combined resistance during cutoff. This allows for faster switching speeds. Furthermore, even though the resistance values ​​of the second resistor R2 and the third resistor R3 decrease with increasing temperature, no current flows through the second resistor R2 during cutoff, thus suppressing surge voltage during cutoff.

[0082] In addition, the semiconductor module 3 of embodiment 3 includes a second diode D2, which is disposed between the control terminal and the first terminal 14 connected to the other end of the second resistor R2, and is connected in series with the second resistor R2 and connected in reverse parallel with the first diode D1.

[0083] Therefore, it is easy to set the combined resistance when conducting and the combined resistance when cut off to the desired values.

[0084] In addition, the semiconductor modules 1, 2, and 3 of embodiments 1 to 3 include: a first conductive pattern 11 provided with a semiconductor chip 13; and a second conductive pattern 12 provided with a second resistor R2, a third resistor R3, and a first diode D1.

[0085] Thus, the temperature of the components mounted on the second conductive pattern 12 can remain almost constant.

[0086] In addition, the semiconductor module 3 of embodiment 3 further includes: a first conductive pattern 11 provided with a semiconductor chip 13; and a second conductive pattern 12 provided with a second resistor R2, a third resistor R3, a first diode D1 and a second diode D2.

[0087] Thus, the temperature of the components mounted on the second conductive pattern 12 can remain almost constant.

[0088] Furthermore, in semiconductor modules 1, 2, and 3 of embodiments 1 to 3, the second resistor R2 and the semiconductor chip 13 are separated by a predetermined distance, so that the temperature rise of the second resistor R2 occurs after a predetermined time t has elapsed since the temperature rise of the semiconductor chip 13. a It happened again.

[0089] In addition, in the semiconductor modules 2 and 3 of embodiments 2 and 3, the second resistor and the third resistor are disposed at a predetermined distance from the semiconductor chip 13, so that the temperature rise of the second resistor R2 and the third resistor R3 occurs after a predetermined time has elapsed since the temperature rise of the semiconductor chip.

[0090] Furthermore, in semiconductor modules 1, 2, and 3 of embodiments 1 to 3, the specified time is more than 1 second and less than 120 seconds. This allows for the suppression of oscillations that occur when the operating state changes or when the load state suddenly changes to a light load state, and also suppresses switching losses.

[0091] Furthermore, in semiconductor modules 1, 2, and 3 of embodiments 1 to 3, the specified distance is 0.5 mm or more and 60 mm or less. This allows for the suppression of oscillations that occur when the operating state changes or when the load state suddenly changes to a light load state, and also suppresses switching losses.

[0092] In addition, in the semiconductor modules 1, 2, and 3 of embodiments 1 to 3, the switching element 130 is an IGBT or a MOS transistor.

[0093] In addition, in the semiconductor modules 1, 2, and 3 of embodiments 1 to 3, the semiconductor chip 13 is a chip using any one of Si, SiC, and GaN substrates.

[0094] The above-described embodiments are provided for ease of understanding of the present invention and are not intended to limit or explain the present invention. Modifications or improvements can be made to the present invention without departing from its spirit, and equivalent inventions are also included within the scope of the present invention.

[0095] Label Explanation

[0096] 1 Semiconductor Module

[0097] 10 Insulation Board

[0098] 11 First conductive pattern

[0099] 12 Second conductive pattern

[0100] 13 Semiconductor chips

[0101] 130 Switching element

[0102] 131 Gate terminal

[0103] 132 source terminal

[0104] 14 First terminal

[0105] 15 Second terminal

[0106] 16 Third terminal

[0107] 17. Casing

[0108] 2 Semiconductor Modules

[0109] 3 Semiconductor Modules

[0110] R1 is the first resistor.

[0111] R2 is the second resistor.

[0112] R3 is the third resistor.

[0113] D1 First diode

[0114] D2 is the second diode.

Claims

1. A semiconductor module, characterized in that, include: A semiconductor chip having a switching element and a control terminal connected to a control electrode of the switching element, wherein a first resistance between the control electrode and the control terminal has a positive temperature coefficient; A second resistor, which is connected to the control terminal, has a negative temperature coefficient; A third resistor, connected in parallel with the second resistor and having a negative temperature coefficient; and The first diode connected in series with the third resistor The temperature coefficient of the combined resistance of the resistors connected to the control terminal is below 0.

2. The semiconductor module as described in claim 1, characterized in that, The temperature coefficient of the synthesized resistor is below 0 at least within the temperature range in which the semiconductor module operates.

3. The semiconductor module as described in claim 1, characterized in that, It includes a second diode connected in series with the second resistor and connected in reverse parallel with the first diode.

4. The semiconductor module as described in claim 2, characterized in that, It includes a second diode connected in series with the second resistor and connected in reverse parallel with the first diode.

5. The semiconductor module as described in claim 1, characterized in that, include: The semiconductor chip is provided with a first conductive pattern; and A second conductive pattern is provided, comprising the second resistor, the third resistor, and the first diode.

6. The semiconductor module as described in claim 2, characterized in that, include: The semiconductor chip is provided with a first conductive pattern; and A second conductive pattern is provided, comprising the second resistor, the third resistor, and the first diode.

7. The semiconductor module as described in claim 3, characterized in that, Also includes: The semiconductor chip is provided with a first conductive pattern; and A second conductive pattern is provided, comprising the second resistor, the third resistor, the first diode, and the second diode.

8. The semiconductor module as described in claim 4, characterized in that, Also includes: The semiconductor chip is provided with a first conductive pattern; and A second conductive pattern is provided, comprising the second resistor, the third resistor, the first diode, and the second diode.

9. The semiconductor module as described in any one of claims 1 to 4, characterized in that, The second resistor is disposed at a predetermined distance from the semiconductor chip, so that the temperature rise of the second resistor occurs after a predetermined time has elapsed since the temperature rise of the semiconductor chip.

10. The semiconductor module as described in any one of claims 5 to 8, characterized in that, The second resistor and the third resistor are disposed at a predetermined distance from the semiconductor chip, so that the temperature rise of the second resistor and the third resistor occurs only after a predetermined time has elapsed since the temperature rise of the semiconductor chip.

11. The semiconductor module as claimed in claim 9, characterized in that, The specified time is between 1 second and 120 seconds.

12. The semiconductor module as claimed in claim 10, characterized in that, The specified time is between 1 second and 120 seconds.

13. The semiconductor module as described in claim 9, characterized in that, The specified distance is 0.5mm or more and 60mm or less.

14. The semiconductor module as claimed in claim 10, characterized in that, The specified distance is 0.5mm or more and 60mm or less.

15. The semiconductor module as described in claim 11 or 12, characterized in that, The specified distance is 0.5mm or more and 60mm or less.

16. The semiconductor module as claimed in any one of claims 1 to 8, characterized in that, The switching element is an IGBT or a MOS transistor.

17. The semiconductor module as claimed in any one of claims 1 to 8, characterized in that, The semiconductor chip is a chip using any of the following substrates: Si, SiC, and GaN.

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