Display device

Abstract

The present application relates to a display device. According to an exemplary embodiment of the present disclosure, a display device includes: a display panel divided into a display area, a non-display area, a bending area, and a pad area, and bent in one direction in the bending area; a plurality of pixels arranged in the display area; at least one gate driver arranged in the non-display area and configured to provide a gate voltage to the plurality of pixels; a flexible film connected to a plurality of pads arranged in the pad area; and at least one electrostatic discharge (ESD) circuit arranged in the pad area and connected to the at least one gate driver via a discharge line.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a display device including an electrostatic discharge (ESD) circuit. Background Art

[0002] Display devices used in computer monitors, TVs, and mobile phones include organic light emitting displays (OLEDs) and the like that emit light by themselves, and liquid crystal displays (LCDs) and the like that require a separate light source.

[0003] Such various display devices include a display panel containing a plurality of sub-pixels and a driving unit for driving the display panel. The driving unit includes a gate driver that provides a gate signal to the display panel and a data driver that provides a data voltage. When signals such as the gate signal and the data voltage are supplied to the sub-pixels, the selected sub-pixels emit light, thereby displaying an image.

[0004] Furthermore, to reduce the bezel, the driving unit may be disposed on the rear surface of the display panel, and lines configured to connect the driving unit and the sub-pixels may be bent from the front to the rear of the display panel.

[0005] As described above, when the wires are bent from the front to the rear of the display panel, cracks in peripheral components or separation between peripheral components are caused.

[0006] Therefore, there is a problem that the ESD circuit adjacent to the bending region is electrically corroded or oxidized due to moisture penetration caused by cracks or separation of components. Summary of the Invention

[0007] An object of the present disclosure is to provide a display device including an electrostatic discharge circuit in a pad area.

[0008] Another object of the present disclosure is to provide a display device in which oxygen and moisture cannot penetrate into an electrostatic discharge circuit.

[0009] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0010] To solve the above problems, according to an exemplary embodiment of the present disclosure, a display device may include: a display panel divided into a display area, a non-display area, a bending area, and a pad area, and bent in one direction in the bending area; a plurality of pixels arranged in the display area; at least one gate driver arranged in the non-display area and configured to provide a gate voltage to the plurality of pixels; a flexible film connected to a plurality of pads arranged in the pad area; and at least one electrostatic discharge (ESD) circuit arranged in the pad area and connected to the at least one gate driver through a discharge line.

[0011] Additional details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0012] According to the present disclosure, by discharging static electricity through an electrostatic discharge circuit, a gate driver and a plurality of pixels connected thereto can be protected.

[0013] According to the present disclosure, due to the first and second grooves, the planarization layer configured to cover the electrostatic discharge circuit does not fall off even when the display panel is bent, so that external moisture or oxygen cannot penetrate into the electrostatic discharge circuit.

[0014] Effects according to the present disclosure are not limited to the contents of the above examples, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0016] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure.

[0017] Figure 2 is a plan view of an electrostatic discharge circuit of a display device according to an exemplary embodiment of the present disclosure.

[0018] Figure 3 is a circuit diagram of an electrostatic discharge circuit of a display device according to an exemplary embodiment of the present disclosure.

[0019] Figure 4 It is along Figure 2 A cross-sectional view taken along line IV-IV' shown in FIG.

[0020] Figure 5 It is along Figure 2 A cross-sectional view taken along line V-V' shown in FIG.

[0021] Figure 6 It is along Figure 2 A cross-sectional view taken along line VI-VI' shown in FIG.

[0022] Figure 7 is a cross-sectional view of an electrostatic discharge circuit of a display device according to another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] The advantages and features of the present disclosure and methods for achieving them will be more clearly understood through the exemplary embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following exemplary embodiments, but can be implemented in various different forms. The exemplary embodiments are provided only to make the disclosure of the present disclosure complete and to fully provide the category of the present disclosure to those of ordinary skill in the art to which the present disclosure belongs, and the present disclosure will be defined by the appended claims.

[0024] The shapes, sizes, ratios, angles, quantities, etc. used to describe the exemplary embodiments of the present disclosure illustrated in the accompanying drawings are merely examples, and the present disclosure is not limited thereto. Throughout the specification, similar reference numerals generally represent similar elements. In addition, in the following description of the present disclosure, detailed descriptions of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," "having," and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only." Unless expressly stated otherwise, any reference to the singular may include the plural.

[0025] Even if not explicitly stated, components are interpreted as including ordinary margins of error.

[0026] When terms such as "on," "over," "below," and "next to" are used to describe the positional relationship between two components, unless these terms are used with the term "immediately" or "directly," one or more components may be disposed between the two components.

[0027] When an element or layer is referred to as being “on” another element or layer, it can be directly on the other element or layer, or intervening elements or layers may be present.

[0028] Although the terms "first," "second," and the like are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of the present disclosure, the first component to be mentioned below may be the second component.

[0029] Throughout the specification, like reference numerals generally refer to like elements.

[0030] Since the size and thickness of each component shown in the drawings are illustrated for convenience of description, the present disclosure is not necessarily limited to the size and thickness of each component shown.

[0031] The features of the various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may be technically interlocked and operated in various ways, and the embodiments may be performed independently of each other or in association with each other.

[0032] The transistor used in the display device of the present disclosure can be implemented as at least one of an n-channel transistor (NMOS) and a p-channel transistor (PMOS). The transistor can be implemented as an oxide semiconductor transistor having an oxide semiconductor as an active layer or a low-temperature polysilicon (LTPS) transistor having an LTPS as an active layer. The transistor may include at least a gate electrode, a source electrode, and a drain electrode. The transistor can be implemented as a thin film transistor (TFT) on a display panel. In the transistor, carriers flow from the source electrode to the drain electrode. In the case of an n-channel transistor (NMOS), since the carriers are electrons, the source voltage has a voltage level lower than the voltage level of the drain voltage, so that electrons can flow from the source electrode to the drain electrode. In an n-channel transistor (NMOS), current can flow from the drain electrode to the source electrode, and the source electrode can be an output terminal. In the case of a p-channel transistor (PMOS), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source electrode to the drain electrode. In a p-channel transistor (PMOS), since holes flow from the source electrode to the drain electrode, current flows from the source electrode of the transistor to the drain electrode, and the drain electrode can be an output terminal. Therefore, it should be noted that the source and drain electrodes of the transistor are not fixed, because the source and drain electrodes can change according to the applied voltage. In this disclosure, it is assumed that the transistor is an n-channel transistor (NMOS), but it is not limited to this. In addition, a p-channel transistor (PMOS) can be used, so the circuit configuration can be changed.

[0033] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0034] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 1 , the display device 100 includes a display panel 110 , a gate driver 120 , a flexible film 130 , and a printed circuit board 140 .

[0035] The display panel 110 is a panel for displaying images. The display panel 110 may include various circuits, lines, and light-emitting elements provided on a substrate. Specifically, the display panel 110 may be divided into a display area AA, a non-display area NA, a bending area BA, and a pad area PA.

[0036] The display area AA of the display panel 110 is an area where an image is displayed. A plurality of pixels PX may be provided, and the plurality of pixels PX are divided and connected to the plurality of data lines and the plurality of gate lines that intersect with each other in the display area AA of the display panel 110. In addition, the plurality of pixels PX may include a display element that emits light and a pixel circuit that drives the display element. For example, when the display panel 110 is an organic light-emitting display panel, the display element may be an organic light-emitting element including an anode, an organic light-emitting layer, and a cathode. Alternatively, when the display panel 110 is an inorganic light-emitting display panel, the display element may be or include a micro-LED (micro-LED) or a light-emitting diode (LED) having an n-type semiconductor layer, a p-type semiconductor layer, and a light-emitting layer. However, the present disclosure is not limited thereto, and the display element may be configured in various ways.

[0037] In addition, the non-display area NA of the display panel 110 is an area surrounding the display area AA and not displaying an image. At least one gate driver for driving a plurality of pixels may be provided in the non-display area NA of the display panel 110. In addition, a plurality of gate lines configured to connect the at least one gate driver and the plurality of pixels PX, as well as high-potential driving voltage lines and low-potential driving voltage lines for applying driving voltages to the plurality of pixels PX may be provided in the non-display area NA of the display panel 110. However, the components provided in the non-display area NA of the display panel 110 are not limited thereto, and various circuits and lines may be additionally provided.

[0038] In addition, the pad area PA of the display panel 110 is an area where a plurality of pads are provided. Pads connected to a plurality of data lines may be provided in the pad area PA of the display panel 110. Therefore, a flexible film may be attached to the pad area PA of the display panel 110. In addition, an electrostatic discharge (ESD) circuit may be provided in the pad area PA of the display panel 110.

[0039] In addition, the bending area BA of the display panel 110 refers to an area where the display panel 110 bends in one direction. In addition, the display area AA and the non-display area NA may be provided on one side of the bending area BA, and the pad area PA may be provided on the other side of the bending area BA. Therefore, as the display panel 110 bends in the bending area BA, the pad area PA may be provided below the display area AA and the non-display area NA.

[0040] The gate driver 120 provides a gate signal to a plurality of pixels PX. The gate driver 120 includes a plurality of stages, and the respective stages may be electrically connected to each other. Therefore, a gate voltage output from one stage may be transmitted to another stage. In addition, the respective stages may sequentially provide the gate voltage to the plurality of pixels PX connected to the respective stages through the gate line. In addition, as Figure 1As shown, it may be formed in the non-display area NA of the display panel 110 in a gate in panel (GIP) form.

[0041] The plurality of flexible films 130 are bonded to the pad area PA of the display panel 110. The flexible film 130 is a film in which various components are provided on a flexible base film to provide signals to the display element and the circuit unit, and can be electrically connected to the display panel 110. The plurality of flexible films 130 can provide a power supply voltage, a data voltage, etc. to the display panel 110. In addition, in Figure 1 , it is illustrated that the plurality of flexible films 130 are four flexible films 130 and are bonded to the long sides of the display panel 110 , but the number and arrangement of the plurality of flexible films 130 may be changed in various ways according to design and are not limited thereto.

[0042] Driver integrated circuits such as data drivers may be provided on the plurality of flexible films 130. The driver integrated circuits are components that process data for displaying an image and drive signals for processing the data. The driver integrated circuits may be provided in a method such as a chip on glass (COG), a chip on film (COF), or a tape carrier package (TCP) method according to a mounting method. For ease of description, although the driver integrated circuits have been described as being a chip on film (COF) method in which they are mounted on the plurality of flexible films 130, the present disclosure is not limited thereto.

[0043] The printed circuit board 140 is electrically connected to the plurality of flexible films 130. The printed circuit board 140 is a component that provides signals to the driver integrated circuits of the flexible films 130. Various components for providing various signals (such as drive signals and data signals) to the driver integrated circuits may be provided on the printed circuit board 140. For example, a plurality of printed lines for transmitting various signals such as drive signals and data signals may be formed on the printed circuit board 140. In addition, printed circuits for controlling and compensating various signals such as drive signals and data signals may also be formed on the printed circuit board 140.

[0044] In addition, despite the Figure 1 One printed circuit board 140 is illustrated in FIG. 1 , but the number of printed circuit boards 140 may be changed in various ways according to design, but is not limited thereto.

[0045] The electrostatic discharge (ESD) circuit 150 discharges static electricity applied to the display panel 110. Specifically, the electrostatic discharge circuit 150 can be provided in the pad area PA and can be connected to at least one gate driver 120 via a discharge line DL. In addition, since at least one gate driver 120 is provided in the non-display area NA, the discharge line DL can be provided in the bending area BA. However, embodiments of the present disclosure are not limited thereto. For example, the electrostatic discharge circuit 150 can be connected to other components of the display device 100 (e.g., gate lines, data lines, or multiple pixels PX) via the discharge line DL.

[0046] The electrostatic discharge circuit 150 includes a plurality of transistors, and when external static electricity is applied to one electrode of the plurality of transistors, the static electricity is discharged through the lines connected to the other electrodes of the plurality of transistors. Therefore, since external static electricity can be prevented from being applied to at least one gate driver, the electrostatic discharge circuit 150 can protect the gate driver. In addition, since external static electricity can be prevented from being applied to the plurality of pixels PX connected to the gate driver 120, the electrostatic discharge circuit 150 can also protect the plurality of pixels PX.

[0047] In the following, we will refer to Figures 2 to 6 A more detailed description of the electrostatic discharge circuit is given below.

[0048] Figure 2 is a plan view of an electrostatic discharge circuit of a display device according to an exemplary embodiment of the present disclosure.

[0049] Figure 3 is a circuit diagram of an electrostatic discharge circuit of a display device according to an exemplary embodiment of the present disclosure.

[0050] Figure 4 It is along Figure 2 A cross-sectional view taken along line IV-IV' shown in FIG.

[0051] Figure 5 It is along Figure 2 A cross-sectional view taken along line V-V' shown in FIG.

[0052] Figure 6 It is along Figure 2 A cross-sectional view taken along line VI-VI' shown in FIG.

[0053] Reference Figure 2 , the electrostatic discharge circuit 150 may be divided into a first area A1 disposed at the center thereof and a second area A2 surrounding the first area A1. For example, the first area A1 may have a rectangular shape, and the second area A2 may have a strip shape surrounding the first area A1.

[0054] In addition, the first transistor TR1 and the second transistor TR2 may be disposed in the first area A1, and the connection electrode CE and the discharge line DL may be disposed in the second area A2.

[0055] In addition, refer to Figure 3 , the first transistor TR1 may be electrically connected to the low potential voltage line VLL and the discharge line DL, and the second transistor TR2 may be electrically connected to the high potential voltage line VHL and the discharge line DL.

[0056] Specifically, if Figures 3 to 6 As shown, a first gate electrode G1 of the first transistor TR1 is connected to the discharge line DL, a first source electrode S1 of the first transistor TR1 is also connected to the discharge line DL, and a first drain electrode D1 of the second transistor TR2 is connected to the low potential voltage line VLL.

[0057] Furthermore, a second gate electrode G2 of the second transistor TR2 is connected to the high potential voltage line VHL, a second source electrode S2 of the second transistor TR2 is connected to the discharge line DL, and a second drain electrode D2 of the second transistor TR2 is connected to the high potential voltage line VHL.

[0058] Therefore, when high electrostatic charge is applied to the discharge line DL (indicated by a dotted line), the high electrostatic charge is input to the first source electrode S1 of the first transistor TR1, and a voltage equal to or greater than the breakdown voltage is applied between the first drain electrode D1 and the first source electrode S1 of the first transistor TR1. Therefore, the first transistor TR1 breaks down, so that the high electrostatic charge applied to the first source electrode S1 of the first transistor TR1 can be discharged to the low potential voltage line VLL.

[0059] On the contrary, when low electrostatic charge is applied to the discharge line DL, the low electrostatic charge is input to the second source electrode S2 of the second transistor TR2, and a voltage equal to or greater than the breakdown voltage is applied between the second drain electrode D2 and the second source electrode S2 of the second transistor TR2. Therefore, the second transistor TR2 breaks down, so that the low electrostatic charge applied to the second source electrode S2 of the second transistor TR2 can be discharged to the high potential voltage line VHL.

[0060] In the following, reference will be made to Figures 4 to 6 A cross-sectional structure of a display device is described in detail.

[0061] A first active layer ACT1 of the first transistor TR1 and a second active layer ACT2 of the second transistor TR2 are disposed on a substrate 101 .

[0062] The substrate 101 is a flexible substrate and is a substrate for supporting various components of the display device. For example, the substrate 101 may be made of polyimide (PI), polyacrylate, polyacetate, or the like.

[0063] In addition, if necessary, a buffer layer may be provided on the substrate 101. The buffer layer is formed on the substrate 101 to protect the various components of the display device 100 from the penetration of external moisture (H2O) and oxygen (O2). The buffer layer may be composed of an insulating material, for example, a single layer or multiple layers of an inorganic layer composed of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), etc.

[0064] The first active layer ACT1 of the first transistor TR1 and the second active layer ACT2 of the second transistor TR2 may be provided on the same layer to be spaced apart from each other. In addition, each of the first active layer ACT1 of the first transistor TR1 and the second active layer ACT2 of the second transistor TR2 may also be composed of an oxide semiconductor, and may be composed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or an organic semiconductor.

[0065] The gate insulating layer 102 is provided on the first active layer ACT1 of the first transistor TR1 and the second active layer ACT2 of the second transistor TR2. The gate insulating layer 102 is a layer for electrically insulating the first active layer ACT1 of the first transistor TR1 from the first gate electrode G1 of the first transistor TR1 and electrically insulating the second active layer ACT2 of the second transistor TR2 from the second gate electrode G2 of the second transistor TR2. In addition, the gate insulating layer 102 can be composed of an insulating material. For example, the gate insulating layer 102 can be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) as an inorganic material, or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0066] The first gate electrode G1 of the first transistor TR1 and the second gate electrode G2 of the second transistor TR2 are disposed on the gate insulating layer 102. The first gate electrode G1 of the first transistor TR1 and the second gate electrode G2 of the second transistor TR2 are disposed to be spaced apart from each other on the gate insulating layer 102. In addition, the first gate electrode G1 of the first transistor TR1 overlaps with the first active layer ACT1 of the first transistor TR1, and the second gate electrode G2 of the second transistor TR2 overlaps with the second active layer ACT2 of the second transistor TR2.

[0067] Each of the first gate electrode G1 of the first transistor TR1 and the second gate electrode G2 of the second transistor TR2 may be formed of any one of various metal materials (e.g., molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu)) or an alloy of two or more of these materials, or a multilayer thereof, but the present disclosure is not limited thereto.

[0068] In addition, a plurality of connection electrodes CE and a high-potential voltage line VHL and a low-potential voltage line VLL are provided on the gate insulating layer 102. In addition, each of the plurality of connection electrodes CE, the high-potential voltage line VHL, and the low-potential voltage line VLL may also be composed of the same material as the first gate electrode G1 of the first transistor TR1 and the second gate electrode G2 of the second transistor TR2 on the same layer. That is, the plurality of connection electrodes CE and the high-potential voltage line VHL and the low-potential voltage line VLL may be composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of two or more of these materials, or a multilayer thereof, but the present disclosure is not limited thereto.

[0069] The interlayer insulating layer 103 is provided on the first gate electrode G1 of the first transistor TR1, the second gate electrode G2 of the second transistor TR2, the plurality of connection electrodes CE, the high potential voltage line VHL, and the low potential voltage line. The interlayer insulating layer 103 insulates the first gate electrode G1 of the first transistor TR1, the second gate electrode G2 of the second transistor TR2, the plurality of connection electrodes CE, the high potential voltage line VHL, and the low potential voltage line VLL. The interlayer insulating layer 103 may be composed of an inorganic material. For example, the interlayer insulating layer 103 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) as an inorganic material, or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx), but the present disclosure is not limited thereto.

[0070] The first source electrode S1 and the first drain electrode D1 of the first transistor TR1 are disposed on the interlayer insulating layer 103. In addition, the second source electrode S2 and the second drain electrode D2 of the second transistor TR2 are disposed on the interlayer insulating layer 103. In the first transistor TR1, the first source electrode S1 and the first drain electrode D1 may be electrically connected to the first active layer ACT1 in such a manner that they are in contact with the first active layer ACT1. In addition, in the second transistor TR2, the second source electrode S2 and the second drain electrode D2 may be electrically connected to the second active layer ACT2 in such a manner that they are in contact with the second active layer ACT2.

[0071] The first source electrode S1 and the first drain electrode D1 of the first transistor TR1 and the second source electrode S2 and the second drain electrode D2 of the second transistor TR2 can be composed of any one of various metal materials (for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu)) or alloys of two or more of these materials, or multilayers thereof, but the present disclosure is not limited thereto.

[0072] Furthermore, although it has been described herein that the first transistor TR1 and the second transistor TR2 have a coplanar structure, various transistors such as a staggered structure may be used.

[0073] In addition, a plurality of discharge lines DL are provided on the interlayer insulating layer 103. In addition, the plurality of discharge lines DL may be formed of the same material as the source electrodes S1 and S2 and the drain electrodes D1 and D2 on the same layer. That is, the plurality of discharge lines DL and the source electrodes S1 and S2 and the drain electrodes D1 and D2 may be formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys of two or more of these materials, or multilayers thereof, but the present disclosure is not limited thereto.

[0074] A planarization layer 104 is formed on the source electrodes S1 and S2, the drain electrodes D1 and D2, and the discharge line DL. The planarization layer 104 flattens the upper portions of the first transistor TR1, the second transistor TR2, and the discharge line DL. The planarization layer 104 can be composed of a single layer or multiple layers and can be made of an organic material. Therefore, the planarization layer 104 can be referred to as an organic insulating layer. For example, the planarization layer 104 can be made of an acrylic organic material, but is not limited thereto.

[0075] A first trench T1 is formed in the planarization layer 104 in the second area A2. The first trench T1 may have the same shape as the second area A2. That is, since the second area A2 has a band shape surrounding the first area A1, the first trench T1 may also have a band shape surrounding the first area A1. In other words, the first trench T1 may be a trench formed in the planarization layer 104 and extending in a predetermined direction along the second area A2. In addition, the first trench T1 may be formed between the first transistor TR1 and the discharge line DL and overlap with the connection electrode CE. Alternatively, the first trench T1 may be formed between the second transistor TR2 and the discharge line DL and overlap with the connection electrode CE. Due to the first trench T1, the planarization layer 104 may be separated in the second area A2. Therefore, as Figures 5 and 6 As shown, the planarization layer 104 may be separated into an inner planarization layer 104 a having an island shape and an outer planarization layer 104 b surrounding the inner planarization layer 104 a .

[0076] A passivation layer 105 is formed on the planarization layer 104. That is, the passivation layer 105 protects the first transistor TR1 and the second transistor TR2 from penetration of moisture and oxygen. Specifically, the passivation layer 105 can be provided not only on the upper surface of the planarization layer 104 but also inside the first trench T1 formed in the planarization layer 104. In addition, the passivation layer 105 can be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) as an inorganic material, or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0077] As described above, in the display device 100 according to the exemplary embodiment of the present disclosure, the first trench T1 may be formed in the planarization layer 104. As described above, the electrostatic discharge circuit 150 is disposed in the pad area PA adjacent to the bending area BA, and due to the bending of the display panel 110 in the bending area BA, it may have an impact up to the pad area PA. However, since the first trench T1 is formed in the planarization layer 104, the outer planarization layer 104b disposed outside the first trench T1 is affected by the bending in the bending area BA, and thus, the outer planarization layer 104b may be spaced apart from the interlayer insulating layer 103, but the inner planarization layer 104a is not affected by the bending in the bending area BA. As a result, external moisture or oxygen does not penetrate into the multiple transistors TR1 and TR2 disposed below the inner planarization layer 104a. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, even when the display panel 110 is bent, external moisture or oxygen does not penetrate into the electrostatic discharge circuit 150, so that the electrostatic discharge circuit 150 is not damaged. Therefore, the reliability of the electrostatic discharge circuit 150 in the display device 100 according to the exemplary embodiment of the present disclosure may be improved.

[0078] Hereinafter, a display device according to another exemplary embodiment of the present disclosure will be described in detail.

[0079] Since the display device 200 according to another exemplary embodiment of the present disclosure is different from the display device 100 according to the exemplary embodiment of the present disclosure only in terms of the second groove T2 of the passivation layer 205, redundant content of the display device 100 according to the exemplary embodiment of the present disclosure and the display device 200 according to another exemplary embodiment of the present disclosure will be omitted, and the second groove T2 of the passivation layer 205 will be described in detail.

[0080] Figure 7 is a cross-sectional view of an electrostatic discharge circuit of a display device according to another exemplary embodiment of the present disclosure.

[0081] like Figure 7As shown, a second trench T2 is formed in the passivation layer 205 in the second area A2. Furthermore, the second trench T2 can be formed within the first trench T1. Therefore, the second trench T2 can also have the same shape as the second area A2. That is, since the second area A2 has a strip shape surrounding the first area A1, the second trench T2 can also have a strip shape surrounding the first area A1. In other words, the second trench T2 can be a trench formed in the passivation layer 205 and extending in a predetermined direction along the second area A2. Furthermore, the second trench T2 can be formed between the first transistor TR1 and the discharge line DL and overlap the connection electrode CE. Alternatively, the second trench T2 can be formed between the second transistor TR2 and the discharge line DL and overlap the connection electrode CE. Due to the second trench T2, the passivation layer 205 can be separated in the second area A2. Therefore, the passivation layer 205 can be separated into an inner passivation layer 205a having an island shape and an outer passivation layer 205b surrounding the inner passivation layer 205a.

[0082] In addition, the width W2 of the second trench may be smaller than the width W1 of the first trench. Therefore, the inner surface or side surface of the planarization layer 104 formed by the first trench T1 may be covered by the passivation layer 205. Therefore, the inner surface or side surface of the planarization layer 104 is not exposed to the outside, and external moisture or oxygen does not penetrate into the electrostatic discharge circuit provided below the planarization layer, so that the electrostatic discharge circuit is not damaged.

[0083] As described above, in the display device according to another exemplary embodiment of the present disclosure, the first trench T1 is formed in the planarization layer 104, and the second trench T2 is formed in the passivation layer 205. This allows the inner planarization layer 104a and the inner passivation layer 205a disposed within the first trench T1 and the second trench T2 to be unaffected by the bend in the bending area BA. As a result, external moisture or oxygen does not penetrate into the plurality of transistors disposed below the inner planarization layer 104a and the inner passivation layer 205a. Therefore, the reliability of the electrostatic discharge circuit of the display device according to another exemplary embodiment of the present disclosure can be further improved.

[0084] Exemplary embodiments of the present disclosure may also be described as follows:

[0085] According to an exemplary embodiment of the present disclosure, a display device includes: a display panel divided into a display area, a non-display area, a bending area, and a pad area, and bent in one direction in the bending area; a plurality of pixels arranged in the display area; at least one gate driver arranged in the non-display area and configured to provide a gate voltage to the plurality of pixels; a flexible film connected to a plurality of pads arranged in the pad area; and at least one electrostatic discharge circuit arranged in the pad area and connected to the at least one gate driver through a discharge line.

[0086] Each of the at least one electrostatic discharge circuits can be divided into a first area and a second area surrounding the first area, and can include: a plurality of transistors arranged in the first area; a connecting electrode arranged in the second area and configured to connect the plurality of transistors and a discharge line; a planarization layer configured to cover the plurality of transistors and composed of an organic material; and a passivation layer arranged on the planarization layer and composed of an inorganic material.

[0087] A first trench may be formed in the planarization layer in the second region.

[0088] The first trench may overlap the connection electrode and surround the first region.

[0089] The planarization layer may be separated into an inner planarization layer and an outer planarization layer by the first trench.

[0090] A plurality of transistors may be disposed below the inner planarization layer.

[0091] A second trench may be formed in the passivation layer in the second region.

[0092] The passivation layer may be separated into an inner passivation layer and an outer passivation layer by the second trench.

[0093] A plurality of transistors may be disposed beneath the inner passivation layer.

[0094] The second trench may be formed within the first trench.

[0095] The plurality of transistors may include a first transistor connected to a low potential voltage line and a second transistor connected to a high potential voltage line.

[0096] The discharge line may be provided on the same layer as the source electrode and the drain electrode of each of the plurality of transistors.

[0097] The connection electrode may be provided on the same layer as the gate electrode of each of the plurality of transistors.

[0098] CROSS-REFERENCE TO RELATED APPLICATIONS

[0099] This application claims the benefit of and priority to Korean Patent Application No. 10-2020-0110817, filed in Korea on September 1, 2020, which is hereby expressly incorporated by reference into this application in its entirety.

Claims

1. A display device, comprising: a display panel, the display panel being divided into a display area, a non-display area, a bending area, and a pad area, and being bent in one direction in the bending area, the bending area being located between the non-display area and the pad area; a plurality of pixels, the plurality of pixels being arranged in the display area; as well as at least one electrostatic discharge circuit disposed in the pad area and connected to a discharge line extending from the pad area to the non-display area, Each of the at least one electrostatic discharge circuits is divided into a first area and a second area surrounding the first area, and each of the at least one electrostatic discharge circuits includes: a plurality of transistors disposed in the first region; and A connection electrode is provided in the second region and is configured to connect the plurality of transistors and the discharge line.

2. The display device according to claim 1, further comprising: at least one gate driver disposed in the non-display area and configured to provide a gate voltage to the plurality of pixels, The at least one electrostatic discharge circuit is connected to the at least one gate driver through the discharge line.

3. The display device according to claim 1, further comprising: A flexible film is connected to a plurality of pads provided in the pad area.

4. The display device according to claim 1, wherein The discharge line overlaps the bending area.

5. The display device according to claim 1, in, Each of the at least one electrostatic discharge circuit further comprises: a planarization layer configured to cover the plurality of transistors and composed of an organic material; and A passivation layer is provided on the planarization layer and is made of an inorganic material.

6. The display device according to claim 5, in, A first trench is formed in the planarization layer in the second region.

7. The display device according to claim 6, in, The first trench overlaps the connection electrode and surrounds the first region.

8. The display device according to claim 6, in, The planarization layer is separated into an inner planarization layer and an outer planarization layer by the first trench, and The plurality of transistors are arranged below the inner planarization layer.

9. The display device according to claim 6, in, A second trench is formed in the passivation layer in the second region.

10. The display device according to claim 9, in, The second trench overlaps the connection electrode and surrounds the first region.

11. The display device according to claim 9, in, The passivation layer is separated into an inner passivation layer and an outer passivation layer by the second trench, and The plurality of transistors are arranged below the inner passivation layer.

12. The display device according to claim 9, in, The second trench is formed within the first trench.

13. The display device according to claim 12, wherein: A side surface of the planarization layer formed in the first trench is covered by the passivation layer.

14. The display device according to claim 12, wherein: The width of the second trench is smaller than the width of the first trench.

15. The display device according to claim 1, in, The plurality of transistors include: a first transistor connected to a low potential voltage line; and A second transistor is connected to the high potential voltage line.

16. The display device according to claim 15, wherein A source electrode and a gate electrode of the first transistor are connected to the discharge line and a drain electrode of the first transistor is connected to the low potential voltage line, and The drain electrode and the gate electrode of the second transistor are connected to the discharge line and the source electrode of the second transistor is connected to the high potential voltage line.

17. The display device according to claim 15, wherein: The low potential voltage line and the high potential voltage line are provided on the same layer as a gate electrode of each of the plurality of transistors.

18. The display device according to claim 1, in, The discharge line is disposed on the same layer as a source electrode and a drain electrode of each of the plurality of transistors.

19. The display device according to claim 1, in, The connection electrode is provided on the same layer as a gate electrode of each of the plurality of transistors.

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