Semiconductor memory devices

By forming an amorphous silicon layer in a semiconductor memory device and performing laser annealing, combined with insulating layer coverage and planarization, the problem of difficult connection between the semiconductor layer and the source line under high integration is solved, ensuring the stability and performance of the device.

CN114121965BActive Publication Date: 2026-05-26KIOXIA CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
KIOXIA CORP
Filing Date
2021-02-03
Publication Date
2026-05-26

AI Technical Summary

Technical Problem

In semiconductor memory devices, with increasing integration, the aspect ratio of through-holes is constantly increasing, making it difficult to effectively remove the gate insulating film. This leads to difficulties in connecting the semiconductor layer and the source line, and heat treatment may cause metal atom diffusion, affecting device performance.

Method used

By forming an amorphous silicon layer on the upper end of the semiconductor layer and performing laser annealing to crystallize it, while covering the upper end of the conductive layer with an insulating layer and performing planarization, heat diffusion is avoided, ensuring a stable connection between the semiconductor layer and the source line.

Benefits of technology

Stable manufacturing of semiconductor memory devices has been achieved, avoiding metal atom diffusion and ensuring the reliability of the current path and the good performance of the device.

✦ Generated by Eureka AI based on patent content.

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Abstract

An embodiment provides a semiconductor memory device that can be readily manufactured. The semiconductor memory device of the embodiment includes a substrate having a first region and a second region arranged in a first direction. Furthermore, the first region of the semiconductor memory device includes: a plurality of first conductive layers and a plurality of first insulating layers alternately deposited in a second direction; a first semiconductor layer extending in the second direction and facing the plurality of first conductive layers and the plurality of first insulating layers; and a second semiconductor layer connected to the first semiconductor layer and extending in the first direction. The same structure is also provided in the second region of the semiconductor memory device. Additionally, the semiconductor memory device includes a third conductive layer bonded to the second semiconductor layers provided in the first and second regions. Furthermore, the second semiconductor layers provided in the first and second regions are spaced apart from each other in the first direction.
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