Semiconductor memory device

Abstract

A semiconductor storage device of the present application includes: a substrate; a memory cell array separated from the substrate in a first direction; and a plurality of first pad electrodes arranged in a second direction, away from the memory cell array in a third direction, and operable for input and output of data. The substrate includes a plurality of first regions and a plurality of second regions alternately arranged in the second direction. The memory cell array includes: a plurality of conductive layers extending in the second direction across the plurality of first regions and the plurality of second regions, and arranged in the first direction; a plurality of semiconductor layers provided in the plurality of first regions; and a plurality of first contacts provided in the plurality of second regions, and extending in the first direction. When a distance between a center position of a first pad electrode and a center position of a first contact closest to the first pad electrode is set as a first distance, a difference between a maximum distance and a minimum distance among the plurality of first distances is 400 nm or less.

Description

[0001] Reference to Related Applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2020-141836, filed on August 25, 2020, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present embodiment relates to a semiconductor storage device. BACKGROUND

[0004] A semiconductor storage device is known, which includes a substrate, a plurality of conductive layers laminated in a direction intersecting a surface of the substrate, and a semiconductor layer facing the plurality of conductive layers. SUMMARY

[0005] One embodiment provides a semiconductor storage device that is easily highly integrated.

[0006] A semiconductor storage device of one embodiment includes a substrate, a memory cell array provided separately from the substrate in a first direction intersecting a surface of the substrate, and a plurality of first pad electrodes arranged in a second direction intersecting the first direction, provided at positions apart from the memory cell array in a third direction intersecting the first direction and the second direction, and used for inputting data written to the memory cell array and outputting data read from the memory cell array. The substrate includes a plurality of first regions and a plurality of second regions arranged alternately in the second direction. The memory cell array includes a plurality of conductive layers extending in the second direction across the plurality of first regions and the plurality of second regions, and arranged in the first direction, a plurality of semiconductor layers provided in the plurality of first regions, extending in the first direction, and facing the plurality of conductive layers, and a plurality of first contacts provided in the plurality of second regions, extending in the first direction, one end of the first direction closer to the substrate than the plurality of conductive layers, and the other end of the first direction farther from the substrate than the plurality of conductive layers. When a distance between a center position of one of the plurality of first pad electrodes in the second direction and the third direction and a center position of the first contact closest to the one of the plurality of first pad electrodes in the second direction and the third direction is set to a first distance, a difference between a maximum distance and a minimum distance of a plurality of first distances corresponding to the plurality of first pad electrodes is 400 nm or less.

[0007] The semiconductor storage device of one embodiment includes a substrate, a memory cell array provided apart from the substrate in a first direction intersecting a surface of the substrate, a plurality of first pad electrodes arranged in a second direction intersecting the first direction, provided at positions apart from the memory cell array in a third direction intersecting the first and second directions, and used for inputting data written to the memory cell array and outputting data read from the memory cell array, a plurality of first driver circuits connected to the plurality of first pad electrodes and including a plurality of first transistors connected in parallel between the first pad electrodes and a voltage supply line, and a plurality of second driver circuits connected to the plurality of first pad electrodes and including comparators connected to the first pad electrodes. The substrate includes a plurality of first regions and a plurality of second regions arranged alternately in the second direction, and a plurality of third regions provided at positions apart from the plurality of first regions and the plurality of second regions in the third direction and arranged in the second direction. The memory cell array includes a plurality of conductive layers extending in the second direction across the plurality of first regions and the plurality of second regions and arranged in the first direction, a plurality of semiconductor layers provided in the plurality of first regions, extending in the first direction, and facing the plurality of conductive layers, and a plurality of first contacts provided in the plurality of second regions, extending in the first direction, one end of the first direction closer to the substrate than the plurality of conductive layers, and the other end of the first direction farther from the substrate than the plurality of conductive layers. The plurality of third regions each include a plurality of transistors included in one of the plurality of first driver circuits and a plurality of transistors included in one of the plurality of second driver circuits. When a distance between a center of one of the plurality of third regions in the second and third directions and a center of a first contact closest to the one of the plurality of third regions in the second and third directions is set to a first distance, a difference between a maximum distance and a minimum distance of a plurality of first distances corresponding to the plurality of third regions is less than or equal to 400 nm.

[0008] According to the above configuration, a semiconductor storage device that is easily highly integrated can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a schematic block diagram illustrating a configuration of a memory system 10 of the first embodiment.

[0010] Figure 2 is a schematic side view illustrating an example of the configuration of the memory system 10 of the first embodiment.

[0011] Figure 3 is a schematic plan view illustrating an example of the configuration of the memory system 10 of the first embodiment.

[0012] Figure 4 is a schematic block diagram illustrating a configuration of a memory die MD of the first embodiment.

[0013] Figure 5 is a schematic circuit diagram showing a part of the memory die MD of the first embodiment.

[0014] Figure 6 is a schematic circuit diagram showing a part of the memory die MD of the first embodiment.

[0015] Figure 7 is a schematic circuit diagram showing a part of the memory die MD of the first embodiment.

[0016] Figure 8 is a schematic circuit diagram showing a part of the memory die MD of the first embodiment.

[0017] Figure 9 is a schematic plan view of the memory die MD of the first embodiment.

[0018] Figure 10 is a schematic cross-sectional view of the configuration shown in Figure 9 , viewed in the direction of the arrows.

[0019] Figure 11 is a schematic plan view showing a part of Figure 9 , shown by the portion indicated by C.

[0020] Figure 12 is a schematic plan view showing a part of Figure 11 , shown by the portion indicated by D.

[0021] Figure 13 is a schematic cross-sectional view of the configuration shown in Figure 12 , viewed in the direction of the arrows.

[0022] Figure 14 is a schematic plan view showing a part of Figure 13 , shown by the portion indicated by F.

[0023] Figure 15 is a schematic cross-sectional view of the configuration shown in Figure 11 , viewed in the direction of the arrows.

[0024] Figure 16 is a schematic plan view showing a part of Figure 8 .

[0025] Figure 17 is a schematic cross-sectional view showing a part of the memory die MD of the first embodiment.

[0026] Figure 18is a schematic cross-sectional view showing a part of the constitution of the memory die MD of the first embodiment.

[0027] Figure 19 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0028] Figure 20 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0029] Figure 21 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0030] Figure 22 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0031] Figure 23 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0032] Figure 24 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0033] Figure 25 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0034] Figure 26 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0035] Figure 27 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0036] Figure 28 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0037] Figure 29 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0038] Figure 30 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0039] Figure 31 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0040] Figure 32 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0041] Figure 33 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0042] Figure 34 is a schematic cross-sectional view showing a manufacturing method of the memory die MD of the first embodiment.

[0043] Figure 35 is a schematic plan view showing a part of the configuration of the memory die of another embodiment.

[0044] Figure 36 is a schematic plan view showing a part of the configuration of the memory die of another embodiment.

[0045] Figure 37 is a schematic cross-sectional view for explaining the kind of the transistor mountable on the memory die MD of the first embodiment and the memory die of the other embodiments. DETAILED DESCRIPTION

[0046] A semiconductor storage device of an embodiment is explained in detail with reference to the drawings. Furthermore, the following embodiment is only an example and does not intend to limit the present application. In addition, the following drawings are schematic diagrams and a part of the configuration or the like is sometimes omitted for convenience of explanation. In addition, the same symbol is sometimes attached to a part common to a plurality of embodiments and the explanation is omitted.

[0047] In addition, in the present specification, when such expression as "semiconductor storage device" is adopted, it sometimes means a memory die and sometimes means a memory chip, a memory card, an SSD (Solid State Drive), or the like including a controller die. Furthermore, it sometimes means a configuration including a host such as a smartphone, a tablet terminal, a personal computer, or the like.

[0048] In addition, in the present specification, when such expression as "control circuit" is adopted, it sometimes means a peripheral circuit such as a sequencer provided on a memory die and sometimes means a controller die or a controller chip or the like connected to a memory die. Furthermore, it sometimes means a configuration including both of them.

[0049] In addition, in the present specification, when such expression as "electrically connected" between a first configuration and a second configuration is adopted, the first configuration can be directly connected to the second configuration or the first configuration can be connected to the second configuration via a wiring, a semiconductor component, or a transistor or the like. For example, in the case where three transistors are connected in series, even if the second transistor is in an OFF state, the first transistor is "electrically connected" to the third transistor.

[0050] In addition, in the present specification, when the expression "connected to" the first configuration with the second configuration and the third configuration is used, it sometimes means that the first configuration, the second configuration, and the third configuration are connected in series, and the second configuration is connected to the first configuration and the third configuration.

[0051] In addition, in the present specification, when the expression that a circuit or the like makes two or more wirings or the like "conduct" is used, it sometimes means, for example, that the circuit or the like includes a transistor or the like provided on a current path between the two or more wirings, and the transistor or the like is in an ON state.

[0052] In addition, in the present specification, a prescribed direction parallel to the upper surface of a substrate is referred to as an X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as a Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as a Z direction.

[0053] In addition, in the present specification, a direction along a prescribed surface is sometimes referred to as a first direction, a direction along the prescribed surface and intersecting the first direction is sometimes referred to as a second direction, and a direction intersecting the prescribed surface is sometimes referred to as a third direction. The first direction, the second direction, and the third direction can or can not correspond to any of the X direction, the Y direction, and the Z direction.

[0054] In addition, in the present specification, expressions such as "upper" or "lower" are based on a substrate. For example, a direction away from the substrate in the Z direction is referred to as upper, and a direction close to the substrate in the Z direction is referred to as lower. In addition, when the expression lower surface or lower end is used for a certain configuration, it means a surface or an end portion on the substrate side of the configuration, and when the expression upper surface or upper end is used, it means a surface or an end portion on the side opposite to the substrate of the configuration. In addition, a surface intersecting the X direction or the Y direction is referred to as a side surface or the like.

[0055] In addition, in the present specification, when the expression "width", "length", or "thickness" of a prescribed direction, or "distance" between configurations, components, or the like is used, it sometimes means a width, a length, or a thickness, or a distance, and the like observed on a cross section or the like by SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy) or the like.

[0056] [First Embodiment]

[0057] [Memory system 10]

[0058] Figure 1 is a schematic block diagram showing the configuration of the memory system 10 of the first embodiment.

[0059] The memory system 10 performs readout, write, erasure, and the like of user data in accordance with a signal transmitted from the host 20. The memory system 10 is, for example, a memory chip, a memory card, an SSD, or another system capable of storing user data. The memory system 10 has a plurality of memory dies MD that store user data, and a controller die CD that is connected to the plurality of memory dies MD and the host 20. The controller die CD has, for example, a processor, a RAM (Random Access Memory), and the like, and performs processing such as conversion of a logical address and a physical address, bit error detection / correction, garbage collection (compression), wear leveling, and the like.

[0060] Figure 2 is a schematic side view showing a configuration example of the memory system 10 of the present embodiment. Figure 3 is a schematic plan view showing a configuration example of the memory system 10 of the present embodiment. For ease of explanation, a part of the configuration is omitted in Figure 2 and Figure 3 .

[0061] As shown in Figure 2 , the memory system 10 of the present embodiment has a mounting substrate MSB, a plurality of memory dies MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory dies MD. In the upper surface of the mounting substrate MSB, an end region in the Y direction is provided with a pad electrode P, and another part of the region is adhered to the lower surface of the memory die MD via an adhesive or the like. In the upper surface of the memory die MD, an end region in the Y direction is provided with a pad electrode P, and the other region is adhered to the lower surface of another memory die MD or the controller die CD via an adhesive or the like. In the upper surface of the controller die CD, an end region in the Y direction is provided with a pad electrode P.

[0062] As shown in Figure 3 , the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD each have a plurality of pad electrodes P arranged in the X direction. The plurality of pad electrodes P provided on the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD are connected to each other via a wire B.

[0063] Furthermore, Figure 2 and Figure 3 show configurations only as examples, and the specific configuration can be appropriately adjusted. For example, in the example shown in Figure 2 and Figure 3 , the plurality of memory dies MD have the controller die CD stacked thereon, and these configurations are connected by the wire B. In this configuration, the plurality of memory dies MD and the controller die CD are included in the same package. However, the controller die CD can also be included in a different package from the memory dies MD.

[0064] [Configuration of the memory die MD]

[0065] Figure 4 is a schematic block diagram showing the configuration of the memory die MD of the first embodiment. Figures 5-8 is a schematic circuit diagram showing a part of the configuration of the memory die MD.

[0066] Further, Figure 4 A plurality of control terminals and the like are shown in the Figure 4 In the Figure 4 , the symbol of the control terminal corresponding to the low-level active signal contains an overline. In the present specification, the symbol of the control terminal corresponding to the low-level active signal contains a slash (“ / ”). Further, Figure 4 The description of the Figure 4 is an example, and the specific form can be adjusted as appropriate. For example, a part or all of the high-level active signals can be low-level active signals, or a part or all of the low-level active signals can be high-level active signals.

[0067] As shown in Figure 4 , the memory die MD includes a memory cell array MCA that stores data, and a peripheral circuit PC connected to the memory cell array MCA. The peripheral circuit PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. In addition, the peripheral circuit PC includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. In addition, the peripheral circuit PC includes an input / output control circuit I / O, and a logic circuit CTR.

[0068] As shown in Figure 5 , the memory cell array MCA includes a plurality of memory blocks BLK. The plurality of memory blocks BLK each include a plurality of string units SU. The plurality of string units SU each include a plurality of memory strings MS. One end of the plurality of memory strings MS is connected to the peripheral circuit PC via a bit line BL, respectively. In addition, the other end of the plurality of memory strings MS is connected to the peripheral circuit PC via a common source line SL, respectively.

[0069] The memory string MS has a drain side selection transistor STD, a plurality of memory cells MC (memory transistors), a source side selection transistor STS, and a source side selection transistor STSb connected in series between the bit line BL and the source line SL. Hereinafter, the drain side selection transistor STD, the source side selection transistor STS, and the source side selection transistor STSb are sometimes referred to simply as selection transistors (STD, STS, STSb).

[0070] The memory cell MC is a field effect transistor having a semiconductor layer functioning as a channel region, a gate insulating film including a charge accumulation film, and a gate electrode. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge accumulation film. The memory cell MC stores one bit or a plurality of bits of data. Further, a word line WL is connected to the gate electrode of each of a plurality of memory cells MC corresponding to one memory string MS. These word lines WL are commonly connected to all memory strings MS in one memory block BLK, respectively.

[0071] The selection transistors (STD, STS, STSb) are field effect transistors having a semiconductor layer functioning as a channel region, a gate insulating film, and a gate electrode. A selection gate line (SGD, SGS, SGSb) is connected to the gate electrode of each of the selection transistors (STD, STS, STSb). The drain side selection gate line SGD is provided corresponding to the string unit SU and is commonly connected to all memory strings MS in one string unit SU. The source side selection gate line SGS is commonly connected to all memory strings MS in a plurality of string units SU. The source side selection gate line SGSb is commonly connected to all memory strings MS in a plurality of string units SU.

[0072] The voltage generation circuit VG Figure 4 includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit. These step-down and step-up circuits are connected to voltage supply lines to which a power supply voltage V CC and a ground voltage V SS are supplied, respectively. These voltage supply lines are connected to, for example, the pad electrode P described with reference to Figure 2 , Figure 3 The voltage generation circuit VG generates, for example, a plurality of operation voltages to be applied to the bit line BL, the source line SL, the word line WL, and the selection gate lines (SGD, SGS, SGSb) at the time of readout operation, write operation, and erase operation of the memory cell array MCA in accordance with a control signal from the sequencer SQC, and outputs them to a plurality of voltage supply lines at the same time. The operation voltages output from the voltage supply lines can be adjusted as appropriate in accordance with the control signal from the sequencer SQC.

[0073] The row decoder RD includes, for example, an address decoder that decodes address data ADD, and a switching circuit that, based on the output signal of the address decoder, appropriately connects the word lines in the memory cell array MCA to the voltage supply lines.

[0074] The sense amplifier module (SAM) includes, for example, multiple sense amplifier units corresponding to multiple bit lines BL. Each sense amplifier unit includes a sense amplifier connected to the bit line BL. The sense amplifier includes a sense circuit connected to the bit line BL, a voltage transfer circuit connected to the bit line BL, and a latch circuit connected to the sense circuit and the voltage transfer circuit. The sense circuit includes: a sense transistor that becomes in an on state corresponding to the voltage or current of the bit line BL; and a wiring that is charged or discharged corresponding to the on / off state of the sense transistor. The latch circuit latches "1" or "0" data based on the voltage of the wiring. The voltage transfer circuit connects the bit line BL to either of the two voltage supply lines based on the data latched in the latch circuit.

[0075] The cache memory CM has multiple latching circuits connected to the latching circuitry within the sense amplifier module SAM via a wiring DBUS. The data DAT contained in these latching circuits is sequentially transferred to the sense amplifier module SAM or the input / output control circuitry I / O. Additionally, a decoding circuit and a switching circuit (not shown) are connected to the cache memory CM. The decoding circuit holds data in the address register ADR (…). Figure 4 The column address CA in the decoder is decoded. The switching circuit, based on the output signal of the decoding circuit, causes the latch circuit corresponding to column address CA to connect with the bus DB. Figure 4 ) Conduction.

[0076] Sequencer SQC ( Figure 4 According to the command data D held in the command register CMR CMD The internal control signals are output to the line decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG. Additionally, the sequencer SQC appropriately outputs the state data D representing its own state. ST Output to the status register STR.

[0077] Additionally, the sequencer SQC generates a ready / busy signal and outputs it to the RY / / BY terminal. When the RY / / BY terminal is in the "L" state, access to the memory die MD is essentially disabled. Conversely, when the RY / / BY terminal is in the "H" state, access to the memory die MD is enabled. Furthermore, the RY / / BY terminal is, for example, referenced... Figure 2 , Figure 3 The pad electrode P described herein is used to achieve this.

[0078] The input / output control circuit I / O has data signal input / output terminals DQ0 to DQ7, data strobe signal input / output terminals DQS, / DQS, and input circuits such as comparators and output circuits such as OCD circuits connected to the data signal input / output terminals DQ0 to DQ7. In addition, the input / output circuit I / O has a shift register connected to these input circuits and output circuits, and a buffer circuit. The data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS, / DQS are realized, for example, by referring to the pad electrodes P described in Figure 2 , Figure 3 The data input via the data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR in accordance with the internal control signal from the logic circuit CTR. In addition, the data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit in accordance with the internal control signal from the logic circuit CTR.

[0079] The logic circuit CTR receives external control signals from the controller die CD via the external control terminals / CEn, CLE, ALE, / WE, RE, / RE, and outputs internal control signals to the input / output control circuit I / O in accordance therewith. Further, the external control terminals / CEn, CLE, ALE, / WE, RE, / RE are realized, for example, by referring to the pad electrodes P described in Figure 2 , Figure 3

[0080] Figure 6 is a schematic block diagram showing a part of the configuration of the input / output control circuit I / O. Figure 7 and Figure 8 are schematic circuit diagrams showing a part of the configuration of the input / output control circuit I / O.

[0081] For example, as shown in Figure 6 , the input / output control circuit I / O has a plurality of input circuits 210 connected to the data signal input / output terminals DQ0 to DQ7, an input circuit 220 connected to the data strobe signal input / output terminals DQS, / DQS, and an input buffer circuit 230 connected to the input circuits 210, 220. As the "second drive circuit", the input circuits 210, the input circuit 220, and the input buffer circuit 230 can be included. The "second drive circuit" can be only the input circuits 210, only the input circuit 220, or only the input buffer circuit 230.

[0082] For example, as shown in Figure 7 ​As shown, the input circuit 210 includes a comparator 211 connected to the data signal input / output terminals DQ0 to DQ7, and a signal transmission circuit 212 for transmitting the output signal of the comparator 211. In the comparator 211, one input terminal is connected to any one of the data signal input / output terminals DQ0 to DQ7, and the other input terminal is connected to the voltage supply line supplying the reference voltage VREF. The signal transmission circuit 212 transmits the output signal of the comparator 211. The signal Din transmitted by the signal transmission circuit 212 is a signal corresponding to the data input via the data signal input / output terminals DQ0 to DQ7.

[0083] For example, such as Figure 7 As shown, the input circuit 220 includes a comparator 221 connected to the data strobe signal input / output terminals DQS and / DQS, and signal transmission circuits 222 and 223 for transmitting the output signal of the comparator 221. In the comparator 221, one input terminal is connected to the data strobe signal input / output terminal DQS, and the other input terminal is connected to the data strobe signal input / output terminal / DQS. The signal transmission circuits 222 and 223 transmit the output signal of the comparator 221. The signals Sig1 and Sig2 transmitted by the signal transmission circuits 222 and 223 are data strobe signals input via the data strobe signal input / output terminals DQS and / DQS. That is, signals Sig1 and Sig2 are timing control signals that control the data acquisition timing, and also function as clock signals. Furthermore, signal Sig2 is the inverted signal of signal Sig1.

[0084] For example, such as Figure 7 As shown, the input buffer circuit 230 includes a circuit element 230e that latches the even-numbered data and a circuit element 230o that latches the odd-numbered data.

[0085] Circuit element 230e includes a time-controlled inverter 231e and a latch circuit 232e. The time-controlled inverter 231e includes PMOS transistors 233e and 234e, which operate under a supplied voltage V. CCQThe voltage supply line is connected in series with the output terminal N1; and NMOS transistors 235e and 236e are connected in series between the output terminal N1 and the voltage supply line supplying the ground voltage VSS. The gate electrode of PMOS transistor 233e is connected to the output terminal of signal transmission circuit 212. The gate electrode of PMOS transistor 234e is connected to the output terminal of signal transmission circuit 223. The gate electrode of NMOS transistor 235e is connected to the output terminal of signal transmission circuit 222. The gate electrode of NMOS transistor 236e is connected to the output terminal of signal transmission circuit 212. The latch circuit 232e includes inverters 237e and 238e. The input terminal of inverter 237e and the output terminal of inverter 238e are connected to the output terminal N1 of timing inverter 231e. The output terminal of inverter 237e and the input terminal of inverter 238e are connected to circuits such as a FIFO buffer (not shown).

[0086] Circuit element 230o includes a time-controlled inverter 231o and a latch circuit 232o. The time-controlled inverter 231o includes PMOS transistors 233o and 234o, which operate under a supplied voltage V. CCQ The voltage supply line is connected in series with the output terminal N1; and NMOS transistors 235o and 236o are connected in series between the output terminal N2 and the voltage supply line supplying the ground voltage VSS. The gate electrode of PMOS transistor 233o is connected to the output terminal of signal transmission circuit 212. The gate electrode of PMOS transistor 234o is connected to the output terminal of signal transmission circuit 222. The gate electrode of NMOS transistor 235o is connected to the output terminal of signal transmission circuit 223. The gate electrode of NMOS transistor 236o is connected to the output terminal of signal transmission circuit 212. The latch circuit 232o includes inverters 237o and 238o. The input terminal of inverter 237o and the output terminal of inverter 238o are connected to the output terminal N1 of timing inverter 231o. The output terminal of inverter 237o and the input terminal of inverter 238o are connected to circuits such as a FIFO buffer (not shown).

[0087] Additionally, for example, such as Figure 6 As shown, the input / output control circuit (I / O) includes multiple output circuits 240 connected to data signal input / output terminals DQ0 to DQ7, multiple output circuits 250 connected to data strobe signal input / output terminals DQS and / DQS, and an output buffer circuit 260 connected to the output circuits 240. The "first drive circuit" may include both the output circuits 250 and the output buffer circuit 260. The "first drive circuit" may consist only of the output circuits 250 or only of the output buffer circuit 260.

[0088] For example, such as Figure 8As shown, the output circuit 240 has seven OCD units 241 connected in parallel with the data signal input / output terminals DQ0 to DQ7, respectively, and seven OCD unit control circuits 242 connected with the seven OCD units 241.

[0089] The seven OCD units 241 have, for example, an impedance of 240Ω, respectively. In addition, the seven OCD units 241 are connected with the signal line OCD_EN<6:0>, and the number of the OCD units 241 driven is controlled in accordance with the signal line OCD_EN<6:0>. For example, in a case where the signal 0000001 (01 in hexadecimal notation) is input to the signal line OCD_EN<6:0>, one OCD unit 241 is driven, and the impedance Z DRV of the output circuit 240 is set to around 240Ω. In addition, for example, in a case where the signal 0011111 (1F in hexadecimal notation) is input to the signal line OCD_EN<6:0>, five OCD units 241 are driven, and the impedance Z DRV of the output circuit 240 is set to around 240Ω / 5 = 48Ω. The signal of the signal line OCD_EN<6:0> is controlled by, for example, a user.

[0090] The OCD units 241 each have a pull-up circuit 243 connected between a voltage supply line supplied with the voltage V CCQ and any one of the data signal input / output terminals DQ0 to DQ7. In addition, the OCD units 241 each have a pull-down circuit 244 connected between any one of the data signal input / output terminals DQ0 to DQ7 and a voltage supply line supplied with the ground voltage VSS.

[0091] The pull-up circuit 243 has a resistance element 245 connected with the data signal input / output terminals DQ0 to DQ7, and n+1 (n is a natural number) transistors 246 connected in parallel between the resistance element 245 and a voltage supply line supplied with the voltage V CCQ . The transistors 246 are PMOS transistors. The n+1 transistors 246 have at least one of different channel widths and channel lengths, and have n+1 different resistance values. The gate electrodes of the n+1 transistors 246 are connected with the signal lines Up<0> to Up<6>, respectively. The n+1-bit data input to the signal lines Up<0> to Up<6> is adjusted so that the impedance of the pull-up circuit 243 when driven is around 240Ω.

[0092] The pull-down circuit 244 includes a resistance element 247 connected to the data signal input / output terminals DQ0 to DQ7, and m+1 (m is a natural number) transistors 248 connected in parallel between the resistance element 247 and a voltage supply line supplying a ground voltage VSS. The transistors 248 are NMOS transistors. The m+1 transistors 248 have different resistance values by having at least one of different channel widths and different channel lengths. The gate electrodes of the m+1 transistors 248 are connected to the signal lines Dn※<0> to Dn※<m> (※ is any one of 0 to 6), respectively. The impedance of the m+1 bits of data input to the signal lines Dn※<0> to Dn※<m> when the pull-down circuit 244 is driven is adjusted to about 240Ω.

[0093] The OCD unit control circuit 242 includes, for example, n+1 OR circuits 251 and m+1 AND circuits 252.

[0094] One input terminal of the n+1 OR circuits 251 is connected to an output terminal of a signal transmission circuit 253. The signal transmission circuit 253 transmits a signal of "1" or "0" output from the data signal input / output terminals DQ0 to DQ7. In addition, the corresponding bit of n+1 bits of data PCODE<n:0> corresponding to the n+1 transistors 246 included in the pull-up circuit 243 is input to the other input terminal of the n+1 OR circuits 251. In addition, the output terminals of the n+1 OR circuits 251 are connected to the gate electrodes of the corresponding transistors 246, respectively.

[0095] One input terminal of the m+1 AND circuits 252 is connected to the output terminal of the signal transmission circuit 253. In addition, the corresponding bit of m+1 bits of data NCODE<m:0> corresponding to the m+1 transistors 248 included in the pull-down circuit 244 is input to the other input terminal of the m+1 AND circuits 252. In addition, the output terminals of the m+1 AND circuits 252 are connected to the gate electrodes of the corresponding transistors 248, respectively.

[0096] Figure 6The output circuit 250 is basically configured in the same manner as the output circuit 240, and has 7 OCD units 241 connected in parallel to the data strobe signal input / output terminals DQS, / DQS, and 7 OCD unit control circuits 242 connected to the 7 OCD units 241. However, the output terminals of these OCD units 241 are connected to the data strobe signal input / output terminals DQS or / DQS, rather than to any of the data signal input / output terminals DQ0 to DQ7. In addition, the signal transmission circuit 253 transmits the data strobe signal output from the data strobe signal input / output terminals DQS, / DQS, rather than the signal of "1" or "0" output from the data signal input / output terminals DQ0 to DQ7.

[0097] [Configuration of memory die MD]

[0098] Figure 9 is a schematic plan view of the memory die MD. Figure 10 is a schematic cross-sectional view of the configuration shown in Figure 9 , taken along the line A-A' and the line B-B', and viewed in the direction of the arrows. Figure 11 is a schematic plan view of the portion shown in Figure 9 , shown on an enlarged scale. Figure 12 is a schematic plan view of the portion shown in Figure 11 , shown on an enlarged scale. Figure 13 is a schematic cross-sectional view of the configuration shown in Figure 12 , taken along the line E-E', and viewed in the direction of the arrows. Figure 14 is a schematic plan view of the portion shown in Figure 13 , shown on an enlarged scale. Figure 15 is a schematic cross-sectional view of the configuration shown in Figure 11 , taken along the line G-G', and viewed in the direction of the arrows.

[0099] For example, as shown in Figure 9 , the memory die MD has a semiconductor substrate 100. In the example shown, on the semiconductor substrate 100, there are provided 4 memory cell array regions R MCA arranged in the X direction and the Y direction. MCA The memory cell array region R MH has memory hole regions R MH as a plurality of "first regions" arranged in the X direction, and through-contact regions R C4T as a plurality of "second regions" provided between these memory hole regions R MH . In addition, at both ends in the X direction of the memory cell array region R MCA , there are provided wiring regions R HU . In addition, at the end in the Y direction of the semiconductor substrate 100, there is provided a peripheral region RP In addition, the peripheral region R P has the input / output circuit region R IO .

[0100] For example, as Figure 10 shown, the memory die MD has: a semiconductor substrate 100; a transistor layer L TR， provided on the semiconductor substrate 100; a wiring layer D0 provided above the transistor layer L TR ; a wiring layer D1 provided above the wiring layer D0; a wiring layer D2 provided above the wiring layer D1; a memory cell array layer L MCA provided above the wiring layer D2; a wiring layer M0 provided above the memory cell array layer L MCA ; a wiring layer M1 provided above the wiring layer M0; and a wiring layer M2 provided above the wiring layer M1.

[0101] [Configuration of the semiconductor substrate 100]

[0102] The semiconductor substrate 100 is, for example, a semiconductor substrate containing P-type silicon (Si) containing a P-type impurity such as boron (B). For example, as Figure 10 shown, the surface of the semiconductor substrate 100 has provided thereon: an N-type well region 100N containing an N-type impurity such as phosphorus (P); a P-type well region 100P containing a P-type impurity such as boron (B); a semiconductor substrate region 100S in which neither the N-type well region 100N nor the P-type well region 100P is provided; and an insulating region 100I.

[0103] [Configuration of the transistor layer L TR ]

[0104] For example, as Figure 10 shown, on the upper surface of the semiconductor substrate 100, a wiring layer GC is provided with an insulating layer not shown therebetween. The wiring layer GC contains a plurality of electrodes gc facing the surface of the semiconductor substrate 100. In addition, each of the regions of the semiconductor substrate 100 and the plurality of electrodes gc contained in the wiring layer GC is connected to a contact CS.

[0105] The N-type well region 100N, the P-type well region 100P, and the semiconductor substrate region 100S of the semiconductor substrate 100 each function as a channel region of a plurality of transistors Tr and one electrode of a plurality of capacitors Cap, which constitute a peripheral circuit PC.

[0106] Each of the plurality of electrodes gc contained in the wiring layer GC functions as a gate electrode of a plurality of transistors Tr and another electrode of a plurality of capacitors Cap, which constitute the peripheral circuit PC.

[0107] The contact CS extends along the Z direction and is connected at its lower end to the upper surface of the semiconductor substrate 100 or the electrode gc. An impurity region containing N-type or P-type impurities is provided at the connection portion between the contact CS and the semiconductor substrate 100. The contact CS may, for example, comprise a barrier conductive film such as titanium nitride (TiN) or a multilayer film of a metal film such as tungsten (W).

[0108] Furthermore, in the illustrated example, in the input / output circuit region R... IO A capacitor Cap is located in the area overlapping with the solder pad electrode P when viewed in the Z direction. Additionally, a capacitor Cap is located in the input / output circuit area R. IO Multiple transistors Tr in the structure, for example, serve as a reference. Figures 6-8 The transistors in the described input circuits 210, 220, input buffer circuit 230, and output circuits 240, 250 function.

[0109] [Construction of wiring layers D0, D1, and D2]

[0110] For example, such as Figure 10 As shown, the multiple wirings contained in wiring layers D0, D1, and D2 are electrically connected to at least one of the components in the memory cell array MCA and the peripheral circuit PC.

[0111] The wiring layers D0, D1, and D2 each contain multiple wirings d0, d1, and d2. These multiple wirings d0, d1, and d2 may, for example, be multilayer films containing barrier conductive films such as titanium nitride (TiN) or metal films such as tungsten (W).

[0112] Furthermore, in the illustrated example, an insulating layer 104, such as silicon nitride (SiN), is provided on the upper surface of the wiring layer D2. The insulating layer 104 spans the entire surface and covers the configuration of the wiring layer D2. However, the insulating layer 104 is not provided in the through-contact region R. C4T At least a part of it.

[0113] [Storage cell array layer L] MCA memory hole area R MH [Construction in]

[0114] For example, such as Figure 9 As shown, in the storage cell array layer L MCA It contains multiple memory blocks (BLKs) arranged along the Y direction. For example, as... Figure 11 As shown, a memory block BLK has multiple serial cells SU arranged along the Y direction. An inter-block insulating layer ST, such as silicon oxide (SiO2), is provided between two adjacent memory blocks BLK in the Y direction. For example, as... Figure 12 As shown, an inter-string insulating layer SHE, such as silicon oxide (SiO2), is provided between two adjacent string units SU in the Y direction.

[0115] For example, such as Figure 13 As shown, the memory block BLK includes: a plurality of conductive layers 110 arranged along the Z direction; a plurality of semiconductor layers 120 extending along the Z direction; and a plurality of gate insulating films 130 disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0116] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction. The conductive layer 110 may comprise a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, the conductive layer 110 may comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged along the Z direction.

[0117] A conductive layer 111 is disposed below the conductive layer 110. The conductive layer 111 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). In addition, an insulating layer 101 such as silicon oxide (SiO2) is disposed between the conductive layer 111 and the conductive layer 110.

[0118] A conductive layer 112 is disposed below the conductive layer 111. The conductive layer 112 includes a semiconductor layer 113 connected to the lower end of the semiconductor layer 120, and a conductive layer 114 connected to the lower surface of the semiconductor layer 113. The semiconductor layer 113 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 114 may, for example, contain a conductive layer of a metal such as tungsten (W), tungsten silicide, or other conductive layers. In addition, an insulating layer 101 such as silicon oxide (SiO2) is disposed between the conductive layer 112 and the conductive layer 111.

[0119] Conductive layer 112 serves as the source line SL ( Figure 5 ) to perform its function. For example, for the memory cell array region R MCA ( Figure 9 All memory blocks BLK contained therein are shared by an active pole line SL.

[0120] Conductive layer 111 serves as the source-side gate selection line SGSb ( Figure 5 The gate electrodes of the multiple source-side selection transistors (STSb) connected thereto function as a conductive layer 111. Each memory block BLK is electrically independent.

[0121] Additionally, one or more of the bottommost conductive layers 110 among the plurality of conductive layers 110 serve as the source-side selected gate line (SGS). Figure 5 The gate electrodes of the multiple source-side selection transistors (STS) connected thereto function as the multiple conductive layers 110. These multiple conductive layers 110 are electrically independent in each memory block BLK.

[0122] Additionally, multiple conductive layers 110 located above it serve as word lines WL ( Figure 5 ) and multiple storage units MC connected to it Figure 5 The gate electrode of the memory block BLK functions. These multiple conductive layers 110 are electrically independent in each memory block BLK.

[0123] Additionally, one or more conductive layers 110 located above it serve as drain-side selected gate lines SGD and multiple drain-side selected transistors STD connected thereto. Figure 5 The gate electrode of the conductive layer 110 functions as a series cell. The width of each conductive layer 110 in the Y direction is smaller than that of the other conductive layers 110. Furthermore, an inter-cell insulating layer SHE is provided between two adjacent conductive layers 110 in the Y direction. Each conductive layer 110 is electrically independent within each series cell SU.

[0124] For example, such as Figure 12 As shown, semiconductor layer 120 is arranged in a specified pattern along the X and Y directions. Semiconductor layer 120 serves as a memory string (MS). Figure 5 The multiple memory cells MC and the channel regions of the selection transistors (STD, STS, STSb) contained in the semiconductor layer 120 function as such. The semiconductor layer 120 is, for example, a semiconductor layer of polycrystalline silicon (Si). For example, such as... Figure 13 As shown, the semiconductor layer 120 has a generally bottomed cylindrical shape, and an insulating layer 125 such as silicon oxide is disposed in the central portion. In addition, the outer peripheral surfaces of the semiconductor layer 120 are surrounded by conductive layers 110 and face each other.

[0125] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the upper end of the semiconductor layer 120. The impurity region 121 is connected to contact Ch and contact Vy. Figure 12 ) is connected to bit line BL.

[0126] An impurity region 122 containing N-type impurities such as phosphorus (P) is provided at the lower end of the semiconductor layer 120. The impurity region 122 is connected to the semiconductor layer 113 of the conductive layer 112. The portion of the semiconductor layer 120 located directly above the impurity region 122 functions as a channel region for the source-side selection transistor STSb. The outer peripheral surface of the impurity region 122 is surrounded by the conductive layer 111 and faces the conductive layer 111.

[0127] The gate insulating film 130 has a generally bottomed cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. For example, as Figure 14As shown, the gate insulating film 130 has a tunnel insulating film 131, a charge accumulation film 132, and a barrier insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 are, for example, insulating films of silicon oxide (SiO2) or the like. The charge accumulation film 132 is, for example, a film capable of accumulating electric charges such as silicon nitride (Si3N4) or the like. The tunnel insulating film 131, the charge accumulation film 132, and the barrier insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer circumferential surface of the semiconductor layer 120.

[0128] Further, Figure 14 An example is shown in which the gate insulating film 130 has the charge accumulation film 132 of silicon nitride or the like. However, the gate insulating film 130 may, for example, also have a floating gate of polysilicon or the like containing N-type or P-type impurities.

[0129] [Storage cell array layer L MCA of through-contact region R C4T ]

[0130] For example, as shown in Figure 11 , in the through-contact region R C4T , between the two interblock insulating layers ST arranged in the Y direction, two insulating layers ST O arranged in the Y direction are provided. In addition, between the two insulating layers ST O , a contact connection small region r C4T is provided. In addition, between the interblock insulating layer ST and the insulating layer ST O , a conductive layer connection small region r 110 is provided. These regions extend in the X direction along the interblock insulating layer ST.

[0131] For example, as shown in Figure 15 , the insulating layer ST O extends in the Z direction and is connected to the conductive layer 112 at the lower end. The insulating layer ST O contains, for example, silicon oxide (SiO2).

[0132] The contact connection small region r C4T has a plurality of insulating layers 110A arranged in the Z direction, and contacts C4 as a plurality of "first contacts" extending in the Z direction.

[0133] The insulating layer 110A is a substantially plate-shaped insulating layer extending in the X direction. The insulating layer 110A can include an insulating layer of silicon nitride (SiN) or the like. Between the plurality of insulating layers 110A arranged in the Z direction, an insulating layer 101 of silicon oxide (SiO2) or the like is provided.

[0134] For example, as shown in Figure 10As shown, multiple contacts C4 are arranged along the X direction. Contacts C4 may comprise a barrier conductive film such as titanium nitride (TiN) or a multilayer film of a metal film such as tungsten (W). The outer peripheral surfaces of contacts C4 are surrounded by insulating layers 110A and 101, respectively, and are connected to these insulating layers 110A and 101. Furthermore, contacts C4 extend along the Z direction, connecting at their upper end to wiring m0 in wiring layer M0 and at their lower end to wiring d2 in wiring layer D2.

[0135] For example, such as Figure 11 As shown, the conductive layer connects to a small region r. 110 A narrow width portion 110 having multiple conductive layers 110 arranged along the Z direction C4T Two adjacent memory hole regions R in the X direction MH The multiple conductive layers 110 contained therein are located via the narrow width portion 110 C4T And they are interconnected.

[0136] [Storage cell array layer L] MCA Input / output circuit area R IO [Construction in]

[0137] For example, such as Figure 10 As shown, the input / output circuit region R IO It has an insulating layer 103 of silicon oxide (SiO2) and a plurality of contacts C3 extending along the Z direction.

[0138] The contact C3 may comprise a multilayer film of a barrier conductive film such as titanium nitride (TiN) or a metal film such as tungsten (W). The outer peripheral surfaces of the contact C3 are surrounded by insulating layers 103, and the contact C3 is connected to these insulating layers 103. Furthermore, the contact C3 extends along the Z-direction, connecting at its upper end to wiring m0 in wiring layer M0 and at its lower end to wiring d2 in wiring layer D2.

[0139] [Construction of wiring layers M0, M1, and M2]

[0140] For example, such as Figure 10 As shown, the wiring layers M0, M1, and M2 contain multiple wirings, for example, connected to the memory cell array layer L. MCA The composition and transistor layer L TR At least one of the components constitutes an electrical connection.

[0141] The wiring layer M0 comprises multiple wirings m0. These multiple wirings m0 may, for example, comprise a stacked film of a barrier conductive film such as titanium nitride (TiN) or a metal film such as copper (Cu). Furthermore, a portion of the multiple wirings m0 serves as a potential line BL (…). Figure 5 ) to perform its function. For example, such as Figure 12As shown, the bit lines BL extend in the X direction and the Y direction. In addition, each of the plurality of bit lines BL is connected to one semiconductor layer 120 included in each string unit SU.

[0142] The wiring layer M1 includes a plurality of wirings m1. The plurality of wirings m1 may, for example, include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu), and the like.

[0143] The wiring layer M2 includes a plurality of wirings m2. The plurality of wirings m2 may, for example, include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as aluminum (Al), and the like. In addition, a part of the plurality of wirings m2 provided in the peripheral region R P functions as the pad electrode P Figure 2 , Figure 3 .

[0144] [Configuration of the input / output circuit region R IO ]

[0145] Figure 16 is a schematic plan view that amplifies a part of Figure 9 . In the peripheral region R P , a plurality of pad electrodes P arranged in the X direction are provided. In addition, the pad electrodes P (hereinafter, sometimes referred to as "input / output pad electrodes P (DQ)") that function as the data signal input / output terminals DQ0 to DQ7, or the data strobe signal input / output terminals DQS, / DQS among the plurality of pad electrodes P are provided in the input / output circuit region R IO .

[0146] In the example of Figure 16 , the positions of the plurality of pad electrodes P in the Y direction are all aligned. In addition, the center positions in the X direction of the plurality of input / output pad electrodes P (DQ) respectively coincide with the middle positions in the X direction of the two through-contact regions R C4T adjacent in the X direction. That is, in the example of Figure 16 , when a distance from the center position on the XY plane of the input / output pad electrode P (DQ) to the center position on the XY plane of the contact C4 in the through-contact region R C4T closest to the input / output pad electrode P (DQ) is set to a distance d P-C4 , the distance d P-C4 is the same in all of the input / output pad electrodes P (DQ).

[0147] In addition, it is desirable that all of the distances d P-C4 corresponding to all of the input / output pad electrodes P (DQ) are the same. However, the distance d P-C4Sometimes, due to design flaws or manufacturing errors, they may not be completely consistent. In such cases, for example, the ideal distance d... P-C4 The difference between the maximum and minimum values ​​is less than 400 nm.

[0148] In addition, Figure 16 In the example, multiple input / output circuit regions R IO All positions are aligned in the Y direction. Additionally, multiple input / output circuit regions R... IO The center position in the X direction is respectively connected to the two adjacent through-connection points R in the X direction. C4T The midpoints in the X direction are consistent. That is, in Figure 16 In the example, the input / output circuit region R will be used. IO The center position on the XY plane to the region R closest to the input / output circuit IO The through-connection area R C4T The region R closest to the input / output circuit IO Let the distance from the center position of the junction C4 in the XY plane be d. IO-C4 At that time, the distance d IO-C4 In all input / output circuit regions R IO The same applies to all of them. Additionally, for example, when viewed along the Y direction, the continuous junction area R... C4T With input / output circuit region R IO (Input / output pad electrodes P(DQ)) do not overlap. That is, when viewed along the Y direction, the region R closest to the input / output circuit is... IO (Input / output pad electrode P(DQ)) contact C4 and input / output circuit area R IO (Input / output pad electrodes P(DQ)) do not overlap. At this time, all input / output circuit regions R... IO (Input / output pad electrodes P(DQ)) can be configured to not be connected to the through contact area R. C4T Overlapping along the Y direction. For example, when viewed along the Y direction, the continuous junction area R... C4T Can be used with power pad electrode P(V) SS ), P(V CCQ Overlap. When viewed along the Y direction, the continuous junction area R... C4T It can be configured not to be connected to the power pad electrode P(V) SS ), P(V CCQ )overlapping.

[0149] Additionally, for example, in Figure 16 In the middle, the power pad electrode P(V) can be used. SS ), P(V CCQ ) and input / output circuit region R IO (Input and output pad electrodes P(DQ)) can be interchanged. Even so, the distance d can be made...IO-C4 In all input / output circuit regions R IO The same applies to both.

[0150] Furthermore, ideally, it should be compatible with all input / output circuit regions R. IO All corresponding distances d IO-C4 All are the same. However, the distance d IO-C4 Sometimes, due to design flaws or manufacturing errors, they may not be completely consistent. In such cases, for example, the ideal distance d... IO-C4 The difference between the maximum and minimum values ​​is less than 400 nm.

[0151] [Set in input / output circuit area R] IO The transistor Tr in

[0152] As described above, in the transistor layer L of the memory die MD TR The circuit includes multiple transistors Tr that form the peripheral circuit PC. These transistors Tr include high-voltage transistors that are supplied with relatively large voltages and low-voltage transistors that are supplied with relatively small voltages. The low-voltage transistors can operate at higher speeds than the high-voltage transistors.

[0153] Furthermore, as mentioned above, in the input / output circuit region R IO The middle has a composition reference. Figures 6-8 The input circuits 210 and 220, the input buffer circuit 230, and the output circuits 240 and 250 described herein employ multiple transistors. These transistors are low-voltage transistors as described above. Hereinafter, the N-type transistor in this low-voltage transistor will sometimes be referred to as transistor Tr. NL The P-type transistor is called a transistor Tr. PL .

[0154] For example, such as Figure 17 As shown, N-type transistor Tr NL A P-type well region 100P is disposed on a semiconductor substrate 100. Transistor Tr NLThe device comprises: a portion of a P-type well region 100P; a gate insulating layer 141, such as silicon oxide (SiO2), disposed on the surface of a semiconductor substrate 100; a gate electrode component 142, such as polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P) or arsenic (As), disposed on the upper surface of the gate insulating layer 141; a gate electrode component 143, such as tungsten (W) or tungsten silicide (WSi), disposed on the upper surface of the gate electrode component 142; a top cap insulating layer 144, such as silicon nitride (Si3N4), disposed on the upper surface of the gate electrode component 143; and a sidewall insulating layer 145, such as silicon nitride (Si3N4), disposed on the side surfaces of the gate electrode component 142, the gate electrode component 143, and the top cap insulating layer 144 in the X or Y direction. Furthermore, the gate electrode components 142 and 143 constitute the electrode gc.

[0155] In addition, N-type transistor Tr NL The device includes a pad insulating layer 146 consisting of silicon oxide (SiO2) and silicon nitride (Si3N4) deposited on the surface of the semiconductor substrate 100, the side surface of the gate insulating layer 141 in the X or Y direction, the side surface of the sidewall insulating layer 145 in the X or Y direction, and the upper surface of the top cover insulating layer 144.

[0156] Additionally, in the N-type transistor Tr NL The upper part is connected to three contacts CS extending along the Z direction. NL CS (Contact Point) NL Examples include stacked films containing barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W). Three junctions CS NL One of the contacts CS NL The insulating layer 147, the insulating layer 146, and the top cover insulating layer 144 are connected to the upper surface of the gate electrode component 143, serving as the transistor Tr. NL It functions as part of the gate electrode. Three contacts CS NL The two contacts CS NL Through the insulating pads 147 and 146, it is connected to the surface of the semiconductor substrate 200, serving as a transistor Tr. NL The source or drain electrode performs its function.

[0157] In addition, N-type transistor Tr NL The surface of the semiconductor substrate 100 facing the gate electrode component 142 is designated as a channel region. Additionally, the surface of the semiconductor substrate 100 facing the contact CS... NL The connecting portion is provided with an impurity region 148. The impurity region 148 contains, for example, N-type impurities such as phosphorus (P) or arsenic (As).

[0158] For example, such as Figures 19-34 As shown, P-type transistor Tr PL Basically with N-type transistor Tr NL It is constructed in the same way.

[0159] However, P-type transistor Tr PL It is located in the N-type well region 100N rather than the P-type well region 100P.

[0160] In addition, P-type transistor Tr PL It includes an insulating layer 151 such as silicon nitride (SiN) disposed between the gate insulating layer 141 and the gate electrode component 142.

[0161] In addition, P-type transistor Tr PL A gate electrode component 152 is provided instead of a gate electrode component 142. The gate electrode component 152 may include, for example, polysilicon containing P-type impurities such as boron (B).

[0162] Additionally, in the P-type transistor Tr PL The upper connection has 3 CS contacts. PL To replace 3 contacts CS NL These three contact points CS PL In the middle and transistor Tr PL The junction CS of the drain or source region PL The system includes a semiconductor layer 153 connected to a semiconductor substrate 100, a semiconductor layer 154 connected to the semiconductor layer 153, and a conductive layer 155 connected to the semiconductor layer 154. The semiconductor layers 153 and 154 are, for example, single-crystal silicon (Si) formed by methods such as epitaxial growth. The semiconductor layer 154 contains p-type impurities such as boron (B). The semiconductor layer 153 may or may not contain p-type impurities such as boron (B). When the semiconductor layer 153 contains p-type impurities, the impurity concentration of the p-type impurities in the semiconductor layer 153 is less than the impurity concentration of the p-type impurities in the semiconductor layer 154. The conductive layer 155 may, for example, comprise a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0163] In addition, P-type transistor Tr PL Impurity region 158 is provided instead of impurity region 148. Impurity region 158 may contain, for example, P-type impurities such as boron (B).

[0164] [Manufacturing Method]

[0165] Next, refer to Figures 19-21 The manufacturing method of memory die MD is explained. Figure 23 , Figures 25-29 , Figure 31 ,Figure 33 and Figure 13 are schematic cross-sectional views for explaining a manufacturing method of the memory die MD, showing cross sections corresponding to Figure 22 Figure 24 , Figure 30 , Figure 32 , Figure 34 and Figure 15 are schematic cross-sectional views for explaining a manufacturing method of the memory die MD, showing cross sections corresponding to Figure 10

[0166] When the memory die MD of the present embodiment is manufactured, first, the transistor layer L TR , the wiring layer DO, the wiring layer Dl, and the wiring layer D2 Figure 19 are formed on the semiconductor substrate 100. Further, the insulating layer 104 and the insulating layer 101 are formed on the upper surface of the wiring layer D2.

[0167] Next, for example, as shown in Figure 20 , the conductive layer 114, the semiconductor layer 113A of silicon or the like, the sacrificial layer 113B of silicon oxide or the like, the sacrificial layer 113C of silicon or the like, the sacrificial layer 113D of silicon oxide or the like, the semiconductor layer 113E of silicon or the like, the insulating layer 101, and the conductive layer 111 are formed on the insulating layer 101. Further, a plurality of the insulating layer 101 and a plurality of the insulating layer 110A are alternately formed. This step is performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0168] Next, for example, as shown in Figure 21 , a plurality of memory holes MH are formed at positions corresponding to the semiconductor layer 120. The memory hole MH is a through hole extending in the Z direction, penetrating the insulating layer 101 and the insulating layer 110A, the conductive layer 111, the semiconductor layer 113E, the sacrificial layer 113D, the sacrificial layer 113C, and the sacrificial layer 113B, and exposing the upper surface of the semiconductor layer 113A. This step is performed, for example, by a method such as RIE (Reactive ion etching).

[0169] Next, for example, as shown in Figure 22 , the gate insulating film 130, the semiconductor layer 120, and the insulating layer 125 are formed on the inner peripheral surface of the memory hole MH. In this step, for example, a film of amorphous silicon is formed inside the memory hole MH by CVD or the like. Further, for example, the crystal structure of the amorphous silicon film is modified by an annealing process or the like.

[0170] Next, for example, as shown in Figure 23 , the insulating layer ST O ​​In this step, for example, by means of methods such as RIE, the insulating layer ST is... O A groove is formed at the corresponding location. Furthermore, an insulating layer ST is formed inside the groove using methods such as CVD. O .

[0171] Next, for example, such as Figure 24 and Figure 25 As shown, a groove STA is formed. The groove STA extends along the Z and X directions, and divides the insulating layer 101, insulating layer 110A, conductive layer 111, semiconductor layer 113E, and sacrificial layer 113D in the Y direction, exposing the upper surface of the sacrificial layer 113C. This step is performed, for example, by a method such as RIE.

[0172] Next, for example, such as Figure 26 As shown, a protective film STSW, such as silicon nitride, is formed on the side surface of the tank STA in the Y direction. In this step, an insulating film, such as silicon nitride, is formed on the side and bottom surfaces of the tank STA in the Y direction, for example, by a method such as CVD. Furthermore, the portion of the insulating film covering the bottom surface of the tank STA is removed by a method such as RIE.

[0173] Next, for example, such as Figure 27 As shown, a portion of the sacrificial layers 113B, 113C, 113D and the gate insulating film 130 is removed, exposing a portion of the semiconductor layer 120. This step is performed, for example, by a method such as wet etching.

[0174] Next, for example, such as Figure 28 As shown, a semiconductor layer 113 is formed. This step is performed, for example, by methods such as epitaxial growth.

[0175] Next, for example, such as Figure 29 As shown, the protective film STSW is removed. This step is performed, for example, by methods such as wet etching.

[0176] Next, for example, such as Figure 30 and Figure 30 As shown, insulating layer 110A is removed via trench STA. This forms a plurality of insulating layers 101 disposed in the Z direction, and a hollow structure supporting the insulating layers 101, including the structure within the memory hole MH (semiconductor layer 120, gate insulating film 130, and insulating layer 125). This step is performed, for example, by a method such as wet etching. Furthermore, as... Figure 31 As shown, in this step, the contact connects the small region r. C4T The insulating layer 110A may also remain in the middle.

[0177] Next, for example, such as Figure 32 and Figure 33 As shown, a conductive layer 110 is formed. This step is performed, for example, by a method such as CVD.

[0178] Next, for example, such as Figure 34 and Figures 6-8 As shown, an inter-block insulating layer ST is formed within the STA trench. This step is performed, for example, by methods such as CVD and RIE.

[0179] Subsequently, wiring is formed, and the wafer is divided by dicing to form the memory die (MD).

[0180] [Effect]

[0181] As described above, the memory die MD of this embodiment has multiple input / output pad electrodes P(DQ). Here, data is input to the memory die MD within a certain timing range of a clock signal, and data is output from the memory die MD. Therefore, it is preferable to have multiple circuits connected to the multiple input / output pad electrodes P(DQ) (for example, refer to...). Figure 9 The input circuits 210, 220, input buffer circuit 230, and output circuits 240, 250 described all operate at the same speed.

[0182] Here, as shown in the reference Figure 21 As explained, in this embodiment, multiple insulating layers 110A and multiple insulating layers 101 are formed by methods such as CVD. The insulating layers 110A formed in this manner sometimes contain hydrogen. Additionally, a reference is provided. Figure 18 During the heat treatment process described, this hydrogen may sometimes diffuse.

[0183] Here, refer to Figure 10 The transistor Tr described PL The gate electrode component 152 contains p-type impurities such as boron (B). When hydrogen reaches the gate electrode component 152, there is a possibility that the hydrogen reacts with the boron, breaking the bonds between the silicon (Si) and boron (B) in the gate electrode component 152. Furthermore, there is a possibility that the boron (B) diffuses into the semiconductor substrate 100, affecting the transistor Tr. PL The threshold voltage and other characteristics change.

[0184] To suppress this transistor Tr PL Due to variations in characteristics, in the semiconductor memory device of the first embodiment, an insulating layer 104 comprising silicon nitride (SiN) or the like is provided on the upper surface of the wiring layer D2. Figure 16 Therefore, it is possible to significantly suppress the L-axis of the memory cell array layer. MCA Hydrogen diffuses into transistor layer L TR .

[0185] However, as mentioned above, sometimes the connection area R is penetrated. C4TThere are areas in the transistor where the insulating layer 104 is not provided. In such cases, hydrogen can sometimes permeate from these areas into the transistor layer L. TR Additionally, it is sometimes placed in the transistor layer L. TR Multiple transistors Tr PL The central and connecting junction area R C4T The smaller the distance, the greater the change in properties caused by hydrogen, and the greater the change in properties related to the through junction region R. C4T The greater the distance, the smaller the characteristic change caused by hydrogen. In this case, when the effect of hydrogen is present in multiple input / output circuit regions R... IO When there are differences between them, there is a risk of uneven operating speed among multiple circuits connected to multiple input / output pad electrodes P(DQ).

[0186] Therefore, in the semiconductor memory device of the first embodiment, for example, as referred to Figures 1-34 As explained, this causes the input / output circuit region R to... IO The center position on the XY plane to the region R closest to the input / output circuit IO The through-connection area R C4T The region R closest to the input / output circuit IO The distance d from the center position of the junction C4 in the XY plane IO-C4 In all input / output circuit regions R IO All circuits are identical. Based on this configuration, the effect of hydrogen, as described above, can be uniformly controlled to the same degree across multiple circuits connected to multiple input / output pad electrodes P(DQ). This suppresses uneven operating speeds among these multiple circuits.

[0187] [Other Implementation Methods]

[0188] Above, refer to Figure 16 The semiconductor memory device according to the first embodiment will be described. However, this configuration is only an example, and the specific configuration may be adjusted as appropriate.

[0189] For example, as referenced Figure 35 As explained, in the first embodiment, two adjacent through-connection regions R in the X direction C4T One input / output pad electrode P(DQ) and its corresponding input / output circuit area R are set at the corresponding positions. IO However, this configuration is merely an example, and specific configurations can be adjusted accordingly. For example, such as... Figure 35 As shown, it can also be in the X direction between two adjacent through-connection regions R C4T Two input / output pad electrodes P(DQ) are arranged along the X direction between them.

[0190] In addition,Figure 35 In the example, the distance from the center position of the input / output pad electrode P(DQ) on the XY plane to the through contact area R closest to the input / output pad electrode P(DQ) is... C4T The distance d is defined as the distance between the center position of the contact C4 closest to the input / output pad electrode P(DQ) on the XY plane. P-C4-35-1 At that time, the distance d P-C4-35-1 The same applies to all input / output pad electrodes P(DQ). Additionally, in Figure 35 In the example, the distance from the center position of the input / output pad electrode P(DQ) on the XY plane to the second through-contact region R near the input / output pad electrode P(DQ) is... C4T The distance d is defined as the distance between the center position of the contact C4 closest to the input / output pad electrode P(DQ) on the XY plane. P-C4-35-2 At that time, the distance d P-C4-35-2 All input and output pad electrodes P(DQ) are the same.

[0191] Furthermore, ideally, this would be all distances d corresponding to all input and output pad electrodes P(DQ). P-C4-35-1 d P-C4-35-2 All are the same. However, the distance d P-C4-35-1 d P-C4-35-2 Sometimes, due to design flaws or manufacturing errors, they may not be completely consistent. In such cases, for example, the ideal distance d... P-C4-35-1 d P-C4-35-2 The difference between the maximum and minimum values ​​is less than 400 nm.

[0192] In addition, Figure 35 In the example, the input / output circuit region R will be used. IO The center position on the XY plane to the region R closest to the input / output circuit IO The through-connection area R C4T The region R closest to the input / output circuit IO Let the shortest distance to the center position of the junction C4 in the XY plane be the distance d. IO-C4-35-1 At that time, the distance d IO-C4-35-1 In all input / output circuit regions R IO The same applies to all of them. Additionally, in Figure 35 In the example, the input / output circuit region R will be used. IO The center position on the XY plane to the second region R near the input / output circuit IO The through-connection area R C4T The region R closest to the input / output circuit IO Let the shortest distance to the center position of the junction C4 in the XY plane be the distance d. IO-C4-35-2 At that time, the distance d IO-C4-35-2In all input / output circuit regions R IO The same applies to both.

[0193] Furthermore, ideally, it should be compatible with all input / output circuit regions R. IO All corresponding distances d IO-C4-35-1 d IO-C4-35-2 All are the same. However, the distance d IO-C4-35-1 d IO-C4-35-2 Sometimes, due to design flaws or manufacturing errors, they may not be completely consistent. In such cases, for example, the ideal distance d... IO-C4-35-1 d IO-C4-35-2 The difference between the maximum and minimum values ​​is less than 400 nm.

[0194] In addition, when adopting Figure 35 In this configuration, regarding the even-numbered input / output circuit region R counting from the X direction... IO The configuration of transistors Tr, etc., and the odd-numbered input / output circuit region R starting from the X direction. IO The configuration of transistors Tr, etc., in the system allows for a symmetrical pattern with the Y direction as the axis (in... Figure 16 In the example, it is configured as a symmetrical pattern. Based on this configuration, even in the input / output circuit region R... IO Even when the internal hydrogen concentration is uneven, the effects of hydrogen, as described above, can be uniformly controlled to the same degree across multiple circuits connected to multiple input / output pad electrodes P (DQ).

[0195] Additionally, for example, as referenced Figure 36 As explained, in the first embodiment, there are multiple input / output pad electrodes P(DQ) and their corresponding input / output circuit regions R. IO The center position in the X direction is respectively connected to the two adjacent through-connection points R in the X direction. C4T The midpoints in the X direction are consistent. However, this configuration is only an example, and specific configurations can be adjusted accordingly. For example, as... Figure 36 As shown, multiple input / output pad electrodes P(DQ) and their corresponding input / output circuit regions R IO The center position in the X direction can also be connected to the two adjacent through-connection points R in the X direction. C4T The middle positions in the X direction are inconsistent.

[0196] In addition, Figure 36 In the example, the distance from the center position of the input / output pad electrode P(DQ) on the XY plane to the through contact area R closest to the input / output pad electrode P(DQ) is... C4T The distance d is defined as the distance between the center position of the contact C4 closest to the input / output pad electrode P(DQ) on the XY plane.P-C4-36-1 At that time, the distance d P-C4-36-1 The same applies to all input / output pad electrodes P(DQ). Additionally, in Figure 36 In the example, the distance from the center position of the input / output pad electrode P(DQ) on the XY plane to the second through-contact region R near the input / output pad electrode P(DQ) is... C4T The distance d is defined as the distance between the center position of the contact C4 closest to the input / output pad electrode P(DQ) on the XY plane. P-C4-36-2 At that time, the distance d P-C4-36-2 It is the same in all input and output pad electrodes P(DQ).

[0197] Furthermore, ideally, this would be all distances d corresponding to all input and output pad electrodes P(DQ). P-C4-36-1 d P-C4-36-2 All are the same. However, the distance d P-C4-36-1 d P-C4-36-2 Sometimes, due to design flaws or manufacturing errors, they may not be completely consistent. In such cases, for example, the ideal distance d... P-C4-36-1 d P-C4-36-2 The difference between the maximum and minimum values ​​is less than 400 nm.

[0198] In addition, Figure 36 In the example, the input / output circuit region R will be used. IO The center position on the XY plane to the region R closest to the input / output circuit IO The through-connection area R C4T The region R closest to the input / output circuit IO Let the distance from the center position of the junction C4 in the XY plane be d. IO-C4-36-1 At that time, the distance d IO-C4-36-1 In all input / output circuit regions R IO The same applies to all of them. Additionally, in Figure 36 In the example, the input / output circuit region R will be used. IO The center position on the XY plane to the second region R near the input / output circuit IO The through-connection area R C4T The region R closest to the input / output circuit IO Let the distance from the center position of the junction C4 in the XY plane be d. IO-C4-36-2 At that time, the distance d IO-C4-36-2 In all input / output circuit regions R IO The same applies to both.

[0199] Furthermore, ideally, it should be compatible with all input / output circuit regions R. IO All corresponding distances d IO-C4-36-1 d IO-C4-36-2All are the same. However, the distance d IO-C4-36-1 d IO-C4-36-2 Sometimes, due to design flaws or manufacturing errors, they may not be completely consistent. In such cases, for example, the ideal distance d... IO-C4-36-1 d IO-C4-36-2 The difference between the maximum and minimum values ​​is less than 400 nm.

[0200] In addition, when adopting Figure 16 In this configuration, in all input / output circuit regions R IO In this configuration, transistors such as Tr can be arranged in the same pattern. Based on this configuration, even in the input / output circuit region R... IO Even when the internal hydrogen concentration is uneven, the effects of hydrogen, as described above, can be uniformly controlled to the same degree across multiple circuits connected to multiple input / output pad electrodes P (DQ).

[0201] In addition, Figure 35 , Figure 36 and Figure 37 In the diagram, the center position of the input / output pad electrode P(DQ) on the XY plane is relative to the input / output circuit region R. IO The center position on the XY plane is consistent with that of the input / output pad electrode P(DQ). However, this configuration is only an example, and the specific configuration can be adjusted accordingly. For example, the center position on the XY plane of the input / output pad electrode P(DQ) is consistent with that of the input / output circuit region R. IO The center positions on the XY plane may also be inconsistent.

[0202] [TransistorTr]

[0203] As described above, in the transistor layer L of the memory die MD TR It contains both high-voltage and low-voltage transistors. See below for reference. Figure 37 This will be explained in more detail. Figure 37 This is a schematic cross-sectional view used to illustrate the types of transistors that can be mounted on the memory die MD of the first embodiment and memory dies of other embodiments.

[0204] Figure 4 The transistor Tr is shown in the figure. NL and transistor Tr NL 'As an N-type low-voltage transistor. Additionally, the transistor Tr is shown.' PL and transistor Tr PL 'As a P-type low-voltage transistor. Additionally, transistor Tr is shown.' NH As an N-type high-voltage transistor. Additionally, transistor Tr is shown. PH As a P-type high-voltage transistor.

[0205] Transistor TrNL , Tr PL than the transistor Tr NL , Tr PL , Tr NH , Tr PH act faster. Therefore, the transistor Tr NL , Tr PL are used for a portion required to act fastest in the peripheral circuit PC. For example, as described above, the transistor Tr NL , Tr PL is included in the input / output control circuit I / O( Figure 4 ).

[0206] The transistor Tr NL , Tr PL has a larger withstand voltage than the transistor Tr NL , Tr PL . In addition, the transistor Tr NL , Tr PL acts faster than the transistor Tr NH , Tr PH . The transistor Tr NL , Tr PL is used for a portion which performs signal transfer, operation, decoding, or the like in the peripheral circuit PC. For example, the transistor Tr NL , Tr PL is included in the sense amplifier module SAM, the sequencer SQC, the cache memory CM, the address register ADR, the command register CMR, the status register STR( Figure 4 ), and the like.

[0207] The transistor Tr NH , Tr PH has a larger withstand voltage than the transistor Tr NL , Tr PL , Tr NL , Tr PL . The transistor Tr NL , Tr PL is used for a portion which performs voltage generation, voltage transfer, or the like in the peripheral circuit PC. For example, the transistor Tr NH , Tr PH is included in the voltage generation circuit VG, the row decoder RD( Figure 37 ), and the like.

[0208] As described above, the transistor Tr NL , for example, has a P-type well region 100P of the semiconductor substrate 100 as a channel region. As described above, the transistor Tr PL , for example, has an N-type well region 100N of the semiconductor substrate 100 as a channel region. The transistor TrNL For example, the P-type well region 100P of the semiconductor substrate 100 is used as the channel region. The transistor Tr PL For example, the N-type well region 100N of the semiconductor substrate 100 is used as the channel region. The transistor Tr NH For example, the semiconductor substrate region 100S of the semiconductor substrate 100 is used as the channel region. The transistor Tr PH For example, the N-type well region 100N of the semiconductor substrate 100 is used as the channel region.

[0209] In addition, as described above, the gate electrode of the transistor Tr NL includes a gate electrode member 142 containing polycrystal silicon (Si) or the like containing an N-type impurity. In addition, as described above, the gate electrode of the transistor Tr PL includes a gate electrode member 152 containing polycrystal silicon (Si) or the like containing a P-type impurity. The transistor Tr NL , Tr PL , Tr NH , Tr PH The gate electrode of the transistor Tr NL includes a gate electrode member 142' containing polycrystal silicon (Si) or the like containing an N-type impurity, similarly to the gate electrode of the transistor Tr

[0210] In addition, ​ the transistor Tr NL , Tr PL The thickness of the gate insulating film of the transistor Tr L in the Z direction is represented by T NL . In addition, the thickness of the gate insulating film of the transistor Tr PL in the Z direction is represented by T L . In addition, the thickness of the gate insulating film of the transistor Tr NH , Tr PH in the Z direction is represented by T H . In addition, T L is smaller than T L . In addition, T L ' is smaller than T H .

[0211] [Others]

[0212] While several embodiments of the present application have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the application. Indeed, the novel methods and systems described herein can be embodied in a variety of other ways, as will be apparent to those skilled in the art. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein can be made without departing from the spirit of the application. The embodiments and their variations encompassed within the scope of the appended claims and their equivalents are intended to be covered.

Claims

1. A semiconductor memory device comprising: Substrate; The memory cell array is disposed separately from the substrate in a first direction intersecting the surface of the substrate; as well as Multiple first pad electrodes are arranged along a second direction intersecting the first direction and are positioned away from the memory cell array in a third direction intersecting the first and second directions, and can be used to input data written to the memory cell array and output data read from the memory cell array; The substrate has a plurality of first regions and a plurality of second regions arranged alternately along the second direction. The storage cell array includes: Multiple conductive layers extend across the multiple first regions and the multiple second regions along the second direction and are arranged along the first direction; Multiple semiconductor layers are disposed in the multiple first regions, extend along the first direction, and face the multiple conductive layers; as well as A plurality of first contacts are disposed in the plurality of second regions and extend along the first direction, one end of the first direction being closer to the substrate than the plurality of conductive layers, and the other end of the first direction being farther away from the substrate than the plurality of conductive layers; When the distance between the center position of one of the plurality of first pad electrodes in the second direction and the center position of the first contact point closest to that first pad electrode in the second direction and the center position in the third direction is defined as the first distance in the second direction and the third direction, The difference between the maximum and minimum distances among the plurality of first distances corresponding to the plurality of first pad electrodes is less than 400 nm.

2. The semiconductor memory device according to claim 1, wherein When the distance between the center position of one of the plurality of first pad electrodes in the second direction and the center position of the closest first contact point among the plurality of first contacts included in the second region adjacent to the first pad electrode in the second direction and the center position of the first contact point among the plurality of first pad electrodes in the second direction and the center position of the first contact point among the plurality of first pad electrodes in the second direction and the center position of the first contact point among the plurality of first contact points included in the second region adjacent to the first pad electrode in the second direction and the center position of the first contact point in the third direction is defined as the second distance in the second direction and the third direction, The difference between the maximum and minimum distances among the plurality of second distances corresponding to the plurality of first pad electrodes is less than 400 nm.

3. The semiconductor memory device according to claim 1, wherein... When the center position of two adjacent second regions in the second direction is set as the first position in the second direction, The plurality of first pad electrodes each include portions disposed at the plurality of the first positions.

4. The semiconductor memory device according to claim 1, wherein When the center position of two adjacent second regions in the second direction is set as the first position in the second direction, The center position of the plurality of first pad electrodes in the second direction is not the same as any of the plurality of first positions.

5. The semiconductor memory device according to claim 1, wherein... Two center positions in the second direction, corresponding to the two first pad electrodes, are provided between two adjacent second regions in the second direction.

6. The semiconductor memory device according to claim 1, comprising: A plurality of first driving circuits are respectively connected to the plurality of first pad electrodes, and include a plurality of transistors connected in parallel between the first pad electrodes and the voltage supply line; and A plurality of second driving circuits are respectively connected to the plurality of first pad electrodes, and include a comparator connected to the first pad electrodes; The substrate has a plurality of third regions, which are disposed in a third direction away from the plurality of first regions and the plurality of second regions, and are arranged along the second direction. The plurality of third regions each contain a plurality of transistors constituting one of the plurality of first driving circuits and a plurality of transistors constituting one of the plurality of second driving circuits.

7. The semiconductor memory device according to claim 6, wherein When the distance between the center position of one of the plurality of third regions in the second direction and the center position of the first contact point closest to that third region in the second direction and the center position in the third direction is defined as the third distance, The difference between the maximum and minimum distances among the plurality of third distances corresponding to the plurality of third regions is less than 400 nm.

8. The semiconductor memory device according to claim 6, wherein When the distance between the center position of one of the plurality of third regions in the second direction and the center position of the closest first contact point among the plurality of first contacts contained in the second region adjacent to the third region in the second direction and the center position of the first contact point in the second direction and the third direction is defined as the fourth distance, The difference between the maximum and minimum distances among the multiple fourth distances corresponding to the multiple third regions is less than 400 nm.

9. The semiconductor memory device according to claim 6, wherein The gate electrode of at least one of the plurality of transistors contained in the third region contains boron (B).

10. A semiconductor memory device comprising: Substrate; The memory cell array is disposed separately from the substrate in a first direction intersecting the surface of the substrate; Multiple first pad electrodes are arranged along a second direction intersecting the first direction and are positioned away from the memory cell array in a third direction intersecting the first and second directions, and can be used to input data written to the memory cell array and output data read from the memory cell array; A plurality of first driving circuits are respectively connected to the plurality of first pad electrodes, and include a plurality of transistors connected in parallel between the first pad electrodes and the voltage supply line; as well as A plurality of second driving circuits are respectively connected to the plurality of first pad electrodes, and include a comparator connected to the first pad electrodes; The substrate comprises: Multiple first regions and multiple second regions are arranged alternately along the second direction; as well as Multiple third regions are located in the third direction at positions away from the multiple first regions and the multiple second regions, and are arranged along the second direction; The storage cell array includes: Multiple conductive layers extend across the multiple first regions and the multiple second regions along the second direction and are arranged along the first direction; Multiple semiconductor layers are disposed in the multiple first regions, extend along the first direction, and face the multiple conductive layers; as well as A plurality of first contacts are disposed in the plurality of second regions and extend along the first direction, one end of the first direction being closer to the substrate than the plurality of conductive layers, and the other end of the first direction being farther away from the substrate than the plurality of conductive layers; The plurality of third regions each contain a plurality of transistors constituting one of the plurality of first driving circuits and a plurality of transistors constituting one of the plurality of second driving circuits. When the distance between the center position of one of the plurality of third regions in the second direction and the center position of the first contact point closest to that third region in the second direction and the center position in the third direction is defined as the first distance in the second direction and the third direction, The difference between the maximum and minimum distances among the multiple first distances corresponding to the multiple third regions is less than 400 nm.

11. The semiconductor memory device of claim 10, wherein... When the distance between the center position of one of the plurality of third regions in the second direction and the center position of the closest first contact point among the plurality of first contacts contained in the second region adjacent to the third region in the second direction and the center position of the first contact point in the third region in the second direction and the third direction is defined as the second distance, The difference between the maximum and minimum distances among the multiple second distances corresponding to the multiple third regions is less than 400 nm.

12. The semiconductor memory device of claim 10, wherein... When the center position of two adjacent second regions in the second direction is set as the first position in the second direction, The plurality of third regions each include portions disposed at the plurality of the first positions.

13. The semiconductor memory device of claim 10, wherein... When the center position of two adjacent second regions in the second direction is set as the first position in the second direction, The center position of each of the plurality of third regions in the second direction is not the same as any of the plurality of first positions.

14. The semiconductor memory device of claim 13, wherein... The plurality of transistors are configured in the same pattern between the plurality of third regions.

15. The semiconductor memory device according to claim 10, wherein Two center positions in the second direction, corresponding to the two third regions, are provided between two adjacent second regions in the second direction.

16. The semiconductor memory device of claim 15, wherein Between the two third regions, the plurality of transistors are arranged in a symmetrical pattern with the third direction as the axis.

17. The semiconductor memory device of claim 10, wherein... The gate electrode of at least one of the plurality of transistors contained in the third region contains boron (B).

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