A display panel and a method for manufacturing the same

Abstract

The present application provides a display panel and a manufacturing method thereof, wherein the display panel comprises: a substrate and a thin film transistor layer disposed on the substrate, the thin film transistor layer comprises an interlayer dielectric layer and a metal layer disposed on the interlayer dielectric layer, the metal layer comprises a plurality of metal electrodes disposed at intervals; wherein the interlayer dielectric layer comprises a base dielectric layer and a non-insulating dielectric layer disposed on the base dielectric layer, the base dielectric layer is disposed adjacent to the metal electrode, and the non-insulating dielectric layer is disposed in the gap region between the metal electrodes. The present application forms a non-insulating dielectric layer in the gap region between the metal electrodes corresponding to the interlayer dielectric layer, thereby reducing the reflectivity of the plasma on the interlayer dielectric layer during the patterning process of the metal layer, optimizing the side morphology of the metal electrode, greatly reducing the probability of black-scale stripes, bright and dark lines, and other problems occurring in the display panel, and achieving the purpose of improving the yield of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof. Background Art

[0002] Liquid Crystal Display (LCD) has been widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, desktop computers, etc. due to its advantages of high image quality, power saving, thin body and wide application range, becoming the mainstream of display devices.

[0003] The array substrate in the liquid crystal display includes thin film transistors arranged in an array, and the low-temperature polycrystalline silicon (LTPS) thin film transistor can enable the transistor to obtain a higher switching current ratio due to its higher carrier mobility. Under the condition of meeting the required charging current, each pixel transistor can be smaller in size, increasing the light transmission area of ​​each pixel, increasing the panel aperture ratio, improving the panel bright spots and high resolution, and reducing the panel power consumption, thereby obtaining a better visual experience. It has been widely used in the field of liquid crystal displays.

[0004] However, in the existing LTPS liquid crystal display panel, the source and drain metal layer arranged on the interlayer dielectric layer (ILD) is generally a composite metal film layer including multiple materials. There are differences in the etching rates of different materials. This will cause the gradually exposed interlayer dielectric layer to reflect the plasma in the reaction chamber when the etching of the source and drain metal layer is about to be completed. The plasma will bombard the sides of the source and drain, which is more likely to cause undercutting (Under Cut) phenomenon, resulting in poor morphology of the side of the source and drain, causing the liquid crystal display panel to have black stripes, bright and dark lines and other problems when displaying the picture, seriously affecting the product yield and performance. This problem needs to be solved urgently. Summary of the invention

[0005] The present application provides a display panel and a manufacturing method thereof, which can greatly reduce the probability of black scale stripes, bright and dark lines and other problems occurring in the display panel, thereby achieving the purpose of improving the yield of the display panel.

[0006] The embodiment of the present application provides a display panel, the display panel comprising: a base substrate and a thin film transistor layer arranged on the base substrate, the thin film transistor layer comprising an interlayer dielectric layer and a metal layer arranged on the interlayer dielectric layer, the metal layer comprising a plurality of metal electrodes arranged at intervals;

[0007] The interlayer dielectric layer includes a base dielectric layer and a non-insulating dielectric layer located on the base dielectric layer. The base dielectric layer is disposed adjacent to the metal electrodes, and the non-insulating dielectric layer is located in a gap region between the metal electrodes.

[0008] Optionally, the non-insulating dielectric layer is located in a region of the gap region close to an edge of the metal electrode.

[0009] Optionally, the base dielectric layer is a non-metallic nitride film layer, and the non-insulating dielectric layer is a metal nitride film layer.

[0010] Optionally, the interlayer dielectric layer also includes a first interlayer dielectric layer and a second interlayer dielectric layer, the second interlayer dielectric layer is located on the first interlayer dielectric layer, the base dielectric layer is located on the second interlayer dielectric layer, and the first interlayer dielectric layer is made of the same material as the base dielectric layer and different from the material of the second interlayer dielectric layer.

[0011] Optionally, the first interlayer dielectric layer and the base dielectric layer are silicon nitride film layers, and the second interlayer dielectric layer is a silicon oxide film layer.

[0012] Optionally, the metal layer includes a first metal layer, a second metal layer and a third metal layer which are sequentially stacked on the interlayer dielectric layer, and the first metal layer is made of the same material as the third metal layer and different from the second metal layer.

[0013] Optionally, the first metal layer is a titanium metal film layer, the second metal layer is an aluminum metal film layer, and the non-insulating dielectric layer is a titanium nitride film layer.

[0014] Optionally, the thin film transistor layer includes an active layer, a gate insulating layer, a gate layer, the interlayer dielectric layer and the metal layer which are sequentially stacked on the base substrate, and the metal electrode includes a source electrode and a drain electrode.

[0015] Optionally, the display panel includes a light shielding layer, a buffer layer, the thin film transistor layer, a planarization layer, a common electrode layer, a passivation layer and a pixel electrode layer which are stacked in sequence.

[0016] Accordingly, the embodiment of the present application further provides a method for manufacturing a display panel, comprising the following steps:

[0017] Providing a base substrate, and sequentially forming a light shielding layer, a buffer layer, a thin film transistor layer, a planarization layer, a common electrode layer, a passivation layer and a pixel electrode layer on the base substrate;

[0018] Among them, the thin film transistor layer includes an interlayer dielectric layer and a metal layer arranged on the interlayer dielectric layer, the metal layer includes a plurality of metal electrodes arranged at intervals, the interlayer dielectric layer includes a base dielectric layer and a non-insulating dielectric layer located on the base dielectric layer, the base dielectric layer is arranged adjacent to the metal electrodes, and the non-insulating dielectric layer is located in the gap area between the metal electrodes.

[0019] The present application forms a non-insulating dielectric layer in the gap area between the metal electrodes corresponding to the interlayer dielectric layer, thereby reducing the reflectivity of the plasma on the interlayer dielectric layer during the patterning process of the metal layer, optimizing the side morphology of the metal electrode, and greatly reducing the probability of black stripes, bright and dark lines and other problems on the display panel, thereby achieving the purpose of improving the yield of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a schematic diagram of the structure of an array substrate of a display panel provided in an embodiment of the present application;

[0022] Figure 2 is a schematic diagram of the structure of an interlayer dielectric layer provided in an embodiment of the present application;

[0023] Figure 3 is a schematic diagram of the structure of the metal layer provided in an embodiment of the present application;

[0024] Figure 4 It is a flow chart of the manufacturing method of the display panel provided in the embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0026] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials. The following is described in detail respectively, and it should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0027] In the LTPS liquid crystal display panel in the prior art, the source and drain metal layers arranged on the interlayer dielectric layer are prone to undercutting during the etching process, resulting in poor side morphology of the source and drain formed by etching, making it easy for the liquid crystal display panel to have problems such as black stripes, bright and dark lines when displaying images, seriously affecting the product yield and performance.

[0028] Based on the above problems, an embodiment of the present invention provides a display panel, wherein the metal layer of the display panel includes a plurality of spaced-apart metal electrodes, and the display panel forms a non-insulating dielectric layer in the gap area between the metal electrodes corresponding to the interlayer dielectric layer, thereby reducing the reflectivity of the plasma on the interlayer dielectric layer during the patterning process of the metal layer, optimizing the side morphology of the metal electrode, and greatly reducing the probability of the display panel having problems such as black stripes and bright and dark lines, thereby achieving the purpose of improving the yield of the display panel.

[0029] The following detailed description is given using a liquid crystal display panel as an example, but the present application does not limit the type of the display panel. The display panel may also be an organic light emitting diode (OLED) display panel or a micro light emitting diode (Micro LED or Mini LED) display panel. As long as the above-mentioned display panel has an interlayer dielectric layer and a patterned metal layer structure located on the interlayer dielectric layer, the inventive concept of the present application may be used.

[0030] In this embodiment, the display panel is a liquid crystal display panel, and the display panel includes, for example, an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. It should be noted that the color filter substrate is used to form a liquid crystal box with the array substrate, but the color filter substrate is not necessarily provided with a color filter, and the color filter can also be directly disposed on the array substrate.

[0031] In this embodiment, in a direction perpendicular to the array substrate, a plurality of data lines extending along a first direction and a plurality of scan lines extending along a second direction are formed on the array substrate, and the second direction is, for example, perpendicular to the first direction, and sub-pixel units are correspondingly formed in a grid structure defined by the staggered data lines and the scan lines, and a pixel electrode is arranged in each sub-pixel unit. An array-arranged thin-film transistor is also formed on the array substrate, and the thin-film transistor includes a gate, a source and a drain, the gate is electrically connected to the scan line, the source is electrically connected to the data line, and the drain is electrically connected to the pixel electrode.

[0032] The film layer structure of the thin film transistor and the film layer structures above and below the thin film transistor layer are further described in detail below.

[0033] Figure 1 is a schematic diagram of the structure of an array substrate of a display panel provided in an embodiment of the present application, Figure 2 is a schematic diagram of the structure of the interlayer dielectric layer provided in the embodiment of the present application, Figure 3 Schematic diagram of the structure of the metal layer provided in the embodiment of the present application. Figure 1 , Figure 2 and Figure 3 As shown, the array substrate includes: a base substrate 10, which can be a rigid substrate or a flexible substrate, and its material includes one or more of glass, plastic, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyimide or polyurethane.

[0034] In this embodiment, the array substrate also includes: a thin film transistor layer, which is arranged on the base substrate 10, and the thin film transistor layer includes an interlayer dielectric layer 70 and a metal layer 80 arranged on the interlayer dielectric layer 70, and the metal layer 80 includes a plurality of spaced metal electrodes 810; wherein the interlayer dielectric layer 70 includes a base dielectric layer 730 and a non-insulating dielectric layer 740 located on the base dielectric layer 730, the base dielectric layer 730 is adjacent to the metal electrode 810, and the non-insulating dielectric layer 740 is located in the gap area between the metal electrodes 810.

[0035] Specifically, the metal layer 80 includes a plurality of spaced metal electrodes 810, and the plurality of spaced metal electrodes 810 are formed by the metal layer 80 through a patterning process, and the patterning process is, for example, an etching process, and the etching process is, for example, dry etching. When etching the metal layer 80, it is necessary to place the metal layer 80 in a reaction chamber of a specific environment, and the ions in the plasma in the reaction chamber are accelerated under the action of an electric field to bombard the surface of the metal layer 80. The applicant has found that the film layer of the current interlayer dielectric layer on the side close to the metal layer is a silicon oxide film layer, and the silicon oxide film layer will generate an insulating medium with the metal ions in the metal layer when the metal layer is about to be etched, and the insulating medium has a high reflectivity to the plasma, and the plasma reflected by the insulating medium will bombard the side of the metal layer, resulting in a poor side morphology of the metal layer, forming an edge slope (Taper) angle that cannot meet the requirements, thereby causing poor display and reduced yield of the display panel. Furthermore, when the metal layer is a multi-layer structure including multiple materials, the inconsistency of etching rates of each layer will further deteriorate the side morphology.

[0036] In this embodiment, the interlayer dielectric layer 70 forms a non-insulating dielectric layer 740 on the gap area corresponding to the metal electrode 810. The non-insulating dielectric layer 740 has a low reflectivity to the plasma and can effectively pull the plasma to the surface of the non-insulating dielectric, thereby reducing the bombardment on the side of the metal electrode 810, optimizing the side shape and Taper angle of the metal electrode 810, and improving the display effect of the display panel.

[0037] In this embodiment, the non-insulating dielectric layer 740 is located in the gap region near the edge of the metal electrode 810. Specifically, the metal layer 80 includes a first stage and a second stage located after the first stage when etching is about to be completed, wherein, in the first stage, the non-insulating dielectric layer 740 corresponding to the gap region formed between the metal electrodes 810 has a larger area, for example, at this time, the non-insulating dielectric layer 740 is arranged corresponding to the entire gap region, and the non-insulating dielectric layer 740 can pull the plasma to the surface of the non-insulating dielectric 740, thereby effectively preventing the deterioration of the side morphology of the metal electrode 810; as the etching continues and finally ends, that is, in the second stage, the area of ​​the non-insulating dielectric layer 740 will gradually shrink, and finally only the non-insulating dielectric layer 740 is retained in the gap region near the edge of the metal electrode 810.

[0038] In this embodiment, the interlayer dielectric layer 70 further includes a base dielectric layer 730, and the base dielectric layer 730 is disposed adjacent to the metal layer 80. The non-insulating dielectric layer 740 is located on the surface of the base dielectric layer 730 and corresponds to the gap region between the metal electrodes 810. The non-insulating dielectric layer 740 is formed by the composite transformation of the base dielectric layer 730 and the metal ions in the metal layer 80. The base dielectric layer 730 is a non-metallic nitride, and the non-insulating dielectric layer 740 is a metal nitride. Specifically, when the metal layer 80 is about to be etched, the metal ions in the bottom metal layer 80 can be recombined with the base dielectric layer 730 under the action of the plasma to generate the non-insulating dielectric layer 740. Preferably, the base dielectric layer 730 is a silicon nitride film layer, but the present application does not limit the specific material of the base dielectric layer 730, and it can also be other non-metallic nitride film layers, and the other non-metals are, for example, other non-metallic elements of the same family as silicon.

[0039] In this embodiment, the interlayer dielectric layer 70 also includes a first interlayer dielectric layer 710 and a second interlayer dielectric layer 720 stacked in sequence on the base substrate 10, and the first interlayer dielectric layer 710 is made of the same material as the base dielectric layer 730, and is different from the second interlayer dielectric layer 720. Preferably, the second interlayer dielectric layer 720 is a silicon oxide film layer, and the first interlayer dielectric layer 710 is also a silicon nitride film layer. The structure of silicon nitride film layer / silicon oxide film layer / silicon nitride film layer stacked in sequence on the base substrate 10 can improve the electrical performance of the interlayer dielectric layer 70 while ensuring the optical performance of the interlayer dielectric layer 70. And because in the etching process, under the action of the same etching gas, the silicon nitride film layer is easier to etch, and the silicon oxide film layer is relatively difficult to etch, so when the metal layer 80 is about to be etched, the occurrence of lateral etching can be further reduced. Preferably, the etching gas is, for example, BCl3 and / or Cl2.

[0040] In this embodiment, the metal layer 80 includes a first metal layer 810, a second metal layer 820 and a third metal layer 830 which are sequentially stacked on the interlayer dielectric layer 70, and the first metal layer 810 is made of the same material as the third metal layer 830, and is different from the second metal layer 820. Preferably, the first metal layer 810 and the third metal layer 830 are titanium metal film layers, and the second metal layer 820 is an aluminum metal film layer. Correspondingly, when the etching of the metal layer 80 is about to be completed, the bottom layer of the first metal layer 810 can be recombined with the gradually exposed base dielectric layer 730 under the action of the plasma as the etching continues to proceed to generate the non-insulating dielectric layer 740. Preferably, the non-insulating dielectric layer 740 is a titanium nitride film layer. The embodiment of the present application can well avoid the problem of poor side morphology of the metal layer by setting the non-insulating dielectric layer 740 that has a traction effect on the plasma.

[0041] In this embodiment, the thin film transistor layer includes an active layer 40, a gate insulating layer 50, a gate layer 60, an interlayer dielectric layer 70 and a metal layer 80 which are sequentially stacked on the base substrate 10. The active layer 40 includes a channel region 41, a heavily doped region 42 and a lightly doped region 43, wherein the lightly doped region 43 is located on both sides of the channel region 41, and the heavily doped region 42 is located on both sides of the lightly doped region 43 away from the channel region 41; the gate layer 60 includes a gate, and the metal electrode 810 includes a source electrode 81 and a drain electrode 82. Furthermore, the metal electrode 810 also includes a binding electrode 83.

[0042] In this embodiment, the thin film transistor layer also includes a first via hole 71 arranged corresponding to the heavily doped region 42, and the first via hole 71 passes through the gate insulation layer 50 and the interlayer dielectric layer 70, and the source 81 and the drain 82 are overlapped with the heavily doped region 42 of the active layer 40 through the first via hole 71.

[0043] In this embodiment, the thin film transistors in the thin film transistor layer are low-temperature polycrystalline silicon thin film transistors, and the material forming the channel region 41 of the active layer 40 is low-temperature polycrystalline silicon. The high carrier mobility of the low-temperature polycrystalline silicon thin film transistor can enable the transistor to obtain a higher switching current ratio. Under the condition of meeting the required charging current, each thin film transistor can be smaller in size, increasing the light-transmitting area of ​​each sub-pixel unit, increasing the aperture ratio of the display panel, improving the bright spots and high resolution of the display panel, and reducing the power consumption of the display panel, thereby obtaining a better visual experience.

[0044] In this embodiment, the display panel includes a shading layer 20, a buffer layer 30, the thin film transistor layer, a planarization layer 90, a common electrode layer 100, a passivation layer 110 and a pixel electrode layer 120 which are stacked in sequence, wherein the vertical projection of the shading layer 20 on the base substrate 10 covers the vertical projection of the active layer 40 on the base substrate 10, and the shading layer 20 is used to prevent the performance of the active layer 40 from deteriorating due to light exposure; the buffer layer 30 has a buffering function and ensures the film forming quality of the active layer 40; the planarization layer 90 is used to planarize the thin film transistor layer; the common electrode layer 100 is formed with a common electrode and a touch electrode line; the passivation layer 110 is used to electrically insulate the common electrode layer 100 and the pixel electrode layer 120; the pixel electrode layer 120 is formed with a pixel electrode electrically connected to the drain 82. Specifically, the display panel also includes a second via hole 91 and a third via hole 111. The second via hole 91 is formed on the flat layer 90 and is arranged corresponding to the binding electrode 83. The touch electrode line is overlapped with the binding electrode 83 through the second via hole 91. The third via hole 111 is formed on the passivation layer 110 and the flat layer 90 and is arranged corresponding to the drain electrode 82. The pixel electrode is overlapped with the drain electrode 82 through the third via hole 111.

[0045] On the other hand, the present application also provides a method for manufacturing a display panel. Figure 4 is a flow chart of a method for manufacturing a display panel provided in an embodiment of the present application, Figure 1-Figure 4 As shown, the present invention provides a method for manufacturing a display panel, which is used to manufacture the display panel in the above embodiment. Specifically, the method for manufacturing the display panel uses 10 masks in total and includes the following steps:

[0046] S10 : providing a base substrate 10 , and forming a light shielding layer 20 on the base substrate 10 through a first photomask.

[0047] S20: forming a buffer layer 30 on the light shielding layer 20, and forming an active layer 40 on the light shielding layer 20 by a second masking process.

[0048] S30 : forming an N-type heavily doped region 42 on the active layer 40 by using a third photomask.

[0049] S40: forming a gate insulating layer 50 on the active layer 40, and forming a gate layer 60 including a gate on the gate insulating layer 50 through a fourth photomask, and then using the gate as a hard mask to form an N-type lightly doped region 43.

[0050] S50 : forming an interlayer dielectric layer 70 on the gate layer 60 , and opening first via holes 71 on the gate insulating layer 50 and the interlayer dielectric layer 70 through a fifth mask, wherein positions of the first via holes 71 correspond to the N-type heavily doped regions 42 .

[0051] In this embodiment, the interlayer dielectric layer 70 includes a first interlayer dielectric layer 710, a second interlayer dielectric layer 720, and a base dielectric layer 730 which are sequentially stacked on the base substrate 10. The first interlayer dielectric layer 710 and the base dielectric layer 730 are silicon nitride film layers, and the second interlayer dielectric layer 720 is a silicon oxide film layer.

[0052] S60: A metal layer 80 including a plurality of metal electrodes 810 is formed on the interlayer dielectric layer 70 through a sixth photomask, wherein the metal electrode 810 includes a source 81, a drain 82 and a binding electrode 83, and the source 81 and the drain 82 are respectively overlapped with the N-type heavily doped region 42 through the first via hole 71.

[0053] In this embodiment, during the etching process of the metal layer 80, when the metal layer 80 is about to be etched, the bottom metal layer 80 can be recombined with the base dielectric layer 730 under the action of the plasma as the etching continues, so as to generate a non-insulating dielectric layer 740 in the gap region between the metal electrodes 810 on the surface of the base dielectric layer 730. The bottom metal layer 80 is, for example, a titanium metal layer. It should be noted that as the etching progresses, the area of ​​the non-insulating dielectric layer 740 formed in the gap region will continue to shrink, and finally only the non-insulating dielectric layer 740 will remain in the gap region near the edge of the metal electrode 810. Specifically, when etching of the metal layer 80 is about to be completed, it includes a first stage and a second stage after the first stage, wherein, in the first stage, the area of ​​the non-insulating dielectric layer 740 corresponding to the gap region formed between the metal electrodes 810 is relatively large. For example, at this time, the non-insulating dielectric layer 740 is arranged corresponding to the entire gap region, and the non-insulating dielectric layer 740 can pull the plasma to the surface of the non-insulating dielectric 740, thereby effectively preventing the deterioration of the side morphology of the metal electrode 810; as the etching continues and finally ends, that is, in the second stage, the area of ​​the non-insulating dielectric layer 740 will gradually shrink, and finally the non-insulating dielectric layer 740 will be retained only in the area of ​​the gap region close to the edge of the metal electrode 810.

[0054] In this embodiment, the metal layer 80 includes a plurality of metal electrodes 810 arranged at intervals, and the metal electrode 810 includes a source electrode 81, a drain electrode 82 and a binding electrode 83. The source electrode 81 and the drain electrode 82 are respectively overlapped with the N-type heavily doped region 42 of the active layer 40 through the first via hole. The metal layer 80 includes a first metal layer 810, a second metal layer 820 and a third metal layer 830 which are sequentially stacked on the interlayer dielectric layer 70, the first metal layer 810 and the third metal layer 830 are titanium metal film layers, and the second metal layer 820 is an aluminum metal film layer.

[0055] S70 : forming a planar layer 90 on the metal layer 80 , and opening a second via hole 91 on the planar layer 90 through a seventh photomask, wherein the position of the second via hole 91 corresponds to the drain electrode 82 .

[0056] S80 : forming a common electrode layer 100 including common electrodes on the flat layer 90 through an eighth photomask, wherein the common electrode layer 100 includes common electrodes and touch signal lines arranged at intervals, and the touch signal lines are overlapped with the binding electrodes 83 through the second via holes 91 .

[0057] S90 : forming a passivation layer 110 on the common electrode layer 100 , and forming a third via hole 111 on the planar layer 90 and the passivation layer 110 through a ninth photomask, wherein the position of the third via hole 111 corresponds to the drain electrode 82 .

[0058] S100 : forming a pixel electrode layer 120 on the passivation layer 110 through a tenth photomask, wherein the pixel electrode layer 120 is overlapped with the drain electrode 82 through the third via hole 111 .

[0059] In summary, the present application provides a display panel and a manufacturing method thereof, wherein the display panel comprises: a base substrate and a thin film transistor layer disposed on the base substrate, the thin film transistor layer comprises an interlayer dielectric layer and a metal layer disposed on the interlayer dielectric layer, the metal layer comprises a plurality of metal electrodes disposed at intervals; wherein the interlayer dielectric layer comprises a base dielectric layer and a non-insulating dielectric layer disposed on the base dielectric layer, the base dielectric layer is disposed adjacent to the metal electrodes, and the non-insulating dielectric layer is located in the gap region between the metal electrodes. The present application forms a non-insulating dielectric layer in the gap region between the metal electrodes corresponding to the interlayer dielectric layer, thereby reducing the reflectivity of the plasma on the interlayer dielectric layer during the patterning process of the metal layer, optimizing the side morphology of the metal electrode, greatly reducing the probability of the display panel having problems such as black-scale stripes and bright and dark lines, and achieving the purpose of improving the yield of the display panel.

[0060] The display panel and the manufacturing method thereof provided by the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A display panel, characterized in that: The display panel comprises: a base substrate and a thin film transistor layer arranged on the base substrate, the thin film transistor layer comprises an interlayer dielectric layer and a metal layer arranged on the interlayer dielectric layer, the metal layer comprises a plurality of metal electrodes arranged at intervals; The interlayer dielectric layer includes a base dielectric layer and a non-insulating dielectric layer on the base dielectric layer. The base dielectric layer is arranged adjacent to the metal electrode, and the non-insulating dielectric layer is located in the gap region between the metal electrodes and close to the edge of the metal electrode.

2. The display panel according to claim 1, characterized in that: The base dielectric layer is a non-metallic nitride film layer, and the non-insulating dielectric layer is a metal nitride film layer.

3. The display panel according to claim 2, characterized in that: The interlayer dielectric layer also includes a first interlayer dielectric layer and a second interlayer dielectric layer, the second interlayer dielectric layer is located on the first interlayer dielectric layer, the base dielectric layer is located on the second interlayer dielectric layer, and the first interlayer dielectric layer is made of the same material as the base dielectric layer and different from the second interlayer dielectric layer.

4. The display panel according to claim 3, characterized in that: The first interlayer dielectric layer and the base dielectric layer are silicon nitride film layers, and the second interlayer dielectric layer is a silicon oxide film layer.

5. The display panel according to claim 4, characterized in that: The metal layer includes a first metal layer, a second metal layer and a third metal layer which are sequentially stacked on the interlayer dielectric layer. The first metal layer is made of the same material as the third metal layer and is different from the second metal layer.

6. The display panel according to claim 5, characterized in that: The first metal layer is a titanium metal film layer, the second metal layer is an aluminum metal film layer, and the non-insulating dielectric layer is a titanium nitride film layer.

7. The display panel according to claim 1, characterized in that: The thin film transistor layer includes an active layer, a gate insulating layer, a gate layer, the interlayer dielectric layer and the metal layer which are sequentially stacked on the base substrate, and the metal electrode includes a source electrode and a drain electrode.

8. The display panel according to claim 7, characterized in that: The display panel includes a light shielding layer, a buffer layer, the thin film transistor layer, a planarization layer, a common electrode layer, a passivation layer and a pixel electrode layer which are sequentially stacked.

9. A method for manufacturing a display panel, characterized in that: The method comprises the following steps: providing a base substrate, and sequentially forming a light shielding layer, a buffer layer, a thin film transistor layer, a flat layer, a common electrode layer, a passivation layer and a pixel electrode layer on the base substrate; Among them, the thin film transistor layer includes an interlayer dielectric layer and a metal layer arranged on the interlayer dielectric layer, the metal layer includes a plurality of metal electrodes arranged at intervals, the interlayer dielectric layer includes a base dielectric layer and a non-insulating dielectric layer located on the base dielectric layer, the base dielectric layer is arranged adjacent to the metal electrodes, and the non-insulating dielectric layer is located in the gap area between the metal electrodes and close to the edge of the metal electrode.

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