Control circuit and method for reducing electromagnetic interference

Abstract

The embodiment of the present application provides a control circuit and method for reducing electromagnetic interference, the control circuit comprising: a bias unit, a driving unit, a plurality of switch tubes and a flying capacitor; the driving unit is coupled to the bias unit; the first end of the plurality of switch tubes is connected to the flying capacitor; the bias unit is adapted to generate a bias voltage or a bias current; the driving unit is adapted to receive a control signal, the bias voltage or the bias current, and output a first voltage, wherein the first voltage is used for controlling the opening or closing of the plurality of switch tubes; the second end of part of the plurality of switch tubes is adapted to input a second voltage; the second end of at least one of the plurality of switch tubes is adapted to output a third voltage. The technical scheme of the embodiment of the present application can reduce the electromagnetic interference generated by the flying capacitor in the charging and discharging process, and reduce the area of the control circuit while not affecting the driving capability of the charge pump.

Description

Technical Field

[0001] This invention relates to the field of circuit design, and more particularly to control circuits and methods for reducing electromagnetic interference. Background Technology

[0002] A charge pump can provide bias voltage to the display driver chip of an LCD panel in an electronic device; it can include a boost unit or multiple cascaded boost units, each of which can increase the output voltage relative to its input voltage, for example, by up to twice.

[0003] The boost unit includes several switching transistors and flying capacitors; the boost process of the charge pump is the energy transfer process of the flying capacitors.

[0004] Figure 1 The diagram illustrates a boost unit in a charge pump. The boost unit 10 includes four switching transistors S1, S2, S3, and S4, and a flying capacitor Cfly. One end of each of the switching transistors S1 and S2 is connected to one end of the flying capacitor Cfly, and the other end is connected to the input voltage V1 and the output voltage V2, respectively. One end of each of the switching transistors S3 and S4 is connected to the other end of the flying capacitor Cfly, and the other end is connected to ground and the input voltage V1, respectively.

[0005] The energy transfer process of the flying capacitor Cfly includes a charging process and a discharging process. During the charging process, switches S1 and S3 are closed while S2 and S4 are open, and the input voltage V1 charges the flying capacitor Cfly until its voltage reaches V1. During the discharging process, switches S1 and S3 are open while S2 and S4 are closed, and the input voltage V1 and the flying capacitor Cfly simultaneously charge the output terminal, making the output voltage V2 equal to twice the input voltage V1.

[0006] However, this energy transfer process generates strong electromagnetic interference (EMI), which affects the operation of related components in electronic devices. Summary of the Invention

[0007] The technical problem solved by this invention is that charge pumps generate strong electromagnetic interference during energy transfer.

[0008] To address the aforementioned technical problems, embodiments of the present invention provide a control circuit for reducing electromagnetic interference, comprising: a bias unit; a drive unit; a plurality of switching transistors; and a flying capacitor; the drive unit is coupled to the bias unit; the first terminals of the plurality of switching transistors are connected to the flying capacitor; the bias unit is adapted to generate a bias voltage or a bias current; the drive unit is adapted to receive a control signal, a bias voltage or a bias current, and output a first voltage, wherein the first voltage is used to control the opening or closing of the plurality of switching transistors; the second terminals of some of the plurality of switching transistors are adapted to input a second voltage; and the second terminal of at least one of the plurality of switching transistors is adapted to output a third voltage.

[0009] Optionally, the bias unit includes at least one bias unit, and the drive unit includes multiple drive units, wherein at least one bias unit provides a bias voltage or bias current to the multiple drive units.

[0010] Optionally, the bias voltage or bias current can be continuously and / or discretely adjusted.

[0011] Optionally, the bias unit includes at least one switch, the input of which receives control voltage or control current, and the output of which is connected to the drive unit.

[0012] Optionally, the rate of change of the first voltage during its rise or fall is controllable.

[0013] Optionally, the rate of change of voltage across the flying capacitor can be controlled by multiple switching transistors.

[0014] Optionally, the drive unit includes multiple drive units, each of which drives at least one switching transistor.

[0015] Optionally, at least one of the multiple driving units includes a first PMOS transistor, a first NMOS transistor, a first variable current source, a second variable current source, an input terminal, and an output terminal; the input terminal is used to receive a control signal; and the output terminal is used to output a first voltage.

[0016] Optionally, the gates of both the first PMOS transistor and the first NMOS transistor are connected to the input terminal to receive the control signal, and the drains of both are connected to the output terminal to output the first voltage. The source of the first PMOS transistor is connected to the power supply voltage through a first variable current source, and the source of the first NMOS transistor is connected to ground through a second variable current source.

[0017] Optionally, the bias unit provides a bias voltage to at least one drive unit, the bias voltage including a first bias voltage and a second bias voltage provided to a first variable current source and a second variable current source, respectively; wherein at least one of the first bias voltage and the second bias voltage can be continuously adjusted.

[0018] Optionally, the bias unit provides a bias voltage to each drive unit, the bias voltage including a first bias voltage and a second bias voltage provided to a first variable current source and a second variable current source respectively to each drive unit; wherein, at least one of the first bias voltages can be continuously adjusted, and at least one of the second bias voltages can be continuously adjusted.

[0019] Optionally, the bias unit includes a low-dropout linear regulator, whose input receives an adjustable control voltage and whose output is connected to a first variable current source or a second variable current source.

[0020] Optionally, the bias unit includes a first low-dropout linear regulator and a second low-dropout linear regulator. The input terminal of the first low-dropout linear regulator receives an adjustable first control voltage, and the output terminal is connected to a first variable current source of the drive unit. The input terminal of the second low-dropout linear regulator receives an adjustable second control voltage, and the output terminal is connected to a second variable current source.

[0021] Optionally, the low dropout linear regulator includes an operational amplifier, a first resistor, and a second resistor, wherein the non-inverting input of the operational amplifier receives an adjustable control voltage, the inverting input is connected to the second terminal of the first resistor and the first terminal of the second resistor, the first terminal of the first resistor is connected to the output terminal of the operational amplifier for providing a bias voltage, and the second terminal of the second resistor is grounded.

[0022] Optionally, the low dropout linear regulator includes an operational amplifier, a first resistor, a second resistor, a first switch, and a second switch. The non-inverting input of the operational amplifier receives an adjustable control voltage, and the inverting input is connected to the second terminal of the first resistor and the first terminal of the second resistor. The first terminal of the first resistor is connected to the output terminal of the operational amplifier for providing a bias voltage. The second terminal of the second resistor is grounded. The first terminal of the first switch is connected to the power supply voltage, and the second terminal is connected to the output terminal of the operational amplifier. The first terminal of the second switch is connected to the output terminal of the operational amplifier, and the second terminal is connected to ground.

[0023] Optionally, the bias unit provides a bias current to at least one drive unit. The bias current includes a first bias current and a second bias current provided to a first variable current source and a second variable current source, respectively, to the drive unit. At least one of the first bias current and the second bias current can be continuously adjusted.

[0024] Optionally, the bias unit provides a bias current to each drive unit. The bias current includes a first bias current and a second bias current provided to a first variable current source and a second variable current source, respectively, to each drive unit. At least one of the first bias currents and at least one of the second bias currents are continuously adjustable.

[0025] Optionally, the control current supplied to the bias unit is regulated by a current mirror.

[0026] Optionally, the bias unit includes a MOSFET, whose input receives an adjustable control current and whose output is connected to a first variable current source or a second variable current source.

[0027] Optionally, the bias unit includes a second PMOS transistor and a second NMOS transistor. The input terminal of the second PMOS transistor receives an adjustable first control current, and its output terminal is connected to a first variable current source. The input terminal of the second NMOS transistor receives an adjustable second control current, and its output terminal is connected to a second variable current source.

[0028] This invention also provides a method for reducing electromagnetic interference in the aforementioned control circuit, comprising: receiving a bias voltage or bias current; receiving a control signal; receiving a second voltage; and outputting a third voltage based on the control signal, the bias voltage or bias current, and the second voltage.

[0029] Optionally, outputting a third voltage based on a control signal, a bias voltage or a bias current, and a second voltage includes: determining a first voltage based on the control signal, the bias voltage or the bias current; controlling the opening or closing time of a plurality of switching transistors based on the first voltage; controlling the rate of change of voltage across the flying capacitor based on the opening or closing time of the plurality of switching transistors and the second voltage; and outputting a third voltage.

[0030] Compared with the prior art, the technical solution of the present invention can reduce the electromagnetic interference generated by the flying capacitor during charging and discharging, and reduce the area of ​​the control circuit without affecting the driving capability of the charge pump. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the structure of a boost unit in the prior art;

[0032] Figure 2 This is a schematic diagram of the control circuit in an embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of the drive unit in an embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of the control circuit including a voltage-controlled bias unit in an embodiment of the present invention;

[0035] Figure 5 This is a schematic diagram of the control circuit including a current-controlled bias unit in an embodiment of the present invention;

[0036] Figure 6 This is a schematic diagram of the continuously adjustable bias unit in an embodiment of the present invention;

[0037] Figure 7 and 8 This is a schematic diagram of the discrete adjustable bias unit in an embodiment of the present invention, which shows the structure for generating bias signals BP and BN respectively;

[0038] Figure 9 This is a schematic diagram of the structure of continuous and discrete adjustable bias units in the embodiments of the present invention;

[0039] Figure 10 This is a flowchart of a method for reducing electromagnetic interference in an embodiment of the present invention. Detailed Implementation

[0040] The switching transistor of the charge pump or boost unit has a switching frequency fs. Within one cycle (1 / fs), the flying capacitor can complete one charging and discharging process. The voltage at the flying capacitor is ideally a square wave. According to formula (1), extremely large instantaneous current pulses will be generated at the rising and falling edges of the square wave, which will cause electromagnetic interference to related components in electronic devices.

[0041] I=C*dV / dt (1)

[0042] Where I, C, and V are the current, capacitance, and voltage parameters of the flying capacitor, respectively.

[0043] The spectrum of a transient current pulse is distributed at a frequency point of M*fs (where M is an integer greater than or equal to 1). For example, for a switching frequency fs with an operating range of 1kHz to 1MHz, the corresponding spectrum will generate strong electromagnetic interference to electronic equipment, especially components operating in the low-to-medium frequency range.

[0044] In embodiments of the present invention, the control circuit includes a bias unit and a drive unit. The bias unit can generate a bias voltage or a bias current, and the drive unit can receive a control signal, a bias voltage or a bias current, and output a first voltage for controlling the opening or closing of multiple switching transistors. The multiple switching transistors are connected to a flying capacitor, and the opening or closing of the multiple switching transistors (such as their opening or closing time Δt) can be controlled by changing the rate of change of the first voltage (e.g., the rising rate of change of voltage, the falling rate of change of voltage), so as to adjust the rate of change of voltage of the flying capacitor during charging or discharging (i.e., dV / dt), thereby selectively reducing the electromagnetic interference generated therefrom.

[0045] In embodiments of the present invention, the rate of change of voltage of the flying capacitor during charging or discharging can be reduced without reducing the size or number of switching transistors, which would reduce the electromagnetic interference generated by the flying capacitor. This is because such a method would reduce the driving capability of the switching transistors, resulting in a decrease in the output voltage of the charge pump. Instead, the rate of change of voltage of the flying capacitor during charging or discharging can be adjusted by a bias unit and a driving unit, thereby selectively reducing the electromagnetic interference generated therefrom. In this case, the size or number of switching transistors is not reduced, and therefore the driving capability of the switching transistors and the output voltage of the charge pump are not reduced.

[0046] In embodiments of the present invention, the rate of change of voltage of the flying capacitor during charging or discharging can be adjusted without driving each of the multiple switching transistors by multiple driving units. This can reduce the electromagnetic interference generated by the flying capacitor, because this method applies multiple driving units for each switching transistor, increasing the area of ​​the driving unit or driving circuit. Instead, the rate of change of voltage of the flying capacitor during charging or discharging can be adjusted by biasing units and driving units, thereby selectively reducing the electromagnetic interference generated by the flying capacitor. In this case, each driving unit drives at least one switching transistor, instead of multiple driving units driving one switching transistor, thereby reducing the number of driving units and thus reducing the area of ​​the control circuit.

[0047] In embodiments of the present invention, instead of providing multiple bias units to provide bias voltages or bias currents to multiple drive units respectively, only one bias unit may be provided, which provides bias voltages or bias currents to multiple drive units respectively, thereby reducing the number of bias units and thus reducing the area of ​​the control circuit.

[0048] In embodiments of the present invention, the bias voltage or bias current can be adjusted not only discretely but also continuously. Discretely adjusting the bias voltage or bias current allows for precise adjustment of the rate of voltage change of the flying capacitor during charging or discharging, thus avoiding both electromagnetic interference caused by a high rate of change and performance degradation caused by a low rate of change. Continuously adjusting the bias voltage or bias current also allows for precise adjustment of the rate of voltage change of the flying capacitor during charging or discharging, thus more effectively balancing the needs for reducing electromagnetic interference and preventing charge pump performance degradation. Specifically, during the charging or discharging process of the flying capacitor, the problem of strong electromagnetic interference caused by a large rate of voltage change is avoided, as is the problem of slow charging and discharging of the flying capacitor due to a low rate of voltage change, which leads to decreased charge pump performance.

[0049] In the specification of this invention, components with the same name have the same or similar functions, positional relationships, and connection relationships; signals with the same or similar markings have the same or similar functions, transmitting components, and receiving components.

[0050] To make the above-mentioned objectives, features and beneficial effects of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0051] Figure 2 The diagram illustrates a control circuit for reducing electromagnetic interference in an embodiment of the present invention. The control circuit 100 includes a bias unit 110, a drive unit 120, multiple switching transistors 130, and a flying capacitor 140.

[0052] The control circuit 100 can be installed inside the electronic device.

[0053] Specifically, the electronic device can be a device that includes a display panel (such as a liquid crystal display panel), for example, mobile terminal devices such as mobile phones, laptops, and tablets. The driver chip for the display panel may include a control circuit 100.

[0054] The bias unit 110 can generate a bias signal, which can be a bias voltage or a bias current; the drive unit 120 is coupled to the bias unit 110 to receive the bias signal, and the drive unit 120 can also receive a control signal.

[0055] The bias signal can change the bias operating point of the drive unit 120, thereby changing the driving capability of the boost unit of the charge pump (i.e., changing its output first voltage).

[0056] The bias signals may include bias signals BP and BN respectively provided to the PMOS and NMOS transistors in the drive unit 120. The drive unit 120 may include multiple drive units, such as... Figure 2 The diagram shows multiple driving units 1, ..., and multiple driving units N (N is an integer greater than or equal to 1). The bias signals may include bias signals BP1, BP2, ..., BPN provided to the PMOS transistors in each driving unit, and bias signals BN1, BN2, ..., BNN provided to the NMOS transistors in each driving unit.

[0057] In embodiments of the present invention, instead of providing bias signals to each driving unit in the driving unit 120 through multiple bias units, only one bias unit can be provided, which provides a bias voltage to each driving unit, thereby reducing the area of ​​the control circuit 100.

[0058] The first terminal of each of the multiple switching transistors 130 is connected to the flying capacitor 140. The second terminal of some of the switching transistors can be input with a second voltage, and the second terminal of at least one of the other switching transistors can output a third voltage. The rate of change of voltage across the flying capacitor 140 can be controlled by the multiple switching transistors 130, and the opening or closing of each of the multiple switching transistors 130 (such as the opening or closing time Δt) can be controlled by the first voltage output by the drive unit 120.

[0059] Each drive unit in drive unit 120 drives at least one switching transistor. For example... Figure 2 As shown, each driving unit can correspond to only one switching transistor. There can be multiple driving units 1, each driving unit 1's output voltage driving one switching transistor. For example, the output voltage of the first driving unit 1 can drive switching transistor M11, the output voltage of the second driving unit 1 can drive switching transistor M12, and the output voltages of multiple driving units 1 can drive switching transistors M11, ..., M1i (i is an integer greater than or equal to 1). There can also be multiple driving units N, each driving unit N's output voltage driving one switching transistor. For example, the output voltage of the first driving unit N can drive switching transistor MN1, the output voltage of the second driving unit N can drive switching transistor MN2, and the output voltages of multiple driving units N can drive switching transistors MN1, ..., MNj (j is an integer greater than or equal to 1).

[0060] In some embodiments, multiple switching transistors 130 and flying capacitors 140 can form a boost unit. For example, the boost unit may include switching transistors M11, M12, M21, M22, and flying capacitor 140. This boost unit requires two drive units 1 to drive switching transistors M11 and M12 respectively, and two drive units 2 to drive switching transistors M21 and M22 respectively. If multi-stage boosting is required, multiple boost units are needed, and a corresponding number of drive units 1, 2, ..., N need to be configured. The combination of multiple boost units can form a charge pump with a certain driving capability.

[0061] The opening or closing of each of the multiple switching transistors 130 (such as the opening or closing time Δt) can be controlled by the first voltage output by the drive unit 120.

[0062] During the charging process of the flying capacitor 140, some of the switching transistors can be turned on, so that the second voltage charges the flying capacitor 140; during the discharging process of the flying capacitor 140, some of the switching transistors and at least one switching transistor can be turned on, so that the second voltage and the flying capacitor 140 are connected in series to output a third voltage.

[0063] Figure 3The diagram illustrates one of the drive units in drive unit 120. Drive units 200 and 250 include a first variable current source 201, a second variable current source 202, a first PMOS transistor 203, a first NMOS transistor 204, input terminals VIN, VIN1, and VIN2, and an output terminal VOUT. The first variable current source 201 and the second variable current source 202 are adjusted by bias signals BP and BN, respectively. The input terminal VIN is used to receive control signals, and the output terminal VOUT is used to output a first voltage.

[0064] In some embodiments, such as child Figure 3 As shown in Figure a, the gates of the first PMOS transistor 203 and the first NMOS transistor 204 can both be connected to the input terminal VIN.

[0065] In other embodiments, such as sub Figure 3 As shown in Figure b, the gates of the first PMOS transistor 203 and the first NMOS transistor 204 can be connected to the first input terminal VIN1 and the second input terminal VIN2, respectively.

[0066] The gates of the first PMOS transistor 201 and the first NMOS transistor 202 are both connected to the input terminal VIN to receive control signals, and their drains are both connected to the output terminal VOUT to output the first voltage. Their sources are connected to the power supply voltage VDD and ground respectively through the first variable current source 201 and the second variable current source 202.

[0067] In practical implementation, the rate of change of the first voltage can be changed by continuously or discretely adjusting the control signal or bias signal (e.g., reducing the rising slope and / or falling slope of the first voltage) to control the opening or closing of the switching transistor (e.g., the opening or closing time Δt), thereby adjusting the rate of change of the voltage of the flying capacitor during charging or discharging (e.g., reducing the rate of change of voltage dV / dt), and thus reducing the electromagnetic interference generated by the flying capacitor.

[0068] Discretely adjusting the bias signal can mean discretely adjusting the bias voltage, so that each bias voltage is 1, 2, ..., 2 times a certain voltage. K The multiple can also be used to discretely adjust the bias current, so that each bias current is 1, 2, ..., 2 times a certain current. K The multiple; where K is an integer greater than 1.

[0069] Figure 4 A specific control circuit is illustrated. The control circuit 300 includes a voltage-controlled bias unit 310 and a drive unit 320, as well as multiple switching transistors and flying capacitors (not shown).

[0070] The bias unit 310 includes low dropout regulators (LDOs) 311 and 312, whose input terminals receive adjustable control voltages VBP and VBN, and whose output terminals provide bias signals BP and BN. The bias signals BP and BN are signals provided to the PMOS transistor and NMOS transistor in the drive unit 320, respectively, and the control voltages VBP and VBN are signals that adjust the bias signals BP and BN, respectively.

[0071] like Figure 4 As shown, the low dropout linear regulators 311 and 312 include operational amplifiers, whose non-inverting inputs receive adjustable control voltages VBP and VBN respectively, and whose inverting inputs are connected to the outputs of the operational amplifiers respectively. The outputs provide bias signals BP and BN.

[0072] The drive unit 320 includes a first variable current source 321 and a second variable current source 322, which can respectively... Figure 4 A schematic diagram of PMOS and NMOS transistors. (Compared to...) Figure 3 Similar to the first variable current source 201 and the second variable current source 202 shown, the first variable current source 321 and the second variable current source 322 each receive a bias signal.

[0073] Specifically, the first variable current source 321 and the second variable current source 322 are connected to the output terminals of the low dropout linear regulators 311 and 312 to receive bias signals BP and BN.

[0074] exist Figure 4 In the example, the control voltages VBP and VBN include a first control voltage VBP and a second control voltage VBN; the bias signal is a bias voltage, which includes a first bias voltage BP and a second bias voltage BN respectively provided to the first variable current source 321 and the second variable current source 322.

[0075] In a specific implementation, the bias unit 310 includes a first low-dropout linear regulator 311 and a second low-dropout linear regulator 312. The input terminal of the first low-dropout linear regulator 311 receives an adjustable first control voltage VBP, and the output terminal is connected to the first variable current source 321 of the drive unit to output a first bias voltage BP. The input terminal of the second low-dropout linear regulator 312 receives an adjustable second control voltage VBN, and the output terminal is connected to the second variable current source 322 to output a second bias voltage BN.

[0076] The bias unit 310 can provide a bias voltage to at least one of a plurality of drive units. For example... Figure 4 As shown, the bias voltage includes a first bias voltage BP and a second bias voltage BN provided to the first variable current source 321 and the second variable current source 322, respectively.

[0077] The bias unit 310 can, for example, continuously adjust one of the first bias voltage BP and the second bias voltage VBN by continuously changing at least one of the first control voltage VBP and the second control voltage VBN. This allows the rate of change of the first voltage output by the drive unit 320 to be adjusted. For example, by reducing the rising slope and / or falling slope of the first voltage to control the opening or closing of the switch (such as its opening or closing time Δt), the rate of change of the flying capacitor voltage during charging or discharging can be adjusted (such as reducing the rate of change of voltage dV / dt), thereby reducing the electromagnetic interference generated by the flying capacitor.

[0078] The bias unit 310 can also provide a bias voltage to each of the plurality of drive units. The bias voltage includes a plurality of first bias voltages BP and a plurality of second bias voltages BN provided to the first variable current source and the second variable current source in each drive unit, respectively.

[0079] The bias unit 310 can, for example, continuously change at least one of a plurality of first control voltages VBP and at least one of a plurality of second control voltages VBN, so that a corresponding one of the plurality of first bias voltages BP and a corresponding one of the plurality of second bias voltages VBN can be continuously adjusted. This allows the rate of change of the first voltage output by the drive unit 320 to be adjusted, for example, by reducing the rising slope and / or falling slope of the first voltage to control the opening or closing of the switch (such as its opening or closing time Δt), thereby adjusting the rate of change of the voltage of the flying capacitor during charging or discharging (such as reducing the rate of change of voltage dV / dt), and thus reducing the electromagnetic interference generated by the flying capacitor.

[0080] One or more of the control voltages VBP and VBN can be used not only to adjust the bias voltages BP and BN, but also to adjust the slew rate (SR) of the operational amplifiers in the low dropout linear regulators 311 and 312 to meet specific operating requirements.

[0081] Figure 5 Another specific control circuit is illustrated. The control circuit 400 includes a current-controlled bias unit 410 and a drive unit 420, as well as multiple switching transistors and flying capacitors (not shown).

[0082] The bias unit 410 includes MOS transistors 411 and 412, whose input terminals receive adjustable control currents IBP and IBN, and whose output terminals provide bias signals BP and BN; wherein, the bias signals BP and BN are signals provided to the PMOS transistor and NMOS transistor in the drive unit 420 respectively, and the control currents IBP and IBN are signals that adjust the bias signals BP and BN respectively.

[0083] The drive unit 420 includes a first variable current source 421 and a second variable current source 422, such as Figure 5 The PMOS and NMOS transistors within the drive unit 420 are shown. (And...) Figure 3 Similar to the first variable current source 201 and the second variable current source 202 shown, the first variable current source 421 and the second variable current source 422 each receive a bias signal.

[0084] Specifically, the first variable current source 421 and the second variable current source 422 are both connected to the output terminals (gate terminals) of MOS transistors 411 and 412 to receive bias signals BP and BN.

[0085] exist Figure 5 In the embodiments, the control currents IBP and IBN are control currents, which include a first control current IBP and a second control current IBN; the bias signal is a bias current, which includes a first bias current BP and a second bias current BN respectively provided to the first variable current source 421 and the second variable current source 422.

[0086] In practice, the control currents IBP and IBN can be adjusted by a current mirror. For example, the output control currents IBP and IBN can be adjusted by the input current of the current mirror.

[0087] In a specific implementation, the bias unit 410 includes a PMOS transistor 411 and an NMOS transistor 412. The input terminal of the PMOS transistor 411 receives an adjustable first control current IBP, and the output terminal is connected to the first variable current source 421 to output the first bias current BP. The input terminal of the NMOS transistor 412 receives an adjustable second control current IBN, and the output terminal is connected to the second variable current source 422 to output the second bias current BN.

[0088] The bias unit 410 can provide bias current to at least one of the multiple drive units. For example... Figure 5 As shown, the bias current includes a first bias current BP and a second bias current BN provided to the first variable current source 421 and the second variable current source 422, respectively.

[0089] The bias unit 410 can, for example, continuously adjust the corresponding one of the first bias current BP and the second bias current BN by continuously changing at least one of the first control current IBP and the second control current IBN. This allows the rate of change of the first voltage output by the drive unit 420 to be adjusted, for example, by reducing the rising slope and / or falling slope of the first voltage to control the opening or closing of the switch (such as its opening or closing time Δt), thereby adjusting the rate of change of the voltage of the flying capacitor during charging or discharging (such as reducing the rate of change of voltage dV / dt), and thus reducing the electromagnetic interference generated by the flying capacitor.

[0090] The bias unit 410 can also provide a bias current to each of the plurality of drive units. The bias current includes a plurality of first bias currents BP and a plurality of second bias currents BN provided to a first variable current source and a second variable current source in each drive unit, respectively.

[0091] The bias unit 410 can, for example, continuously change at least one of a plurality of first control currents IBP and at least one of a plurality of second control currents IBN, so that a corresponding one of the plurality of first bias currents BP and a corresponding one of the plurality of second bias currents BN can be continuously adjusted, thereby making the rate of change of the first voltage output by the drive unit 420 adjustable. For example, by reducing the rising slope and / or falling slope of the first voltage to control the opening or closing of the switch (such as its opening or closing time Δt), the rate of change of the voltage of the flying capacitor during charging or discharging can be adjusted (such as reducing the rate of change of voltage dV / dt), thereby reducing the electromagnetic interference generated by the flying capacitor.

[0092] The following description is based on specific embodiments.

[0093] In the first embodiment, as Figure 6 As shown, the bias unit 500 includes a low dropout linear regulator, which includes an operational amplifier 510, a first resistor (R1) 521 and a second resistor (R2) 522.

[0094] The operational amplifier 510 can be of type A, B or AB. Its non-inverting input receives adjustable control voltages VBP and VBN, and its inverting input is connected to the second terminal of the first resistor 521 and the first terminal of the second resistor 522. The first terminal of the first resistor 521 is connected to the output terminal of the operational amplifier 510, which provides bias voltages BP and BN. The second terminal of the second resistor 522 is grounded.

[0095] The bias voltages BP and BN can be calculated using the following formulas:

[0096] BP=VBP*(1+R1 / R2) (2)

[0097] BN=VBN*(1+R1 / R2) (3)

[0098] According to formula (2), the bias voltage BP can be continuously adjusted by any combination of the control voltage VBP, the first resistor 521 and the second resistor 522.

[0099] Similarly, according to formula (3), the bias voltage BN can be continuously adjusted by any combination of the control voltage VBN, the first resistor 521 and the second resistor 522.

[0100] By continuously adjusting the bias voltages BP and BN, the rate of change of the first voltage output by the drive unit can be adjusted. For example, by reducing the rising slope and / or falling slope of the first voltage, the switching transistor can be controlled to open or close (e.g., its opening or closing time Δt). This allows adjustment of the rate of change of the flying capacitor's voltage during charging or discharging (e.g., reducing the rate of change of voltage dV / dt), thereby reducing the electromagnetic interference generated by the flying capacitor.

[0101] By continuously adjusting the bias voltages BP and BN, the rate of change of the flying capacitor's voltage during charging or discharging can be precisely adjusted. This allows for a more effective balance between reducing electromagnetic interference and minimizing charge pump performance. In other words, during the charging or discharging process of the flying capacitor, the problem of strong electromagnetic interference caused by a large rate of change of the flying capacitor's voltage is avoided, as is the problem of slow charging and discharging of the flying capacitor due to a small rate of change of the voltage, which leads to a decrease in charge pump performance.

[0102] In the second embodiment, as Figure 7 and 8 As shown, the bias unit 600 includes at least one switch, whose input terminal receives control voltage or control current and whose output terminal is connected to the drive unit.

[0103] The bias unit 600 can be a voltage-controlled bias unit.

[0104] The bias unit 600 may include at least one switch SW11, SW21, ..., SWN1. The input terminals of these switches may receive control voltages VBP_1, VBP_2, ..., VBP_N respectively. The closing and opening of these switches may be controlled by a timing control circuit or a digital register, so that one switch is closed while the others are open, thereby providing the control voltage to the output terminal as the bias voltage BP of the PMOS transistor in the drive unit.

[0105] Among them, the control voltages VBP_1, VBP_2, ..., VBP_N can be 1, 2, ..., 2 of a certain voltage. K The bias voltage BP can be adjusted discretely by multiples of K (where K is an integer greater than 1).

[0106] The bias unit 600 also includes at least one switch SW12, SW22, ..., SWN2. The input terminals of these switches can receive control voltages VBN_1, VBN_2, ..., VBN_N respectively. The closing and opening of these switches can be controlled by a timing control circuit or a digital register, so that one switch is closed while the others are open, thereby providing the control voltage to the output terminal as the bias voltage BN of the NMOS transistor in the drive unit.

[0107] Wherein, the control voltages VBN_1, VBN_2, ..., VBN_N can be 1, 2, ..., 2 of a certain voltage. K The bias voltage BN can be discretely adjusted by multiples of K (where K is an integer greater than 1).

[0108] Since the control voltages VBP_1, VBP_2, ..., VBP_N can be unequal to each other, the bias voltage BP can be discretely adjusted; since the control voltages VBN_1, VBN_2, ..., VBN_N can be unequal to each other, the bias voltage BN can be discretely adjusted.

[0109] The bias unit 600 can also be a current-controlled bias unit.

[0110] The bias unit 600 includes at least one switch SW11, SW21, ..., SWN1. The input terminals of these switches can receive control currents IBP_1, IBP_2, ..., IBP_N respectively. The closing and opening of these switches can be controlled by a timing control circuit or a digital register, so that one switch is closed while the others are open, thereby providing the control current to the output terminal as the bias current BP of the PMOS transistor in the drive unit.

[0111] Wherein, the control currents IBP_1, IBP_2, ..., IBP_N can be 1, 2, ..., 2 of a certain current. K The bias current BP can be discretely adjusted by multiples of K (where K is an integer greater than 1).

[0112] The bias unit 600 also includes at least one switch SW12, SW22, ..., SWN2. The input terminals of these switches can receive control currents IBN_1, IBN_2, ..., IBN_N respectively. The closing and opening of these switches can be controlled by a timing control circuit or a digital register, so that one switch is closed while the others are open, thereby providing the control current to the output terminal as the bias current BN of the NMOS transistor in the drive unit.

[0113] Wherein, the control currents IBN_1, IBN_2, ..., IBN_N can be 1, 2, ..., 2 of a certain current. K The bias current BN can be discretely adjusted by multiples of K (where K is an integer greater than 1).

[0114] Since the control currents IBP_1, IBP_2, ..., IBP_N can be unequal to each other, the bias current BP can be discretely adjusted; since the control currents IBN_1, IBN_2, ..., IBN_N can be unequal to each other, the bias current BN can be discretely adjusted.

[0115] By discretely adjusting the bias voltage or bias current BP and BN, the rate of change of the first voltage output by the drive unit can be adjusted. For example, by reducing the rising slope and / or falling slope of the first voltage, the switching transistor can be controlled to open or close (e.g., its opening or closing time Δt). This allows adjustment of the rate of change of the flying capacitor's voltage during charging or discharging (e.g., reducing the rate of change of voltage dV / dt), thereby reducing the electromagnetic interference generated by the flying capacitor.

[0116] In the third embodiment, as Figure 9 As shown, the bias unit 700 includes a low dropout linear regulator, which includes an operational amplifier 710, a first resistor (R1) 711 and a second resistor (R2) 712, a first switch 721 and a second switch 722.

[0117] The operational amplifier 710 can be of type A, B or AB. Its non-inverting input receives adjustable control voltages VBP and VBN, and its inverting input is connected to the second terminal of the first resistor 711 and the first terminal of the second resistor 712. The first terminal of the first resistor 711 is connected to the output terminal of the operational amplifier 710, which provides bias voltages BP and BN. The second terminal of the second resistor 712 is grounded.

[0118] The first terminal of the first switch 721 is connected to the power supply voltage VDD, and the second terminal is connected to the output terminal of the operational amplifier 710. The first terminal of the second switch 722 is connected to the output terminal of the operational amplifier 710, and the second terminal is connected to ground.

[0119] In scenario one, both the first switch 721 and the second switch 722 are open. The bias voltages BP and BN can then be calculated using the following formulas:

[0120] BP=VBP*(1+R1 / R2) (4)

[0121] BN=VBN*(1+R1 / R2) (5)

[0122] According to formula (4), the bias voltage BP can be continuously adjusted by any combination of the control voltage VBP, the first resistor 711, and the second resistor 712.

[0123] Similarly, according to formula (5), the bias voltage BN can be continuously adjusted by any combination of the control voltage VBN, the first resistor 711, and the second resistor 712.

[0124] In scenario two, when the first switch 721 is closed and the second switch 722 is open, the bias voltages BP and BN are connected to the power supply voltage VDD, and their magnitude is VDD.

[0125] In scenario three, when the first switch 721 is open and the second switch 722 is closed, the bias voltages BP and BN are connected to ground and their magnitude is zero.

[0126] Depending on cases one through three, the bias voltages BP and BN can be discretely adjusted to VDD, zero, and the voltage calculated as in formulas (4) and (5).

[0127] By discretely adjusting the bias voltages BP and BN, the rate of change of the first voltage output by the drive unit can be adjusted. For example, by reducing the rising slope and / or falling slope of the first voltage, the switching transistor can be controlled to open or close (e.g., its opening or closing time Δt). This allows adjustment of the rate of change of the flying capacitor's voltage during charging or discharging (e.g., reducing the rate of change of voltage dV / dt), thereby reducing the electromagnetic interference generated by the flying capacitor.

[0128] According to Case 1, the bias voltages BP and BN can be continuously adjusted as calculated by formulas (4) and (5).

[0129] By continuously adjusting the bias voltages BP and BN, the rate of change of the first voltage output by the drive unit can be adjusted. For example, by reducing the rising slope and / or falling slope of the first voltage, the switching transistor can be controlled to open or close (e.g., its opening or closing time Δt). This allows adjustment of the rate of change of the flying capacitor's voltage during charging or discharging (e.g., reducing the rate of change of voltage dV / dt), thereby reducing the electromagnetic interference generated by the flying capacitor.

[0130] By continuously adjusting the bias voltages BP and BN, the rate of change of the flying capacitor's voltage during charging or discharging can be precisely adjusted. This allows for a more effective balance between reducing electromagnetic interference and minimizing charge pump performance. In other words, during the charging or discharging process of the flying capacitor, the problem of strong electromagnetic interference caused by a large rate of change of the flying capacitor's voltage is avoided, as is the problem of slow charging and discharging of the flying capacitor due to a small rate of change of the voltage, which leads to a decrease in charge pump performance.

[0131] Although only two switches 721 and 722, respectively connected to the power supply voltage VDD and ground, are shown in the third embodiment, it should be understood that in other embodiments, multiple switches respectively connected to different voltages may also be included.

[0132] Specifically, when all these switches are open, the bias voltages BP and BN can be calculated using formulas (4) and (5), thereby achieving continuous adjustment of the bias voltages BP and BN; when one of these switches is closed and the others are open, the bias voltages BP and BN are equal to the voltage connected to that switch, thereby achieving discrete adjustment of the bias voltages BP and BN.

[0133] Figure 10 This is a flowchart of a method for reducing electromagnetic interference according to an embodiment of the present invention. Method 800 includes:

[0134] Step 810: Receive bias voltage or bias current;

[0135] Step 820: Receive control signals;

[0136] Step 830: Receive the second voltage;

[0137] Step 840: Based on the control signal, bias voltage or bias current, and the second voltage, output the third voltage.

[0138] During the execution of step 810, the drive unit may receive a bias voltage or bias current generated by the bias unit.

[0139] In a specific implementation, the driving unit may include a first variable current source and a second variable current source, which respectively receive a bias voltage or a bias current.

[0140] During the execution of step 820, the drive unit may receive control signals.

[0141] In a specific implementation, the drive unit may include an input terminal that receives control signals.

[0142] During the execution of step 830, some of the multiple switching transistors may receive a second voltage.

[0143] In practice, during the charging process of the flying capacitor, some switching transistors can be turned on to charge the flying capacitor with the second voltage; during the discharging process of the flying capacitor, some switching transistors and at least one switching transistor can be turned on to connect the second voltage and the flying capacitor 140 in series to provide the output voltage to the output terminal.

[0144] During the execution of step 840, the drive unit may output a first voltage based on the control signal, bias voltage or bias current it receives, wherein the first voltage is used to control the opening or closing of a plurality of switching transistors (such as the opening or closing time Δt); some of the switching transistors input a second voltage, and at least one of the switching transistors may output a third voltage based on the first voltage and the second voltage.

[0145] In practical implementation, the opening or closing time of multiple switching transistors can be controlled based on the first voltage, and the rate of change of voltage on the flying capacitor can be controlled based on the opening or closing time of multiple switching transistors and the second voltage to output a third voltage.

[0146] In practical implementation, the rate of change of the first voltage can be changed (e.g., reducing the rising slope and / or falling slope of the first voltage) to control the opening or closing of multiple switching transistors, thereby adjusting the rate of change of the voltage of the flying capacitor during charging or discharging (e.g., reducing the rate of change of voltage dV / dt), and thus reducing the electromagnetic interference generated by the flying capacitor.

[0147] The method for reducing electromagnetic interference in the embodiments of the present invention can be based on the above combination. Figures 2 to 9 The method is implemented using the control circuit described above. Therefore, the execution of each step in the method and the relationship between them can be referred to the above description of the control circuit, and will not be repeated here.

[0148] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A control circuit for reducing electromagnetic interference, characterized in that, include: Bias unit; Drive unit; Multiple switching transistors; And flying capacitors; The driving unit is coupled to the biasing unit; The first terminal of the plurality of switching transistors is connected to the flying capacitor; The biasing unit is adapted to generate a bias voltage or a bias current; The bias voltage or the bias current can be continuously adjusted and / or discretely adjusted; The driving unit is adapted to receive a control signal, the bias voltage or the bias current, and output a first voltage, wherein the first voltage is input to the gate of the plurality of switching transistors to control the opening or closing of the plurality of switching transistors; the driving unit changes the voltage change rate of the first voltage based on the bias current or the bias current, wherein the voltage change rate of the first voltage includes an increasing voltage change rate or a decreasing voltage change rate; The second terminal of some of the plurality of switching transistors is adapted to receive a second voltage; The second terminal of at least one of the plurality of switching transistors is adapted to output a third voltage.

2. The control circuit according to claim 1, characterized in that, The bias unit includes at least one bias unit, and the drive unit includes multiple drive units. The at least one bias unit provides the bias voltage or the bias current to the multiple drive units.

3. The control circuit according to claim 1, characterized in that, The biasing unit includes at least one switch, the input of which receives control voltage or control current, and the output of which is connected to the driving unit.

4. The control circuit according to claim 1, characterized in that, The rate of change of voltage acting on the flying capacitor can be controlled by the plurality of switching transistors.

5. The control circuit according to claim 1, characterized in that, The driving unit includes multiple driving units, and each of the multiple driving units drives at least one switching transistor.

6. The control circuit according to claim 5, characterized in that, At least one of the plurality of driving units includes a first PMOS transistor, a first NMOS transistor, a first variable current source, a second variable current source, an input terminal, and an output terminal; the input terminal is used to receive the control signal; and the output terminal is used to output the first voltage.

7. The control circuit according to claim 6, characterized in that, The gates of both the first PMOS transistor and the first NMOS transistor are connected to the input terminal to receive the control signal, and the drains of both are connected to the output terminal to output the first voltage. The source of the first PMOS transistor is connected to the power supply voltage through the first variable current source, and the source of the first NMOS transistor is connected to ground through the second variable current source.

8. The control circuit according to claim 6, characterized in that, The bias unit provides the bias voltage to the at least one drive unit, the bias voltage including a first bias voltage and a second bias voltage provided to the first variable current source and the second variable current source respectively; wherein, at least one of the first bias voltage and the second bias voltage is continuously adjustable.

9. The control circuit according to claim 8, characterized in that, The bias unit provides the bias voltage to each of the driving units respectively. The bias voltage includes the first bias voltage and the second bias voltage provided to the first variable current source and the second variable current source of each driving unit respectively. Among them, at least one of the first bias voltages and at least one of the second bias voltages can be continuously adjusted.

10. The control circuit according to claim 8, characterized in that, The bias unit includes a low-dropout linear regulator, whose input receives an adjustable control voltage and whose output is connected to either the first variable current source or the second variable current source.

11. The control circuit according to claim 8, characterized in that, The bias unit includes a first low-dropout linear regulator and a second low-dropout linear regulator. The input terminal of the first low-dropout linear regulator receives an adjustable first control voltage, and the output terminal is connected to the first variable current source of the drive unit. The input terminal of the second low-dropout linear regulator receives an adjustable second control voltage, and the output terminal is connected to the second variable current source.

12. The control circuit according to claim 10, characterized in that, The low dropout linear regulator includes an operational amplifier, a first resistor, and a second resistor. The non-inverting input of the operational amplifier receives an adjustable control voltage, and the inverting input is connected to the second terminal of the first resistor and the first terminal of the second resistor. The first terminal of the first resistor is connected to the output terminal of the operational amplifier, which provides the bias voltage. The second terminal of the second resistor is grounded.

13. The control circuit according to claim 10, characterized in that, The low-dropout linear regulator includes an operational amplifier, a first resistor, a second resistor, a first switch, and a second switch. The non-inverting input of the operational amplifier receives an adjustable control voltage, and the inverting input is connected to the second terminal of the first resistor and the first terminal of the second resistor. The first terminal of the first resistor is connected to the output terminal of the operational amplifier for providing the bias voltage. The second terminal of the second resistor is grounded. The first terminal of the first switch is connected to the power supply voltage, and the second terminal is connected to the output terminal of the operational amplifier. The first terminal of the second switch is connected to the output terminal of the operational amplifier, and the second terminal is connected to ground.

14. The control circuit according to claim 6, characterized in that, The bias unit provides the bias current to the at least one drive unit. The bias current includes a first bias current and a second bias current provided to the first variable current source and the second variable current source of the drive unit, respectively, wherein at least one of the first bias current and the second bias current can be continuously adjusted.

15. The control circuit according to claim 14, characterized in that, The bias unit provides the bias current to each drive unit respectively. The bias current includes the first bias current and the second bias current provided to the first variable current source and the second variable current source of each drive unit respectively. At least one of the first bias currents and at least one of the second bias currents can be continuously adjusted.

16. The control circuit according to claim 14, characterized in that, The control current supplied to the bias unit is regulated by a current mirror.

17. The control circuit according to claim 14, characterized in that, The bias unit includes a MOS transistor, whose input terminal receives an adjustable control current and whose output terminal is connected to the first variable current source or the second variable current source.

18. The control circuit according to claim 14, characterized in that, The bias unit includes a second PMOS transistor and a second NMOS transistor. The input terminal of the second PMOS transistor receives an adjustable first control current, and its output terminal is connected to the first variable current source. The input terminal of the second NMOS transistor receives an adjustable second control current, and its output terminal is connected to the second variable current source.

19. A method for reducing electromagnetic interference using a control circuit as described in any one of claims 1 to 18, characterized in that, include: Receive the bias voltage or the bias current; Receive the control signal; Receive the second voltage; Outputting the third voltage based on the control signal, the bias voltage or the bias current, and the second voltage includes: determining the first voltage based on the control signal, the bias voltage or the bias current; controlling the opening or closing time of the plurality of switching transistors based on the first voltage; controlling the rate of change of the voltage on the flying capacitor based on the opening or closing time of the plurality of switching transistors and the second voltage; and outputting the third voltage. The bias voltage or the bias current can be continuously adjusted and / or discretely adjusted; the voltage change rate of the first voltage is based on the change of the bias voltage or the bias current, and the voltage change rate of the first voltage includes an increasing voltage change rate or a decreasing voltage change rate.

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