Crystal Oscillators and Their Phase Noise Reduction Methods

Abstract

A crystal oscillator and a method for reducing phase noise are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit, and a phase noise reduction circuit. The first bias circuit is coupled to the output of the crystal oscillator core circuit, and the phase noise reduction circuit is also coupled to the output of the crystal oscillator core circuit. In operation, the crystal oscillator core circuit is configured to generate a sine wave. The first bias circuit is configured to provide a first voltage level as a bias voltage for the sine wave. The phase noise reduction circuit is configured to reset the bias voltage of the sine wave in response to the voltage level of the sine wave exceeding a specific voltage range. Using this method, the phase noise of the crystal oscillator can be reduced.

Description

Technical Field

[0001] This invention relates to crystal oscillators, and more particularly to crystal oscillators and methods for reducing phase noise of the same. Background Technology

[0002] For electronic systems such as phase-locked loops (PLLs), a reference clock is required. More specifically, the phase noise of the reference clock significantly affects the overall performance of the electronic system, thus requiring improvements in phase noise-related performance. Typically, the reference clock can be generated by a crystal oscillator such as a Pierce oscillator or a Colpitts oscillator. Methods and architectures proposed in related fields significantly increase the amount of additional circuitry required to improve the overall performance of the crystal oscillator (e.g., reduce the phase noise of the crystal oscillator). Therefore, a novel architecture and related approach are needed to reduce the phase noise of the crystal oscillator (more specifically, reduce the phase noise of the reference clock) without introducing any side effects or in a manner unlikely to produce side effects. Summary of the Invention

[0003] In view of this, the object of the present invention is to provide a crystal oscillator and a method for reducing the phase noise of the oscillator, so as to improve the phase noise-related performance of an electronic system, and more specifically, to reduce the phase noise of a reference clock output from a crystal oscillator of an electronic system.

[0004] At least one embodiment of the present invention provides a crystal oscillator. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit, and a phase noise reduction circuit, wherein the first bias circuit is coupled to the output of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output of the crystal oscillator core circuit. In operation of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level as a bias voltage for the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to the voltage level of the sinusoidal wave exceeding a specific voltage range. Optionally, resetting the bias voltage of the sinusoidal wave may involve resetting the bias voltage of the sinusoidal wave to the first voltage level or resetting the bias voltage of the sinusoidal wave to a non-first voltage level.

[0005] At least one embodiment of the present invention provides a method for reducing phase noise of a crystal oscillator. The phase noise reduction method may include: generating a sine wave through a crystal oscillator core circuit of the crystal oscillator; providing a first voltage level as a bias voltage for the sine wave through a first bias circuit of the crystal oscillator; and resetting the bias voltage of the sine wave through the phase noise reduction circuit of the crystal oscillator in response to the voltage level of the sine wave exceeding a specific voltage range.

[0006] The crystal oscillator and phase noise reduction method of the present invention reduce the phase noise of the crystal oscillator by resetting the bias voltage of the sine wave in response to the voltage level of the sine wave exceeding a specific voltage range.

[0007] These and other objects of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the various accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a schematic diagram illustrating a crystal oscillator according to an embodiment of the present invention.

[0009] Figure 2 This is a schematic diagram illustrating how noise from the bias resistor is introduced into the square wave output of the square wave buffer.

[0010] Figure 3 This is a schematic diagram illustrating a crystal oscillator according to an embodiment of the present invention.

[0011] Figure 4 This is a schematic diagram illustrating phase noise reduction by means of a noise reset pulse according to an embodiment of the present invention.

[0012] Figure 5 This is a schematic diagram illustrating a crystal oscillator according to an embodiment of the present invention.

[0013] Figure 6 This is a schematic diagram showing the clamping of a sine wave between the upper bound level and the lower bound level.

[0014] Figure 7 An embodiment of the present invention is shown. Figure 5 The calibration workflow for some voltages is shown below.

[0015] Figure 8 This is a schematic diagram illustrating a crystal oscillator according to an embodiment of the present invention.

[0016] Figure 9 The workflow of a phase noise reduction method for a crystal oscillator according to an embodiment of the present invention is shown. Detailed Implementation

[0017] Certain terms are used throughout the following description and claims, referring to specific components. As those skilled in the art will understand, electronic device manufacturers may use different names to refer to components. This document is not intended to distinguish between components with different names but identical functions. In the following description and claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as meaning "including but not limited to...". Similarly, the term "coupled" is intended to indicate an indirect or direct electrical connection. Thus, if one device is coupled to another device, the connection can be a direct electrical connection or an indirect electrical connection via other devices and connections.

[0018] The crystal oscillator and phase noise reduction method of the present invention can reduce phase noise without requiring calibration of the specific timing of the phase noise removal operation, and can significantly reduce the total cost of achieving phase noise reduction compared to related technologies. Therefore, the present invention can reduce the phase noise of a crystal oscillator (more specifically, reduce the phase noise of a reference clock, such as the phase noise of a pulse wave output from the crystal oscillator) without causing any side effects or in a manner unlikely to produce side effects.

[0019] Figure 1 This is a schematic diagram illustrating a crystal oscillator 10 according to an embodiment of the present invention. The crystal oscillator 10 may include a crystal oscillator core circuit 120, a bias circuit such as a direct current (DC) bias circuit 140, a bias resistor Rbias, and a pulse wave buffer such as a square wave buffer 160 (labeled "NBUF" for simplicity). The crystal oscillator core circuit 120 may be as follows: Figure 1 The Colpitts oscillator shown includes a crystal tank XTAL (which may be referred to as a "crystal oscillator (XO)"), capacitors C1 and C2, a transistor, and a current source, but the invention is not limited thereto. For example, in some embodiments, the core circuitry 120 of the crystal oscillator can be replaced by a Pierce oscillator. In this embodiment, a DC bias circuit 140 is coupled to the output of the crystal oscillator 120 via a bias resistor Rbias, and a square wave buffer 160 is coupled to the output of the crystal oscillator 120. For example, the output of the crystal oscillator and the input of the square wave buffer 160 are coupled to a node of the crystal oscillator 10, and the DC bias circuit 140 is coupled to this node via a bias resistor Rbias, wherein the input impedance of this node can be represented by Zin, which is approximately determined by the bias resistor Rbias.

[0020] In this embodiment, the crystal oscillator core circuit 120 is designed to have a high quality factor (e.g., greater than or equal to 100,000) and is configured to generate a sine wave. The DC bias circuit 140 may include, for example... Figure 1 One or more transistors are shown. In Figure 1 In this configuration, the device is configured to provide a bias voltage for a sine wave, such as a DC bias voltage VB. For example, the sine wave is carried at the level of the DC bias voltage VB (more specifically, the sine wave can vary regularly up and down based on the level of the DC bias voltage VB). Additionally, a pulse wave buffer, such as a square wave buffer 160, can generate a pulse wave, such as a square wave, at the output terminal OUT of the square wave buffer 160 based on the sine wave. For example, the square wave buffer 160 may include an inverter or a series of inverters, wherein the square wave may have a first state (e.g., a first logic value such as "1") when the level of the sine wave is greater than a threshold value of the square wave buffer 160 (e.g., an input voltage level threshold), and a second state (e.g., a second logic value, such as "0") when the level of the sine wave is less than the threshold value of the square wave buffer 160. In some embodiments, the pulse wave generated by the pulse wave buffer may be a rectangular wave, such as a square wave, with a duty cycle equal to 50%. In some embodiments, the pulse wave generated by the pulse wave buffer can be a rectangular wave with a duty cycle other than 50%. The following description uses a square wave as an example only and does not imply any limitation on the invention.

[0021] In one embodiment, the bias resistor Rbias contributes a large portion of the phase noise of the square wave. Specifically, the noise contributed by the bias resistor Rbias is positively correlated with the resistance of the bias resistor Rbias. For example, the higher the resistance of the bias resistor Rbias, the higher the noise generated. The signal power of the sine wave is also positively correlated with the resistance of the bias resistor Rbias. For example, the higher the resistance of the bias resistor Rbias, the higher the signal power of the sine wave (i.e., the lower the resistance of the bias resistor Rbias, the greater the loss in the sine wave, and the lower the signal power; conversely, the higher the resistance of the bias resistor Rbias, the less the loss in the sine wave, and the higher the signal power). Therefore, there is a trade-off between loss and noise, and the present invention aims to overcome this trade-off.

[0022] In detail, because the quality factor of the crystal oscillator core circuit 120 is sufficiently high, the thermal noise from the bias resistor Rbias will not significantly affect the signal-to-noise ratio (SNR) of the sine wave at the output of the crystal oscillator core circuit 120. For example, the crystal oscillator core circuit 120 can filter out most of the noise caused by the bias resistor Rbias at a frequency offset (e.g., 100 kilo Hertz, kHz) relative to the oscillation frequency of the sine wave. Based on the above description, even if the bias resistor Rbias contributes noise, the phase noise of the sine wave is likely to be very small, for example, -185 dBc / Hz (-185 dBc / Hz relative to the carrier in a Hertz bandwidth). However, the phase noise at the output OUT of the square wave buffer may be higher (e.g., -165 dBc / Hz).

[0023] To better understand how the noise from the bias resistor Rbias is introduced into the square wave at the output terminal OUT of the square wave buffer 160, please refer to... Figure 2 If the bias resistor Rbias does not contribute noise, the sine wave can be carried at a constant level VB, as shown in the waveform labeled "XO Out1" (e.g., a 40 MHz sine wave might vary up and down based on a constant level VB), and the pulse width of the square wave can be constant, as shown in the waveform labeled "NBUF Out1". In contrast, if the bias resistor Rbias contributes noise (e.g., it can be modeled as a 100 kHz bias noise source), the sine wave can be carried at a varying level VB + ΔV, as shown in the waveform labeled "XO Out2" (e.g., a 40 MHz sine wave might vary up and down based on a time-varying level of 100 kHz bias noise). Due to the high quality factor of the crystal oscillator core circuit 120, the phase noise of the sine wave does not increase significantly when the noise of the bias resistor Rbias is taken into account. For square waves, the state transition times (e.g., rising and falling edges) can be significantly affected by changes in the voltage level at the input of the square wave buffer. The pulse width of the square wave may vary over time, as shown in the circled portion on the waveform labeled "NBUF Out2" (e.g., the time-varying phase shift Δt), which will generate phase noise at the output OUT of the square wave buffer 160. Figure 2As shown at the bottom, the waveform depicted by the thin line represents the output of the square wave buffer 160 without considering the noise of the bias resistor (with a constant pulse width), and the waveform depicted by the thick line represents the output of the square wave buffer 160 with considering the noise of the bias resistor (with a pulse width that varies with time). The difference between these two waveforms can be described by the phase shift Δt that varies with time, which can be regarded as the phase noise mentioned above.

[0024] Figure 3 This is a schematic diagram illustrating a crystal oscillator 30 according to an embodiment of the present invention. In addition to the crystal oscillator core circuitry 120, DC bias circuitry 140, bias resistor Rbias, and square wave buffer 160, the crystal oscillator 30 may also include a phase noise reduction circuitry 180. The phase noise reduction circuitry 180 is coupled to the output of the crystal oscillator core circuitry 120 and can be configured to generate a reset signal including at least one reset pulse (e.g., one or more pulses, which may be collectively referred to as reset pulses) to reset the bias voltage of the sine wave (e.g., by providing an AC ground path for resistor noise on the bias voltage) (e.g., removing resistor noise on the bias voltage, such as noise contributed by the bias resistor Rbias). More specifically, a reset signal can be generated without calibrating at least one reset pulse to the zero-crossing point of the sine wave, where the zero-crossing point of the sine wave may represent the point in time when the sine wave changes across the level of the DC bias voltage VB. Simulations show that the position of the reset pulse (e.g., the timing of the reset pulse relative to the sine wave phase) does not significantly affect the improvement in phase noise reduction (i.e., the position of the reset pulse is not critical, and similar improvements can be obtained at different positions of the reset pulse). Therefore, the reset pulse can be placed at the zero-crossing point or at the peak of the sine wave output. No complex calibration circuitry is required to make the reset pulse appear at the zero-crossing point of the sine wave.

[0025] like Figure 3As shown, the phase noise reduction circuit 180 may include a reset switch 180SW coupled to the output of the crystal oscillator core circuit 120 and controllable by a reset signal. Additionally, the phase noise reduction circuit 180 may include a pulse generator 180G configured to generate a reset signal. In this embodiment, the reset switch can be turned on in response to a reset pulse to provide an AC ground path for resistor noise on the bias voltage, thereby removing noise from the bias voltage and resetting the sinusoidal bias voltage to a reset level. For example, the reset switch 180SW may be coupled across the bias resistor Rbias, as shown, with both ends of the reset switch 180SW coupled to the two ends of the bias resistor Rbias. When the reset switch is on, noise generated by the bias resistor Rbias can be removed, and the sinusoidally varying bias voltage level can be pulled back to the original voltage level of the DC bias voltage VB. However, the invention is not limited to this.

[0026] To better understand how the phase noise reduction circuit 180 addresses the phase noise issue caused by the bias resistor Rbias, please refer to [reference needed]. Figure 4 .like Figure 4 The upper part of the diagram shows waveforms labeled "XO Out2" and "NBUF Out2," representing a sine wave at the output of the crystal oscillator core circuit 120 and a square wave at the output of the square wave buffer 160, respectively, without the proposed noise reset pulse (e.g., the phase noise reduction circuit 180 is disabled and the reset switch 180SW remains open); as Figure 4 The lower half of the diagram shows waveforms labeled "XO Out3" and "NBUF Out3," representing a sine wave at the output of the crystal oscillator core circuit 120 and a square wave at the output of the square wave buffer 160, respectively, using the proposed noise reset pulse (e.g., phase noise reduction circuit 180 is enabled and pulse generator 180G begins outputting reset pulses to periodically turn on reset switch 180SW). Figure 4As shown, when the phase noise reduction circuit 180 is disabled, the sine wave can fluctuate based on the time-varying level VB+ΔV, therefore, the pulse width of the square wave varies over time, resulting in phase noise. In contrast, when the phase noise reduction circuit 180 is enabled and the pulse generator begins outputting reset pulses to the reset switch 180SW (e.g., periodically outputting reset pulses to the reset switch 180SW), in response to the reset pulses, the DC bias voltage level of the sine wave is reset (e.g., reset to the original voltage level of the DC bias voltage VB), and the pulse width of the square wave can be substantially constant, or the amount of variation in the bias level of the sine wave can be reduced (e.g., ΔV can be reduced). Therefore, the pulse width of the square wave can be constant or substantially constant, and thus phase noise is reduced.

[0027] It should be noted that the resistance of the bias resistor Rbias and the input capacitance at the output of the crystal oscillator core circuit 120 can both be designed to be quite large. A large resistance-capacitance (RC) time constant will prevent the noise in the bias resistor Rbias from significantly altering the sine wave level. For example, after resetting the bias voltage level of the sine wave and turning off the reset switch 180SW again, the noise in the bias resistor Rbias will not immediately cause a large change in the bias voltage level of the sine wave because the time constant is large enough. Furthermore, when the noise accumulates and causes a slight change in the bias voltage level of the sine wave, the next reset pulse can reset the bias voltage level again. Figure 4As shown. Therefore, the frequency of the reset signal should preferably be fast enough to better suppress noise in the bias resistor Rbias, thereby maintaining the bias voltage level of the sine wave. Through simulation, assuming a sine wave frequency of 40 MHz, a significant improvement in noise-related performance can be observed when the reset signal frequency is 40 MHz; the noise-related performance is further improved when the reset signal frequency is 400 MHz. Therefore, a higher frequency reset signal is preferred for better noise-related performance, but the invention is not limited thereto. In some embodiments, the phase noise reduction circuit 180 may further include a frequency multiplier configured to generate a signal having a frequency that is N times the frequency of the square wave output from the square wave buffer 160, and thus making the frequency of the reset signal N times the square wave frequency (e.g., there may be N reset pulses within one period of the sine wave or square wave), where N can be a positive integer greater than or equal to 2. In some embodiments, the frequency of the reset signal may be less than or equal to the frequency of the sine wave. In some embodiments, reset pulses may be generated periodically, and the frequency of the reset pulses may be any suitable positive value. In some embodiments, the reset pulse is not generated periodically. For example, the pulse generator 180G may generate the reset pulse randomly, or the occurrence of the reset pulse may be controlled by another controller within the crystal oscillator 30.

[0028] Besides the noise generated by the bias resistor Rbias (referred to as Rbias noise for simplicity), several other factors can affect the SNR of a sine wave, such as the on-time T of the reset pulse. ON (For example, the pulse width of the reset pulse, which indicates the length of time the reset switch 180SW is turned on), and the on-resistance R of the reset switch 180SW. ON (For example, the resistor of reset switch 180SW when reset switch 180SW is on) and the corresponding on-resistance R ON The noise (referred to as R for simplicity) ON (Noise). Through calculation, SNR can be expressed as follows:

[0029]

[0030] The symbol f represents the frequency variable. The symbol R avg This represents the average resistance at the output of the crystal oscillator, which can be further divided by the on-resistance R. ON The resistance R of the bias resistor Rbias BIAS And the parameter α represents, where α = T ON / T XO T XOThis represents the cycle period of the sine wave output from the core circuit 120 of the crystal oscillator. Symbol N Rbias (f) and N Ron (f) represent the Rbias noise and R corresponding to frequency f, respectively. ON Noise. Assume that Rbias noise N can be removed. Rbias (f)(For example, consider Rbias noise N) Rbias (f) Different R values ​​when reduced to the same level ON and T ON (Combined), the above formula may be further arranged as follows:

[0031] The symbol k represents the Boltzmann constant. The symbol T represents absolute temperature. The symbol C... IN This represents the input capacitor at the output terminal of the crystal oscillator core circuit 120. (Symbol: f) XO R represents the frequency of the sine wave. As shown in the equation above, R ON Noise N Ron (f) may include sampling noise and holding noise. Assume the frequency f is greater than the frequency f of the sine wave. XO Much smaller (e.g., when f / f) XO When the value is very close to zero, the above equation can be further simplified as follows:

[0032]

[0033] Based on the equations shown above, it can be noted that, when reducing Rbias noise to the same level, it is preferable to design a smaller α to obtain a better SNR. For example, when reducing Rbias noise to the same level, the SNR of the sine wave can be increased by reducing the pulse width of the reset pulse. Therefore, using a very short reset pulse (e.g., a reset pulse with a very narrow pulse width) to reset Rbias noise (e.g., to eliminate or reduce Rbias noise) is an optimized design for the noise-related performance of the crystal oscillator 30. In fact, a small α can be achieved through exclusive-OR (XOR) logic circuitry and a very short delay line, thereby benefiting from a small area, low current consumption, and low noise of the delay line. The aforementioned very short delay line may include an inverter or a series of inverters, but the invention is not limited thereto. It should be noted that the delay provided by the aforementioned very short delay line is not limited to a specific value and can have any delay capable of resetting the bias voltage level of the sine wave without significantly reducing the SNR, such as 100 picoseconds (ps), 80 ps, ​​etc.

[0034] Figure 5This is a schematic diagram illustrating a crystal oscillator 50 according to an embodiment of the present invention, wherein the crystal oscillator 50 may be... Figure 3 A modified version or example of the crystal oscillator 30 shown. For example... Figure 5 As shown, in this embodiment, the phase noise reduction circuit 180 can be replaced by a phase noise reduction circuit 190, wherein the phase noise reduction circuit 190 is coupled to the output of the crystal oscillator core circuit 120 and can be configured to reset the sinusoidal bias voltage in response to the voltage level of the sinusoidal wave (e.g., the peak value of the sinusoidal wave) exceeding a specific voltage range. In this embodiment, the phase noise reduction circuit 190 may include DC bias circuits 191 and 192. The DC bias circuit 191 can be configured to control the DC voltage level Vcal1, and the DC bias circuit 192 can be configured to control the DC voltage level Vcal2, wherein the specific voltage range is determined according to the DC voltage levels Vcal1 and Vcal2. Furthermore, the phase noise reduction circuit 190 may also include a first control switch and a second control switch, wherein the first control switch is coupled between the output of the crystal oscillator core circuit 120 and the DC bias circuit 191, and the second control switch is coupled between the output of the crystal oscillator core circuit 120 and the DC bias circuit 192. For example, the first control switch can be turned on in response to a sine wave voltage level greater than the upper limit level, and the second control switch can be turned on in response to a sine wave voltage level less than the lower limit level, wherein the upper limit level and the lower limit level can correspond to DC voltage levels Vcal1 and Vcal2, respectively.

[0035] In this embodiment, the first control switch may include a first diode, such as diode D1, and the second control switch may include a second diode, such as diode D2. Figure 5 As shown, the anode of diode D1 can be coupled to the output of the crystal oscillator core circuit 120, and the cathode of diode D1 can be coupled to the DC bias circuit 191. Similarly, the anode of diode D2 can be coupled to the DC bias circuit 192, and the cathode of diode D2 can be coupled to the output of the crystal oscillator core circuit 120. Specifically, diode D1 conducts when the voltage difference between its anode and cathode is greater than its threshold voltage Vth1 (e.g., the first control switch can be considered to be on); otherwise, diode D1 does not conduct (e.g., the first control switch can be considered to be off). Likewise, diode D2 conducts when the voltage difference between its anode and cathode is greater than its threshold voltage Vth2 (e.g., the second control switch can be considered to be on); otherwise, diode D2 does not conduct (e.g., the second control switch can be considered to be off).

[0036] It should be noted that either diode D1 or D2 (e.g., each) is not limited to being implemented by a single diode. For example, either diode D1 or D2 (e.g., each) can be implemented by a cascaded structure of multiple diode units, such as N diode units connected in series to obtain a threshold voltage N*Vth, depending on the basic voltage swing of the sine wave, where Vth can represent the threshold voltage of a single diode unit, and N can represent the number of diode units connected in series. For simplicity, it is assumed that Vth1 = Vth2 = N*Vth, but the invention is not limited thereto. In this embodiment, when the voltage level of the sine wave exceeds the upper limit level, diode D1 conducts in response to the voltage difference across diode D1 exceeding the threshold voltage Vth1, thus the maximum level of the sine wave can be clamped to the upper limit level (e.g., Vcal1 + N*Vth), as... Figure 6 As shown in the diagram. When the voltage level of the sine wave exceeds the lower limit level, diode D2 can conduct in response to the voltage difference across diode D2 exceeding the threshold voltage Vth2. Therefore, the minimum level of the sine wave can be clamped to the lower limit level (e.g., Vcal2-N*Vth), as shown in the diagram. Figure 6 As shown. Based on the fundamental characteristics of diodes, diodes D1 and / or D2 can automatically conduct through the voltage swing of a sine wave, and noise removal related to the DC bias voltage level of the sine wave can be effective at the maximum level (e.g., peak) and / or minimum level (e.g., trough) of the sine wave, as... Figure 6 The reset current shown is (e.g., the current flowing through a node coupled to the output of the crystal oscillator core circuit 120).

[0037] To ensure that DC voltage levels Vcal1 and Vcal2 are set to appropriate levels to enable diodes D1 and / or D2, a calibration procedure can be performed to calibrate DC voltage levels Vcal1 and Vcal2. During the calibration procedure, DC voltage levels Vcal1 and Vcal2 can be initially set to an initial maximum level and an initial minimum level, respectively (e.g., at the beginning of the calibration procedure or in the initial phase of the crystal oscillator). The initial maximum level can be the highest voltage level that DC bias circuit 191 can provide, and the initial minimum level can be the lowest voltage level that DC bias circuit 192 can provide. DC voltage levels Vcal1 can be gradually decreased from the initial maximum level so that the maximum level of the sine wave (e.g., a peak) enables the first control switch, such as diode D1. DC voltage levels Vcal2 can be gradually increased from the initial minimum level so that the minimum level of the sine wave (e.g., a trough) enables the second control switch, such as diode D2.

[0038] For example, the DC bias circuit 191 can control the DC voltage level Vcal1 according to a first calibration code such as a 3-bit code, wherein different values ​​of the first calibration code (e.g., candidate values ​​such as 111, 110, ... and 000) can correspond to different values ​​of the DC voltage level Vcal1 (e.g., candidate values ​​such as Vcal1(7), Vcal1(6), ... and Vcal1(0), where Vcal1(7)>Vcal1(6)>...>Vcal1(0)). When the first calibration code is 111, the DC bias circuit 191 can control the DC voltage level Vcal1 to the highest voltage level (e.g., 0.9V) within the adjustment range of the DC voltage level Vcal1. When the first calibration code is 000, the DC bias circuit 191 can control the DC voltage level Vcal1 to the lowest voltage level (e.g., 0V) within the adjustment range of the DC voltage level Vcal1. The remaining values ​​of the first calibration code can be deduced by analogy. For example, {Vcal1(7), Vcal1(6), Vcal1(5), Vcal1(4), Vcal1(3), Vcal1(2), Vcal1(1), Vcal1(0)} can be {0.9V, 0.79V, 0.68V, 0.45V, 0.34V, 0.22V, 0.11V, 0V}. The first calibration code can be initially set to 111, and the DC voltage level Vcal1 corresponding to this value of the first calibration code cannot conduct diode D1. Therefore, the first calibration code is progressively switched to 110, 101, 100, etc., to find at least one value of the first calibration code that enables diode D1 to conduct. Similarly, the DC bias circuit 192 can control the DC voltage level Vcal2 according to a second calibration code such as a 3-bit code, wherein different values ​​of the second calibration code (e.g., candidate values ​​such as 111, 110, ... and 000) can respectively correspond to different values ​​of the DC voltage level Vcal2 (e.g., candidate values ​​such as Vcal2(7), Vcal2(6), ... and Vcal2(0), where Vcal2(7)... <Vcal2(6)<…<Vcal2(0)))。When the second calibration code is 111, the DC bias circuit 192 can control the DC voltage level Vcal2 to the lowest voltage level (e.g., 0V) within the adjustment range of the DC voltage level Vcal2. When the second calibration code is 000, the DC bias circuit 192 can control the DC voltage level Vcal2 to the highest voltage level (e.g., 0.9V) within the adjustment range of the DC voltage level Vcal2. The remaining values ​​of the second calibration code can be derived by analogy. For example, {Vcal2(7), Vcal2(6), Vcal2(5), Vcal2(4), Vcal2(3), Vcal2(2), Vcal2(1), Vcal2(0)} can be {0V, 0.11V, 0.22V, 0.34V, 0.45V, 0.68V, 0.79V, 0.9V}. The second calibration code can be initially set to 111, and the corresponding DC voltage level Vcal2 should not turn on diode D2. Therefore, the second calibration code is gradually switched to 110, 101, 100, etc., to find at least one value of the second calibration code that turns on diode D2.

[0039] In one embodiment, the phase noise reduction circuit 190 may further include a peak detector 193 coupled to the output of the crystal oscillator core circuit 120. The peak detector 193 may be configured to detect the swing of a sine wave to generate a detection result (e.g., detecting the peak value of the sine wave to obtain information related to the swing). DC bias circuits 191 and 192 may control DC voltage levels Vcal1 and Vcal2, respectively, based on the detection result. For example, the peak detector 193 may output a DC voltage based on the swing (or peak value) of the sine wave, which may be used to determine whether the swing of the sine wave has changed (e.g., decreased), but the invention is not limited thereto. For instance, assuming the sine wave swing is ±1000mV, the DC voltage output from the peak detector 193 may be 500mV, and when the sine wave swing is ±900mV, the DC voltage output from the peak detector 193 may be 450mV. It should be noted that those skilled in the art should understand the detailed implementation of the peak detector 193 based on the above description, and for the sake of brevity, relevant details have been omitted here.

[0040] Additionally, the current source within the crystal oscillator core circuit 120 may include one or more current units connected in parallel, and the one or more current units may be configured to provide a bias current to the crystal oscillator core circuit 120 to control the swing of the sine wave. For example, the bias current may depend on the number of current units enabled in the current source, while the swing of the sine wave depends on the bias current. In one embodiment, the crystal oscillator core circuit 120 may further include a current calibration (ACAL) circuit 121 coupled to one or more current units, and the number of current units enabled in the current source depends on the calibration code output from the ACAL circuit 121. Therefore, the ACAL circuit 121 can control the swing of the sine wave by controlling the calibration code. In this embodiment, the ACAL circuit 121 can calibrate the current source by the speed / frequency of a square wave at its output OUT (e.g., modifying the calibration code once per cycle of the square wave during calibration of the current source), but the invention is not limited thereto.

[0041] Specifically, at the start of calibration for DC voltage levels Vcal1 and Vcal2, DC voltage level Vcal1 is set to an initial maximum level, and DC voltage level Vcal2 is set to an initial minimum level. Before either (e.g., each) of DC voltage levels Vcal1 and Vcal2 is progressively modified as described above, ACAL circuit 121 can calibrate the bias current so that the swing of the sine wave falls within the range of an adjustable maximum level associated with the initial maximum level (e.g., initial maximum level of Vcal1 + N*Vth) and an adjustable minimum level associated with the initial minimum level (e.g., initial minimum level of Vcal2 – N*Vth). Therefore, it is ensured that calibration for DC voltage levels Vcal1 and Vcal2 begins in a state where the first and second control switches (e.g., diodes D1 and D2) are not conducting in response to the maximum and minimum levels of the sine wave. Then, either (e.g., each) of the DC voltage levels Vcal1 and Vcal2 can be progressively modified based on the detection results (e.g., the DC voltage output from the peak detector 193) so that the first control switch (e.g., diode D1) turns on in response to the maximum level (e.g., peak) of the sine wave, and / or the second control switch (e.g., diode D2) turns on in response to the minimum level (e.g., trough) of the sine wave. For example, suppose that the DC voltage level output from the peak detector 193 is 500mV at the start of the calibration of the DC voltage levels Vcal1 and Vcal2. After the DC voltage level Vcal1 is decreased by one step (e.g., switching the first calibration code from 111 to 110) and / or the DC voltage level Vcal2 is increased by one step (e.g., switching the second calibration code from 111 to 110), if the DC voltage output from the peak detector 193 is still 500mV, the DC voltage level Vcal1 can be further decreased by another step (e.g., switching the first calibration code from 110 to 101) and / or the DC voltage level Vcal2 can be further increased by another step (e.g., switching the second calibration code from 110 to 101); and if the DC voltage output from the peak detector 193 becomes 480mV, this means that the amplitude of the sine wave has decreased due to the noise removal of the DC bias voltage level of the sine wave taking effect, and the current values ​​(e.g., the latest values) of the first calibration code and the second calibration code can be the final values ​​of the first calibration code and the second calibration code, respectively. Therefore, the calibration of the DC voltage levels Vcal1 and Vcal2 is completed.

[0042] Note that the adjustment ranges and calibration codes for the voltage levels mentioned above are for illustrative purposes only and do not imply any limitation on the invention. For example, the number of bits in the first and second calibration codes can vary. For example, the adjustment range of DC voltage level Vcal1 can be the same as the adjustment range of DC voltage level Vcal2. In another example, the adjustment range of DC voltage level Vcal1 can be different from the adjustment range of DC voltage level Vcal2. Furthermore, it is not necessary to perform the calibration of DC voltage level Vcal1 and DC voltage level Vcal2 simultaneously. For example, the calibration of DC voltage level Vcal2 can be performed after the calibration of DC voltage level Vcal1 is completed. In another example, the calibration of DC voltage level Vcal1 can be performed after the calibration of DC voltage level Vcal2 is completed. Moreover, some embodiments may perform calibration only on one of the DC voltage levels Vcal1 and Vcal2. In practice, it is preferable to calibrate both DC voltage levels Vcal1 and Vcal2 to obtain a symmetrical waveform of a sine wave. For example, DC voltage levels Vcal1 and Vcal2 can be calibrated simultaneously using the same calibration code (e.g., the first calibration code can be equal to the second calibration code), but the invention is not limited thereto.

[0043] For a better understanding, please refer to Figure 7 It illustrates the following regarding embodiments of the present invention. Figure 5 The calibration process for the DC voltage levels Vcal1 and Vcal2 is shown. For example, the calibration control circuit within the phase noise reduction circuit 190 can utilize multiple control signals to control the calibration process, but the invention is not limited thereto. It should be noted that... Figure 7 The illustrated workflow is for illustrative purposes only and is not intended to limit the invention. In some embodiments, it may be possible to... Figure 7 Add, delete, or modify one or more steps in the workflow shown. Additionally, if the same result can be obtained, it is not necessary to follow the steps exactly. Figure 7 Perform these steps in the exact order shown.

[0044] In step 710, when the crystal oscillator 50 is enabled, the calibration workflow begins.

[0045] In step 720, the calibration control circuit can control the DC bias circuit 191 to set the DC voltage level Vcal1 to the maximum (e.g., the initial maximum level) and control the DC bias circuit 192 to set the DC voltage level Vcal2 to the minimum (e.g., the initial minimum level).

[0046] In step 730, the calibration control circuit can control the peak detector 193 to detect the swing of the sine wave (which may be referred to as "PD detection"). Assume that the swing of the sine wave detected in this step, Vswing, is Vp (e.g., Vswing = Vp).

[0047] In step 740, the calibration control circuit can control the DC bias circuit 191 to decrease the DC voltage level Vcal1 by one step, and control the DC bias circuit 192 to increase the DC voltage level Vcal2 by one step.

[0048] In step 750, the calibration control circuit can control the peak detector 193 to detect the amplitude of the sine wave again. Assume that the sine wave amplitude Vswing detected in this step is Vdet (e.g., Vswing = Vdet).

[0049] In step 760, the calibration control circuit can determine whether (Vp–Vdet) meets the target (e.g., whether (Vp–Vdet) is greater than a predetermined voltage difference). If the determination result is "yes", the workflow proceeds to step 770; if the determination result is "no", the workflow proceeds to step 740.

[0050] In step 770, the calibration control circuit ends the calibration.

[0051] It should be noted that neither diode D1 nor D2 (e.g., each) need to be implemented as a typical diode. For example, any device including at least one PN junction can be used to implement diodes D1 and D2. In some embodiments, diode D1 can be implemented as a P-type transistor, wherein the drain and gate of the P-type transistor can be coupled to each other to configure the P-type transistor as a diode-connected transistor with characteristics similar to a typical diode. In some embodiments, diode D2 can be implemented as an N-type transistor, wherein the drain and gate of the N-type transistor can be coupled to each other to configure the N-type transistor as a diode-connected transistor with characteristics similar to a typical diode. Based on the above description, those skilled in the art should understand how to... Figure 5 The architecture shown uses diode-connected transistors; for the sake of simplicity, related details are omitted here.

[0052] Figure 8 This is a schematic diagram illustrating a crystal oscillator 80 according to an embodiment of the present invention, wherein the crystal oscillator 80 may be... Figure 5 A modified version or example of the crystal oscillator 50 shown. For example, it can be used... Figure 8 The phase noise reduction circuit 190 is replaced by phase noise reduction circuit 190, and more specifically, diodes D1 and D2 are replaced by P-type transistor M1 and N-type transistor M2, respectively. Figure 8As shown, the gate of P-type transistor M1 is coupled to DC bias circuit 191 to receive DC voltage level Vcal1, the drain of P-type transistor M1 is configured to receive DC voltage level VB1, and the source of P-type transistor M1 is coupled to the output of crystal oscillator core circuit 120. Similarly, the gate of N-type transistor M2 is coupled to DC bias circuit 192 to receive DC voltage level Vcal2, the drain of N-type transistor M2 is configured to receive DC voltage level VB2, and the source of N-type transistor M2 is coupled to the output of crystal oscillator core circuit 120. Based on this architecture, when the voltage level of the sine wave (e.g., the maximum level, such as the peak of the sine wave) exceeds the upper limit level, causing the difference between the voltage level of the sine wave and the DC voltage level Vcal1 to be greater than the threshold voltage (e.g., making Vsin – Vcal1 > |Vthp|, where Vsin represents the instantaneous level of the sine wave, Vthp represents the threshold voltage of the P-type transistor M1, and |Vthp| represents the absolute value of Vthp), the P-type transistor M1 can be turned on, and the DC bias voltage level of the sine wave can be reset to VB1. When the voltage level of the sine wave (e.g., the minimum level, such as the trough of the sine wave) exceeds the lower limit level, causing the difference between the DC voltage level Vcal2 and the voltage level of the sine wave to be greater than the threshold voltage (e.g., making Vcal2 – Vsin > |Vthn|, where Vthn represents the threshold voltage of the N-type transistor M2, and |Vthn| represents the absolute value of Vthn), then the N-type transistor M2 can be turned on, and the DC bias voltage level of the sine wave can be reset to VB2.

[0053] In some embodiments, DC voltage levels VB1 and VB2 can be the same. In some embodiments, DC voltage levels VB1 and VB2 can be different. In some embodiments, both DC voltage levels VB1 and VB2 can be the same as the DC voltage level of the DC bias voltage VB provided by the DC bias circuit 140. In some embodiments, at least one of DC voltage levels VB1 and VB2 (e.g., one or both of them) can be different from the DC voltage level of the DC bias voltage VB provided by the DC bias circuit 140. DC voltage levels VB1 and VB2 are not limited to specific voltage levels, provided that DC voltage levels VB1 and VB2 are clean and constant voltage levels (e.g., each DC voltage level VB1 and VB2 has extremely low noise). Additionally, in Figure 8 The crystal oscillator 80 shown can also employ... Figure 5 The calibration workflow for DC voltage levels Vcal1 and Vcal2 is shown below. For the sake of brevity, similar descriptions related to the calibration of DC voltage levels Vcal1 and Vcal2 will not be repeated here.

[0054] In summary, refer to Figure 9This illustrates the workflow of a phase noise reduction method for a crystal oscillator (e.g., crystal oscillator 50 or crystal oscillator 80) according to an embodiment of the present invention. It should be noted that... Figure 9 The illustrated workflow is for illustrative purposes only and is not intended to limit the invention. In some embodiments, it may be possible to... Figure 9 Add, delete, or modify one or more steps in the workflow shown. Additionally, if the same result can be obtained, it is not necessary to follow the steps exactly. Figure 9 Perform these steps in the exact order shown.

[0055] In step 910, the crystal oscillator can generate a sine wave through the crystal oscillator core circuit (e.g., crystal oscillator core circuit 120).

[0056] In step 920, the crystal oscillator can provide a first voltage level (e.g., the level of the DC bias voltage VB) as a sine wave bias voltage through the first bias circuit of the crystal oscillator (e.g., DC bias circuit 140).

[0057] In step 930, in response to the voltage level of the sine wave exceeding a specific voltage range, the crystal oscillator passes through the crystal oscillator's phase noise reduction circuit (e.g., Figure 5 The phase noise reduction circuit 190 shown Figure 8 The phase noise reduction circuit shown (190M) resets the bias voltage of the sine wave.

[0058] Because each diode / similar diode assembly used in this invention (e.g., diode D1 / D2 or transistor M1 / M2) has the characteristic of automatically turning on in response to a voltage across the diode / similar diode assembly exceeding a threshold value of that diode / similar diode assembly, noise removal with respect to the DC bias voltage level of a sine wave can be effective at least at the peak or trough of the sine wave. Therefore, this invention can improve phase noise-related performance without introducing any side effects or in a manner unlikely to introduce side effects.

[0059] Those skilled in the art will readily observe that various modifications and alterations can be made to the apparatus and method while maintaining the teachings of the present invention. Therefore, the above disclosure should be interpreted as being limited only by the scope of the appended claims.

Claims

1. A crystal oscillator, characterized in that, include: The core circuit of the crystal oscillator is configured to generate a sine wave; The first bias circuit, coupled to the output of the core circuit of the crystal oscillator, is configured to provide a first voltage level as the bias voltage of the sine wave. as well as A phase noise reduction circuit, coupled to the output of the core circuit of the crystal oscillator, is configured to reset the bias voltage of the sine wave in response to the voltage level of the sine wave exceeding a specific voltage range. The phase noise reduction circuit includes: The second bias circuit is used to control the second voltage level; The third bias circuit is used to control the third voltage level; and A peak detector, coupled to the output of the core circuit of the crystal oscillator, is configured to detect the amplitude of the sine wave to generate a detection result; The second bias circuit and the third bias circuit control the second voltage level and the third voltage level respectively according to the detection result; wherein the specific voltage range is determined based on the second voltage level and the third voltage level.

2. The crystal oscillator according to claim 1, characterized in that, The phase noise reduction circuit further includes: A first control switch, coupled between the output of the crystal oscillator core circuit and the second bias circuit, is configured to turn on in response to a voltage level of the sine wave exceeding an upper limit level; and The second control switch, coupled between the output of the crystal oscillator core circuit and the third bias circuit, is configured to turn on in response to the voltage level of the sine wave being less than the lower limit level. Wherein, the upper limit level and the lower limit level correspond to the second voltage level and the third voltage level, respectively.

3. The crystal oscillator according to claim 2, characterized in that, The second voltage level gradually decreases from the initial maximum level so that the maximum level of the sine wave can turn on the first control switch.

4. The crystal oscillator according to claim 2, characterized in that, The third voltage level gradually increases from the initial minimum level so that the minimum level of the sine wave can turn on the second control switch.

5. The crystal oscillator according to claim 2, characterized in that, In the initial stage of the crystal oscillator, the second voltage level is set to the initial maximum level, and the third voltage level is set to the initial minimum level; as well as Based on the detection results, either the second voltage level or the third voltage level is gradually modified so that either the first control switch or the second control switch can be turned on in response to either the maximum or minimum level of the sine wave.

6. The crystal oscillator according to claim 5, characterized in that, The core circuit of the crystal oscillator includes: One or more current units are configured to provide bias current to the core circuit of the crystal oscillator to control the swing of the sine wave; and A current calibration circuit, coupled to the one or more current units, calibrates the bias current before gradually changing either the second voltage level or the third voltage level, so that the swing of the sine wave falls within a range between an adjustable maximum level and an adjustable minimum level, wherein the adjustable maximum level is related to the initial maximum level and the adjustable minimum level is related to the initial minimum level.

7. The crystal oscillator according to claim 2, characterized in that, The first control switch includes a first diode, and the first anode of the first diode is coupled to the output terminal of the crystal oscillator core circuit, and the first cathode of the first diode is coupled to the second bias circuit. The second control switch includes a second diode, the second anode of the second diode is coupled to the third bias circuit, and the second cathode of the second diode is coupled to the output terminal of the crystal oscillator core circuit.

8. The crystal oscillator according to claim 2, characterized in that, The first control switch includes a P-type transistor, and the source terminal of the P-type transistor is coupled to the output terminal of the core circuit of the crystal oscillator, and the gate terminal of the P-type transistor is coupled to the second bias circuit. The second control switch includes an N-type transistor, and the source terminal of the N-type transistor is coupled to the output terminal of the crystal oscillator core circuit, while the gate terminal of the N-type transistor is coupled to the third bias circuit.

9. A method for reducing phase noise in a crystal oscillator, characterized in that, include: The core circuit of the crystal oscillator generates a sine wave. The first bias circuit of the crystal oscillator provides a first voltage level as the bias voltage for the sine wave; as well as In response to the voltage level of the sine wave exceeding a specific voltage range, the phase noise reduction circuit of the crystal oscillator resets the bias voltage of the sine wave; In response to the voltage level of the sine wave exceeding the specific voltage range, the phase noise reduction circuit of the crystal oscillator resets the bias voltage of the sine wave by: The amplitude of the sine wave is detected by a peak detector to generate a detection result; The second bias circuit and the third bias circuit control the second voltage level and the third voltage level respectively according to the detection result. The specific voltage range is determined based on the second voltage level controlled by the second bias circuit and the third voltage level controlled by the third bias circuit.

10. The phase noise reduction method according to claim 9, characterized in that, In response to the voltage level of the sine wave exceeding the specific voltage range, the phase noise reduction circuit of the crystal oscillator resets the bias voltage of the sine wave by: In response to the voltage level of the sine wave being greater than the upper limit level, the first control switch coupled between the output terminal of the core circuit of the crystal oscillator and the second bias circuit is turned on; and In response to the voltage level of the sine wave being less than the lower limit level, the second control switch coupled between the output terminal of the core circuit of the crystal oscillator and the third bias circuit is turned on. Wherein, the upper limit level and the lower limit level correspond to the second voltage level and the third voltage level, respectively.

11. The phase noise reduction method according to claim 10, characterized in that, The second voltage level is gradually reduced from the initial maximum level so that the maximum level of the sine wave can turn on the first control switch.

12. The method for reducing phase noise according to claim 10, characterized in that, The third voltage level is gradually increased starting from the initial minimum level so that the minimum level of the sine wave can turn on the second control switch.

13. The method for reducing phase noise according to claim 10, characterized in that, Also includes: In the initial stage of the crystal oscillator, the second voltage level is set to the initial maximum level, and the third voltage level is set to the initial minimum level; as well as Based on the detection results, either the second voltage level or the third voltage level is gradually modified so that either the first control switch or the second control switch can be turned on in response to either the maximum or minimum level of the sine wave.

14. The method for reducing phase noise according to claim 13, characterized in that, The core circuit of the crystal oscillator generates the sine wave by: The bias current of the crystal oscillator core circuit is provided through one or more current units to control the amplitude of the sine wave; and Before progressively modifying either the second voltage level or the third voltage level, the bias current is calibrated by a current calibration circuit so that the swing of the sine wave falls within the range between an adjustable maximum level and an adjustable minimum level, wherein the adjustable maximum level is related to the initial maximum level and the adjustable minimum level is related to the initial minimum level.

15. The method for reducing phase noise according to claim 10, characterized in that, The first control switch includes a first diode, and the first anode of the first diode is coupled to the output terminal of the core circuit of the crystal oscillator, and the first cathode of the first diode is coupled to the second bias circuit. The second control switch includes a second diode, the second anode of which is coupled to the third bias circuit, and the second cathode of which is coupled to the output of the core circuit of the crystal oscillator.

16. The method for reducing phase noise according to claim 10, wherein, The first control switch includes a P-type transistor, and the source terminal of the P-type transistor is coupled to the output terminal of the core circuit of the crystal oscillator, and the gate terminal of the P-type transistor is coupled to the second bias circuit. The second control switch includes an N-type transistor, and the gate of the N-type transistor is coupled to the output of the core circuit of the crystal oscillator, and the gate of the N-type transistor is coupled to the third bias circuit.

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