A Doherty power amplifier circuit

Abstract

A Doherty power amplifier circuit operates in a 28 GHz Doherty PA circuit. The power amplifier circuit includes: an input matching power splitting circuit and a synthesizer circuit for combining the main and auxiliary PAs with output matching, which is composed of cascode circuits of double-stacked transistors. The input matching power splitting circuit performs power distribution through filtering formed by passive components such as the first inductor L1, the first capacitor C1, the fourth inductor L4, and the fourth capacitor C4, and through input load matching. The double-stacked cascode circuit combines the main and auxiliary PA circuits using lumped elements, and both the main and auxiliary PAs adopt the double-stacked cascode circuit structure; the operation of the main and auxiliary PAs is controlled by adjusting the different bias voltages of VG1 / VG1' and VG2 / VG2'.

Description

Technical Field

[0001] The present invention belongs to the technical field of millimeter-wave radio frequency chip integrated circuits in the field of wireless communication, and particularly relates to a highly reliable and high-performance power amplifier circuit. Background Art

[0002] Power Amplifiers (PA) are widely used in civilian and military fields such as 5G wireless communication technology, radar, electronic warfare, and navigation. The radio frequency power amplifier is the core part of these systems. Among them, PAs with low power consumption, high efficiency, and small volume have become crucial. As the part that consumes the most power in the radio frequency transmitter, reducing the power consumption of the power amplifier is also a key step. Improving the efficiency of the PA directly determines the power loss of the radio frequency front-end system. In recent years, high integration and small size have always been the focus of technology research. For power combiners, quarter-wavelength transmission lines are generally used, but this is not conducive to integration, and the transmission lines will also generate losses. In the existing Doherty architecture technology, the output power of the main power amplifier is relatively large, while the output power of the auxiliary power amplifier is relatively small. These two amplifiers are designed such that when the input signal power is very low, the main power amplifier works and the auxiliary power amplifier does not work; when the input signal power increases to a certain extent, the auxiliary power amplifier outputs a certain amount of power to compensate for the gain compression of the main power amplifier, and as the input power increases, the output power of the auxiliary amplifier also gradually increases. When the output powers of the two power amplifiers are combined, an approximately linearized output power is obtained. The Doherty technology can improve the average efficiency of the power amplifier and can also improve the linearity of the power amplifier to a certain extent. Nowadays, synthesizers using LC lumped elements have been applied in the 45nm CMOS SOI process, the volume has been improved, and the linearity of the power amplifier has also been appropriately improved.

[0003] However, the improvement measures of the existing technology have the following technical problems: 1. Many current power combiners are designed using microstrip lines, which are not conducive to integration and have large areas. Traditional combiners have higher losses than optimized combiners. 2. Because the existing circuits have low linearity and relatively low additional peak efficiency, they are not conducive to the front-end circuits of radio frequency transceiver systems and will cause high losses. Summary of the Invention

[0004] Object of the Invention:

[0005] Aiming at the above deficiencies of the existing circuit technology: large area, not conducive to integration, low linearity, low peak efficiency, high loss, etc., the present invention needs to design and develop a high-performance and linear PA circuit with high gain, low cost, and easy integration.

[0006] Technical solution:

[0007] A Doherty power amplifier circuit, a Doherty PA circuit operating at 28 GHz, the power amplifier circuit includes: an input matching power splitting circuit and a synthesizer circuit for combining the main and auxiliary PAs and output matching composed of a cascode circuit of double-stacked transistors.

[0008] The input matching power splitting circuit performs power distribution through filtering formed by passive components such as the first inductor L1, the first capacitor C1, the fourth inductor L4, and the fourth capacitor C4, and through input load matching.

[0009] The cascode circuit of the double-stacked transistors combines the main and auxiliary PA circuits using lumped elements. Both the main and auxiliary PAs adopt the cascode circuit structure of double-stacked transistors; by adjusting the different bias voltages of VG1 / VG1' and VG2 / VG2', the operation of the main and auxiliary PAs is controlled to implement the Doherty technology, thereby improving the overall linearity and improving the efficiency with respect to the maximum output power back-off.

[0010] The synthesizer circuit uses a lumped element network to optimize the traditional lumped element network synthesizer and proposes a new power synthesizer.

[0011] The Doherty PA circuit includes: the first NMOS transistor M1, the second NMOS transistor M2, the first NMOS transistor M1', the second NMOS transistor M2', the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the capacitor Cr, the capacitor Cg, the capacitor Cr', the capacitor Cg', the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the fifth inductor L5, the sixth inductor L6, the first resistor R1, the second resistor R2, the first resistor R1', the second resistor R2';

[0012] The positive plate of the first capacitor C1 is connected to one end of the first inductor L1 and is connected to the IN of the main PA. The other end of the fourth inductor L1 is grounded. The negative plates of the first capacitor C1 and the fourth capacitor C4 are connected to the input RFIN, and RFIN is matched with a 50Ω resistor; the positive plate of the fourth capacitor C4 is connected to one end of the fourth inductor L4 and is connected to the IN of the auxiliary PA. The other end of the fourth inductor L4 is grounded.

[0013] The OUT of the main PA is connected to one end of the second inductor L2 and one end of the third inductor L3. The other end of the third inductor L3 is connected to the first voltage VDD1. The other end of the second inductor L2, the positive plate of the second capacitor C2, and the positive plate of the third capacitor C3 are connected together. The negative plate of the third capacitor C3 is grounded. The negative plate of the second capacitor C2, the negative plate of the fifth capacitor C5, and the output RFOUT are connected together. RFOUT is matched with a 50Ω resistor. The positive plate of the fifth capacitor C5, the positive plate of the sixth capacitor C6, and one end of the fifth inductor L5 are connected together. The negative plate of the sixth capacitor C6 is grounded. The other end of the fifth inductor L5 is connected to one end of the sixth inductor L6 and is also connected to the OUT of the auxiliary PA. The other end of the sixth inductor L6 is connected to the second voltage VDD2.

[0014] The connection of the main PA is as follows: The gate of the first NMOS transistor M1 of the main PA in the circuit is connected to the positive plate of the capacitor Cr through one end of the resistor R1, and finally connected to the input matching circuit composed of LC lumped elements to complete the matching of the input end of the power amplifier. The gate of the second NMOS transistor M2 is not directly grounded. Instead, it is connected to one end of the second resistor R2, and then connected to the positive plate of the capacitor Cg and then grounded, reducing the swing of the gate voltage. Among them, VG1 and VG2 are respectively connected to the other ends of the first resistor R1 and the second resistor R2 as the bias voltage input terminals.

[0015] The connection of the auxiliary PA is as follows: The gate of the first NMOS transistor M1' of the auxiliary PA in the circuit is connected to the positive plate of the capacitor Cr' through one end of the resistor R1', and finally connected to the input matching circuit composed of LC lumped elements to complete the matching of the input end of the power amplifier. The gate of the second NMOS transistor M2' is not directly grounded. Instead, it is connected to one end of the second resistor R2', and then connected to the positive plate of the capacitor Cg' and then grounded, reducing the swing of the gate voltage. Among them, VG1' and VG2' are respectively connected to the other ends of the first resistor R1' and the second resistor R2' as the bias voltage input terminals.

[0016] The sources of the first NMOS transistors M1 / M1' of the main and auxiliary PAs are grounded. The drains of the first NMOS transistors M1 / M1' are connected to the sources of the second NMOS transistors M2 / M2'. The drains of the second NMOS transistors M2 / M2' are respectively connected to the two input terminals of the synthesizer, and power synthesis is performed through the output matching and synthesizing circuit.

[0017] For the double-stacked transistor driving circuit, the gates of the first NMOS transistors M1 / M1' are connected to one end of the first resistor R1 and the positive plates of the Cr / Cr' capacitors. The negative plates of the Cr / Cr' capacitors are connected to the input IN. The sources of the first NMOS transistors M1 / M1' are grounded. The drains of the first NMOS transistors M1 are connected to the sources of the second NMOS transistors M2 / M2'. The gates of the second NMOS transistors M2 / M2' are connected to one end of the second resistor R2 and the positive plates of the Cg / Cg' capacitors. The negative plates of the Cg / Cg' capacitors are grounded. The drains of the second NMOS transistors M2 / M2' are connected to the output OUT.

[0018] The INs of the internal circuits of the main and auxiliary PAs are connected to both ends of the input distribution circuit of the Doherty PA. The OUTs of the drains of M2 / M2' are respectively connected to both ends of the input of the output combining circuit.

[0019] Advantages and effects:

[0020] The entire circuit uses double-stacked MOS transistors for driving. The gates of the first NMOS transistors M1 / M1' are connected to capacitors, reducing the voltage swing. The operating states of the main and auxiliary PAs are controlled by the bias voltages VG1 / VG1' and VG2 / VG2', thereby improving the overall linearity. The input power distribution circuit is designed using LC lumped elements, and the matching design of the output combiner circuit replaces the traditional microstrip line design, greatly improving the integration of the circuit chip and also benefiting the reduction of the chip area.

[0021] The design of the input distribution circuit and the output combining circuit using a lumped element network reduces the loss, facilitates the integration of the circuit, and also reduces the area. The Doherty PA with double-stacked driving improves the linearity of the overall power amplifier. The circuit design structure is simple and convenient for popularization and use.

[0022] This design uses a CMOS 65nm process to design a power amplifier operating in the 28GHz band, which can be used in the front-end components of similar millimeter-wave radio frequency transceivers. Description of the drawings

[0023] Figure 1 It is a schematic diagram of the existing Doherty technology;

[0024] Figure 2 It is the circuit diagram of the Doherty PA of the present invention;

[0025] Figure 3 It is the linearity diagram of the 1dB compression point of the overall power amplifier of the present invention;

[0026] Figure 4 It is the linearity diagram of the saturated output power of the present invention;

[0027] Figure 5 This is a linear graph of the peak power added efficiency of the present invention. Detailed implementation manners

[0028] The present invention will be further described below in conjunction with the accompanying drawings:

[0029] Embodiment:

[0030] A Doherty power amplifier circuit operates in a 28 GHz Doherty PA circuit. The power amplifier circuit includes: an input matching power splitting circuit and a double-stacked cascode circuit structure composed of a main PA, a auxiliary PA and an output matching synthesizer circuit.

[0031] The input matching power splitting circuit performs power distribution through filtering formed by passive components such as a first inductor L1, a first capacitor C1, a fourth inductor L4, and a fourth capacitor C4, and through input load matching.

[0032] The cascode circuit of the double-stacked transistors combines the main and auxiliary PA circuits using lumped elements. Both the main and auxiliary PAs adopt the cascode circuit structure of double-stacked transistors; by adjusting the different bias voltages of VG1' and VG2 / VG2', the operation of the main and auxiliary PAs is controlled to implement the Doherty technology, thereby improving the overall linearity and the efficiency with respect to the maximum output power back-off.

[0033] The synthesizer circuit uses lumped elements, optimizes the synthesizer of the traditional lumped element network, and proposes a new power synthesizer.

[0034] The Doherty PA circuit includes: a first NMOS transistor M1, a second NMOS transistor M2, a first NMOS transistor M1', a second NMOS transistor M2', a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a capacitor Cr, a capacitor Cg, a capacitor Cr', a capacitor Cg', a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, a first resistor R1, a second resistor R2, a first resistor R1', a second resistor R2';

[0035] The positive plate of the first capacitor C1 is connected to one end of the first inductor L1 and is connected to the IN of the main PA. The other end of the fourth inductor L1 is grounded. The negative plates of the first capacitor C1 and the fourth capacitor C4 are connected to the input RFIN, and RFIN is matched with a 50Ω resistor; the positive plate of the fourth capacitor C4 is connected to one end of the fourth inductor L4 and is connected to the IN of the auxiliary PA. The other end of the fourth inductor L4 is grounded.

[0036] The OUT of the main PA is connected to one end of the second inductor L2 and one end of the third inductor L3. The other end of the third inductor L3 is connected to the first voltage VDD1. The other end of the second inductor L2, the positive plate of the second capacitor C2, and the positive plate of the third capacitor C3 are connected together. The negative plate of the third capacitor C3 is grounded. The negative plate of the second capacitor C2, the negative plate of the fifth capacitor C5, and the output RFOUT are connected together. RFOUT is matched with a 50Ω resistor. The positive plate of the fifth capacitor C5, the positive plate of the sixth capacitor C6, and one end of the fifth inductor L5 are connected together. The negative plate of the sixth capacitor C6 is grounded. The other end of the fifth inductor L5 is connected to one end of the sixth inductor L6 and is also connected to the OUT of the auxiliary PA. The other end of the sixth inductor L6 is connected to the second voltage VDD2.

[0037] The source electrodes of the first NMOS transistors M1 / M1' of the main and auxiliary PAs are grounded. The drain electrodes of the first NMOS transistors M1 / M1' are connected to the source electrodes of the second NMOS transistors M2 / M2'. The drain electrodes of the second NMOS transistors M2 / M2' are respectively connected to the two input ends of the combiner. Then, through the output matching and combining circuit, the power is combined, realizing the topological function of the Doherty power amplifier. By the different working states of the main and auxiliary PAs, the power reduced by the class-B power amplifier is compensated, thereby improving the linearity of the overall power amplifier and also improving the back-off efficiency relative to the maximum output power.

[0038] Figure 3 The 1dB compression point of the overall power amplifier is about 20.7dBm, having high linearity. As can be seen from the figure, when the input signal is weak, there is a linear relationship between the output power of the power amplifier and the input signal power, and the gain is constant at this time. When the input signal power increases to a certain value, the gain begins to decrease, and the output power begins to deviate from the linear straight line. Figure 4 The saturated output power is 25.4dBm. Figure 5 The peak power added efficiency reaches 35.2%. This PA realizes low power consumption and high efficiency, achieving the design of a high-linearity and high-efficiency overall Doherty power amplifier.

Claims

1. A Doherty power amplifier circuit, characterized in that: A Doherty power amplifier circuit operating at 28 GHz, the power amplifier circuit comprising: an input matching power splitting circuit and a synthesizer circuit for output matching composed of a cascode circuit of double-stacked transistors for the main and auxiliary PAs; The input matching power splitting circuit performs power splitting through filtering formed by passive components such as the first inductor L1, the first capacitor C1, the fourth inductor L4, and the fourth capacitor C4, and through input load matching; The cascode circuit of the double-stacked transistors combines the main and auxiliary PA circuits using lumped elements, and both the main and auxiliary PAs adopt the cascode circuit structure of double-stacked transistors; the operation of the main and auxiliary PAs is controlled by adjusting the different bias voltages of VG1 / VG1' and VG2 / VG2'; The Doherty PA circuit includes: the first NMOS transistor M1, the second NMOS transistor M2, the first NMOS transistor M1', the second NMOS transistor M2', the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the capacitor Cr, the capacitor Cg, the capacitor Cr', the capacitor Cg', the first inductor L1, the second inductor L2, the electrical three inductor L3, the fourth inductor L4, the fifth inductor L5, the sixth inductor L6, the first resistor R1, the second resistor R2, the first resistor R1', and the second resistor R2'; The positive plate of the first capacitor C1 is connected to one end of the first inductor L1 and is connected to the IN of the main PA, the other end of the fourth inductor L1 is grounded, the negative plates of the first capacitor C1 and the fourth capacitor C4 are connected to the input RFIN, and RFIN is matched with a 50Ω resistor; the positive plate of the fourth capacitor C4 is connected to one end of the fourth inductor L4 and is connected to the IN of the auxiliary PA, and the other end of the fourth inductor L4 is grounded; The OUT of the main PA is connected to one end of the second inductor L2 and one end of the third inductor L3, the other end of the third inductor L3 is connected to the first voltage VDD1, the other end of the second inductor L2 and the positive plate of the second capacitor C2 are connected to the positive plate of the third capacitor C3, the negative plate of the third capacitor C3 is grounded, the negative plate of the second capacitor C2 is connected to the negative plate of the fifth capacitor C5 and the output RFOUT, and RFOUT is matched with a 50Ω resistor; the positive plate of the fifth capacitor C5 is connected to the positive plate of the sixth capacitor C6 and one end of the fifth inductor L5, the negative plate of the sixth capacitor C6 is grounded, the other end of the fifth inductor L5 is connected to one end of the sixth inductor L6 and is connected to the OUT of the auxiliary PA, and the other end of the sixth inductor L6 is connected to the second voltage VDD2.

2. The Doherty power amplifier circuit according to claim 1, characterized in that: The sources of the first NMOS transistors M1 / M1' of the main and auxiliary PAs are grounded, the drains of the first NMOS transistors M1 / M1' are connected to the sources of the second NMOS transistors M2 / M2', and the drains of the second NMOS transistors M2 / M2' are respectively connected to the two input ends of the synthesizer, and power synthesis is performed through the output matching synthesis circuit.

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