An NRZ code conversion circuit, conversion method, and NRZ code converter

Abstract

The application provides an NRZ code conversion circuit, a conversion method and an NRZ code converter, and the NRZ code conversion circuit comprises a first comparator, a second comparator, a first rising edge delay circuit, a second rising edge delay circuit and an OR gate, wherein: the first comparator and the second comparator are used for inputting a PAM signal; the input end of the first rising edge delay circuit is connected with the output end of the first comparator, and is used for delaying the rising edge of a first signal to obtain a second signal; the input end of the second rising edge delay circuit is connected with the output end of the second comparator, and is used for delaying the rising edge of a third signal to obtain a fourth signal; and the OR gate is used for outputting a target signal converted from the PAM signal. The application reduces the requirement for the input edge and the sensitivity of the circuit to the edge conversion time, and solves the problem that the period of the changed data after the long edge conversion NRZ is changed due to the slow PAM rising edge conversion time.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal processing, and particularly relates to an NRZ code conversion circuit, a conversion method and an NRZ code converter. BACKGROUND

[0002] In a standard 100BASE-T1 protocol, a three-level pulse amplitude modulation signal, i.e. a PAM3 (Pulse Amplitude Modulation) signal, is transmitted. The PAM3 signal has three levels of -1, 0 and 1. In order to recover a signal clock from the three-level data at the time of reception, the PAM3 signal needs to be converted into a double-level non-return-to-zero signal, i.e. an NRZ (Non-Return-to-Zero) signal.

[0003] Figure 1 A PAM3 waveform diagram in the prior art actual transmission can be referred to as shown in Figure 1 The conversion edges of adjacent levels of the PAM3 signal are called short edges, i.e. four edges of 0 to 1, 0 to -1, 1 to 0 and -1 to 0. At this time, the converted NRZ is called a short edge conversion output signal. The conversion edges of non-adjacent levels of the PAM3 signal are called long edges, i.e. two edges of 1 to -1 and -1 to 1. At this time, the converted NRZ is called a long edge conversion output signal. When conversion is performed through a PAM3-NRZ signal conversion circuit, the edge period of the converted NRZ signal needs to correctly reflect the clock edge period of the PAM3 signal.

[0004] Figure 2 A PAM3-NRZ conversion circuit diagram in the prior art can be referred to as shown in Figure 2 As shown in Figure 2As shown, the traditional signal conversion method is to input the PAM3 signal to the input ends of two comparators (for ease of description, the two comparators are named as comparator A and comparator B), the comparator A is used to extract the PAM3 signal edges of -1 to 1, 0 to 1, 1 to 0, 1 to -1, and the comparator B is used to extract the PAM3 signal edges of -1 to 1, 0 to -1, -1 to 0, 1 to -1, the output ends of the comparator A and the comparator B are electrically connected with the same OR gate, and the output signal of the OR gate after performing the OR logic operation is the NRZ signal. In the existing conversion circuit, the conversion of the NRZ signal is extremely susceptible to the long edge of the PAM3 signal between the two comparators, and the conversion time of the OR gate to the PAM3 signal edge is very short in order to convert the PAM3 signal into the NRZ signal, which is extremely harsh. Once the conversion time of the long edge of the PAM3 signal becomes slow, the intersection point level of the output edges of the two comparators will be lower than the high-low level threshold vth of the OR gate, a negative pulse signal is obtained, that is, a long edge is converted into two edges, that is, the NRZ signal actually converts the long edge of the PAM3 signal twice, which changes the period of the data. However, in order to reduce the electromagnetic interference (Electromagnetic Interference, EMI for short) problem, the edge conversion time of the transmitted three-level pulse signal cannot be too fast, and at the same time, due to the attenuation of the matching circuit, the common mode choke (CMC for short) circuit, the ESD (Electro Static Discharge) circuit and the twisted pair on the channel path, the edge conversion time of the received three-level pulse signal is not fixed, and is even further increased. Therefore, in order to avoid the conversion of the long edge of the PAM3 signal changing the clock period of the NRZ signal, there is an urgent need for an NRZ code conversion circuit, a conversion method and an NRZ code converter to solve the above problems. SUMMARY

[0005] In view of the problems in the prior art, the present application provides an NRZ code conversion circuit, a conversion method and an NRZ code converter.

[0006] The present application provides an NRZ code conversion circuit, comprising a first comparator, a second comparator, a first rising edge delay circuit, a second rising edge delay circuit and an OR gate, wherein:

[0007] The first comparator and the second comparator are used to input a PAM signal to be converted;

[0008] The input end of the first rising edge delay circuit is connected with the output end of the first comparator, and is used to delay the rising edge of a first signal to obtain a second signal, wherein the first signal is the PAM signal to be converted, which is output by the first comparator after being input to the first comparator.

[0009] The input end of the second rising edge delaying circuit is connected with the output end of the second comparator, for delaying the rising edge of the third signal to obtain a fourth signal, wherein the third signal is the PAM signal to be converted, and the signal output by the second comparator after inputting the PAM signal to be converted;

[0010] The OR gate is used for outputting a target signal converted from the PAM signal, wherein the target signal is an NRZ signal converted from the second signal and the fourth signal after passing through the OR gate.

[0011] According to the present application, an NRZ code conversion circuit is provided, and the NRZ code conversion circuit further comprises a first shaping circuit and a second shaping circuit, wherein:

[0012] The input end of the first shaping circuit is connected with the output end of the first rising edge delaying circuit, for inverting the second signal to obtain a fifth signal;

[0013] The input end of the second shaping circuit is connected with the output end of the second rising edge delaying circuit, for inverting the fourth signal to obtain a sixth signal;

[0014] The output ends of the first shaping circuit and the second shaping circuit are connected with the input ends of the OR gate, so that the fifth signal and the sixth signal pass through the OR gate to generate an NRZ signal.

[0015] According to the present application, an NRZ code conversion circuit is provided, and the first rising edge delaying circuit comprises a first PMOS tube and a first NMOS tube, and the second rising edge delaying circuit comprises a second PMOS tube and a second NMOS tube, wherein:

[0016] The gate of the first PMOS tube and the first NMOS tube is connected with the output end of the first comparator, and the drain of the first PMOS tube is connected with the drain of the first NMOS tube;

[0017] The gate of the second PMOS tube and the second NMOS tube is connected with the output end of the second comparator, and the drain of the second PMOS tube is connected with the drain of the second NMOS tube;

[0018] The signals output by the first comparator and the second comparator are sent to the OR gate through the drains of the first PMOS tube and the first NMOS tube, and the drains of the second PMOS tube and the second NMOS tube.

[0019] According to the NRZ code conversion circuit provided by the application, the first shaping circuit comprises a third PMOS tube and a third NMOS tube, the second shaping circuit comprises a fourth PMOS tube and a fourth NMOS tube, wherein:

[0020] The gate of the third PMOS tube and the third NMOS tube is connected to the output end of the first rising delay circuit, and the drain of the third PMOS tube and the third NMOS tube is connected to the input end of the OR gate.

[0021] The gate of the fourth PMOS tube and the fourth NMOS tube is connected to the output end of the second rising delay circuit, and the drain of the fourth PMOS tube and the fourth NMOS tube is connected to the input end of the OR gate.

[0022] According to the NRZ code conversion circuit provided by the application, the width-length ratio of the first PMOS tube and the second PMOS tube is less than a first preset width-length ratio threshold and greater than a second preset width-length ratio threshold, wherein the first preset width-length ratio threshold and the second preset width-length ratio threshold are both less than 1.

[0023] The application further provides an NRZ code conversion method based on any of the above-mentioned NRZ code conversion circuits, comprising:

[0024] The PAM signal to be converted is input into the first comparator and the second comparator respectively to obtain a first signal and a third signal, wherein the first signal is the PAM signal to be converted, and the signal output by the first comparator after the PAM signal to be converted is input into the first comparator; the third signal is the PAM signal to be converted, and the signal output by the second comparator after the PAM signal to be converted is input into the second comparator;

[0025] The rising edge of the first signal is delayed by the first rising edge delay circuit to obtain a second signal, and the rising edge of the third signal is delayed by the second rising edge delay circuit to obtain a fourth signal.

[0026] The second signal and the fourth signal are input into the OR gate to obtain an NRZ signal.

[0027] According to the NRZ code conversion method provided by the application, before the second signal and the fourth signal are input into the OR gate to obtain an NRZ signal, the method further comprises:

[0028] The second signal and the fourth signal are respectively inverted to obtain an inverted second signal and an inverted fourth signal.

[0029] The inverted second signal and the inverted fourth signal are input into the OR gate to obtain an NRZ signal.

[0030] The application also provides an NRZ code converter, which comprises the above-mentioned NRZ code conversion circuit.

[0031] The NRZ code conversion circuit, conversion method and NRZ code converter provided by the application can reduce the sensitivity to the conversion time of the input PAM code edge when converting the NRZ code by setting the rising edge delaying circuit, and further eliminate the NRZ conversion error caused by the long edge PAM code; compared with the prior art, the application is controllable, simple and feasible, reduces the strict requirement of the prior art on the input edge and the sensitivity of the circuit to the edge conversion time, and solves the problem of changing the data cycle after converting the NRZ code due to the slow rising edge conversion time of the PAM. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1 PAM3 waveform schematic diagram in prior art actual transmission;

[0034] Figure 2 PAM3-NRZ conversion circuit schematic diagram in prior art;

[0035] Figure 3 PAM3 signal conversion circuit in prior art when converting the PAM3 signal waveform schematic diagram of output signal of each module;

[0036] Figure 4 Comparator output comparison schematic diagram in prior art;

[0037] Figure 5 NRZ code conversion circuit structure schematic diagram provided by the application;

[0038] Figure 6 Rising edge delaying circuit and shaping circuit circuit structure schematic diagram provided by the application;

[0039] Figure 7 NRZ code conversion circuit overall structure schematic diagram provided by the application;

[0040] Figure 8 Rising edge delaying circuit and shaping circuit processing waveform schematic diagram provided by the application;

[0041] Figure 9A schematic diagram of the signal waveform after processing by the rising edge delay circuit and the shaping circuit provided by the present invention;

[0042] Figure 10 This is a flowchart illustrating the NRZ code conversion method provided by the present invention.

[0043] Figure 11 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0045] Figure 3 The diagram below shows the waveforms of the output signals of each module in the existing signal conversion circuit when converting PAM3 signals. This can be used as a reference. Figure 1 and Figure 3 As shown, part A represents the waveform of the output signal of comparator A in the existing signal conversion circuit, part B represents the waveform of the output signal of comparator B in the existing signal conversion circuit, and part C represents the waveform of the output signal of the OR gate in the existing signal conversion circuit. (For reference...) Figure 3 As shown, when using the existing signal conversion method, when the short edges of the input PAM3 signal change from 1 to 0 and from 0 to 1, the output of comparator A changes, while the output of comparator B remains unchanged; when the short edges of the PAM3 signal change from -1 to 0 and from 0 to -1, the output of comparator B changes, while the output of comparator A remains unchanged; however, when the long edges of the PAM3 signal change from 1 to -1 and from -1 to 1, the outputs of both comparator A and comparator B change.

[0046] Therefore, the conversion of the NRZ signal is extremely susceptible to the long edge of the PAM3 signal between the two comparators, and the conversion time of the OR gate for converting the PAM3 signal into the NRZ signal is extremely short and extremely harsh. Once the conversion time of the long edge of the PAM3 signal is slow, the crossing point level of the output edges of the two comparators is lower than the high-low level threshold vth of the OR gate, thereby obtaining a negative pulse signal, that is, a long edge is converted into two edges, that is, the NRZ signal actually converts the long edge of the PAM3 signal twice, resulting in a change in the period of the data. However, in order to reduce the EMI problem, the edge conversion time of the transmitted three-level pulse signal cannot be too fast, and at the same time, due to the attenuation of the matching circuit, the CMC circuit, the ESD circuit and the twisted pair on the channel path, the edge conversion time of the received three-level pulse signal is not fixed, and is even further increased.

[0047] In order to avoid the above situation, the prior art proposes that one of the comparators always outputs 0, for example, comparator B continuously outputs 0, and then the obtained NRZ signal is converted by the signal output by comparator A. However, the NRZ signal can also be converted by the two PAM3 signal edges of -1 to 1 and 0 to 1, and the edge of -1 to 1 belongs to the long edge of the PAM3 signal, and the edge of 0 to 1 belongs to the short edge of the PAM3 signal. The conversion time of the two is different, and the duty cycle output by comparator A is also different. Therefore, the NRZ signal converted in this way becomes a signal composed of two different duty cycles, and the signal conversion method has not been improved from the root.

[0048] Reference can be made to Figure 3 As shown in the figure, when the input is a short edge, only one comparator outputs an edge signal; when the input is a long edge, both comparators output an edge signal. For example, when the input is -1 to 1, the rising edge signal output by comparator A reaches the logic high level at t2, and the falling edge signal output by comparator B reaches the logic high level at t1. Similarly, when the input is 1 to -1, the falling edge signal output by comparator A reaches the logic high level at t3, and the rising edge signal output by comparator B reaches the logic high level at t4. Figure 4 For the output comparison diagram of the comparator in the prior art, reference can be made to Figure 4As shown, when t2 is close to t1, the falling edge of the output of the comparator B intersects with the rising edge of the output of the comparator A at the level of point M, which is higher than the judgment threshold vth of the logic high and low; similarly, when t4 is close to t3, the falling edge of the output of the comparator A intersects with the rising edge of the output of the comparator B at the level of point N, which is higher than the judgment threshold vth of the logic high and low, at this time, the output of the OR operation is high, eliminating the long edge conversion output signal. But when the input edge becomes slow, the distance between t2 and t1 increases, the level of point M is lower than the judgment threshold vth of the logic high and low, the distance between t4 and t3 increases, the level of point N is lower than the judgment threshold vth of the logic high and low, at this time, the output of the OR operation is low pulse, that is, two edges appear. That is, the obtained NRZ signal is actually converted twice from the long edge of the PAM3 signal, which changes the period of the data.

[0049] Therefore, in order to avoid the conversion of the long edge of the PAM3 signal changing the clock period of the NRZ signal, and to eliminate the problem of different duty cycles of the NRZ signal caused by the different conversion times of the long edge and the short edge of the PAM3 signal, the application provides a conversion circuit for converting the PAM code to the NRZ code which is not sensitive to the edge conversion time, by setting the rising edge delay circuit and the shaping circuit, the duty cycle of the output signal of the comparator is improved, and then the output signal converted from the long edge (-1 to 1 and 1 to -1) of the PAM3 signal is removed by the OR operation, thereby eliminating the problem of changing the period of the data caused by the long edge conversion of the NRZ signal due to the slow rising edge of the PAM, and at the same time, since only the short edge conversion output signal is left, the problem of different duty cycles caused by the different conversion times of the long edge and the short edge of the PAM is also eliminated.

[0050] Figure 5 The structure diagram of the NRZ code conversion circuit provided by the application is shown as Figure 5 The application provides an NRZ code conversion circuit, which comprises a first comparator 501, a second comparator 502, a first rising edge delay circuit 503, a second rising edge delay circuit 504 and an OR gate 505, wherein:

[0051] The first comparator 501 and the second comparator 502 are used for inputting the PAM signal to be converted.

[0052] In the application, the anode input end of the first comparator 501 and the cathode input end of the second comparator 502 are used for inputting the PAM signal to be converted, the cathode input end of the first comparator 501 is used for inputting a first preset threshold level, and the anode input end of the second comparator 502 is used for inputting a second preset threshold level, wherein the first preset threshold level is greater than the second preset threshold level, that is, the first preset threshold level is a high threshold level VH, and the second preset threshold level is a low threshold level VL.

[0053] The input end of the first rising edge delaying circuit 503 is connected with the output end of the first comparator 501, for delaying the rising edge of the first signal, to obtain the second signal, wherein the first signal is the PAM signal to be converted, and the signal output by the first comparator 501 after inputting the first signal;

[0054] The input end of the second rising edge delaying circuit 504 is connected with the output end of the second comparator 502, for delaying the rising edge of the third signal, to obtain the fourth signal, wherein the third signal is the PAM signal to be converted, and the signal output by the second comparator 502 after inputting the third signal.

[0055] In the present application, the rising edge delaying circuit is used to convert the signal output by the traditional comparator into a rising edge delaying waveform, so that the rising edge of the signal output from the rising edge delaying circuit is delayed after the signal output by the comparator passes through the rising edge delaying circuit, thereby prolonging the time of logic low, and solving the problem of changing the data period after converting the long edge PAM into NRZ due to the slow rising edge of the PAM.

[0056] The OR gate 505 is used to output the target signal converted from the PAM signal, and the target signal is an NRZ signal converted from the second signal and the fourth signal after passing through the OR gate 505.

[0057] In the present application, the signal input into the OR gate is an NRZ signal after the logic operation of the OR gate.

[0058] The NRZ code conversion circuit provided by the present application can reduce the sensitivity to the input PAM code edge conversion time when converting the NRZ code by setting the rising edge delaying circuit, and further eliminate the NRZ conversion error caused by the corresponding long edge PAM code; compared with the prior art, the present application is controllable, simple and feasible, reduces the harsh requirements of the prior art on the input edge and the sensitivity of the circuit to the edge conversion time, thereby solving the problem of changing the data period after converting the long edge PAM into NRZ due to the slow rising edge conversion time of the PAM.

[0059] On the basis of the above embodiment, the first rising edge delaying circuit comprises a first PMOS tube and a first NMOS tube, and the second rising edge delaying circuit comprises a second PMOS tube and a second NMOS tube, wherein:

[0060] The gate of the first PMOS tube and the first NMOS tube is connected with the output end of the first comparator, and the drain of the first PMOS tube is connected with the drain of the first NMOS tube.

[0061] a gate of the second PMOS transistor and a gate of the second NMOS transistor are connected to an output terminal of the second comparator, and a drain of the second PMOS transistor and a drain of the second NMOS transistor are connected to each other;

[0062] The signals output by the first comparator and the second comparator are transmitted to the OR gate through the drains of the first PMOS transistor and the first NMOS transistor and the drains of the second PMOS transistor and the second NMOS transistor.

[0063] Preferably, in order to eliminate the problem of different duty cycles caused by different conversion times of long edges and short edges of PAM, on the basis of the above-mentioned embodiments, the NRZ code conversion circuit further comprises a first shaping circuit and a second shaping circuit, wherein:

[0064] The input terminal of the first shaping circuit is connected to the output terminal of the first rising edge delay circuit, and is used for inverting the second signal to obtain a fifth signal;

[0065] The input terminal of the second shaping circuit is connected to the output terminal of the second rising edge delay circuit, and is used for inverting the fourth signal to obtain a sixth signal;

[0066] The output terminals of the first shaping circuit and the second shaping circuit are connected to the input terminals of the OR gate, so that the fifth signal and the sixth signal generate an NRZ signal through the OR gate.

[0067] Specifically, the first shaping circuit comprises a third PMOS transistor and a third NMOS transistor, and the second shaping circuit comprises a fourth PMOS transistor and a fourth NMOS transistor, wherein:

[0068] The gates of the third PMOS transistor and the third NMOS transistor are connected to the output terminal of the first rising delay circuit, and the drains of the third PMOS transistor and the third NMOS transistor are connected to the input terminals of the OR gate;

[0069] The gates of the fourth PMOS transistor and the fourth NMOS transistor are connected to the output terminal of the second rising delay circuit, and the drains of the fourth PMOS transistor and the fourth NMOS transistor are connected to the input terminals of the OR gate.

[0070] In the present application, Figure 6 The circuit structure diagram of the rising edge delay circuit and the shaping circuit provided by the present application is as follows: Figure 6The circuit structure of the first rising edge delaying circuit and the first shaping circuit is shown in the figure, and the circuit structure of the second rising edge delaying circuit and the second shaping circuit can be referred to the following description. Specifically, the output terminal of the first comparator is connected to the gate of a first PMOS tube (i.e. MP1) and the gate of a first NMOS tube (i.e. MN1), the drain of the first PMOS tube is connected to the drain of the first NMOS tube and the gate of a third PMOS tube (i.e. MP2) and a third NMOS tube (i.e. MN2), the source of the first PMOS tube and the third PMOS tube is connected to a direct current power supply, the drain of the third PMOS tube and the third NMOS tube is connected to the input terminal of an OR gate, and the source of the first NMOS tube and the third NMOS tube is grounded.

[0071] Figure 7 The overall structure schematic diagram of the NRZ code conversion circuit provided by the present application can be referred to Figure 7 As shown in the figure, in the present application, the PAM3 signal Vin is input to the positive terminal of comparator 1 (i.e. the first comparator) and the negative terminal of comparator 2 (i.e. the second comparator) respectively. The negative terminal of comparator 1 is connected to a high threshold level VH (i.e. the first preset threshold level), and the positive terminal of comparator 2 is connected to a low threshold level VL (i.e. the second preset threshold level). When the PAM3 signal is input to comparator 1 and comparator 2 respectively, at this time, comparator 1 outputs signal 1 (i.e. the first signal), and comparator 2 outputs signal 4 (i.e. the second signal). Figure 8 The waveform schematic diagram processed by the rising edge delaying circuit and the shaping circuit provided by the present application can be referred to Figure 7 and Figure 8 As shown in the figure, the signal output by the first comparator is described. In the present application, signal 1 passes through the rising edge delaying circuit to obtain signal 2, and the rising edge of signal 2 is delayed, so that the time of logic low is prolonged, and then the inverse of the shaping circuit is passed through, so as to obtain signal 3, and the level holding time of logic high is increased, and Figure 8 It can be seen that the duty cycle of signal 3 output by the shaping circuit is improved compared with signal 1.

[0072] Specifically, the input signal in Figure 3 is taken as an example for description, and the signal in Figure 3 is input to the NRZ code conversion circuit of the present application (i.e. the NRZ code conversion circuit in Figure 6 ), and the signals obtained at each stage can be referred to Figure 9 As shown in the figure, Figure 9 The signal waveform schematic diagram processed by the rising edge delaying circuit and the shaping circuit provided by the present application is shown in the figure. As Figure 9As shown, the high level holding time of signal 3 is t3-t2, which is increased to t5-t2, and the increase is t5-t3. In this embodiment, t5 needs to be greater than t4, i.e. the rising edge of the long-edge conversion output waveform of signal 6 (the sixth signal output by the second shaping circuit) corresponds in time to the high level of signal 3, and the falling edge of the long-edge conversion output waveform of signal 3 corresponds in time to the high level of signal 6.

[0073] Similarly, signal 4 (i.e. the signal output by the second comparator) is input to the second rising edge delay circuit to obtain signal 5 (i.e. the fourth signal output by the second rising edge delay circuit), and signal 5 is input to the second shaping circuit to obtain signal 6. Figure 9 The high level holding time of signal 6 is increased to t6-t1. In this embodiment, t6 needs to be greater than t2, i.e. the falling edge of the long-edge conversion output waveform of signal 6 corresponds in time to the high level of signal 3, and the rising edge of the long-edge conversion output waveform of signal 3 corresponds in time to the high level of signal 6.

[0074] Finally, signal 3 and signal 6 are input to the OR gate to output Vout as an NRZ signal. In this embodiment, the edges of the long-edge conversion output waveforms of signal 3 and signal 6 correspond in time to the high levels of the other, so the result of the OR operation is high, and the edges of the long-edge conversion output waveforms are eliminated, while the edges of the short-edge conversion output waveforms are retained.

[0075] On the basis of the above embodiment, the width-length ratio of the first PMOS transistor and the second PMOS transistor is less than a first preset width-length ratio threshold and greater than a second preset width-length ratio threshold, wherein the first preset width-length ratio threshold and the second preset width-length ratio threshold are both less than 1.

[0076] In the application, the PMOS tubes (i.e. the first PMOS tube and the second PMOS tube) in the first rising edge delaying circuit and the second rising edge delaying circuit are P tubes with low width-length ratio (the width-length ratio is the ratio between the width and the length of the conductive channel in the MOS tube) to increase the charging time to delay the rising edge, and the NMOS tubes (i.e. the first NMOS tube and the second NMOS tube) in the first rising edge delaying circuit and the second rising edge delaying circuit are N tubes with normal width-length ratio; the PMOS tubes (i.e. the third PMOS tube and the fourth PMOS tube) and the NMOS tubes (i.e. the third NMOS tube and the fourth NMOS tube) in the first shaping circuit and the second shaping circuit are composed of P tubes with normal width-length ratio and N tubes with normal width-length ratio to restore the normal waveform. Since the edge transition time of the PAM is in positive relationship with the delay value of the delaying circuit, when the corresponding input edge is delayed, the delay value of the delaying circuit needs to be increased, therefore, the width-length ratio of the PMOS tubes in the first rising edge delaying circuit and the second rising edge delaying circuit is reduced in the application, so that the width-length ratio is less than the first preset width-length ratio threshold and greater than the second preset width-length ratio threshold, by setting a high threshold (i.e. the first preset width-length ratio threshold), the long edge transition time can be eliminated, but if the width-length ratio of the PMOS tubes in the first rising edge delaying circuit and the second rising edge delaying circuit is low enough, the short edge transition time can also be eliminated, therefore, a low threshold (i.e. the second preset width-length ratio threshold) also needs to be set, that is, the low threshold < the width-length ratio < the high threshold, so that by adjusting the delay value of the delaying circuit, the sensitivity of the NRZ code to the input PAM code edge transition time can be reduced, and then the NRZ conversion error caused by the corresponding long edge PAM code can be eliminated. Taking the input rising edge of 10 ns as an example, the ratio between the width and the length of the conductive channel corresponding to the first preset width-length ratio threshold and the second preset width-length ratio threshold is less than 1, that is, the width of the conductive channel is less than the length in the two preset thresholds, for example, the first preset width-length ratio threshold can be set as 1u / 4u, and the second preset width-length ratio threshold can be set as 1u / 30u, and the common size of the existing PMOS tube is 2u / 0.18u.

[0077] Figure 10 The flowchart of the NRZ code conversion method provided by the application is shown in Figure 10 The application provides an NRZ code conversion method, which comprises the following steps:

[0078] In step 1001, the PAM signal to be converted is input into a first comparator and a second comparator respectively to obtain a first signal and a third signal, wherein the first signal is the PAM signal to be converted, and the signal output by the first comparator after the PAM signal to be converted is input into the first comparator; the third signal is the PAM signal to be converted, and the signal output by the second comparator after the PAM signal to be converted is input into the second comparator;

[0079] Step 1002, the rising edge of the first signal is delayed by a first rising edge delay circuit to obtain a second signal; the rising edge of the third signal is delayed by a second rising edge delay circuit to obtain a fourth signal;

[0080] Step 1003, the second signal and the fourth signal are input into an OR gate to obtain an NRZ signal.

[0081] In the present application, the signal output by the existing comparator is converted into a rising edge delay waveform by using a rising edge delay circuit, so that the rising edge of the signal output from the rising edge delay circuit is delayed after the signal output by the comparator passes through the rising edge delay circuit, thereby prolonging the time of logic low and solving the problem of changing the data period after long edge conversion NRZ caused by slow PAM rising edge.

[0082] The NRZ code conversion method provided by the present application can reduce the sensitivity to the input PAM code edge conversion time when converting NRZ code, and further eliminate the NRZ conversion error caused by the corresponding long edge PAM code; compared with the prior art, the present application is controllable, simple and feasible, reduces the harsh requirements of the prior art on the input edge and the sensitivity of the circuit to the edge conversion time, thereby solving the problem of changing the data period after long edge conversion NRZ caused by slow PAM rising edge conversion time.

[0083] On the basis of the above embodiment, before the second signal and the fourth signal are input into the OR gate to obtain the NRZ signal, the method further comprises:

[0084] The second signal and the fourth signal are respectively inverted to obtain an inverted second signal and an inverted fourth signal;

[0085] The inverted second signal and the inverted fourth signal are input into the OR gate to obtain the NRZ signal.

[0086] In the present application, in order to avoid the conversion of the long edge of the PAM3 signal changing the clock period of the NRZ signal, and at the same time, in order to eliminate the problem of different conversion times of the long edge of the PAM3 signal and the short edge of the PAM3 signal causing different duty cycles of the NRZ signal, the signal output by the existing comparator is converted into a rising edge delay waveform by using a rising edge delay circuit, and then the duty cycle of the signal after rising edge delay is improved by using a shaping circuit, so that the two shaped signals obtained are subjected to OR operation to output a Vout signal, which is not sensitive to the edge conversion time of the input signal.

[0087] The application further provides an NRZ code converter comprising the NRZ code conversion circuit provided by each of the above embodiments.

[0088] The NRZ code converter provided by the application can reduce the sensitivity to the conversion time of the input PAM code edge when converting the NRZ code by setting the rising edge delay circuit, and further eliminate the NRZ conversion error caused by the corresponding long edge PAM code; compared with the prior art, the application is controllable, simple and feasible, reduces the strict requirement of the prior art on the input edge and the sensitivity of the circuit to the edge conversion time, thereby solving the problem of changing the data cycle after converting the NRZ code due to the slow rising edge conversion time of the PAM. Meanwhile, the duty cycle of the signal after the rising edge delay can be improved by using the shaping circuit, thereby further eliminating the problem of different duty cycles caused by the different conversion times of the long edge and short edge of the PAM.

[0089] Figure 11 The electronic device provided by the application has the structure as shown in the accompanying drawings, Figure 11 As shown in the accompanying drawings, the electronic device can include a processor 1101, a communications interface 1102, a memory 1103 and a communications bus 1104, wherein the processor 1101, the communications interface 1102 and the memory 1103 complete the communication with each other through the communications bus 1104. The processor 1101 can call the logical instructions in the memory 1103 to execute the NRZ code conversion method, which includes: inputting the PAM signal to be converted into a first comparator and a second comparator respectively to obtain a first signal and a third signal, wherein the first signal is the PAM signal to be converted, and the signal output by the first comparator after the PAM signal to be converted is input into the first comparator; the third signal is the PAM signal to be converted, and the signal output by the second comparator after the PAM signal to be converted is input into the second comparator; delaying the rising edge of the first signal through a first rising edge delay circuit to obtain a second signal; delaying the rising edge of the third signal through a second rising edge delay circuit to obtain a fourth signal; inputting the second signal and the fourth signal into an OR gate to obtain an NRZ signal.

[0090] In addition, the logic instructions in the memory 1103 described above can be implemented in the form of a software function unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0091] In another aspect, the present application also provides a computer program product, which comprises a computer program stored on a non-transitory computer readable storage medium, and the computer program comprises program instructions, when the program instructions are executed by a computer, the computer can execute the NRZ conversion method provided by the above-mentioned method, and the method comprises: inputting a PAM signal to be converted into a first comparator and a second comparator respectively to obtain a first signal and a third signal, wherein the first signal is the PAM signal to be converted, and the signal output by the first comparator after inputting the first signal into the first comparator; the third signal is the PAM signal to be converted, and the signal output by the second comparator after inputting the third signal into the second comparator; delaying the rising edge of the first signal through a first rising edge delay circuit to obtain a second signal; delaying the rising edge of the third signal through a second rising edge delay circuit to obtain a fourth signal; inputting the second signal and the fourth signal into an OR gate to obtain an NRZ signal.

[0092] In yet another aspect, the present application also provides a non-transitory computer readable storage medium having stored thereon a computer program, which, when executed by a processor, implements the NRZ conversion method provided by any of the above embodiments, and the method comprises: inputting a PAM signal to be converted into a first comparator and a second comparator respectively to obtain a first signal and a third signal, wherein the first signal is the PAM signal to be converted, and the first signal is output by the first comparator after being input into the first comparator; the third signal is the PAM signal to be converted, and the third signal is output by the second comparator after being input into the second comparator; delaying the rising edge of the first signal through a first rising edge delay circuit to obtain a second signal; delaying the rising edge of the third signal through a second rising edge delay circuit to obtain a fourth signal; inputting the second signal and the fourth signal into an OR gate to obtain an NRZ signal.

[0093] The apparatus embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment scheme according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0094] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software plus necessary general hardware platforms, and of course can also be realized by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0095] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An NRZ code conversion circuit, characterized in that, It includes a first comparator, a second comparator, a first rising edge delay circuit, a second rising edge delay circuit, and an OR gate, wherein: The first comparator and the second comparator are used to input the PAM signal to be converted; The input terminal of the first rising edge delay circuit is connected to the output terminal of the first comparator, and is used to delay the rising edge of the first signal to obtain the second signal. The first signal is the signal output by the first comparator after the PAM signal to be converted is input to the first comparator. The input of the second rising edge delay circuit is connected to the output of the second comparator, and is used to delay the rising edge of the third signal to obtain the fourth signal. The third signal is the signal output by the second comparator after the PAM signal to be converted is input to the second comparator. The OR gate is used to output the target signal converted from the PAM signal. The target signal is the NRZ signal converted from the second signal and the fourth signal after passing through the OR gate. The NRZ code conversion circuit further includes a first shaping circuit and a second shaping circuit, wherein: The input terminal of the first shaping circuit is connected to the output terminal of the first rising edge delay circuit, and is used to invert the second signal to obtain the fifth signal; The input terminal of the second shaping circuit is connected to the output terminal of the second rising edge delay circuit, and is used to invert the fourth signal to obtain the sixth signal; The output terminals of the first shaping circuit and the second shaping circuit are connected to the input terminal of the OR gate, so that the fifth signal and the sixth signal are generated into an NRZ signal through the OR gate.

2. The NRZ code conversion circuit according to claim 1, characterized in that, The first rising edge delay circuit includes a first PMOS transistor and a first NMOS transistor, and the second rising edge delay circuit includes a second PMOS transistor and a second NMOS transistor, wherein: The gates of the first PMOS transistor and the first NMOS transistor are connected to the output terminal of the first comparator, and the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The gates of the second PMOS transistor and the second NMOS transistor are connected to the output terminal of the second comparator, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. The signals output by the first comparator and the second comparator are sent to the OR gate through the drains of the first PMOS transistor and the first NMOS transistor, and the drains of the second PMOS transistor and the second NMOS transistor.

3. The NRZ code conversion circuit according to claim 1, characterized in that, The first shaping circuit includes a third PMOS transistor and a third NMOS transistor, and the second shaping circuit includes a fourth PMOS transistor and a fourth NMOS transistor, wherein: The gates of the third PMOS transistor and the third NMOS transistor are connected to the output of the first rising edge delay circuit, and the drains of the third PMOS transistor and the third NMOS transistor are connected to the input of the OR gate. The gates of the fourth PMOS transistor and the fourth NMOS transistor are connected to the output of the second rising edge delay circuit, and the drains of the fourth PMOS transistor and the fourth NMOS transistor are connected to the input of the OR gate.

4. The NRZ code conversion circuit according to claim 2, characterized in that, The width-to-length ratio of the first PMOS transistor and the second PMOS transistor is less than a first preset width-to-length ratio threshold and greater than a second preset width-to-length ratio threshold, wherein both the first preset width-to-length ratio threshold and the second preset width-to-length ratio threshold are less than 1.

5. An NRZ code conversion method based on the NRZ code conversion circuit according to any one of claims 1 to 4, characterized in that, include: The PAM signal to be converted is input to a first comparator and a second comparator respectively to obtain a first signal and a third signal. The first signal is the signal output by the first comparator after the PAM signal to be converted is input to the first comparator; the third signal is the signal output by the second comparator after the PAM signal to be converted is input to the second comparator. The rising edge of the first signal is delayed by a first rising edge delay circuit to obtain a second signal; the rising edge of the third signal is delayed by a second rising edge delay circuit to obtain a fourth signal. The second signal and the fourth signal are input into an OR gate to obtain the NRZ signal.

6. The NRZ code conversion method according to claim 5, characterized in that, Before inputting the second signal and the fourth signal into an OR gate to obtain the NRZ signal, the method further includes: The second signal and the fourth signal are respectively inverted to obtain the inverted second signal and the inverted fourth signal; The second signal and the fourth signal after inversion are input into the OR gate to obtain the NRZ signal.

7. An NRZ code converter, characterized in that, The NRZ code converter includes the NRZ code conversion circuit as described in any one of claims 1 to 4.

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