Interface Circuit, Protection Method for Interface Circuit, and Terminal Device

By introducing switching units and isolation resistors into the interface circuit, the device burning problem caused by short circuits of multiplexed function pins and power input pins in the mobile device interface is solved, and the normal use and protection of the interface is achieved.

CN114124079BActive Publication Date: 2025-07-25HUAWEI TECH CO LTD
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Patent Information

Application Number
CN202010906577.4
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2020-08-31
Publication Date
2025-07-25
Estimated Expiration
2040-08-31

AI Technical Summary

Technical Problem

In the interface of a mobile device, when the multiplex function pin is short-circuited with the power input pin, the device will burn, affecting the normal use of the interface.

Method used

The switching unit, power input terminal, function pin, control signal input terminal, detection port, ground output terminal and isolation resistor are introduced into the interface circuit. The switching unit is protected in the short circuit through the on-off device to avoid current overload.

Benefits of technology

Effectively protect the switching unit from being burned by the high voltage during short circuit, ensure the normal use of the interface and do not affect the normal operation of the switching chip.

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Abstract

This application is applicable to the field of terminal technologies, and provides an interface circuit, a protection method for the interface circuit, and a terminal device. The interface circuit includes: a switching unit, a power input terminal, a first functional pin, a second functional pin, a control signal input terminal, a detection port, a ground output terminal, a first resistor, a second resistor, a third resistor, a fourth resistor, and a switching device. Since the first resistor, the second resistor, the third resistor, and the fourth resistor are respectively connected in series as isolation resistors on their respective paths, when a short circuit occurs, the current flowing through the switching unit is less than the burnout current of the switching unit. And when the switching unit is not working, the ground output terminal of the switching unit is suspended through the switching device, so that the switching unit is in a floating state when not working and will not be burned by the voltage input during a short circuit, ensuring the normal use of the interface.
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Description

Technical Field

[0001] This application relates to the field of terminals, and in particular, to an interface circuit, a protection method for the interface circuit, and a terminal device. Background Art

[0002] Currently, the interfaces of mobile devices can generally be multiplexed. For example, it can be used as a headphone interface and also as a charging interface. For example, taking the Universal Serial Bus Type-c (Type-c) interface as an example, when a headphone is connected through the Type-c interface, this interface is the headphone interface; when a data cable is connected through the Type-c interface, this interface is the data port or the charging interface.

[0003] When the interface of a mobile device is multiplexed, pins for implementing the multiplexing function will be provided. For example, when a headphone is connected through the Type-c interface, the Sideband Use (SBU) pins of the Type-c interface can be used for multiplexing, and the microphone / ground (MIC / GND) switching of the headphone can be realized. Since there are no symmetric pins set for the SBU pins, in the prior art, a switch chip for MIC / GND is generally used to switch between MIC and GND to ensure that the headphone can be used normally regardless of whether it is plugged in correctly or reversely when the headphone is connected.

[0004] However, in the interface of a mobile device, the pins for implementing the multiplexing function may be adjacent to the power input pins. For example, in the Type-c port, the SBU1 pin and the SBU2 pin are respectively adjacent to the Vbus pin. During the use of the Type-c interface, corrosion or deformation may occur, causing the SBU1 pin and / or the SBU2 pin to be short-circuited with the Vbus pin. When a short circuit occurs and the Type-c interface is used for charging, the charging voltage will be input to the SBU1 pin and / or the SBU2 pin, resulting in the burning of the switch chip and affecting the normal use of the Type-c interface. Summary of the Invention

[0005] Embodiments of this application provide an interface circuit, a protection method for the interface circuit, and a terminal device, which can improve the problem that in the interface of a mobile device, if the pins for multiplexing function and the power input pins are short-circuited and charging is performed through the power input pins, the device connected to the pins for multiplexing function will be burned out, affecting the normal use of the interface.

[0006] In a first aspect, embodiments of this application provide an interface circuit. The interface circuit includes a switching unit, a power input terminal, a first function pin, a second function pin, a control signal input terminal, a detection port, a ground output terminal, a first resistor, a second resistor, a third resistor, a fourth resistor, and a switching device.

[0007] The switching unit includes a wire grounding GND terminal, a circuit power supply Vcc terminal, a first switching circuit, and a second switching circuit. Among them, the first switching circuit includes a first input terminal, a second input terminal, a first control terminal, and a first output terminal. The second switching circuit includes a third input terminal, a fourth input terminal, a second control terminal, and a second output terminal. The first output terminal is connected to the first functional pin, and the second output terminal is connected to the second functional pin. A first resistor is connected in series between the Vcc terminal and the power input terminal. One end of the second resistor is connected to the GND terminal, and the other end of the second resistor is grounded. One end of the third resistor is connected to the control signal input terminal, and the other end is connected to the first control terminal and the second control terminal. One end of the fourth resistor is connected to the detection port, and the other end is connected to the first input terminal and the third input terminal.

[0008] The on-off device includes: an input pin, a first on-off pin, and a second on-off pin. The input pin is connected to the power input terminal. The first on-off pin is respectively connected to the second input terminal and the fourth input terminal. The second on-off pin is grounded and connected to the ground output terminal. When a low level is input to the input pin, the first on-off pin is disconnected from the second on-off pin. When a high level is input to the input pin, the first on-off pin is connected to the second on-off pin. The switching unit is used to respond to the control signal input through the control signal input terminal and switch the functions corresponding to the first functional pin and the second functional pin.

[0009] In this embodiment, when the interface circuit is used for charging, if the first functional pin and / or the second functional pin of the interface circuit are short-circuited with the adjacent power input pin, a charging voltage (the same as the charging voltage, such as 10V or 20V) will be input from the first functional pin and / or the second functional pin to the switching unit. In this case, since the interface is used for charging, a low level is input to the Vcc terminal of the switching unit, that is, the first on-off pin is disconnected from the second on-off pin, and the second input terminal and the fourth input terminal of the first normally-on pin and the second normally-closed pin are no longer grounded. Since the first resistor, the second resistor, the third resistor, and the fourth resistor are respectively connected in series as isolation resistors on their respective paths, the current flowing through the Vcc terminal, the GND terminal, the first control terminal and the second control terminal, the first input terminal and the third input terminal is less than the burnout current of the switching unit. By the on-off device and setting isolation resistors for each port, the switching unit is in a floating state when not working and will not be burned by the voltage input during short-circuit, ensuring the normal use of the interface.

[0010] In some embodiments, the switching unit is a switch chip, and the switch chip includes a Vcc pin, a GND pin, a first general-purpose pin, a second general-purpose pin, a first input pin, a second input pin, a first normally-on pin, a second normally-on pin, a first normally-closed pin, and a second normally-closed pin;

[0011] The Vcc terminal is the Vcc pin; the GND terminal is the GND pin; the first input terminal is the first normally-conducting pin; the second input terminal is the second normally-conducting pin; the third input terminal is the second normally-closed pin; the fourth input terminal is the first normally-closed pin; the first control terminal is the first input pin; the second control terminal is the second input pin; the first output terminal is the first general-purpose pin; the second output terminal is the second general-purpose pin.

[0012] In some embodiments, the switching device is an NMOS transistor. The gate of the NMOS transistor is the input pin, the drain of the NMOS transistor is the first switching pin, and the source of the NMOS transistor is the second switching pin.

[0013] In some embodiments, the switching device is a PMOS transistor. The gate of the PMOS transistor is the input pin, the source of the PMOS transistor is the first switching pin, and the drain of the PMOS transistor is the second switching pin.

[0014] In some embodiments, the resistance value range of the fourth resistor is from 100 to 300 ohms.

[0015] In some embodiments, the interface circuit is an interface circuit of a Universal Serial Bus type-C (Type-c) interface. The first functional pin is the first Sideband Use (SBU) pin of the Type-c interface, and the second functional pin is the second SBU pin of the Type-c interface.

[0016] In some embodiments, the interface circuit further includes a first filter capacitor. The Vcc terminal is grounded through the first filter capacitor.

[0017] In some embodiments, the interface circuit further includes a second filter capacitor. One end of the second filter capacitor is connected to the input pin, and the other end of the second filter capacitor is connected to the first switching pin.

[0018] In a second aspect, an embodiment of the present application provides a protection method for an interface circuit. The method is applied to the interface circuit provided in the first aspect, and the method includes: detecting the type of the device connected to the interface circuit. If the device type is a charging device, then output a low level to the Vcc terminal.

[0019] In a third aspect, an embodiment of the present application provides a terminal device. The terminal device includes the interface circuit provided in the first aspect.

[0020] It can be understood that the beneficial effects of the above second aspect and third aspect can be referred to the relevant descriptions in the above first aspect, and will not be elaborated here. Description of the Drawings

[0021] Figure 1 It is a schematic diagram of an application scenario of an interface circuit provided by an embodiment of the present application;

[0022] Figure 2Schematic diagram of the structure of the Type-c interface provided by the embodiment of the present application;

[0023] Figure 3 Schematic diagram of the structure of an interface circuit provided by the embodiment of the present application;

[0024] Figure 4 Schematic diagram of the structure of an acquisition circuit connected to the interface circuit provided by the embodiment of the present application;

[0025] Figure 5 Schematic diagram of the structure of another interface circuit provided by the embodiment of the present application;

[0026] Figure 6 Schematic flow chart of a method for protecting an interface circuit provided by the embodiment of the present application. Detailed implementation manners

[0027] In the following description, specific details such as specific system architectures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.

[0028] As used in the specification of the present application and the appended claims, the term "if" can be interpreted as "when" or "once" or "in response to determining" or "in response to detecting" according to the context. Similarly, the phrases "if determined" or "if detected" can be interpreted as meaning "once determined" or "in response to determining" or "once detected" or "in response to detecting" according to the context.

[0029] In addition, in the description of the specification of the present application and the appended claims, the terms "first", "second", "third", etc. are only used for differentiating descriptions and cannot be understood as indicating or implying relative importance.

[0030] Referring to "one embodiment" or "some embodiments" described in the specification of the present application means that specific features, structures, or characteristics described in connection with the embodiment are included in one or more embodiments of the present application. Thus, the statements "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0031] The interface circuit provided by this application can be a reusable interface. For example, it can be used for the reuse of charging and audio devices, or the reuse of charging and data transmission, etc. Exemplarily, Figure 1 shows an application scenario of an interface circuit. As Figure 1 shown, take the Type-c interface as an example for illustration.

[0032] Referring to Figure 1 the shown interface, which is a Type-c interface, then this interface circuit can be applied to terminal devices with a Type-c interface, such as smart phones, tablets, smart watches, etc.

[0033] In this scenario, the interface circuit provided by this application can be a microphone circuit accessed through the Type-c interface in the terminal device. This interface circuit can protect the switching unit in the microphone circuit from being burned by the current when short-circuited. The switching unit is used to respond to the control signal input through the control signal input terminal and switch the functions corresponding to SBU1 and SBU1. For example, referring to Figure 2 the shown Type-c interface, the Type-c interface includes two sets of symmetrically arranged ports, and it can be used normally whether the Type-c interface is inserted correctly or reversely. When a headset is inserted into the Type-c interface, CC1 and CC2 can be used to determine the port direction when the Type-c interface accesses the headset, so as to determine which ports to use for data transmission of the headset.

[0034] As an example, if the application processor determines that the set of ports including CC1 is facing up, then the D+ port of A6 can be used to transmit the audio right channel data, and the D- of B7 can be used to transmit the audio left channel data. The headset can receive the left and right channel audio data through A6 and B7, and play the corresponding audio data through the left and right headsets respectively. At the same time, after the application processor determines the port direction through CC1, it also needs to control the switching unit to set SBU1 as the microphone input port and SBU2 as the ground port. After the microphone receives the audio signal, it transmits the audio signal to the encoder, and the encoder processes the audio signal and then sends it to the application processor or sends it to the headset for playback. Correspondingly, if the application processor determines the port direction through CC2, it also needs to control the switching unit to set SBU1 as the ground port and SBU2 as the microphone input port.

[0035] However, in the Type-C port, since SBU1 and SBU2 are adjacent to Vbus respectively, the Type-C interface may be corroded or deformed during use, causing a short circuit between SBU1 and / or SBU2 and Vbus. When a short circuit occurs and the Type-C interface is used for charging, the charging voltage will be input to SBU1 and / or SBU2, resulting in the burnout of the switching chip and affecting the normal use of the Type-C interface.

[0036] For this reason, the present application provides an interface circuit, which can improve the problem that when SBU1 and / or SBU2 are short-circuited with Vbus and charging is carried out through Vbus in the Type-C interface, the switching unit is burned out, affecting the normal use of the Type-C interface.

[0037] Figure 3 The structural schematic diagram of the interface circuit provided by the present application is shown.

[0038] In Figure 3 the interface circuit, the switching circuit is implemented in the form of a switching chip. The switching chip includes a Vcc pin (Vcc), a GND pin (GND), a first general-purpose pin (COM1), a second general-purpose pin (COM2), a first input pin (IN1), a second input pin (IN2), a first normally-open pin (NO1), a second normally-open pin (NO2), a first normally-closed pin (NC1), and a second normally-closed pin (NC2).

[0039] Among them, the Vcc terminal is the Vcc pin (Vcc); the GND terminal is the GND pin (GND); the first input terminal is the first normally-open pin (NO1); the second input terminal is the second normally-open pin (NO2); the third input terminal is the second normally-closed pin (NC2); the fourth input terminal is the first normally-closed pin (NC1); the first control terminal is the first input pin (IN1); the second control terminal is the second input pin (IN2); the first output terminal is the first general-purpose pin (COM1); the second output terminal is the second general-purpose pin (COM2).

[0040] It should also be noted that in Figure 3 the on-off device is an NMOS transistor. The gate (G) of the NMOS transistor is the input pin, the drain (D) of the NMOS transistor is the first on-off pin, and the source (S) of the NMOS transistor is the second on-off pin. Alternatively, in other embodiments, the on-off device can also be a PMOS transistor.

[0041] When the on-off device is a PMOS transistor, the gate (G) of the PMOS transistor is the input pin, the source (S) of the PMOS transistor is the first on-off pin, and the drain (D) of the PMOS transistor is the second on-off pin.

[0042] In some embodiments, Figure 3The interface circuit shown is an interface circuit applied to the Type-c interface. The first functional pin is the first SBU pin (Type-c SBU1) of the Type-c interface, and the second functional pin is the second SBU pin (Type-c SBU2) of the Type-c interface. Of course, this interface circuit can also be an interface where other functional pins are adjacent to the power input pin, which is not limited here.

[0043] Figure 3 In the shown interface circuit, the COM1 pin of the switch chip is connected to the SBU1 pin of the Type-c interface, and the COM2 pin of the switch chip is connected to the SBU2 pin of the Type-c interface. The first resistor 101 is connected in series between the Vcc pin of the switch chip and the power input terminal (Vout). One end of the second resistor is connected to the GND pin of the switch chip, and the other end of the second resistor is grounded. One end of the third resistor is connected to the IN1 pin and IN2 pin of the switch chip to form a control signal input network (GPIO_R), and the other end is connected to the control signal input terminal (GPIO). One end of the fourth resistor is connected to the NO1 pin and NC2 pin of the switch chip to form a sampling signal input network (MIC_TEST), and the other end is connected to the detection port (MBHC_IN). The gate of the NMOS transistor is connected to the power input terminal (Vcc). The drain of the NMOS transistor is respectively connected to the NO2 pin and NC1 pin of the switch chip to form a ground output network (GND_TEST_R). The source of the NMOS transistor is grounded and connected to the ground output terminal (GND_TEST). When a low level is input to the input pin, the first switching pin and the second switching pin are disconnected. When a high level is input to the input pin, the first switching pin and the second switching pin are connected. The switching unit is used to respond to the control signal input through the control signal input terminal and switch the functions corresponding to the first functional pin and the second functional pin.

[0044] It should also be noted that the first resistor 103, the second resistor 104, the third resistor 105, and the fourth resistor 106 are isolation resistors for protection. In order to play a role in protection and isolation, their resistance values need to meet the preset requirements to limit the current magnitude of each circuit where the resistor is located. Make the current flowing through the switch chip less than the damage current of the switch chip. For example, Figure 3 In the shown scenario, the resistance value of the first resistor can be 3.3 kΩ, the resistance value of the second resistor 104 can be 1.5 kΩ, the resistance value of the third resistor 105 can be 1 kΩ, and the resistance value of the fourth resistor 106 can be 100 - 300 Ω, but not limited to this.

[0045] Among them, the fourth resistor is arranged in the sampling circuit connected to the interface circuit, and the sampling circuit is used to sample the audio signal. Figure 4 The structural schematic diagram of a sampling circuit is shown.

[0046] Reference Figure 4 , by way of example, the acquisition circuit includes a first inductor 201, a fourth resistor 106, a first capacitor 202, a second capacitor 203, a third capacitor 206, a fourth capacitor 207, a fifth capacitor 209, a sixth capacitor 210, a seventh capacitor 211, an eighth capacitor 212, a fifth resistor 204, a sixth resistor 205, and a signal input port (MIC_TEST), a signal control port (MBHC_IN), a bias voltage input port of the microphone (MICBIAS), a positive output port of the microphone (MIC_P), and a negative output port of the microphone (MIC_N). One end of the first capacitor 202, the second capacitor 203, the third capacitor 206, the fourth capacitor 207, the seventh capacitor 211, and the eighth capacitor 212 among the above devices is grounded, and the other end is respectively connected to multiple positions in the circuit for filtering the clutter in the circuit. The fifth capacitor 209 is connected in series between the signal input port and the positive output port of the microphone for isolating the DC signal. The sixth capacitor 210 is connected in series between the signal input port and the negative output port of the microphone, also for isolating the DC signal. The fifth resistor 204 and the sixth resistor 205 are connected in series between the signal input port and the bias voltage input port of the microphone for isolating the signal input port and the bias voltage input port of the microphone.

[0047] Among them, by way of example, the first capacitor 202 can be a 10 nF capacitor; the second capacitor 203, the seventh capacitor 211, and the eighth capacitor 212 can be 33 pF capacitors; the third capacitor 206 can be a 2.2 μF capacitor; the fifth capacitor 209 and the sixth capacitor 210 can be 100 nF capacitors; and the fourth capacitor 207 can be a 1 μF capacitor. The resistance values of the fifth resistor 204 and the sixth resistor 205 can be 1.1 k ohms.

[0048] When the Type-c interface is used for charging, the charging interface is connected to the Vbus pin of the Type-c interface power output, and the charging voltage is input from the Vbus pin. If the Vbus pin of the Type-c interface is short-circuited with the first SBU pin and / or the second SBU pin. In this case, the first common signal pin and / or the second common signal pin of the switch chip will input a high voltage (the same as the charging voltage, such as 10V or 20V). When the Type-c interface is used for charging, the input pin inputs a low level, that is, the first on-off pin and the second on-off pin are disconnected, and the first normally-on pin and the second normally-closed pin are disconnected from the ground terminal. Since the first resistor isolates the Vcc pin and the input port of the Vcc pin, the second resistor isolates the GND pin and the ground terminal, the third resistor isolates the control input port and the control pin connected to the third resistor, and the fourth resistor isolates the signal input port and the signal control port. At the same time, in the acquisition circuit, the sixth resistor isolates the signal input port and the bias voltage input port of the microphone, the fifth capacitor isolates the DC signal between the signal input port and the positive output port of the microphone, and the sixth capacitor isolates the DC signal between the signal input port and the negative output port of the microphone. The input high voltage will be shunted to the resistors corresponding to each port, so that the currents flowing through the Vcc pin, the GND pin, the second normally-on pin, the first normally-closed pin, the first control pin and the second control pin are less than the burnout current of the switch chip. The first normally-on pin and the second normally-closed pin are disconnected from the ground terminal, so that the first normally-on pin and the second normally-closed pin are disconnected from the ground terminal. By means of the on-off device and setting isolation resistors for the pins, the switch chip is in a floating state and will not be burned out by the high voltage input during short circuit.

[0049] Moreover, when the switch chip is working normally, since the working current of the switch itself is only 10uA and its voltage drop to the ground is 0.01V, after connecting multiple resistors in series, it will not affect the operation of the switch chip, and the switch chip can still achieve normal signal communication.

[0050] It should be noted that since the current value passing through the signal control port can be used to determine whether the earphone connected to the Type interface and entering the low-power mode exits the low-power mode. In order to ensure that the mobile device can correctly exit the low-power mode of the earphone, it is necessary to ensure that after the earphone button is pressed, the input level of MBHC_IN is less than 125mV. For this reason, the resistance value of the fourth resistor should be between 100 and 300 ohms.

[0051] For example, the impedance of the earphone when pressing the button is 338 - 740 ohms. When the resistance value of the fourth resistor is 300 ohms, the input level of MBHC_IN after pressing the earphone button rises from 86 mV when not connected in series to 125 mV, still ensuring normal exit from the low-power mode when the impedance of the earphone button is the largest. At the same time, since the minimum impedance of the earphone microphone is 800 ohms and its level is 0.19 V, the input level of MBHC_IN is greater than 125 mV when not pressing the button, and it will not be accidentally triggered into the low-power mode.

[0052] Figure 5 The structural schematic diagram of another interface circuit provided by the present application is shown.

[0053] In some embodiments, referring to Figure 5 , the interface circuit further includes a first filter capacitor and a second filter capacitor. The Vcc terminal is grounded through the first filter capacitor. One end of the second filter capacitor is connected to the input pin, and the other end of the second filter capacitor is connected to the first on-off pin.

[0054] In this embodiment, by adding a first filter capacitor and a second filter capacitor in the interface circuit, the clutter in the circuit can be filtered out, ensuring the stability of the interface circuit.

[0055] Figure 6 The protection method of another interface circuit provided by the present application is shown.

[0056] Referring to Figure 6 , this method is applied to the above-provided interface circuit, and this method includes:

[0057] S31. Detect the type of device accessed by the interface circuit.

[0058] S32. If the device type is a charging device, output a low level to the Vcc terminal.

[0059] In some embodiments, taking the interface circuit as a Type-c interface as an example, the application processor of the terminal device can determine the type of the device connected to the interface circuit by obtaining the pins used after the access device is connected to the interface. For example, for a charging device, the pins that will be used include Vbus, GND, etc. For an audio device, pins such as SBU1, SBU2, CC1 or CC2, and D+, D- will be used. When the application processor determines that the type of the connected device is a charging device, such as a charger, a power bank, etc. Since charging uses the Vbus pin, in order to avoid short circuit between Vbus and SBU1 and / or SBU2 resulting in the interface circuit being burned out, the application processor needs to control the power module to set the level of the power input terminal of the interface circuit to a low level. In this case, since the interface is used for charging, the Vcc terminal of the switching unit inputs a low level, that is, the first on-off pin and the second on-off pin are disconnected, and the second input terminal and the fourth input terminal of the first normally-on pin and the second normally-closed pin are no longer grounded. Since the first resistor, the second resistor, the third resistor, and the fourth resistor are respectively connected in series as isolation resistors on their respective paths, the currents flowing through the Vcc terminal, the GND terminal, the first control terminal and the second control terminal, the first input terminal and the third input terminal are less than the burnout current of the switching unit. By means of the on-off device and setting isolation resistors for each port, the switching unit is in a floating state when not working and will not be burned out by the voltage input during short circuit, ensuring the normal use of the interface.

[0060] In still other embodiments, when the application processor determines that the type of the connected device is an external device, such as an audio device. The application processor can control the power module to set the level of the power input terminal of the interface circuit to a high level so that the interface circuit can work normally.

[0061] The embodiment of the present application further provides a terminal device, and the terminal device includes the interface circuit provided above.

[0062] As an example, if the interface circuit is a Type-c interface circuit, the terminal device is a smart phone, a tablet computer, a laptop computer, a wearable device, etc. with a Type-c interface.

[0063] In the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0064] Those of ordinary skill in the art can realize that the circuit modules and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. A professional technician can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0065] In the embodiments provided in this application, it should be understood that the disclosed transmission devices and methods can be implemented in other ways. For example, the above-described embodiments are merely illustrative. For example, the division of each circuit module in the transmission device is only a logical function division. In actual implementation, there may be other division methods. For example, multiple components can be combined or integrated into another circuit module, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling, direct coupling, or communication connection to each other can be an indirect coupling or communication connection through some interfaces, devices, or units, and can be in an electrical or other form.

[0066] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place, or can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0067] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of each embodiment of this application, and should all be included in the protection scope of this application.

Claims

1. An interface circuit, characterized in that, The interface circuit includes a switching unit, a power input terminal, a first functional pin, a second functional pin, a control signal input terminal, a detection port, a ground output terminal, a first resistor, a second resistor, a third resistor, a fourth resistor, and a connection and disconnection device; The switching unit includes a wire grounding GND terminal, a circuit power supply Vcc terminal, a first switching circuit, and a second switching circuit. Among them, the first switching circuit includes a first input terminal, a second input terminal, a first control terminal, and a first output terminal, and the second switching circuit includes a third input terminal, a fourth input terminal, a second control terminal, and a second output terminal; The first output terminal is connected to the first functional pin, and the second output terminal is connected to the second functional pin; The first resistor is connected in series between the Vcc terminal and the power input terminal; One end of the second resistor is connected to the GND terminal, and the other end of the second resistor is grounded; One end of the third resistor is connected to the control signal input terminal, and the other end is connected to the first control terminal and the second control terminal; One end of the fourth resistor is connected to the detection port, and the other end is connected to the first input terminal and the third input terminal; The connection and disconnection device includes: an input pin, a first connection and disconnection pin, and a second connection and disconnection pin; The input pin is connected to the power input terminal; The first connection and disconnection pin is respectively connected to the second input terminal and the fourth input terminal; The second connection and disconnection pin is grounded and connected to the ground output terminal; When a low level is input to the input pin, the first connection and disconnection pin is disconnected from the second connection and disconnection pin; When a high level is input to the input pin, the first connection and disconnection pin is connected to the second connection and disconnection pin; The switching unit is used to respond to a control signal input through the control signal input terminal and switch the functions corresponding to the first functional pin and the second functional pin.

2. The interface circuit according to claim 1, wherein The switching unit is a switch chip, and the switch chip includes a Vcc pin, a GND pin, a first general-purpose pin, a second general-purpose pin, a first input pin, a second input pin, a first normally-conducting pin, a second normally-conducting pin, a first normally-closed pin, and a second normally-closed pin; The Vcc terminal is the Vcc pin; the GND terminal is the GND pin; the first input terminal is the first normally-conducting pin; the second input terminal is the second normally-conducting pin; the third input terminal is the second normally-closed pin; the fourth input terminal is the first normally-closed pin; The first control terminal is the first input pin; The second control terminal is the second input pin; the first output terminal is the first general-purpose pin; the second output terminal is the second general-purpose pin.

3. The interface circuit according to claim 1, wherein The connection and disconnection device is an NMOS transistor; The gate of the NMOS transistor is the input pin, the drain of the NMOS transistor is the first connection and disconnection pin, and the source of the NMOS transistor is the second connection and disconnection pin.

4. The interface circuit according to claim 1, wherein The connection and disconnection device is a PMOS transistor; The gate of the PMOS transistor is the input pin, the source of the PMOS transistor is the first connection and disconnection pin, and the drain of the PMOS transistor is the second connection and disconnection pin.

5. The interface circuit according to claim 1, characterized in that The resistance value range of the fourth resistor is 100 to 300 ohms.

6. The interface circuit according to claim 1, wherein The interface circuit is an interface circuit of a Universal Serial Bus Type-C interface. The first functional pin is the first Sideband Use (SBU) pin of the Type-C interface, and the second functional pin is the second SBU pin of the Type-C interface.

7. The interface circuit according to claim 1, wherein The interface circuit further includes a first filter capacitor, and the Vcc terminal is grounded through the first filter capacitor.

8. The interface circuit according to any one of claims 1-7, characterized in that, The interface circuit further includes a second filter capacitor. One end of the second filter capacitor is connected to the input pin, and the other end of the second filter capacitor is connected to the first on-off pin.

9. A protection method for an interface circuit, characterized in that, The method is applied to the interface circuit according to any one of claims 1-8, and the method includes: Detecting the type of the device connected to the interface circuit; If the device type is a charging device, outputting a low level to the Vcc terminal.

10. A terminal device, characterized in that, The terminal device includes the interface circuit according to any one of claims 1-8.

Citation Information

Patent Citations

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