Flash analog-to-digital converter and calibration method

Abstract

A flash analog-to-digital converter includes a plurality of dual differential comparator circuits and a correction circuit. Each dual differential comparator circuit compares a first input signal with a corresponding one of a first set of reference voltages, and compares a second input signal with a corresponding one of a second set of reference voltages, to generate a corresponding one of a plurality of first signals. The correction circuit outputs a first test signal as a first input signal and a second test signal as a second input signal in a test mode, and corrects the common mode level of each of the first input signal and the second input signal according to the distribution of the first signals, or corrects at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages.

Description

Technical Field

[0001] The present application relates to a flash analog-to-digital converter, and more particularly to a flash analog-to-digital converter and a correction method for correcting a systematic offset by observing a plurality of digital codes. Background Art

[0002] In the prior art, all comparator circuits in a flash analog-to-digital converter have the same circuit structure. If there is a systematic offset, these comparator circuits may not operate correctly in a default operating region, thereby causing the operation of the flash analog-to-digital converter to fail. Summary of the invention

[0003] In some embodiments, the flash analog-to-digital converter includes a plurality of dual differential comparator circuits and a calibration circuit. Each dual differential comparator circuit compares a first input signal with a corresponding one of the first set of reference voltages, and compares a second input signal with a corresponding one of the second set of reference voltages to generate a corresponding one of the plurality of first signals. The calibration circuit outputs a first test signal as a first input signal and a second test signal as a second input signal in a test mode, and calibrates the common mode level of each of the first input signal and the second input signal according to the distribution of the first signals, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages.

[0004] In some embodiments, a calibration method is used to calibrate a flash analog-to-digital converter and includes the following operations: outputting a first test signal as a first input signal and outputting a second test signal as a second input signal, wherein the flash analog-to-digital converter includes a plurality of dual differential comparator circuits, each of the dual differential comparator circuits comparing the first input signal with a corresponding one of a first set of reference voltages and comparing the second input signal with a corresponding one of a second set of reference voltages to generate a corresponding one of a plurality of first signals; and calibrating the common mode level of each of the first input signal and the second input signal according to the distribution of these first signals, or calibrating at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages.

[0005] The features, effects and functions of the present application will be described in detail as follows with reference to the preferred embodiments of the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A schematic diagram of a flash analog-to-digital converter according to an embodiment of the present application;

[0007] Figure 2A According to the embodiment of the present application, Figure 1Schematic diagram of the dual differential amplifier circuit in;

[0008] Figure 2B According to the embodiment of the present application, Figure 2A Schematic diagram of the dual differential amplifier circuit affected by systematic offset;

[0009] Figure 2C According to the embodiment of the present application, Figure 2A The schematic diagram of the double differential amplifier circuit after correction;

[0010] Figure 2D According to the embodiment of the present application, Figure 2A The schematic diagram of the double differential amplifier circuit after correction;

[0011] Figure 3 According to the embodiment of the present application, Figure 1 A schematic diagram of the operation of the correction circuit; and

[0012] Figure 4 The figure is a flow chart of a correction method according to an embodiment of the present application. DETAILED DESCRIPTION

[0013] All terms used in this application have their usual meanings. The above terms are defined in commonly used dictionaries, and any use examples of terms discussed herein in the content of this application are only examples and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in the specification.

[0014] As used herein, "coupled" or "connected" may refer to two or more components making physical or electrical contact directly or indirectly, or two or more components operating or acting on each other. As used herein, the term "circuitry" may be a single system formed by at least one circuit, and the term "circuit" may be a device that is connected in a certain manner by at least one transistor and / or at least one active and passive component to process signals.

[0015] As used herein, the term "and / or" includes any combination of one or more of the listed associated items. In this document, the terms first, second, third, etc. are used to describe and distinguish each component. Therefore, the first component in this document may also be referred to as the second component without departing from the original intention of this application. For ease of understanding, similar components in the various drawings will be designated with the same reference numerals.

[0016] Figure 1FIG. 1 is a schematic diagram of a flash analog-to-digital converter 100 according to an embodiment of the present application. The flash analog-to-digital converter 100 can convert an input signal S IN The corresponding digital signal S D- , where the input signal S IN The input signal S IN + and input signal S IN -The difference between.

[0017] The flash analog-to-digital converter 100 includes a reference voltage generating circuit 120, an encoder circuit 140, a comparator circuit system 160, and a calibration circuit 180. The reference voltage generating circuit 120 generates a voltage V RP And the voltage V RN Generate the first reference voltage V x1 ~V xm And the second reference voltage V y1 ~V ym For example, the reference voltage generating circuit 120 includes a plurality of resistors RX and a plurality of resistors RY. The plurality of resistors RX operate as a voltage divider circuit to generate a voltage according to the voltage V RP And the voltage V RN Generate the first reference voltage V x1 ~V xm . Reference voltage V x1 For the first reference voltage V x1 ~V xm The closest voltage V RP voltage, and the reference voltage V xm For the first reference voltage V x1 ~V xm The closest voltage V RN voltage.

[0018] Similarly, the plurality of resistors RY operate as a voltage divider circuit to adjust the voltage V RN And the voltage V RP Generate the second reference voltage V y1 ~V ym . Reference voltage V y1 For the second reference voltage V y1 ~V ym The closest voltage V RN voltage, and the reference voltage V ym For the second reference voltage V y1 ~V ym The closest voltage V RP voltage.

[0019] The above implementation of the reference voltage generating circuit 120 is for illustration only, and the present application is not limited thereto. Various types of reference voltage generating circuits 120 are within the scope of the present application.

[0020] The encoder circuit 140 generates a digital signal S according to the plurality of signals S2. D For example, the encoder circuit 140 may encode the plurality of signals S2 to generate a digital signal S D In some embodiments, the plurality of signals S2 are thermometer codes, and the digital signal S D In some embodiments, the encoder circuit 140 may be implemented by one or more logic circuits.

[0021] The comparator circuit system 160 converts the input signal S IN Respectively with the first reference voltage V x1 ~V xm And the second reference voltage V y1 ~V ym In this embodiment, the comparator circuit system 160 includes a plurality of double-differential comparator circuits, wherein each double-differential comparator circuit includes a double differential amplifier circuit 162 and a latch circuit 164 .

[0022] Each of the plurality of dual differential amplifier circuits 162 compares the input signal S IN + and the first reference voltage V x1 ~V xm and compare the input signal S IN - and the second reference voltage V y1 ~V ym , to generate a corresponding one of the plurality of signals S1. The signal S1 may be a voltage difference between two output terminals of the dual differential amplifier circuit 162. Taking the first dual differential amplifier circuit 162 (labeled as 162-1) as an example, the dual differential amplifier circuit 162-1 compares the input signal S IN + and reference voltage V x1 , and compare the input signal S IN - With reference voltage V y1 , to generate the first of the plurality of signals S1. Similarly, the last dual differential amplifier circuit 162 (labeled as 162-2) compares S IN + and reference voltage V xm , and compare the input signal S IN - With reference voltage V ym , to generate the last one of multiple signals S1.

[0023] The latch circuits 164 generate a plurality of signals S2 according to the plurality of signals S1. In some embodiments, the latch circuits 164 are circuits with positive feedback, which latch the corresponding signals S 1- The voltage is pulled up to a rail-to-rail level to generate a corresponding signal S2.

[0024] The calibration circuit 180 tests the comparator circuit system 160 to calibrate a systematic offset of at least one comparator circuit. The calibration circuit 180 enters a test mode in response to the enable signal EN. In the test mode, the calibration circuit 180 outputs a test signal S T1 The input signal S IN +, and output test signal S T2 The input signal S IN -. In response to the test signal S T1 With the test signal S T2 , a plurality of dual differential comparator circuits generate a plurality of signals S2. The correction circuit 180 can correct the input signal S according to the distribution of these signals S2. IN + and input signal S IN - The common mode level of each, or the calibration of the first reference voltage V x1 ~V xm At least one first reference voltage and a second reference voltage V y1 ~V ym In some embodiments, the calibration circuit 180 calculates a plurality of signals S 2- The standard deviation of the first logic value is used to determine the distribution of the plurality of signals S2. In some embodiments, the correction circuit 180 calculates the maximum number of the plurality of signals S2 having the first logic value to determine the distribution of the plurality of signals S2. The details here will be referred to later. Figure 3 Further explanation.

[0025] In some embodiments, the correction circuit 180 may output a control signal V C1 To calibrate the common mode level, at least one first reference voltage and / or at least one second reference voltage. Figure 1 As shown, the multiple resistors RX and the multiple resistors RY are variable resistors, and the correction circuit 180 can output a control signal V C1 The resistance value of at least one of the plurality of resistors RX and / or the plurality of resistors RY is adjusted to calibrate at least one first reference voltage and / or at least one second reference voltage. In some embodiments, the flash analog-to-digital converter 100 further includes a voltage regulator circuit (not shown) which can adjust the voltage according to the control signal V C1 Generate an offset voltage (for example Figure 2C The offset voltage V OS) to calibrate the common mode level. Alternatively, in other embodiments, the voltage regulator circuit is a low-dropout regulator circuit, which can adjust the common mode level according to the control signal V C1 Adjust voltage V RN With voltage V RP , to calibrate at least one first reference voltage and / or at least one second reference voltage. In some embodiments, if the input signal S IN + and input signal S IN - is an output terminal of a pre-stage circuit (not shown) from the flash analog-to-digital converter 100. The correction circuit 180 can transmit the control signal V C1 To the preceding circuit to adjust the common mode level of the output terminal of the preceding circuit. In some embodiments, the correction circuit 180 can be based on the digital signal S D Determine multiple signals S 2- The standard deviation of .

[0026] In some embodiments, the calibration circuit 180 may be implemented by a digital signal processing circuit. In some embodiments, the calibration circuit 180 may be a foreground calibration circuit in the flash analog-to-digital converter 100. In some embodiments, the calibration circuit 180 may be an auxiliary design system external to the flash analog-to-digital converter 100, which may be used to calibrate the comparator circuit system 160 during the manufacturing process of the flash analog-to-digital converter 100.

[0027] The above configuration of the flash analog-to-digital converter 100 is for example only, and the present application is not limited thereto. In some embodiments, the comparator circuit system 160 may include an interpolation network (not shown) that can perform an interpolation operation to generate a plurality of signals S2. In some embodiments, the interpolation network may be an active network (e.g., one or more amplifiers) or a passive network (e.g., a resistive network). Various flash analog-to-digital converters that can use a dual differential comparator circuit are within the scope of the present application.

[0028] Figure 2A According to the embodiment of the present application, Figure 1Schematic diagram of the dual differential amplifier circuit 162 in FIG. The dual differential amplifier circuit 162 includes a current source circuit 201, a current source circuit 202, a plurality of transistors M1-M8, and a plurality of resistors R1-R2. The current source circuit 201 biases the plurality of transistors M1-M4. A first end of the current source circuit 201 is coupled to a second end (e.g., a source) of both the transistor M1 and the transistor M2, and a second end of the current source circuit 201 receives a ground voltage GND. A first end (e.g., a drain) of the transistor M1 is coupled to a second end of the transistor M3, and a control end (e.g., a gate) of the transistor M1 receives a first set of reference voltages V x1 ~V xm One of the corresponding (marked as V x ). The first terminal of the transistor M3 is coupled to the second terminal of the resistor R2 to generate a signal S1+, and the control terminal of the transistor M3 receives a bias signal V B1 The first end of the resistor R2 receives the power supply voltage VDD. The first end of the transistor M2 is coupled to the second end of the transistor M4, and the control end of the transistor M2 receives the input signal S IN +. The first terminal of the transistor M4 is coupled to the second terminal of the resistor R1 to generate a signal S1-, and the control terminal of the transistor M4 receives a bias signal V B1 The first end of the resistor R1 receives the power supply voltage VDD.

[0029] The first terminal of the current source circuit 202 is coupled to the second terminals of the transistor M5 and the transistor M6, and the second terminal of the current source circuit 202 receives the ground voltage GND. The first terminal of the transistor M5 is coupled to the second terminal of the transistor M7, and the control terminal of the transistor M5 receives the input signal S IN -. The first terminal of the transistor M7 is coupled to the second terminal of the resistor R2 to generate a signal S1+, and the control terminal of the transistor M7 receives a bias signal V B1 The first terminal of the transistor M6 is coupled to the second terminal of the transistor M8, and the control terminal of the transistor M6 receives the second reference voltage V y1 ~V ym One of the corresponding (marked as V y ). The first terminal of the transistor M8 is coupled to the second terminal of the resistor R1 to generate a signal S1-, and the control terminal of the transistor M8 receives a bias signal V B1 .

[0030] The plurality of transistors M1-M2 operate as a first input pair circuit, and the plurality of transistors M5-M6 operate as a second input pair circuit. The aspect ratio of each of the plurality of transistors M1-M2 and the plurality of transistors M5-M6 is the same as each other. Thus, each of the plurality of transistors M1-M2 and the plurality of transistors M5-M6 theoretically has the same transconductance value. By circuit analysis, it can be known that the signal S1 can be expressed as follows:

[0031] S1=S1+-S1-=gm·R·[(S IN +-V x )-(S IN --V y )]

[0032] Wherein, gm is the aforementioned transconductance value, R is the resistance value of each of the resistors R1 and R2, and the difference between the signal S1+ and the signal S1- is Figure 1 signal S1.

[0033] Figure 2B According to the embodiment of the present application, Figure 2A FIG. 1 is a schematic diagram showing the dual differential amplifier circuit 162 being affected by a systematic offset. Figure 2A The dual differential amplifier circuit 162 in Figure 1 The dual differential amplifier circuit 162-1 in the reference voltage V x is the reference voltage V x1- (for example, 0.75 volts), and the reference voltage V y is the reference voltage V y1 (For example, 0.25 volts).

[0034] In case 1, Figure 2A The input signal S IN + and input signal S IN -Each of them has a default common mode level of 0.5 volts and a signal swing of 0.2499 volts. Figure 2A It can be seen that the signal S1- is in response to the input signal S IN + and reference voltage V y1 According to circuit analysis (such as the overlap theorem), it can be known that the signal S1- is the sum V5 of the signal component V1 and the signal component V2, wherein the signal component V1 is based on the reference voltage V y1 The voltage generated, and the signal component V2 is based on the input signal S IN + The voltage generated. In case 1, the reference voltage V y1 (0.25V) is lower than the input signal S IN +(0.7499 volts). Under this condition, the reference voltage V y1The first voltage drop generated on the resistor R1 is smaller than the input signal S IN + The second voltage drop generated on the resistor R1. Therefore, the level of the signal component V1 (ie, the power supply voltage VDD minus the first voltage drop) is higher than the level of the signal component V2 (ie, the power supply voltage VDD minus the second voltage drop).

[0035] Similarly, the signal S1+ may be the sum V6 of the signal component V3 and the signal component V4, wherein the signal component V3 is a sum V6 of the signal component V3 and the signal component V4 according to the input signal S IN - The voltage generated, and the signal component V4 is based on the reference voltage V x1 In case 1, the reference voltage V x1 (0.75 volts) higher than the input signal S IN -(0.2501 volts). Under this condition, the reference voltage V x1 The third voltage drop generated on the resistor R2 is higher than the input signal S IN - A fourth voltage drop is generated on the resistor R2. Therefore, the level of the signal component V3 (i.e., the power supply voltage VDD minus the fourth voltage drop) is higher than the level of the signal component V4 (i.e., the power supply voltage VDD minus the third voltage drop). Thus, in case 1, the common mode level of the signal S1- (i.e., the total V5) can be substantially the same as the common mode level of the signal S1+ (i.e., the total V6).

[0036] If the dual differential amplifier circuit 162-1 has a systematic offset, it can be equivalent to the input signal S IN + and input signal S IN -The common mode level of each of them shifts. For example, in case 2, Figure 2A The input signal S IN + and input signal S IN -The common mode level of each of them deviates from 0.5V to 0.6V. Compared with case 1, the input signal S IN + is increased to 0.8499 volts. Since this level is too high, the voltage on the first terminal of transistor M2 will be limited by transistor M4. As a result, transistor M2 will erroneously operate in a non-default operating region (e.g., a linear region), causing the conductance of transistor M2 to decrease. Under this condition, transistor M2 responds to the input signal S IN + will become lower. Therefore, the second voltage drop will also become lower. As a result, the signal component V2 will increase to the signal component V2'. x1 In cases 1 and 2, the voltage is 0.75V, so the level of signal component V1 remains unchanged. Therefore, the common mode level of signal S1- in case 2 (i.e., the sum V5' of signal component V1 and signal component V2') is higher than the common mode level of signal S1- in case 1 (i.e., the sum V5).

[0037] Compared with case 1, the input signal S IN -increases to 0.3501 volts. Under this condition, transistor M5 responds to the input signal S IN- The generated current becomes higher. Therefore, the fourth voltage drop also becomes higher. In this way, the signal component V3 will be reduced to the signal component V3'. The reference voltage V y1 In cases 1 and 2, the voltage is 0.25 volts, so the level of the signal component V4 remains unchanged. Therefore, the common-mode level of the signal S1+ in case 2 (i.e., the sum V6' of the signal component V3' and the signal component V4) will be lower than the common-mode level of the signal S1+ in case 1 (i.e., the sum V6). In other words, in case 2, the common-mode level of the signal S1+ (i.e., the sum V6') is different from the common-mode level of the signal S1- (i.e., the sum V5'), wherein the difference between the signal S1+ and the signal S1- is a systematic offset, which may cause the corresponding comparator circuit to fail to operate properly.

[0038] Figure 2C According to the embodiment of the present application, Figure 2A Schematic diagram of the dual differential amplifier circuit 162 after correction. To correct the offset, in this example, an offset voltage V of +0.01 volt is applied to the control terminal of transistor M2. OS , and the control terminal of transistor M5 is applied with an offset voltage V of -0.01 volts OS In one experimental example, by applying an offset voltage V OS , the offset of the previous case 2 can be effectively eliminated to avoid comparator circuit operation failure.

[0039] Figure 2D According to the embodiment of the present application, Figure 2A FIG. 1 is a schematic diagram of the dual differential amplifier circuit 162 after correction. Figure 2C In the example of , the correction circuit 180 corrects the systematic offset by adjusting the levels of the signal component V2' and the signal component V3'. Figure 2B As shown, the common-mode level of the signal component S1- (i.e., the sum V5') is related to the signal component V1 and the signal component V2', and the common-mode level of the signal component S1+ (i.e., the sum V6') is related to the signal component V3' and the signal component V4. Therefore, the correction circuit 180 can also correct the offset by adjusting the signal component V1 and the signal component V4. In this example, the control terminal of the transistor M1 is applied with an offset voltage V of -0.01 volts. OS , and the control terminal of transistor M6 is applied with an offset voltage V of +0.01 volt OS Under this condition, the level of the signal component V1 will become low, and the level of the signal component V4 will become high. In this way, the offset can be effectively eliminated to avoid failure of the comparator circuit operation. It should be understood that according to Figure 2C as well as Figure 2D To reduce the offset, different transistors in the same input pair circuit will be applied with offset voltages V of different polarities. OS .

[0040] The above description is based on receiving the reference voltage V x1- And the reference voltage V y1 The dual differential amplifier circuit 162-1 is taken as an example. The reference voltage V x1- With reference voltage V y1 Two extreme bias conditions are formed on the multiple input pair circuits. Compared with other dual differential amplifier circuits 162 (e.g. Figure 1 162-n), the multiple input pairs in the dual differential amplifier circuit 162-1 are more susceptible to systematic offsets. Similarly, in some embodiments, Figure 1 The receiving reference voltage V xm And the reference voltage V ym The dual differential amplifier circuit 162-2 is also susceptible to the influence of the systematic offset. Therefore, in some embodiments, the at least one first reference voltage calibrated by the calibration circuit 180 may include (but is not limited to) a reference voltage V x1 Or reference voltage V xm At least one of the reference voltages V y1 Or reference voltage V ym At least one of them.

[0041] The above configuration of the dual differential amplifier circuit 162 is for example only, and the present application is not limited thereto. Figure 2A The circuit architecture shown. The causes of the systematic offset may be different under different circuit architectures and / or circuit settings (eg, transistor size, actual bias conditions).

[0042] Figure 3 According to the embodiment of the present application, Figure 1 FIG. 1 is a schematic diagram of the operation of the calibration circuit 180. In this example, the calibration circuit 180 can analyze multiple signals S2 to detect systematic offsets. If the comparator circuit system 160 includes 16 comparator circuits, the comparator circuit system 160 will generate 16 signals S2. For example, the 16th signal S2 comes from the dual differential amplifier circuit 162-1 and the corresponding latch circuit 164, and the 1st signal S2 comes from the dual differential amplifier circuit 162-2 and the corresponding latch circuit 164.

[0043] If there is no systematic offset, the transconductance of transistor M2 and / or transistor M5 is a predetermined value. Under this condition, the input signal SIN + and input signal S IN - (hereinafter referred to as ΔV) should correspond to the default reference voltage range ΔVREF after being processed by the transistor M2 and the transistor M5, wherein the default reference voltage range ΔVREF can be obtained by the first set of reference voltages V x1 ~V xm (or the second reference voltage V y1 ~V ym ) is determined by two of them. In this example, under the predetermined signal swing, a total of 12 comparator circuits will respond to the input signal S IN A plurality of signals S2 (assuming the 3rd to 14th signals S2) having a first logic value (eg, logic value 1) are generated. In other words, in an ideal case, there are 12 signals S2 corresponding to the default reference voltage range ΔVREF.

[0044] However, if the systematic offset reduces the conductance of transistor M2 and / or transistor M5, the difference ΔV after being processed by transistor M2 and transistor M5 will be smaller than the default reference voltage range ΔVREF. Under the same signal swing, part of the comparator circuit will determine the input signal S IN Less than the reference voltage V- x- And / or reference voltage V y , and fixedly outputs a signal S2 (eg, the 1st to 3rd signals S2 and the 14th to 16th signals S2) having a second logic value (eg, logic value 0). In this case, only 10 signals S2 correspond to the default reference voltage range ΔVREF.

[0045] To explain it another way, since these comparator circuits are used to determine the input signal S IN Less than the reference voltage V- x- And / or reference voltage V y-- The difference between them will output the signal S2 with the second logic value, so it can be regarded as the reference voltage V- x- And / or reference voltage V y Due to the influence of systematic offset, it is equivalently larger (compared to the ideal situation). The above phenomenon can be called "reference voltage expansion". In this case, it can be observed that the maximum number of the first logic value of the multiple signals S2 corresponding to the predicted reference voltage range ΔVREF is reduced (equivalent to the distribution of the multiple signals S2 is reduced). On the other hand, the correction circuit 180 can count and calculate the standard deviation of the corresponding labels of these signals S2 with the first logic value. If the standard deviation becomes lower, it means that the distribution of the multiple signals S2 is reduced, so it can be regarded as the occurrence of "reference voltage expansion". The correction circuit 180 can output the control signal V C1 To adjust the input signal S IN + and input signal SIN - Common mode level (such as Figure 2C Alternatively, the correction circuit 180 may output a control signal V C1 To adjust and generate the 3rd to 14th signals S 2- - Each comparator circuit receives a reference voltage V x And the reference voltage V y (like Figure 2D to correct this offset.

[0046] In another case, if the systematic offset increases the conductance of transistor M2 and / or transistor M5, the difference ΔV after being processed by transistor M2 and transistor M5 will be greater than the default reference voltage range ΔVREF. Under the same signal swing, more comparator circuits will consider the input signal S IN Greater than the reference voltage V- x- And / or reference voltage V y , and outputs a signal S2 (eg, the 2nd to 15th signal S2) with a specific logic value (eg, logic value 1). In this case, there are 14 signals S2 corresponding to the default reference voltage range ΔVREF.

[0047] To explain it another way, since these comparator circuits are used to determine the input signal S IN Greater than the reference voltage V- x- And / or reference voltage V y-- The difference between the two voltages will output a signal S2 with a specific logic value, so it can be equivalently regarded as the reference voltage V- x- And / or reference voltage V y Because the systematic offset becomes smaller (compared to the ideal situation). The above phenomenon can be called "reference voltage shrinkage". In this case, it can be observed that the maximum number of the multiple signals S2 with the first logic value corresponding to the predicted reference voltage range ΔVREF increases (equivalent to the distribution of the multiple signals S2 increasing). On the other hand, the correction circuit 180 can count and calculate the standard deviation of the corresponding numbers of these multiple signals S2 with the first logic value. If the standard deviation becomes higher, it means that the distribution of the multiple signals S2 increases, so it can be regarded as "reference voltage shrinkage". Similarly, the correction circuit 180 can adjust the input signal S IN + and input signal S IN - Common mode level (such as Figure 2C As shown), or adjust to generate the 2nd to 15th signals S 2- - Each of the comparator circuits receives a reference voltage V x And the reference voltage V y (like Figure 2D to correct this offset.

[0048] It should be understood that the above-mentioned method of detecting the systematic offset is by observing the multiple signals S2 output by the comparator circuit system 160. Therefore, this detection method is not limited to the internal circuit structure of the dual differential amplifier circuit 162, and thus can cover a variety of possible causes of the systematic offset.

[0049] The following table shows the simulation results based on an experimental example:

[0050] Systematic offset (mV) 0 +100 Standard Deviation (No.) 4.4 4

[0051] The systematic shift in the table is equivalent to Figure 2A The input signal S IN + and input signal S IN -. In some embodiments, the calibration circuit 180 may adjust the test signal S with a default common-mode level (ie, a systematic offset of 0 millivolts) to T1 And the test signal S T2 The output is respectively the input signal S IN + and input signal S IN -. In response to this test signal S T1 And the test signal S T2 , the comparator circuit system 160 generates a plurality of signals S2. The calibration circuit 180 may calculate a standard deviation of the signals S2 and record the standard deviation (which corresponds to a predetermined common mode level) as a default value of the distribution of the plurality of signals S2.

[0052] Next, the calibration circuit 180 may add a systematic offset to the test signal S T1 And the test signal S T2 The common mode level and the test signal S T1 And the test signal S T2 The output is respectively the input signal S IN + and input signal S IN Based on the same operation, the calibration circuit 180 can calculate the current standard deviation of the signals S2. The calibration circuit 180 can compare the current standard deviation with the previously recorded default values ​​and adjust the common mode level or at least one first reference voltage and at least one second reference voltage when the current standard deviation is different from the default values.

[0053] For example, as shown in the table above, when no systematic offset is added (ie, 0 millivolts), the default value of the distribution of the multiple signals S2 is 4.4. When an offset voltage of +100 millivolts is added, the multiple signals S 2-- The standard deviation of is 4. Since the current distribution (ie, 4) is smaller than the default value (ie, 4.4), the calibration circuit 180 can confirm that part of the dual differential amplifier circuit 162 in the comparator circuit system 160 is affected by the “reference voltage expansion”.

[0054] Or, if the offset voltage is added, multiple signals S 2-- The standard deviation of is greater than the default value (ie, 4.4), and the calibration circuit 180 can confirm that part of the dual differential amplifier circuit 162 in the comparator circuit system 160 is affected by the “reference voltage internalization”.

[0055] In some embodiments, the test signal S T1 With the test signal S T2 It may be a signal having a predetermined common mode level and a predetermined signal swing. In some embodiments, the test signal S T1 With the test signal S T2 The calibration circuit 180 can sequentially output a plurality of test signals S with different DC levels. T1 With the test signal S T2 , to analyze the distribution of multiple signals S2.

[0056] The above example of using the maximum number or standard deviation of the plurality of signals S2 having the first logic value to determine the distribution of the signal S2 is only for illustration, and the present application is not limited thereto. Various statistical indicators that can reflect the distribution of the signal S2 are within the scope of the present application.

[0057] Figure 4 FIG. 4 is a flow chart of a calibration method 400 according to an embodiment of the present application. In some embodiments, the calibration method 400 may be (but not limited to) Figure 1 The correction circuit 180 performs.

[0058] In operation S410, a first test signal is output as a first input signal, and a second test signal is output as a second input signal, wherein the flash converter includes a plurality of dual differential comparator circuits, each of the dual differential comparator circuits compares the first input signal with a corresponding one of a first set of reference voltages, and compares the second input signal with a corresponding one of a second set of reference voltages to generate a corresponding one of a plurality of first signals.

[0059] In operation S420 , a common mode level of each of the first input signal and the second input signal is calibrated according to a distribution of the plurality of first signals, or at least one first reference voltage of the first reference voltage group and at least one second reference voltage of the second reference voltage group are calibrated.

[0060] The description of the multiple operations of the calibration method 400 can refer to the aforementioned multiple embodiments, so it is not repeated here. The multiple operations are only examples and are not limited to being performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present application, the various operations under the calibration method 400 can be appropriately increased, replaced, omitted or performed in a different order. Alternatively, one or more operations under the calibration method 400 can be performed simultaneously or partially simultaneously.

[0061] In summary, the flash analog-to-digital converter and calibration method in the embodiments of the present application can observe whether a systematic offset occurs in the comparator circuit system by analyzing the distribution of multiple signals, and calibrate the systematic offset to improve the reliability of the overall operation.

[0062] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Ordinary technicians in this technical field can make changes to the technical features of the present application based on the explicit or implicit contents of the present application. All these changes belong to the protection scope of the present application. In other words, the protection scope of the present application shall be based on the protection scope that can be determined in the specification.

[0063] Description of Reference Numerals

[0064] 100: Flash analog-to-digital converter

[0065] 120: Reference voltage generating circuit

[0066] 140: Encoder circuit

[0067] 160: Comparator circuit system

[0068] 162,162-1,162-2,162-n: Dual differential amplifier circuit

[0069] 164: Latch circuit

[0070] 180: Correction circuit

[0071] EN: Enable signal

[0072] RX,RY,R1,R2:resistance

[0073] S1,S2,S 1+ ,S 1- :Signal

[0074] S D :Digital signal

[0075] S IN +,S IN -,S IN :Input signal

[0076] ST1 ,S T2 :Test signal

[0077] V C1 :Control signal

[0078] V RN ,V RP :Voltage

[0079] V x1 ~V xm ,V y1 ~V ym ,V x ,V y :Reference voltage

[0080] 201,202: Current source circuit

[0081] GND: Ground voltage

[0082] M1~M8: Transistor

[0083] V B1 :Bias signal

[0084] VDD: power supply voltage

[0085] V OS :Offset voltage

[0086] V1~V6,V2',V3',V5',V6':Signal components

[0087] ΔVREF: default reference voltage range

[0088] 400: Calibration method

[0089] S410, S420: Operation

Claims

1. A flash analog-to-digital converter, comprising: a plurality of double-differential comparator circuits, wherein each of the plurality of double-differential comparator circuits is used to compare a first input signal with a corresponding one of a first set of reference voltages, and to compare a second input signal with a corresponding one of a second set of reference voltages, so as to generate a corresponding one of a plurality of first signals; as well as A correction circuit is used to output a first test signal as the first input signal and a second test signal as the second input signal in a test mode, and to correct a common mode level of each of the first input signal and the second input signal according to a distribution of multiple second signals, or to correct at least one first reference voltage in the first group of reference voltages and at least one second reference voltage in the second group of reference voltages.

2. The flash analog-to-digital converter according to claim 1, wherein: The calibration circuit is further used for comparing the distribution with a default value to adjust the common mode level or adjust the at least one first reference voltage and the at least one second reference voltage.

3. The flash analog-to-digital converter according to claim 2, wherein: The calibration circuit is used for outputting the first test signal and the second test signal having a default common mode level, and recording the distribution corresponding to the default common mode level as the default value.

4. The flash analog-to-digital converter according to claim 1, wherein: The calibration circuit is used to calculate a standard deviation of the plurality of first signals to determine the distribution.

5. The flash analog-to-digital converter according to claim 1, wherein: Also includes: A reference voltage generating circuit is used to generate the first set of reference voltages and the second set of reference voltages according to a first voltage and a second voltage.

6. The flash analog-to-digital converter according to claim 5, characterized in that: The at least one first reference voltage includes at least one of a third voltage or a fourth voltage, the third voltage is a voltage in the first group of reference voltages that is closest to the first voltage, and the fourth voltage is a voltage in the first group of reference voltages that is closest to the second voltage.

7. The flash analog-to-digital converter according to claim 5, wherein: The at least one second reference voltage includes at least one of a third voltage or a fourth voltage, the third voltage being a voltage in the second set of reference voltages closest to the first voltage, and the fourth voltage being a voltage in the second set of reference voltages closest to the second voltage.

8. A calibration method for calibrating a flash analog-to-digital converter, the calibration method comprising: Outputting a first test signal as a first input signal and outputting a second test signal as a second input signal, wherein the flash analog-to-digital converter comprises a plurality of double-differential comparator circuits, each of the plurality of double-differential comparator circuits being used to compare the first input signal with a corresponding one of a first set of reference voltages and to compare the second input signal with a corresponding one of a second set of reference voltages to generate a corresponding one of a plurality of first signals; as well as A common mode level of each of the first input signal and the second input signal is corrected according to a distribution of a plurality of second signals, or at least one first reference voltage in the first reference voltage group and at least one second reference voltage in the second reference voltage group are corrected.

9. The calibration method according to claim 8, characterized in that: Calibrating the common mode level or calibrating the at least one first reference voltage and the at least one second reference voltage includes: A standard deviation of the first signals is calculated to determine the distribution.

10. The calibration method according to claim 8, characterized in that: Calibrating the common mode level or calibrating the at least one first reference voltage and the at least one second reference voltage includes: comparing the distribution to a default value; and When the distribution is different from the default value, the common mode level is adjusted or the at least one first reference voltage and the at least one second reference voltage are adjusted.

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