Analog front-end circuit and control method for analog-to-digital converter

Abstract

An analog-to-digital converter analog front-end circuit and control method includes a continuous-time linear equalizer, an input buffer, a sample-and-hold circuit, an output buffer, and a clock generation circuit. A differential input signal is connected to the input of the continuous-time linear equalizer. The differential outputs of the continuous-time linear equalizer are connected to the inputs of two input buffers, respectively. The outputs of the two input buffers have opposite phases and serve as the positive and negative inputs of four sample-and-hold circuits, respectively. The differential output of each sample-and-hold circuit is connected to four sampling switches. The outputs of the 4×4 sampling switches serve as inputs to the output buffers, generating a total of 16 differential signals. The clock generation circuit generates four control signals that are connected to the sample-and-hold circuits. The present invention uses a three-stage continuous-time linear equalizer, each stage using the same structure, which reduces design complexity and increases bandwidth and frequency adjustment range.

Description

Technical Field

[0001] The present invention belongs to the field of analog integrated circuit design, and in particular relates to an analog-to-digital converter analog front-end circuit and a control method. Background Art

[0002] The rapid development of digital circuits has led to an increasing proportion of digital modules in most integrated circuit products. The advantages of digital circuits lie in their high speed and strong anti-interference capabilities. Thanks to the continuous advancement of semiconductor processes, the size of individual MOSFETs has been continuously reduced, which has led to faster switching speeds in digital circuits and increased computing power across the entire circuit. To meet the speed demands of digital circuits, research on high-speed, high-precision ADCs is urgently needed. Designing a single ADC with high speed, high precision, and low power consumption places high demands on designers. As ADCs based on single-channel sampling architectures reach performance bottlenecks, ADCs based on time interleaving have emerged to increase ADC sampling rates. Compared to single-channel ADCs, this architecture reduces the sampling rate of each sub-channel while simultaneously operating multiple channels in parallel, achieving a very high overall sampling rate. In practical applications, these high-bandwidth, high-speed ADCs often suffer from high-frequency input signal loss. Therefore, a compensation circuit, integrated between the input and sample-and-hold circuits, is required. The analog front end of an analog-to-digital converter (ADC) typically employs a continuous-time linear equalizer (CTE) module for this purpose. In 2016, Broadcom proposed a 32Gbps, 8-bit precision analog front-end for analog-to-digital converters. Using a one-stage continuous-time linear equalizer and a two-stage programmable gain amplifier, it achieved 14dB of gain adjustment and 7dB of peak control, achieving a data rate of 32bps in a 28nm process. The ENOB was 6.4 bits at low frequencies and 5.85 bits at the Nyquist frequency, with power consumption of 320mW. In 2018, Kevin Zheng et al. proposed an analog front-end for analog-to-digital converters, primarily for short-distance data transmission. This architecture is based on an inverter biased by a regulated ground supply. A ring oscillator-based feedback loop stabilizes the inverter's unity-gain frequency, thereby tracking PVT variations. The continuous-time linear equalizer core measures only 20µm × 15µm and consumes 6mW. In the same year, he also proposed an inverter-based analog receiver front end, which included a hybrid continuous-time linear equalizer for low-frequency and high-frequency peaks and an inverter-based programmable gain amplifier, achieving a 0.00425mm 2 In 2019, Shiva Kiran et al. proposed a two-stage programmable continuous-time linear equalizer. Test results showed that the gain reached 15dB at a frequency of 13GHz and a minimum peak control of 4.7dB could be achieved.

[0003] All of the above technologies require a PGA to compensate and adjust the gain, and a calibration module to calibrate the clock, which increases power consumption and design complexity. Summary of the Invention

[0004] The object of the present invention is to provide an analog-to-digital converter analog front-end circuit and a control method to solve the shortcomings of the above-mentioned prior art, such as complex circuits and low compensation gain of the analog-to-digital converter analog front-end.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] An analog front-end circuit for an analog-to-digital converter includes a continuous-time linear equalizer, an input buffer, a sample-and-hold circuit, an output buffer, and a clock generation circuit. A differential input signal is connected to the input end of the continuous-time linear equalizer. The differential output ends of the continuous-time linear equalizer are respectively connected to the input ends of two input buffers. The output phases of the two input buffers are opposite and serve as the positive and negative inputs of four sample-and-hold circuits, respectively. The differential output of each sample-and-hold circuit is connected to four sampling switches. The outputs of the 4×4 sampling switches serve as the inputs of the output buffers, generating a total of 16 differential signals. The clock generation circuit separates four control signals and connects them to the sample-and-hold circuits.

[0007] Furthermore, the continuous-time linear equalizer has three stages, and the three stages adopt the same configuration, including: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first current source, a second current source, a third current source, a fourth current source, a first resistor, a second resistor, a third resistor, a first capacitor, and a second capacitor; the first NMOS transistor and the second NMOS transistor serve as input transistors, the third NMOS transistor and the fourth NMOS transistor are cross-coupled and connected, the first resistor and the second resistor serve as load resistors for the first, third NMOS transistors and the second and fourth NMOS transistors, respectively, the first, second, third, and fourth current sources serve as source current sources for the first, second, third, and fourth NMOS transistors, respectively, the third resistor and the first capacitor are connected between the sources of the first and second NMOS transistors for frequency compensation, and the second capacitor is connected between the sources of the third and fourth NMOS transistors.

[0008] Furthermore, the sample-and-hold circuit adopts differential input and differential output, and a dummy tube with the same size as the input NMOS is connected between the two outputs.

[0009] Furthermore, the input buffer adopts an adaptive bias source follower.

[0010] Furthermore, the output buffer adopts a source follower.

[0011] Furthermore, the clock generation circuit generates:

[0012] Four control signals: CK4 (0:3), EN4 (0:3), Res4 (0:3) and EN16 (0:15);

[0013] Used to control the working sequence of each branch;

[0014] Its frequency satisfies CK4(0:3)=4EN4(0:3)=4Res4(0:3)=4EN16(0:15).

[0015] Furthermore, the 16 Sub-ADCs are divided into a 4×4 array, and every 4 Sub-ADCs form a unit Ui.

[0016] Furthermore, a control method for an analog front-end circuit of an analog-to-digital converter includes:

[0017] When CK4(0) reaches a high level, Res4(0) and EN4(0) will reach a high level first, eliminating the sampled charge of the previous stage and correcting the mismatch voltage;

[0018] When CK4(0) reaches the high point, Res4(0) becomes low level and EN4(0) remains unchanged. At this time, the input signal is collected on the sampling capacitor of sub-ADC(0). When EN16(0) is high level, the sampled signal is sent to sub-ADC(0) for processing.

[0019] When the next EN4(i) is valid, the sampling of the next Sub-ADC is continued; CK(1), CK(2), and CK(3) are sampled alternately to control U1, U2, and U3 respectively.

[0020] Compared with the prior art, the present invention has the following technical effects:

[0021] This invention uses a three-stage continuous-time linear equalizer, each using the same structure, reducing design complexity while increasing bandwidth and frequency adjustment range. The clock circuit directly outputs a four-phase quadrature clock. When the loop is locked, the phases between the clocks are fixed, eliminating the need for an additional calibration module. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of an analog front end of a digital-to-analog converter according to the present invention;

[0023] Figure 2 A schematic diagram of the clock control logic of the present invention;

[0024] Figure 3 Schematic diagram of a continuous-time linear equalizer according to the present invention;

[0025] Figure 4 Schematic diagram of the sample-and-hold circuit of the present invention;

[0026] Figure 5 is a schematic diagram of the input and output buffers of the present invention;

[0027] Figure 6 This is a diagram showing the AC simulation results of the continuous-time linear equalizer of the present invention;

[0028] Figure 7 This is a simulation result diagram of the sample-and-hold circuit of the present invention;

[0029] Figure 8 This is a simulation result diagram of the input buffer of the present invention;

[0030] Figure 9 This is a simulation result diagram of the output buffer of the present invention. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] The present invention is described in further detail below with reference to the accompanying drawings:

[0034] See also Figure 1An ultra-high-speed analog-to-digital converter analog front-end circuit includes a continuous-time linear equalizer, an input buffer, a sample-and-hold circuit, an output buffer, and a clock generation circuit. A differential input signal is connected to the input of the continuous-time linear equalizer. The differential outputs of the continuous-time linear equalizer are connected to the inputs of two input buffers. The outputs of the two buffers have opposite phases and serve as the positive and negative inputs of four sample-and-hold circuits, respectively. The differential output of each sample-and-hold circuit is connected to four sampling switches. The outputs of the 4×4 sampling switches serve as the inputs of the output buffers, generating a total of 16 differential signals. The 16 sub-ADCs are arranged in a 4×4 array, with each four sub-ADCs forming a unit Ui. The process involves the following steps:

[0035] S1: First, Res4(0) and EN4(0) will reach a high level when CK4(0) reaches a high level. The purpose is to eliminate the sampled charge of the previous stage and also has the function of correcting the mismatch voltage.

[0036] S2: When CK4(0) reaches the high point, Res4(0) becomes low level and EN4(0) remains unchanged. At this time, the input signal is collected on the sampling capacitor of sub-ADC(0). When EN16(0) is high level, the sampled signal is sent to sub-ADC(O) for processing.

[0037] S3: Similarly, when the next EN4(i) is valid, the next Sub-ADC sampling is continued. Similarly, CK(1), CK(2), and CK(3) are sampled alternately to control U1, U2, and U3 respectively.

[0038] See also Figure 2 The clock generation circuit generates four control signals: CK4(0:3), EN4(0:3), Res4(0:3) and EN16(0:15), which are used to control the working timing of each branch. The frequency satisfies CK4(0:3)=4EN4(0:3)=4Res4(0:3)=4EN16(0:15).

[0039] See also Figure 3The continuous-time linear equalizer has three stages, and the three stages adopt the same configuration, including: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first current source, a second current source, a third current source, a fourth current source, a first resistor, a second resistor, a third resistor, a first capacitor, and a second capacitor; the first NMOS transistor and the second NMOS transistor serve as input pairs, the third NMOS transistor and the fourth NMOS transistor are cross-coupled and connected, the first resistor and the second resistor serve as load resistors for the first and third NMOS transistors and the second and fourth NMOS transistors respectively, the first, second, third, and fourth current sources serve as source current sources for the first, second, third, and fourth NMOS transistors respectively, the third resistor and the first capacitor are connected between the sources of the first and second NMOS transistors for frequency compensation, and the second capacitor is connected between the sources of the third and fourth NMOS transistors.

[0040] See also Figure 4 The sample-and-hold circuit uses differential input and differential output. The two outputs are connected with dummy tubes M11 and M12 of the same size as the input NMOS, and dummy tubes M13 and M14 of the same size as the sampling capacitor.

[0041] See also Figure 5 The input buffer uses an adaptive bias source follower to provide high bandwidth. The output branch switches slowly, so a large bandwidth is not required. The output buffer uses a source follower. A buffer has three functions. First, a buffer typically has high input impedance and low output impedance. If a sample-and-hold circuit requires a large bandwidth, the resistance in series with the sampling capacitor needs to be as small as possible. A low-output-impedance buffer can achieve this requirement. Second, since the input signal needs to drive multiple subsequent sub-channels, and the input signal's drive capability is limited, a buffer can increase the drive capability. Third, the buffer can isolate the sample-and-hold circuit from the input signal.

[0042] Figure 6 This is the AC simulation result of the continuous-time linear equalizer. The DC gain of the circuit can be adjusted from -17dB to 9.6dB, and the compensation amplitude at the Nyquist frequency of 2GHz reaches 15dB.

[0043] Figure 7 This is the Fast Fourier Analysis result of the sample-and-hold circuit. Based on the coherent sampling theorem, a 2048-point FFT analysis is performed on the output signal. The spurious-free dynamic range is 59.815dB and the effective number of bits is 95998 bits.

[0044] Figure 8 and Figure 9These are the AC simulation results of the input buffer and output buffer, respectively. The input buffer bandwidth is 14.18 GHz, and the output buffer bandwidth is 9.08 GHz.

Claims

1. An analog-to-digital converter analog front-end circuit, characterized in that: The system comprises a continuous-time linear equalizer, an input buffer, a sample-and-hold circuit, an output buffer, and a clock generation circuit; a differential input signal is connected to the input of the continuous-time linear equalizer; the differential outputs of the continuous-time linear equalizer are respectively connected to the inputs of two input buffers; the outputs of the two input buffers have opposite phases and serve as the positive and negative inputs of four sample-and-hold circuits, respectively; the differential output of each sample-and-hold circuit is connected to four sampling switches; the outputs of the 4×4 sampling switches serve as the inputs of the output buffers, generating a total of 16 differential signals; 16 differential signals are used as input signals for 16 sub-ADCs; the clock generation circuit generates four control signals that are connected to the sample-and-hold circuit; The sample-and-hold circuit uses differential input and differential output. The two outputs are connected with dummy transistors M11 and M12 of the same size as the input NMOS, and dummy transistors M13 and M14 of the same size as the sampling capacitor. The continuous-time linear equalizer has three stages, each using the same configuration, including: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first current source, a second current source, a third current source, a fourth current source, a first resistor, a second resistor, a third resistor, a first capacitor, and a second capacitor; the first NMOS transistor and the second NMOS transistor serve as input transistors, the third NMOS transistor and the fourth NMOS transistor are cross-coupled, the first resistor and the second resistor serve as load resistors for the first and third NMOS transistors, and the second and fourth NMOS transistors, respectively; the first, second, third, and fourth current sources serve as source current sources for the first, second, third, and fourth NMOS transistors, respectively; the third resistor and the first capacitor are connected between the sources of the first and second NMOS transistors for frequency compensation, and the second capacitor is connected between the sources of the third and fourth NMOS transistors.

2. The analog front-end circuit of an analog-to-digital converter according to claim 1, wherein: The input buffer uses an adaptive bias source follower.

3. The analog front-end circuit of an analog-to-digital converter according to claim 1, wherein: The output buffer uses a source follower.

4. The analog front-end circuit of an analog-to-digital converter according to claim 1, wherein: Clock generation circuit generates: Four control signals: CK4 (0:3), EN4 (0:3), Res4 (0:3) and EN16 (0:15); Used to control the working sequence of each branch; Its frequency satisfies CK4(0:3)=4EN4(0:3)=4Res4(0:3)=4EN16(0:15).

5. The analog front-end circuit of an analog-to-digital converter according to claim 1, wherein: The 16 Sub-ADCs are divided into a 4×4 array, and every 4 Sub-ADCs form a unit Ui.

6. A control method for an analog front-end circuit of an analog-to-digital converter, characterized in that: An analog-to-digital converter analog front-end circuit according to any one of claims 1 to 5, comprising: When CK4(0) reaches a high level, Res4(0) and EN4(0) will reach a high level first, eliminating the sampled charge of the previous stage and correcting the mismatch voltage; When CK4(0) reaches the high point, Res4(0) becomes low level and EN4(0) remains unchanged. At this time, the input signal is collected on the sampling capacitor of sub-ADC(0). When EN16(0) is high level, the sampled signal is sent to sub-ADC(0) for processing. When the next EN4(i) is valid, the sampling of the next Sub-ADC is continued; CK(0), CK(1), CK(2), and CK(3) are sampled alternately to control U0, U1, U2, and U3 respectively.

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