A memory test circuit and device

Abstract

A memory test circuit and device, relating to the field of chip technology, solves the problem in the prior art that the built-in self-test circuit of the memory has too large an area overhead and is difficult to implement the test of multiple ports performing read and write operations simultaneously. The test circuit comprises a test controller (301) and an address signal converter (302), wherein the test controller (301) is used to generate a test address and write test data to a memory (303); the address signal converter (302) is used to receive the test address and convert the test address into multiple storage addresses of the test data in the memory (303), and input the multiple storage addresses into multiple address input ports of the memory (303); the test controller (301) is also used to read data from the multiple storage addresses and generate a test result based on the read data.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a memory test circuit and device. Background Art

[0002] As multi-processor computing systems are increasingly used, multi-port static random access memory (SRAM) plays a very important role when the processor needs to initiate multiple read and write operations at the same time. During the production of chips, some chips may have physical defects due to manufacturing process problems. For example, some lines of the read and write control circuits may be short-circuited or open-circuited. Therefore, in order to screen out defective chips, it is usually necessary to test the chips through test circuits. For SRAM, memory built-in self-testing (MBIST) circuits are usually used for testing.

[0003] In order to implement the test of SRAM, in one solution, a group of shared buses can be used to access the SRAM, and an MBIST test circuit needs to be added to the solution. During the test, if multiple SRAMs need to be tested, each SRAM can be accessed through the share bus to complete the test. When testing each SRAM, the existing share bus can only read and write to a group of ports of an SRAM at a time, and the commonly used SRAM does not support simultaneous write operations to an address from multiple ports (two or more write ports). If the share bus is expanded to access more than two addresses, the MBIST test circuit area will be too large, and the circuit production process will be difficult to implement. At the same time, it will also seriously affect the computing performance of the central processing unit (CPU). Another solution is to add a selector at the input end of the memory to select the input signal for normal function and the input signal for test. The input signal for test comes from the test controller. This solution can perform read and write tests on a group of ports of the memory at a time, but if you want to implement simultaneous read and write tests on multiple ports, you need to add multiple test controllers, which will result in too large an area overhead for the test circuit and difficulty in physical implementation. Summary of the invention

[0004] The present application provides a memory test circuit and device, which solves the problem in the prior art that the built-in self-test circuit of the memory has too large an area overhead and is difficult to implement the test of multiple ports performing read and write operations simultaneously.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect, a test circuit for a memory is provided, the test circuit comprising a test controller and an address signal converter, wherein the test controller is used to generate a test address and write test data to the memory; the address signal converter is used to receive the test address, convert the test address into multiple storage addresses of the test data in the memory, and input the multiple storage addresses into multiple address input ports of the memory; the test controller is also used to read data from the multiple storage addresses and generate test results based on the read data.

[0007] In the embodiment of the present application, by setting an address signal converter on the periphery of the memory, the test address generated by the test controller can be converted into multiple storage addresses, input into multiple address input ports of the memory, and the test controller determines the test result according to the data read from the memory. The test circuit can be an MBIST test circuit, thereby realizing an MBIST test circuit, and testing the read / write operation of multiple ports of the memory simultaneously through a group of share bus buses, without the need to expand the share bus bus to test the multi-port memory, and without adding multiple test controllers, solving the problem of large overhead generated by expanding the share bus bus or setting multiple test controllers, and improving the test efficiency of the MBIST test circuit.

[0008] In a possible design, the test address is converted into multiple storage addresses of the test data in the memory, and the multiple storage addresses are input into multiple address input ports of the memory, specifically including: converting the test address into multiple write input addresses, and / or multiple read input addresses, wherein the multiple write input addresses and the multiple read input addresses are different from each other; inputting the multiple write input addresses into the multiple write address input ports of the memory, and inputting the multiple read input addresses into the multiple read address input ports of the memory. In the above possible implementation, the address signal converter converts the test address into multiple write input addresses and / or multiple read input addresses, and inputs them into the multiple write address input ports and / or multiple read address input ports of the memory respectively, so that the multiple ports of the memory can be tested for simultaneous read data operation, simultaneous write data operation, or simultaneous read and write data operation through a group of share bus buses, thereby improving the test efficiency of the test circuit.

[0009] In a possible design, the test circuit further includes a selector; the selector is used to select and output data read from multiple storage addresses of the memory according to a selection signal output by the test controller. In the above possible implementation, the storage data output by the memory is selected and output by the selector, and the data read at the same time can be output to the test controller in turn to judge the test results, which can improve the test efficiency of the test circuit.

[0010] In a possible design, the test controller is also used to generate a read / write control signal, and the test circuit also includes a read / write signal converter; the read / write signal converter is used to receive the read / write control signal and convert the read / write control signal into multiple read control signals and / or multiple write control signals; the multiple write control signals are input into multiple write control ports of the memory, and the multiple read control signals are input into multiple read control ports of the memory. In the above possible implementation, the read / write signal converter converts the read / write control signal generated by the test controller into multiple read control signals and / or multiple write control signals, which are input into the memory to control the read / write data, thereby realizing the test of simultaneous read / write operations on multiple ports of the memory and improving the test efficiency of the test circuit.

[0011] In a possible design, the test controller is also used to generate test data, and the test circuit also includes a data signal converter; the data signal converter is used to receive the test data and convert the test data into multiple test data; the multiple test data are input into multiple write data input ports of the memory; wherein at least two of the multiple test data are different. In the above possible implementation, the data signal converter converts the test data generated by the test controller into multiple test data for inputting into the memory to control the write data, thereby realizing the test of simultaneous write operations on multiple ports of the memory and improving the test efficiency of the test circuit.

[0012] In one possible design, the test controller is further used to generate a test mode signal, and the test mode signal includes a multi-port test signal and a single-port test signal. In the above possible implementation, the test mode signal generated by the test controller can be used to select whether the test circuit performs a single-port test or a multi-port test, thereby improving the flexibility of the test circuit.

[0013] In a possible design, the read / write signal converter is also used to: when the test mode signal is a multi-port test signal, output multiple read control signals and / or multiple write control signals output by the read / write signal converter; when the test mode signal is a single-port test signal, output the read / write control signal generated by the test controller. In the above possible implementation, the read / write signal converter selects to output a single read / write control signal or multiple read / write control signals according to the test mode signal generated by the test controller, so as to select whether the test circuit performs a single-port test or a multi-port test, thereby improving the flexibility of the test circuit.

[0014] In a possible design, the address signal converter is also used to: when the test mode signal is a multi-port test signal, output multiple write input addresses and / or multiple read input addresses output by the address signal converter; when the test mode signal is a single-port test signal, output the test address generated by the test controller. In the above possible implementation, the address signal converter selects to output a single test address or multiple test addresses according to the test mode signal generated by the test controller, so as to select whether the test circuit performs a single-port test or a multi-port test, thereby improving the flexibility of the test circuit.

[0015] In a possible design, the data signal converter is also used to: output multiple test data output by the data signal converter when the test mode signal is a multi-port test signal; and output test data generated by the test controller when the test mode signal is a single-port test signal. In the above possible implementation, the output data signal converter selects to output a single test data or multiple test data according to the test mode signal generated by the test controller, thereby selecting whether the test circuit performs a single-port test or a multi-port test, thereby improving the flexibility of the test circuit.

[0016] In a second aspect, a memory test chip is provided, the memory test chip comprising a test circuit as described in any possible design method of the first aspect. It can be understood that the beneficial effects that can be achieved by the above-mentioned memory test chip can refer to the beneficial effects of the test circuit provided in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a memory chip provided in an embodiment of the present application;

[0018] Figure 2 A schematic diagram of the structure of a memory test circuit provided in an embodiment of the present application;

[0019] Figure 3 A schematic diagram of the structure of another memory test circuit provided in an embodiment of the present application;

[0020] Figure 4 A schematic diagram of the structure of another memory test circuit provided in an embodiment of the present application;

[0021] Figure 5 A schematic diagram of the structure of another memory test circuit provided in an embodiment of the present application;

[0022] Figure 6 A schematic diagram of the structure of another memory test circuit provided in an embodiment of the present application;

[0023] Figure 7 A logic circuit diagram of another address signal converter provided in an embodiment of the present application;

[0024] Figure 8 A logic circuit diagram of another data signal converter provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this embodiment, unless otherwise specified, "plurality" means two or more.

[0026] Before introducing the embodiments of the present application, the technologies involved are first introduced as follows:

[0027] Static Random-Access Memory (SRAM): is a type of random access memory. Static means that the stored data can be kept constant when the memory is powered on; compared with dynamic random access memory (DRAM), it does not require periodic refresh circuits to save the data stored inside.

[0028] Random Access Memory (RAM): Also called main memory, it is an internal memory that directly exchanges data with the CPU. Data can be read and written at any time (except when refreshed) at a very high speed. It is usually used as a temporary data storage medium for operating systems or other running programs. When working, RAM can write (store) or read (retrieve) information from any specified address at any time. According to the working principle of the storage unit, RAM is divided into SRAM and DRAM.

[0029] Memory built-in self-testing (MBIST) is a technology that embeds relevant test functions into the circuit when designing memory chips. It is used to provide self-test functions, thereby reducing the dependence of device testing on automatic test equipment.

[0030] Memory is a memory device used to store data and instructions in electronic computers. It can be an independent chip or integrated with other devices. The main function of memory is to store programs and various data, and to access programs or data at high speed and automatically during computer operation. Types of memory can include: SRAM, RAM, DRAM, non-volatile magnetic random access memory (MRAM), flash memory, etc.

[0031] Logic gate: It is a basic component on an integrated circuit. A simple logic gate can be composed of transistors, so that the high and low levels representing two signals will generate a high or low signal after passing through the logic gate. High and low levels can represent logical "true" and "false" or 1 and 0 in binary, respectively, to achieve logical operations. Common logic gates include AND gates, OR gates, NOT gates, and XOR gates. Logic gates can be used in combination to achieve complex logical operations.

[0032] An embodiment of the present application provides a memory test circuit, which implements simultaneous read / write operations on multiple ports of a memory by adding a logic circuit to an ordinary memory test circuit structure, thereby solving the problem in the prior art that the built-in self-test circuit of the memory has too large an area overhead and is difficult to implement simultaneous read / write operations on multiple ports.

[0033] The embodiments of the present application can be implemented in a computer device, and the memory test circuit can be specifically applied to a multi-processor computing system, that is, a computer system that requires multiple processors to simultaneously initiate multiple data read / write operations on the memory.

[0034] First, the structure and principle of the memory chip involved in the present application are briefly introduced. The following embodiments of the present application are described in detail only by taking the SRAM memory as an example, which does not impose certain limitations on the present application.

[0035] like Figure 1 As shown, a multi-port SRAM memory chip can simultaneously perform n port write data operations and m port read data operations. The memory chip includes multiple write address input ports, multiple read address input ports, multiple write data input ports, multiple write control ports, multiple read control ports, and multiple read data output ports.

[0036] Specifically, it can be, Figure 1 As shown, it includes: write address input port 1, write address input port 2...write address input port n, read address input port 1, read address input port 2...read address input port m, write data input port 1, write data input port 2...write data input port n, write control port 1, write control port 2...write control port n, read control port 1, read control port 2...read control port m, read data output port 1, read data output port 2...read data output port m.

[0037] Among them, write address input port 1, write address input port 2...write address input port n can be used to input the storage address of the write memory chip that needs to be written, which can also be called the write address. The bit width of the write address can be determined by the bit width of the storage unit of the memory chip.

[0038] Read address input port 1, read address input port 2, ... read address input port m can be used to input the storage address of the data to be read in the memory chip, which can also be called the read address. The bit width of the read address can be determined by the bit width of the storage unit of the memory chip.

[0039] Write data input port 1, write data input port 2, ... write data input port n can be used to input storage data that needs to be written into the storage unit of the memory chip, which can also be called write data.

[0040] Write control port 1, write control port 2, ... write control port n can be used to input a write control signal that needs to be written, which can also be called a write enable signal. The write control signal input by the write control port can be used to control the data storage operation of the memory write data input port.

[0041] Read control port 1, read control port 2, ..., read control port m can be used to input a read control signal that needs to be read, which can also be called a read enable signal. The read control signal input to the read control port can be used to control the operation of the memory read data output port.

[0042] Read data output port 1, read data output port 2, ... read data output port m can be used to output the storage data in the storage unit corresponding to the above read address that needs to be read, and can also be called read-out data, which is determined by the storage data previously written into the storage unit.

[0043] Furthermore, the multi-port SRAM memory can perform read and write operations simultaneously because multiple sets of read and write circuits are used inside the memory chip to simultaneously control the read and write operations on the storage unit. For example, the write address input port 1, the write data input port 1, and the write control port 1 are electrically connected to a set of write control circuits inside the memory chip, and can be used to perform write data operations through the gating circuit; the read address input port 2, the read data output port 2, and the read control port 2 are electrically connected to a set of read control circuits inside the memory chip, and can be used to perform read data operations through the gating circuit.

[0044] In an embodiment of the present application, in order to ensure that multiple different storage data are not written to the same storage address, causing abnormal operation of the memory chip, the memory chip can be designed so that when multiple ports perform write operations simultaneously, the write addresses of the multiple ports are different.

[0045] In an embodiment of the present application, when a multi-port SRAM memory performs read operations and write operations simultaneously, the write addresses of the multiple ports are different from the read addresses of the multiple ports to avoid performing read operations and write operations on a storage address at the same time, causing abnormal operation of the memory chip.

[0046] That is to say, a general port SRAM memory does not support multiple ports performing write operations on the same write address at the same time; nor does it support multiple ports performing write operations and read operations on the same address at the same time. Therefore, in the embodiment of the present application, testing the multi-port SRAM memory will avoid the occurrence of the above two abnormal situations.

[0047] Figure 1 As shown in Table 1 below, the internal circuit structure of the multi-port SRAM memory chip can be the following symmetrical structure, including: a bit cell array for storing data and a peripheral logic circuit, wherein the peripheral logic circuit may include a sense amplifier, a row / column decoder, an input / output latch, and a read / write circuit, etc.

[0048] Table 1

[0049]

[0050] Among them, the memory cell array (Bit Cell Array) is composed of a large number of memory cells, which are usually arranged in a matrix of N rows × M columns, and each memory cell can store 1 bit of binary data (0, 1). For example, a certain SRAM includes a memory cell array of 128×8×16: that is, the memory includes a bit cell array with a depth of 128 and a bit width of 8×16, and has 128×128 memory cells.

[0051] Timing control circuit (Control and Clock Tree): Controls the input and output signals of the logic circuit on the memory chip through the drive of the clock signal.

[0052] The sense amplifier is used to compare the difference between two input signals and amplify the difference. Since the symmetrical SRAM chip is implemented with a differential circuit structure, that is, the difference between the two signals is used to represent the output value of the signal as 0 or 1, the input signal with a smaller difference can be amplified by the sense amplifier to determine the output signal.

[0053] Row / Column Decorder: It is used to locate the input address to a specific bit cell array. Specifically, the row address decoder outputs a row selection signal, and the column address decoder outputs a column address selection signal. The intersection of the row selection line and the column selection line is the selected storage cell array.

[0054] Read / write control circuit (Read and Write Circuit): By processing the read command or write command output by the central processing unit and combining the row / column selection signal output by the row / column address decoder, it generates a corresponding read control signal (read enable signal) or write control signal (write enable signal) to determine whether the storage cell array located by the row / column selection signal is to perform a read operation or a write operation. When the read enable signal is valid, it indicates that the storage cell array is to perform a read operation, and when the write enable signal is valid, it indicates that the storage cell array is to perform a write operation.

[0055] Input / output latch: A latch maintains a certain level state to temporarily store the signal, and is used to temporarily store the input or output signal.

[0056] The specific principle of the read and write operation of the memory chip is as follows: each memory cell in the memory array shares electrical connections with other cells in rows and columns. By decoding the input address for row / column addresses, specific row selection lines and column selection lines can be selected. The intersection of the row selection line and the column selection line is the selected memory cell. Each memory cell is uniquely selected in this way, and then the selected memory cell is read or written according to the read control signal or the write control signal. Some memories are designed to simultaneously input and output multi-bit data such as 4 or 8 bits. In this case, 4 or 8 memory cells will be selected at the same time according to the above method, and simultaneous read and write operations of multiple ports will be performed.

[0057] Based on the above-mentioned memory chip, the MBIST test circuit is used to perform circuit fault testing on the storage function of the simultaneous reading and writing of multiple ports, so as to find out the short circuit fault, open circuit fault or other possible concurrent coupling fault etc. that may be caused by the memory chip in the manufacturing process. Usually, the MBIST test circuit can be based on the design of the original memory chip, and the test of the memory 203 is realized by constructing a peripheral logic circuit, such as Figure 2 The MBIST test circuit may include a test controller 201 and a selector 202.

[0058] The selector 202 is used to select the storage signal of the normal function input by the system to control the memory 203 to store data, or the test signal input from the test controller 201 to control the memory 203 to perform a functional test according to the system selection signal.

[0059] The test controller 201 is used to output a test control signal, receive test return data, complete a functional test on the memory 203, and output a test result. As shown in Table 2 below, the test control signal of the test controller 201 may include:

[0060] Table 2

[0061]

[0062]

[0063] Furthermore, the test controller 201 is used to output the above-mentioned test control signal, and after the read / write data operation of the memory 203, the test return data received from the memory 203 is compared with the expected value to determine and output the test result.

[0064] like Figure 2 As shown, the internal structure of the test controller 201 may include an address generator 2011 , a data generator 2012 , an algorithm controller 2013 and a comparator 2014 .

[0065] The address generator 2011 is used to generate different test addresses for testing different storage units of the memory 203. The data generator 2012 is used to generate test data to be written into the test address. The algorithm controller 2013 is used to generate a read / write control signal for controlling the read / write operation. The comparator 2014 is used to compare the test return signal of the memory 203 with the expected data generated by the test controller 201, and determine whether the test data passes the test according to the comparison result. For example, if the test passes, a signal 1 can be output, and if the test fails, a signal 0 can be output.

[0066] The embodiment of the present application provides a memory test circuit. Based on the above-mentioned MBIST test circuit structure, a signal conversion circuit is added on the periphery of a memory chip to realize multi-port simultaneous read and write operations, that is, it is possible to simultaneously perform write operation tests on different storage addresses of multiple ports, simultaneously perform read operation tests on different storage addresses of multiple ports, and simultaneously perform read and write operation tests on different storage addresses of multiple ports, thereby covering possible physical defects of SRAM when performing multi-port simultaneous read and write operations, and solving the problem of excessive area overhead of the MBIST test circuit in the prior art.

[0067] like Figure 3 As shown, the memory test circuit may include: a test controller 301 and an address signal converter 302, which are used to test a memory 303. The connection relationship of the memory test circuit may be: multiple output ports of the test controller 301 are connected to multiple input ports of the address signal converter 302, multiple output ports of the address signal converter 302 are connected to multiple input ports of the memory 303, and the output port of the memory 303 returns a test signal and is connected to the input port of the test controller 301.

[0068] The address signal converter 302 is used to receive the test address output by the test controller 301 , convert the test address into multiple storage addresses of the test data in the memory, and input the multiple storage addresses into multiple address input ports of the memory 303 .

[0069] Further, the address signal converter 302 is used to convert a test address into multiple write input addresses and multiple read input addresses through decoding processing, wherein the multiple write input addresses and multiple read input addresses are different from each other. For example, the memory 303 is designed with 7 write address input ports and 12 read address input ports, then the address signal converter can convert the input test address (Adress_in) through address decoding processing to generate 7 different storage addresses for write operations and 12 storage addresses for read operations.

[0070] In actual circuit design, the address signal converter can be implemented by combining logic gate devices such as AND gates, OR gates, NOT gates, XOR gates, etc. As long as a logic circuit can be implemented to generate multiple different storage addresses from an input address, the address decoding function can be implemented. The specific design of the logic circuit of the address signal converter is not limited in the embodiment of the present application.

[0071] Exemplarily, when the test controller outputs a write control signal and outputs a test address of 0000000 for a write operation test, the address signal converter can be designed to convert the input test address 0000000 through a logic circuit and output a plurality of different storage addresses 1 to 19. The storage addresses 1 to 7 can be respectively input into the write address input port 1 to the write address input port 7 of the memory 303; in this embodiment, the premise is that the number n of the write address input ports of the memory 303 is greater than or equal to 7. The storage addresses 8 to 19 can be respectively input into the read address input port 1 to the read address input port 19 of the memory 303. In this embodiment, the premise is that the number m of the read address input ports of the memory 303 is greater than or equal to 12.

[0072] Among them, the 7 storage addresses input to the write address input port can be:

[0073] The storage address 1 input to the write address input port 1 is: 0000000;

[0074] The storage address 2 inputted by the write address input port 2 is: 0000001;

[0075] The storage address 3 input to the write address input port 3 is: 0000010;

[0076] The storage address 4 inputted by the write address input port 4 is: 0000011;

[0077] The storage address 5 inputted into the write address input port 5 is: 0000100;

[0078] The storage address 6 inputted into the write address input port 6 is: 0000101;

[0079] The storage address 7 input into the write address input port 7 is: 0000110.

[0080] The 12 storage addresses input to the read address input port can be:

[0081] The storage address 8 inputted by the read address input port 1 is: 1000000;

[0082] The storage address 9 inputted by the read address input port 2 is: 1000001;

[0083] The storage address 10 inputted into the read address input port 3 is: 1000010;

[0084] The storage address 11 inputted by the read address input port 4 is: 1000011;

[0085] The storage address 12 inputted by the read address input port 5 is: 1000100;

[0086] The storage address 13 inputted by the read address input port 6 is: 1000101;

[0087] The storage address 14 inputted by the read address input port 7 is: 1000110;

[0088] The storage address 15 inputted by the read address input port 8 is: 1000111;

[0089] The storage address 16 inputted by the read address input port 9 is: 1001000;

[0090] The storage address 17 inputted by the read address input port 10 is: 1001001;

[0091] The storage address 18 inputted by the read address input port 11 is: 1001010;

[0092] The storage address 19 input by the read address input port 12 is: 1001011.

[0093] Further, when the test controller outputs a read control signal and outputs a test address of 0000000 for a read operation test, the address signal converter can be designed to convert the input test address 0000000 into a plurality of different storage addresses 1 to 19 after circuit conversion. The storage addresses 1 to 12 can be respectively input into the read address input port 1 to the read address input port 12 of the memory 303; the storage addresses 13 to 19 can be respectively input into the write address input port 1 to the write address input port 7 of the memory 303. In this embodiment, the premise is that the number n of the write address input ports of the memory 303 is greater than or equal to 7, and the number m of the read address input ports is greater than or equal to 12.

[0094] Among them, the 12 storage addresses input to the read address input port can be:

[0095] The storage address 1 input to the read address input port 1 is: 0000000;

[0096] The storage address 2 inputted by the read address input port 2 is: 0000001;

[0097] The storage address 3 inputted by the read address input port 3 is: 0000010;

[0098] The storage address 4 inputted by the read address input port 4 is: 0000011;

[0099] The storage address 5 inputted by the read address input port 5 is: 0000100;

[0100] The storage address 6 inputted by the read address input port 6 is: 0000101;

[0101] The storage address 7 inputted by the read address input port 7 is: 0000110;

[0102] The storage address 8 inputted by the read address input port 8 is: 0000111;

[0103] The storage address 9 inputted by the read address input port 9 is: 0001000;

[0104] The storage address 10 inputted by the read address input port 10 is: 0001001;

[0105] The storage address 11 inputted by the read address input port 12 is: 0001010;

[0106] The storage address 12 input by the read address input port 12 is: 0001011.

[0107] The 7 storage addresses of the input write address input port can be:

[0108] The storage address 13 input to the write address input port 1 is: 1000000;

[0109] The storage address 14 input to the write address input port 2 is: 1000001;

[0110] The storage address 15 inputted into the write address input port 3 is: 1000010;

[0111] The storage address 16 inputted by the write address input port 4 is: 1000011;

[0112] The storage address 17 inputted into the write address input port 5 is: 1000100;

[0113] The storage address 18 inputted by the write address input port 6 is: 1000101;

[0114] The storage address 19 input into the write address input port 7 is: 1000110.

[0115] The above embodiment merely exemplarily provides an address conversion method of the address signal converter 302 that is easier to implement. There may also be other design methods that convert the test address output by the test controller into multiple different storage addresses, all of which can implement the above technical solutions of the embodiments of the present application.

[0116] The above implementation method can be used to implement a single-port test control circuit to test the simultaneous read and write operations on multiple ports of the memory during the MBIST test, thereby detecting whether there is a fault in the internal logic circuit of the memory and saving the test circuit overhead; at the same time, this implementation method will not perform multiple read or write operations on the same storage address at the same time, and will not cause a read-write conflict in the memory.

[0117] Furthermore, the memory test circuit may further include a selector 304, such as Figure 4 As shown, the port of the test controller 301 outputting the selection signal (port_select) is connected to the input port of the selector 304; the multiple read data output ports of the memory 303 are connected to the multiple input ports of the selector 304; the output port of the selector 304 is connected to the input port of the test controller 301, specifically, it can be connected to the comparator of the test controller 301.

[0118] The selector 304 is used to select and output data read from a plurality of storage addresses of the memory 303 according to a selection signal (port_select) output by the test controller 301 .

[0119] Specifically, multiple data read from the memory can be output sequentially, or only the storage data of the read data output port to be compared can be selected each time to input the test controller 301 to complete the comparison. For example, the selector 304 sequentially outputs the storage data outputted from the read data output port 1, the read data output port 2, ..., the read data output port m of the memory 303.

[0120] In addition, the storage data output by the selector 304 will be returned to the test controller 301, and the comparator of the test controller 301 will compare it with the expected data generated by the test controller 301, and determine whether the test data passes the test based on the comparison result to obtain the test result.

[0121] Further, such as Figure 5 As shown, the memory test circuit may also include a read / write signal converter 305; the read / write signal converter 305 is used to receive the read / write control signal generated by the test controller 301, convert the read / write control signal into multiple read control signals and / or multiple write control signals; input the multiple write control signals into the multiple write control ports of the memory 303, and input the multiple read control signals into the multiple read control ports of the memory 303.

[0122] For example, the test controller 301 outputs a read control signal to the read / write signal converter 305, and the read / write signal converter 305 can output multiple read control signals 1 to read control signal m and multiple write control signals 1 to write control signal n, and the output ports of the read / write signal converter 305 are respectively connected to the read control port 1 to read control port m and the write control port 1 to write control port n of the memory 303.

[0123] In actual circuit design, the read / write signal converter 305 can be implemented by a combination of logic gate devices such as an AND gate, an OR gate, a NOT gate, an XOR gate, etc. As long as a logic circuit that can convert a read control signal or a write control signal into multiple read control signals and multiple write control signals can be implemented, the function of the read / write signal conversion can be realized, and the specific design of the logic circuit of the read / write signal converter is not limited in the embodiment of the present application.

[0124] The above implementation method can be used to implement a single-port test control circuit to test the simultaneous read and write operations on multiple ports of the memory during the MBIST test, thereby detecting whether there is a fault in the internal logic circuit of the memory and saving the test circuit overhead; at the same time, this implementation method will not perform multiple read or write operations on the same storage address at the same time, and will not cause a read-write conflict in the memory.

[0125] In a possible implementation, Figure 6 As shown, the memory test circuit may also include a data signal converter 306, which is used to receive the test data output by the test controller 301 and convert the test data into multiple test data; the multiple test data are respectively input into multiple write data input ports 1 to write data input ports n of the memory 303; wherein at least two of the multiple test data are different.

[0126] Specifically, the data signal converter 306 can generate a plurality of different test data, for example, adjacent test data are different, so that it can be tested whether adjacent data signal lines inside the memory have short circuit, open circuit or concurrent coupling faults.

[0127] In actual circuit design, the data signal converter 306 can be implemented by a combination of logic gate devices such as an AND gate, an OR gate, a NOT gate, and an XOR gate. As long as a logic circuit that can convert an input test data into multiple test data can be implemented, the function of data signal conversion can be realized. The embodiment of the present application does not limit the specific design of the data signal converter logic circuit.

[0128] Furthermore, each bit of the test data is converted by the data converter 306, and the obtained multiple test data are input into the multiple write data input ports of the memory 303, and the test data input into adjacent write data input ports can be set to be different, so as to test the storage function according to whether the output data is correct or not.

[0129] Further, such as Figure 6 As shown, the test controller 301 is also used to output a test mode signal (Test_mode), which may include a multi-port test signal and a single-port test signal. The multi-port test signal is used to indicate a test of a multi-port simultaneous read / write operation, and the single-port test signal is used to indicate a single-port read / write data operation test.

[0130] Specifically, when the test mode signal (Test_mode) indicates a multi-port test signal, the read / write signal converter outputs multiple read control signals and / or multiple write control signals generated by the read / write signal conversion; when the test mode signal (Test_mode) indicates a single-port test signal, the read / write control signal output by the test controller is output.

[0131] Specifically, when the test mode signal (Test_mode) indicates a multi-port test signal, the address signal converter outputs multiple different write input addresses and / or multiple read input addresses generated by address signal conversion; when the test mode signal (Test_mode) indicates a single-port test signal, the test address output by the test controller is output.

[0132] Specifically, when the test mode signal (Test_mode) indicates a multi-port test signal, the data signal converter outputs multiple test data generated by data signal conversion; when the test mode signal (Test_mode) indicates a single-port test signal, the test data output by the test controller is output.

[0133] The above-mentioned implementation method can be used to implement a test of simultaneous read and write operations on multiple ports of a memory during MBIST testing using a single-port test control circuit, converting a set of read / write data control signals into multiple sets of read / write data control signals, thereby detecting whether there is a fault in the simultaneous read / write control circuit inside the memory, thereby saving test circuit overhead.

[0134] The above-mentioned test circuit applied to the memory in the embodiment of the present application is applied to the overall test process of the memory using a specific example as follows:

[0135] Combination Figure 6 and Figure 7As shown, the test controller outputs a test mode signal (Test_mode). Exemplarily, the test mode signal includes a multi-port test signal, that is, when Test_mode=1, the memory test circuit performs a test of multi-port simultaneous read and write operations; a single-port test signal, that is, when Test_mode=0, the memory test circuit performs a single-port read / write operation test.

[0136] The address signal converter can be Figure 7 In the circuit structure shown, for example, the test address mbist_addr input to the address signal converter is 0000000, and the bit width of the test address is 7 bits. Each bit address can be represented by mbist_addr[i]. By setting XOR gates or AND gates for some of the 7 signal lines of the test address, different storage addresses 1 to 7 of write operations are obtained, which are represented by wrn_addr[0:6]. In addition, by inverting the highest bit of the 7 signal lines of the test address, that is, storage address [6], different storage addresses 8 to 19 of read operations are obtained, which are represented by rdm_addr[0:61].

[0137] Among them, the XOR gate is a logic gate that implements the "XOR" operation in the digital logic circuit. When the two input levels are different, the XOR gate output is a high level (logic 1); if the two input levels are the same, the XOR gate output is a low level (logic 1). The AND gate is a logic gate that performs the "AND" operation. When the two inputs are both high (logic 1), the output is a high level (logic 1), otherwise the output is a low level (logic 0).

[0138] It should be noted that Figure 7 The black dot in the middle indicates that the circuit is enabled, and the intersection of other signal lines indicates that the circuit is not connected; since the input test address is 7 bits and there are 7 signal lines, it can be understood that each black dot on the storage address 1 to storage address 19 output by the address signal converter implicitly indicates that there is a signal line of the storage address at that point, for example, wr0_addr[3], shown as A in the figure. The address signal line implicit in each black dot constitutes the 7-bit access address of the storage address.

[0139] For example, Figure 7As shown, when the test mode signal Test_mode=1, the storage address mbist_addr is 0000000, then the storage addresses are: wr0_addr[0:6] is 0000000; wr1_addr[0:6] is 0000001; wr2_addr[0:6] is 0000010; wr3_addr[0:6] is 0000011; wr4_addr[0:6] is 0000100; wr5_addr[0:6] is 0000101; wr6_addr[0:6] is 0000110; rd0_addr[0:6] is 1000000; rd1_addr[0:6] is 1000000; r[0:6] is 1000001; rd2_addr[0:6] is 1000010; rd3_addr[0:6] is 1000011; rd4_addr[0:6] is 1000100; rd5_addr[0:6] is 1000101; rd6_addr[0:6] is 1000110; rd7_addr[0:6] is 1000111; rd8_addr[0:6] is 1001000; rd9_addr[0:6] is 1001001; rd10_addr[0:6] is 1001010; rd11_addr[0:6] is 1001011.

[0140] Furthermore, the data converter may be Figure 8 The circuit structure shown can be used to illustrate one bit of the test data, for example, the i-th bit of the test data, i.e., the test data [i]. By setting a logic circuit combination of an XOR gate or a buffer gate, the i-th bit of the seven test data is obtained, and the test data 1 [i] to the test data 7 [i] are respectively input into the write data input port 1 to the write data input port 7 of the memory.

[0141] Among them, the function of the buffer gate is to identify and buffer the input signal, and its output level is the same as the input level, that is, if the input to the buffer gate is high level (logic 1), the output of the buffer gate is still high level (logic 1), and if the input to the buffer gate is low level (logic 0), the output of the buffer gate is still low level (logic 0).

[0142] Therefore, combined with Figure 8 The circuit can be obtained, if the input test data [i] = 1, the test mode signal Test_mode = 1, then Figure 8It can be seen that test data 1[i]=1, test data 2[i]=0 (XOR gate, input two same levels, output is low level 0), test data 3[i]=1, test data 4[i]=0, test data 5[i]=1, test data 6[i]=0, test data 7[i]=1, then the i-th bit of the output test data, the adjacent two data are different. Similarly, if test data[i]=0, test mode signal Test_mode=1, then by Figure 8 It can be obtained that the output test data 1[i]=0, test data 2[i]=1 (XOR gate, input two different levels, output high and low levels 1), test data 3[i]=0, test data 4[i]=1, test data 5[i]=0, test data 6[i]=1, test data 7[i]=0, and the adjacent data are still different.

[0143] Furthermore, the read / write signal converter can convert a read / write control signal output by the test controller into 7 write control signals (write enable signals) and 12 read control signals (read enable signals). The 7 write control signals (write enable signals) are respectively input into 7 write control ports 1 to 7 of the memory chip, and the 12 read control signals (read enable signals) are respectively input into read control ports 1 to 12.

[0144] According to the above input signals, the memory chip drives 7 sets of write control circuits to perform data storage operations and drives 12 sets of read control circuits to perform storage data output operations through the internal clock driving circuit. The read data output port 1 to the read data output port 12 of the memory chip output the storage data respectively, and the output is selected by the selector and returned to the test controller to complete the comparison of the test data and generate the test results.

[0145] The above-mentioned implementation method can be used to implement a test of simultaneous read and write operations on multiple ports of a memory during MBIST testing using a single-port test control circuit, and convert a set of read / write data control signals into multiple sets of read / write data control signals, thereby detecting whether there is a fault in the control circuit for simultaneous read / write operations on multiple ports inside the memory, thereby saving test circuit overhead.

[0146] An embodiment of the present application also provides a memory test chip, which may include any possible design of the above-mentioned test circuit. The memory test chip can be used to implement the functions that the above-mentioned test circuit can implement, thereby being able to test the control circuit that simultaneously performs read / write operations on multiple ports of the memory, thereby saving the circuit area overhead of the memory multi-port test.

[0147] In the several embodiments provided in the present application, it should be understood that the disclosed circuits and chips can be implemented in other ways. For example, the embodiments of the test circuit described above are only schematic. For example, the division of unit devices is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or devices can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or devices, which can be electrical, mechanical or other forms.

[0148] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0149] In addition, each functional unit in each embodiment of the present application may be integrated into a data processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0150] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A test circuit for a memory, characterized in that: The test circuit includes a test controller and an address signal converter, wherein: The test controller is used to generate a test address and write test data into the memory; The address signal converter is used to receive the test address, convert the test address into a plurality of storage addresses of test data in the memory, and input the plurality of storage addresses into a plurality of address input ports of the memory; The test controller is further configured to read data from the plurality of storage addresses and generate a test result based on the read data.

2. The test circuit according to claim 1, characterized in that: The converting the test address into a plurality of storage addresses of the test data in the memory, and inputting the plurality of storage addresses into a plurality of address input ports of the memory, specifically comprises: Converting the test address into a plurality of write input addresses and / or a plurality of read input addresses, wherein the plurality of write input addresses and the plurality of read input addresses are different from each other; The plurality of write input addresses are input into a plurality of write address input ports of the memory, and the plurality of read input addresses are input into a plurality of read address input ports of the memory.

3. The test circuit according to claim 1 or 2, characterized in that: The test circuit also includes a selector: The selector is used to select and output data read from multiple storage addresses of the memory according to the selection signal output by the test controller.

4. The test circuit according to claim 3, characterized in that: The test controller is also used to generate a read / write control signal, and the test circuit also includes a read / write signal converter; The read / write signal converter is used to receive the read / write control signal and convert the read / write control signal into a plurality of read control signals and / or a plurality of write control signals; The plurality of write control signals are input to a plurality of write control ports of the memory, and the plurality of read control signals are input to a plurality of read control ports of the memory.

5. The test circuit according to claim 4, characterized in that: The test controller is also used to generate test data, and the test circuit also includes a data signal converter; The data signal converter is used to receive test data, convert the test data into multiple test data; input the multiple test data into multiple write data input ports of the memory; Among the multiple test data, at least two test data are different.

6. The test circuit according to claim 5, characterized in that: The test controller is further used to generate a test mode signal, wherein the test mode signal includes a multi-port test signal and a single-port test signal.

7. The test circuit according to claim 6, characterized in that: The read / write signal converter is further used for: When the test mode signal is the multi-port test signal, outputting the multiple read control signals and / or the multiple write control signals output by the read / write signal converter; When the test mode signal is the single-port test signal, the read / write control signal generated by the test controller is output.

8. The test circuit according to claim 6, characterized in that: The address signal converter is further used for: When the test mode signal is the multi-port test signal, outputting the multiple write input addresses and / or the multiple read input addresses output by the address signal converter; When the test mode signal is the single-port test signal, the test address generated by the test controller is output.

9. The test circuit according to claim 6, characterized in that: The data signal converter is further used for: When the test mode signal is the multi-port test signal, outputting the plurality of test data output by the data signal converter; When the test mode signal is the single-port test signal, the test data generated by the test controller is output.

10. A memory test chip, characterized in that: The memory test chip comprises the test circuit as described in any one of claims 1-9.

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