Memory operation method, memory, electronic equipment and storage medium

Abstract

The invention discloses a memory operation method, a memory, electronic equipment and a storage medium. The memory operation method comprises the following steps: in response to an error detected in a memory array of the memory in a working state of the memory, determining an error position of the error in the memory array; after the memory enters the idle state, the memory is controlled to start a post-package repair process, and according to the error position, a target memory unit at the error position is replaced with a replacement memory unit used for the post-package repair process in the memory array; and after the post-package repair process, the memory is switched back to the working state, and the replacement memory unit is used for replacing the target memory unit for operation. The memory operation method can improve the reliability of the memory.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a memory operating method, a memory, an electronic device, and a storage medium. Background Art

[0002] As the demand for memory access in modern computer systems continues to grow, the memory particles in the memory are operating under high load in harsh environments for a long time, and are very likely to fail due to aging and other reasons. The failure of the memory will lead to a decrease in the stability of the computer system, and if the failed part of the memory cannot be repaired in time, it may even cause abnormal phenomena such as system downtime. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a memory operation method, which includes: in response to detecting an error in a storage array of the memory in a working state of the memory, determining an error position of the error in the storage array; after the memory enters an idle state, controlling the memory to start a post-packaging repair process, and according to the error position, replacing a target storage unit at the error position with a replacement storage unit in the storage array for the post-packaging repair process; after the post-packaging repair process, switching the memory back to a working state, and using the replacement storage unit to replace the target storage unit for operation.

[0004] For example, in the memory operation method provided in at least some embodiments of the present disclosure, after the memory enters an idle state, the memory is controlled to start a post-packaging repair process, including: after the memory enters an idle state, the storage array is switched from a working mode to a repair mode, so that the memory starts a post-packaging repair process.

[0005] For example, the memory operation method provided in at least some embodiments of the present disclosure further includes: stopping receiving new access requests to the memory and clearing existing access requests in the memory to put the memory into an idle state.

[0006] For example, in the memory operation method provided by at least some embodiments of the present disclosure, before the memory enters the idle state, the memory operation method further includes: releasing the space of the data buffer occupied by the existing access request.

[0007] For example, in the memory operation method provided in at least some embodiments of the present disclosure, after the memory enters an idle state, the memory operation method further includes: clearing the refresh commands to be sent in the memory, so that the memory array enters a first self-refresh state; and switching the memory array from a working mode to a repair mode in the first self-refresh state.

[0008] For example, in the memory operation method provided in at least some embodiments of the present disclosure, the post-packaging repair process includes: in response to the end of the first self-refresh state, backing up the first data corresponding to the error location, and after the target storage unit is replaced with the replacement storage unit, restoring the first data to the replacement storage unit.

[0009] For example, in the memory operation method provided by at least some embodiments of the present disclosure, backing up the first data corresponding to the error location includes: backing up the first data after processing it through an error correction algorithm.

[0010] For example, in the memory operation method provided by at least some embodiments of the present disclosure, backing up the first data corresponding to the error position also includes: backing up the first data corresponding to the error position to the redundant space of the data buffer space.

[0011] For example, in the memory operation method provided in at least some embodiments of the present disclosure, restoring the first data to a replacement storage unit includes: reorganizing the first data corresponding to the error position and the second data written in parallel with the first data, and performing a write operation on the reorganized data to restore the first data to the replacement storage unit.

[0012] For example, in the memory operation method provided in at least some embodiments of the present disclosure, the storage array is configured to support data masking to restore the first data to the replacement storage unit, including: operating the corresponding data mask to mask the operation of writing the second data in parallel with the first data corresponding to the error position, and restoring the first data to the replacement storage unit.

[0013] For example, the memory operation method provided in at least some embodiments of the present disclosure further includes: sending a compensated refresh command in response to completion of the post-packaging repair process.

[0014] For example, the memory operation method provided in at least some embodiments of the present disclosure further includes: in response to completion of the repair mode, switching the memory array from the repair mode to the working mode in the second self-refresh state.

[0015] For example, in the memory operation method provided by at least some embodiments of the present disclosure, before starting the post-packaging repair process, the memory operation method further includes: reading a repair status register corresponding to the error location to determine whether there are available repair resources.

[0016] For example, the memory operation method provided in at least some embodiments of the present disclosure further includes: in response to a reset operation or an initialization operation on the memory, triggering a hard repair of the memory array to replace the target memory cell at the error location in the memory array of the memory with the repair result of the replacement memory cell in the memory array used for the post-packaging repair process to fix it.

[0017] At least one embodiment of the present disclosure further provides a memory, which includes a storage array, an operation control module, a storage controller and a repair module; the storage controller is configured to read and write the storage array in a working state; the repair module is configured to perform repair operations on the storage array; the operation control module is configured to: in response to an error detected in the storage array of the memory in the working state of the memory, determine the error position of the error in the storage array, and after the memory enters an idle state, control the memory to start the repair module to perform a post-packaging repair process, wherein the repair module is further configured to replace the target storage unit at the error position with a replacement storage unit in the storage array for the post-packaging repair process according to the error position; after the post-packaging repair process, switch the memory back to the working state, so that the storage controller uses the replacement storage unit to replace the target storage unit for operation.

[0018] At least one embodiment of the present disclosure also provides a memory, in which an operation control device includes: a selector, an input end of the selector is connected to a storage controller and a repair control module, and an output end of the selector is connected to a storage array; and a permission switching module is configured to provide a control signal to the selector so that the selector switches the storage array from a working mode to a repair mode, or switches from the repair mode back to a working mode.

[0019] At least one embodiment of the present disclosure further provides a memory, further comprising a data buffer, wherein the data buffer is configured to provide a cache space required for the storage array in a working mode or a repair mode.

[0020] At least one embodiment of the present disclosure further provides a memory, further comprising a repair status register, wherein the repair status register is configured to record whether there are available repair resources at the error location.

[0021] At least some embodiments of the present disclosure also provide an electronic device, comprising the memory provided by any embodiment of the present disclosure.

[0022] At least some embodiments of the present disclosure also provide a non-transitory storage medium that non-transitory stores computer-executable instructions, wherein when the computer-executable instructions are executed by at least one processor, the memory operation method provided by any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0024] Figure 1A schematic flow chart of a memory operation method provided by at least one embodiment of the present disclosure is shown;

[0025] Figure 2 A schematic diagram of data backup provided by at least one embodiment of the present disclosure is shown;

[0026] Figure 3 A schematic diagram of data recovery provided by at least one embodiment of the present disclosure is shown;

[0027] Figure 4 An exemplary flow chart of a memory operation method provided by at least one embodiment of the present disclosure is shown;

[0028] Figure 5 A block diagram of a memory provided by at least one embodiment of the present disclosure is shown;

[0029] Figure 6 A schematic diagram showing the structure of an electronic device provided by at least one embodiment of the present disclosure; and

[0030] Figure 7 A schematic diagram of a non-transitory storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0032] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0033] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of known functions and known components. When any component of the embodiments of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0034] The terms used in the present disclosure are those common terms currently widely used in the art in consideration of the functions of the present disclosure, but these terms may vary according to the intention of a person of ordinary skill in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as an overall description based on the meaning of the terms and the present disclosure.

[0035] Flowcharts are used in this disclosure to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously as required. At the same time, other operations may also be added to these processes, or one or more operations may be removed from these processes.

[0036] The storage in the computer, such as the memory, can be a random access memory (RAM), such as a dynamic random access memory (DRAM). The RAS characteristics of the memory refer to the three key properties of reliability, availability and serviceability, which together ensure the stability of the computer system and the integrity of the data.

[0037] For example, the memory may be a memory using the fourth generation dynamic random access memory technology (Double Data Rate Fourth, DDR4) or the fifth generation dynamic random access memory technology (Double Data Rate Fifth, DDR5).

[0038] Checking for bad spots (i.e., faulty or unreliable memory cells) in memory is an important step to ensure system stability and data integrity. Different types of memory (such as DRAM, SRAM, NAND flash memory, etc.) can have different detection methods, which include hardware diagnostic tools (such as built-in self-test (BIST)) or software diagnostic tools (such as memory test software). After checking for bad spots, you can consider repairing the memory according to the specific situation.

[0039] In DDR4 memory technology, the Post Package Repair (PPR) function was introduced, which significantly improved the reliability and durability of the memory. The PPR function allows the introduction of redundant space in the storage array, and supports the replacement of fixed errors in the storage array through the PPR process, thereby effectively repairing the errors in the storage array. For example, repairing single-bit errors, multi-bit errors, and entire row errors. DDR4 is limited to repairing fixed error types within the same row of the storage array belonging to the memory, but with the advancement of technology, DDR5 has further strengthened the PPR function based on DDR4. DDR5 memory technology implements two major types of repairs in the PPR function: post-package hard repair (hPPR) and post-package soft repair (sPPR).

[0040] Post-package hard repair allows at least one row address to be corrected for each bank in the memory array, and the repair is permanent, and once programmed, the electronic fuse cannot be switched back to the unblown state.

[0041] For example, when the memory detects errors in the storage array, it first needs to determine whether these errors are confined to the same row in the storage array. If the errors are indeed located in the same row, a system interrupt will be sent to put the system into a reset state. After the system exits the reset state, the initialization and training steps of the memory particles in the storage array need to be completed to start the hPPR repair process.

[0042] For example, according to the DDR standard protocol, a command is sent to cause the memory particles to enter the hPPR repair process. Then, the row address that needs to be repaired is passed to the memory particles, and the memory particles then replace the erroneous row address with a row address in a redundant space. After the memory particles complete the hPPR repair process, a command is sent to exit and continue to execute the remaining initialization steps. When the system initialization process is completed, the memory re-enters the working state, and after the fixed error row has been successfully replaced, the memory can perform read and write operations normally.

[0043] Post-package soft repair provides a method to quickly but temporarily repair a row of addresses on a single memory bank. Compared with post-package hard repair, power failure or reset operation after post-package soft repair will cause the repair result to be lost.

[0044] In the case where a server or computer system needs to maintain a long-term stable working state, if a partial failure or error is found in the memory working state of the server or computer system, both post-packaging hard repair (hPPR) and post-packaging soft repair (sPPR) have certain problems to a certain extent.

[0045] For example, if hard post-packaging repair (hPPR) is initiated, the working server or computer system needs to be reset, which takes a long time and requires the server or computer system to be interrupted. If the working state must be maintained, the memory errors cannot be processed in time and accumulate, and may even cause the system to crash.

[0046] For example, if soft post-packaging repair (sPPR) is enabled to temporarily repair a memory in working state, the repair will be limited by the size of the redundant space used for the spPR in the storage array, and all repair results will be lost once power is lost or a reset operation is performed.

[0047] At least one embodiment of the present disclosure provides a memory operation method, which includes: in response to detecting an error in a storage array of the memory in a working state of the memory, determining an error position of the error in the storage array; after the memory enters an idle state, controlling the memory to start a post-packaging repair process, and according to the error position, replacing a target storage unit at the error position with a replacement storage unit in the storage array for the post-packaging repair process; after the post-packaging repair process, switching the memory back to a working state, and using the replacement storage unit to replace the target storage unit for operation.

[0048] In the memory operation method of the above-mentioned embodiment of the present disclosure, since it is possible to respond to errors detected in the memory array of the memory in the working state of the memory, after the memory enters the idle state, the post-packaging repair process is controlled to start, and after the repair is completed, the memory is switched back to the working state, so that when the memory is in the working state, the memory error repair can be performed by timely and dynamically triggering the post-packaging repair process. On the one hand, this improves the working stability of the memory in the working state and avoids the accumulation of errors caused by the long-term operation of the server or computer system. On the other hand, this memory operation method can consider the reasonable use of the existing memory logic as much as possible, avoid the use of complex logic devices, and obtain higher benefits at a lower hardware cost.

[0049] Various embodiments of the present disclosure will be described below with reference to specific examples.

[0050] Figure 1 A flowchart of a memory operation method provided by at least one embodiment of the present disclosure is shown.

[0051] like Figure 1 As shown, in some embodiments of the present disclosure, the memory operation method includes steps S30 to S32.

[0052] Step S30: In response to detecting an error in a memory array of the memory in the working state of the memory, determining an error location of the error in the memory array.

[0053] The memory may be a memory, and the working state of the memory means that the memory has been powered on, for example, the initialization and configuration operations have been completed, so that the memory is in a state that can be accessed or operated, for example, the memory is in a state that can be read, or the memory is in a state that can be written. When the memory is in the working state, for example, the memory system can periodically or regularly detect errors in the storage array of the memory, and when it is detected that there are errors in the storage array when the memory is in the working state, the error position of the error in the storage array is determined.

[0054] For example, the memory includes a storage array, a decoding driving circuit, and a read / write circuit, etc., and is connected to the outside through an address bus, a data bus, and a control bus, such as a communication connection with a processor, a direct memory access (DMA) controller, etc., to receive access requests (such as read and write requests) from these hosts. The storage array includes a plurality of storage cells (storage elements) arranged in an array with multiple rows and columns, such as these storage cells are addressed by rows and columns, and the decoding driving circuit includes an address decoder, a word line driver, a bit line driver, etc. Each storage cell can be a unit circuit such as a dynamic random access memory device (DRAM), a static random access memory device (SRAM), a flash memory (NAND or NOR), etc. according to the type of the memory.

[0055] For example, the presence of an error in the storage array indicates that there are bad cells in the storage array. For example, a certain error row in the storage array may be detected, or several error rows in the storage array may be detected.

[0056] For example, the error row may be determined by detecting when a read request sent to a specific row returns error data, or the error row may be determined when a write request sent to the specific row reports an error.

[0057] For example, when an error in a storage array is detected, the memory system can record the error location of the error, such as the error storage array (Bank Group), the error storage body (Bank), the error row (Row), and the storage unit number (also called the storage particle number); for example, when multiple storage chips are involved, the error storage chip (Rank) to which it belongs can be recorded, and each storage chip is a group of storage particles that can respond to the same chip select (CS) signal. For example, when multiple die are stacked in a three-dimensional chip, the error component identifier (Component ID, CID) can be recorded to distinguish different die layers through the CID.

[0058] Step S31: after the memory enters the idle state, the memory is controlled to start the post-packaging repair process, and according to the error location, the target storage unit at the error location is replaced with a replacement storage unit in the storage array for the post-packaging repair process.

[0059] The idle state (IDLE) of the memory means that all the storage units (such as DRAM particles) of the storage array in the memory currently have no access requests (such as read requests or write requests) that can be executed. The target storage unit can also be called the target storage particle. For example, the target storage particle can be a DRAM particle. It is in a state of waiting for the arrival of the next access request. For example, the idle state of the memory can be a low power consumption mode or a waiting mode of the memory. For example, the memory can be put into an idle state by controlling the power management register (PCON), for example, controlling the IDL bit in the power management register to be 1.

[0060] In some embodiments of the present disclosure, the memory operation method further includes step S300.

[0061] Step S300: Stop receiving new access requests to the memory and clear existing access requests in the memory, so that the memory enters an idle state.

[0062] For example, when an error is detected in a storage array of the memory, the memory in the working state has a plurality of existing access requests to be processed and can accept new access requests. Thus, by stopping receiving new access requests to the memory and clearing existing access requests in the memory, the memory currently has no access requests that can be executed, so that the memory enters an idle state.

[0063] For example, when the memory currently has no access request that can be executed, the memory system can send a precharge command (Precharge PRE) to the memory array to put the memory into an idle state. The precharge command is used to close an open row in a specified memory array or cancel open rows in all memory arrays.

[0064] In some embodiments of the present disclosure, before the memory enters the idle state, the memory operation method further includes step S301.

[0065] Step S301: releasing the space of the data buffer occupied by the existing access request.

[0066] The data buffer may be referred to as a cache for short. The data buffer may be, for example, a cache dedicated to the memory, or may reuse a cache for other purposes, such as a first-level cache, a second-level cache, or a higher-level cache (such as a last-level cache (LLC)). For example, the cache may be cached before accessing the storage array of the memory, so that the cache with a higher storage speed may be used to solve the problem of high latency when accessing the storage array, so as to improve the access performance to the storage array in the memory.

[0067] For example, when the memory receives multiple existing access requests to be processed, it can cache them before accessing the storage array. In the above operation steps, although the existing access requests in the memory are cleared, the data buffer may have cached the data of these existing access requests. Since the existing access requests have been cleared and the corresponding data in the data buffer will no longer be accessed, the space of the data buffer occupied by the existing access requests can be released before the memory enters the idle state.

[0068] Post Package Repair (PPR) is a mechanism for memory to repair bad cells in a storage array. In this process, repair can be performed through preset replacement storage cells, or the progress of the PPR process can be controlled and indicated by reading a repair status register.

[0069] In some embodiments of the present disclosure, before starting the post-packaging repair process, the memory operation method further includes step S310.

[0070] Step S310: Read the repair status register corresponding to the error position to determine whether there are available repair resources.

[0071] For example, a corresponding repair status register may be provided for each storage unit in the storage array. For example, the repair status register may be a mode register MR54, MR55, MR56 or MR57 in the memory. The repair status register may be used to check whether there are available replacement storage units in the storage unit or storage unit group corresponding to the error position, for example, the replacement storage unit is an available repair resource, for example, replacing a row of storage units with an available replacement row (Redundant Row), or a row of storage units with an available replacement column (Redundant Column).

[0072] For example, the repair status register may determine whether repair resources are available by checking the PPR table.

[0073] For example, in order to start the post-packaging repair (PPR) process, a series of operation controls are required. For example, the memory may be a dynamic random access memory (DRAM). For example, a series of PPR instruction sequences may be sent according to the standard protocol of DDR4 / DDR5 to start the PPR process of the storage particles.

[0074] First, the start of the PPR process can be controlled by setting some bits of the repair control register, so that the memory enters the PPR process. For example, the start of the PPR process in different modes can be controlled by the control bits of the repair control register MR4. For example, the A13 bit of the repair control register MR4 is 1 to start the post-package hard repair (hPPR) mode; for example, the A5 bit of the repair control register MR4 is 1 to start the post-package soft repair (sPPR) mode.

[0075] Next, a specified security code sequence (Guard Key) can be sent to ensure the legality and correctness of operations in the PPR process through the security measure of the security code sequence.

[0076] Afterwards, in order to replace the target storage unit at the error location with a replacement storage unit in the storage array for the post-packaging repair process according to the error location, it is necessary to send the error location (for example, the target row address of the target storage unit) through an activation command (Active Command). The activation command is used to make the target storage unit that needs to be replaced in the memory ready so that subsequent operations can be performed on the specified target storage unit (for example, the error row).

[0077] Next, after the activation command, a write command is sent to the memory to write the write data into the previously activated target memory cell, so as to select the target memory cell that needs to perform the PPR process through the write data. Since the write command usually includes the data to be written and the target column address of the target memory cell, the specific and accurate location of the target memory cell of the memory that needs to perform the PPR process can be known (that is, the target row address and the target column address of the target memory cell).

[0078] In some embodiments of the present disclosure, in step S31, after the memory enters an idle state, the memory is controlled to start a post-packaging repair process, and the operating method of the above memory includes step S311.

[0079] Step S311: after the memory enters the idle state, the memory array is switched from the working mode to the repair mode, so that the memory starts the post-packaging repair process.

[0080] When the storage array is in working mode, the memory is in working state, and the storage array performs reading and writing in the working state; when the storage array is in repair mode, the memory starts the post-packaging repair process, and the storage array repairs the error position therein through the post-packaging repair process.

[0081] For example, the memory includes a memory controller, which can control the memory array to read and write in a working state, and the memory includes a repair module, which can perform a repair operation on the error position of the memory array through a post-packaging repair process. For example, in response to detecting an error in the memory array of the memory in the working state of the memory, the control of the memory array can be switched from the memory controller to the repair module, so as to switch the memory array from a working mode to a repair mode, so that the memory starts the post-packaging repair process.

[0082] After the memory enters the post-packaging repair process, the target storage unit (also called target storage particle) at the error position can be replaced with a replacement storage unit in the storage array for the post-packaging repair process according to the error position of the storage array.

[0083] In at least one example, the replacement storage unit is a storage unit that can normally respond to access requests, and the replacement storage unit may be a storage unit in the storage array that is pre-divided for the post-installation repair process.

[0084] Step S32: After the post-packaging repair process, the memory is switched back to the working state, and the replacement memory unit is used to replace the target memory unit for operation.

[0085] Switching the memory back to the working state ends the post-packaging repair process. For example, the end of the PPR process can be controlled by setting some bits of the repair control register. For example, the end of the PPR process can be controlled by the control bit of the repair control register MR4. For example, the A13 bit of the repair control register MR4 is 0 to end the hPPR mode. For example, the A5 bit of the repair control register MR4 is 0 to end the sPPR mode.

[0086] For example, the storage array may be switched from a repair mode to an operating mode, so that the storage array ends the post-packaging repair process. For example, the control of the storage array may be switched from a repair module to a storage controller, so that the storage array ends the post-packaging repair process.

[0087] Since the target storage unit at the error position has been replaced by a replacement storage unit that can normally respond to access requests in the post-packaging repair process, when the memory switches back to the working state, when the memory receives an access to the target storage unit at the error position of the storage array, it will directly access the replacement storage unit, allowing the replacement storage unit to replace the target storage unit to respond to the access request.

[0088] Through the above steps S30 to S32, when the memory is in a working state, in response to an error detected in the storage array of the memory in the working state of the memory, the post-packaging repair process can be triggered in a timely and dynamic manner to perform error repair on the memory in the working state, thereby improving the reliability of the memory.

[0089] In some embodiments of the present disclosure, after the memory enters the idle state, the memory operation method further includes step S313.

[0090] Step S313: clearing the refresh commands to be sent in the memory, so that the memory array enters a first self-refresh state; in the first self-refresh state, the memory array is switched from a working mode to a repair mode.

[0091] For example, in at least one example, after the memory enters the idle state, the post-packaging repair process may not be started immediately, and the memory may need to wait in the idle state. For example, the memory is a dynamic random access memory (DRAM), and the DRAM needs to be refreshed according to a preset cycle to maintain data integrity. For example, after the memory enters the idle state, the memory controller in the memory also needs to issue a refresh command (Refresh, REF) according to a preset cycle.

[0092] Since it is unknown how long it will take to wait in the idle state, in order to make the process of starting the post-packaging repair process of the memory from the working state of the memory smoother and not cause data loss, the pending refresh commands in the memory can be cleared to allow the memory array to enter the self-refresh state (also referred to as the first self-refresh state herein). For example, after clearing the pending refresh commands in the memory controller, the memory controller can send a self-refresh command (Self-Refresh Entry, SRE) to the memory array to allow the memory to enter the first self-refresh state.

[0093] The self-refresh state is a low-power mode of the memory. In this mode, the storage array of the memory can use an internal counter to trigger a refresh without the need for an external refresh command, thereby ensuring that the data inside the memory is not lost even in the low-power mode.

[0094] For example, the memory array can be switched from an operating mode to a repair mode in the first self-refresh state. For example, in the first self-refresh state, the control of the memory array is switched from a memory controller to a repair module, so that the memory starts a post-packaging repair process.

[0095] In some embodiments of the present disclosure, the memory operation method further includes step S314.

[0096] Step S314: In response to completion of the repair mode, switching the memory array from the repair mode to the working mode in the second self-refresh state.

[0097] For example, after the repair mode is completed, the memory may not be able to return to the working mode immediately, and the memory may need to wait. Since it is unknown how long the waiting time is, in order to prevent the data in the memory from being lost and the power consumption of the memory from being too large, the memory may be put into the second self-refresh state. For example, a self-refresh command (Self-Refresh Entry, SRE) may be sent to the storage array to put the memory into the second self-refresh state.

[0098] When the memory can be switched, the memory array can be switched from the repair mode to the working mode in the second self-refresh state. For example, in the second self-refresh state, the control of the memory array is switched from the repair module to the storage controller, so that the memory re-enters the working state.

[0099] In some embodiments of the present disclosure, the above-mentioned post-packaging repair process may include step S40 and step S41.

[0100] Step S40: In response to the first self-refresh state ending, backing up the first data corresponding to the error location.

[0101] After entering the post-packaging repair process, in order to avoid replacing the target storage unit at the error location with a replacement storage unit, which will cause the data originally written in the target storage unit to be unable to be retained (for example, the data in the target storage unit is destroyed), therefore, before replacing the target storage unit, it is necessary to back up the data corresponding to the target storage unit at the error location (also called the first data).

[0102] Because the storage array of the memory has been set to the first self-refresh state before entering the post-packaging repair process, and the data cannot be backed up in the self-refresh state, the storage controller can send a self-refresh exit command (Self-Refresh Exit, SRX) to allow the storage array to exit from the first self-refresh state to back up the first data corresponding to the error location.

[0103] Figure 2A schematic diagram of data backup provided by at least one embodiment of the present disclosure is shown.

[0104] like Figure 2 As shown, in this embodiment, the memory adopts the structure of a dual inline memory module (DIMM) of DDR5 memory technology. In the illustrated DDR5 memory, each DIMM has two channels, such as channel CHA and channel CHB as shown in the figure. For example, channel CHA and channel CHB respectively have control logic corresponding to their channels. For example, each channel of channel CHA and channel CHB has the same number of storage arrays. Channel CHA and channel CHB can work in parallel, thereby significantly improving the bandwidth of the memory and also improving the data transmission rate.

[0105] For example, each channel in channel CHA and channel CHB includes five memory arrays DRAM 0, DRAM 1, DRAM 2, DRAM 3 and DRAM 4. Each memory array (Bank Group) includes multiple memory banks (Bank). For example, each memory array in the five memory arrays DRAM 0-DRAM 4 includes multiple memory banks Bank 0-Bank N, where N is a positive integer.

[0106] For example, taking the example that each of the five storage arrays DRAM 0-DRAM 4 includes storage body Bank0, for example, an error is detected in storage body Bank 0 of storage array DRAM 1, that is, there is an error in storage array DRAM 1. At this time, the error row in storage body Bank 0 of storage array DRAM 1 can be determined, for example, the error row is Row N, where N is a positive integer.

[0107] For example, a read instruction for the error row Row N may be sent through the data backup logic first. After the read instruction accesses the error row Row N of the channel CHA through the instruction interface, the target storage unit (also called the target storage particle) of the error row Row N returns data for backup.

[0108] For example, in the Bank Interleaving technology, multiple storage banks belonging to multiple storage arrays are allowed to distribute access requests for processing. For example, when an access request is issued, the access data will be dispersed and stored in the storage banks of different storage arrays. For example, the access data in an access request is stored in the storage bank Bank 0 in the five storage arrays DRAM 0-DRAM 4. The memory interleaving technology can greatly improve the parallelism of the memory and reduce the delay caused by waiting for the completion of a single storage bank operation, thereby reducing the waiting time for data access.

[0109] For example, for a memory that uses memory interleaving technology, after receiving a read instruction for the error row Row N in the storage body Bank 0 of the storage array DRAM 1, since the access data is written in parallel to the corresponding row Row N of the storage body Bank 0 in the five storage arrays DRAM 0-DRAM 4 when the access data is written in the access request, when reading the error row Row N in the storage body Bank 0 of the storage array DRAM 1, the corresponding row Row N of the storage body Bank0 in other storage arrays will be read out together, that is, the data of the corresponding row Row N of the storage body Bank0 in the five storage arrays DRAM 0-DRAM 4 are read out in parallel as the returned read data.

[0110] In some embodiments of the present disclosure, step S40 includes step S400.

[0111] Step S400: backing up the first data after processing it using an error correction algorithm.

[0112] For example, after the read data is read out, error checking and correction (ECC) may be performed on the read data to obtain error-corrected read data, so that the read data to be backed up can be correct.

[0113] In some embodiments of the present disclosure, step S400 also includes step S4001.

[0114] Step S4001: back up the first data corresponding to the error position to the redundant space of the data buffer space.

[0115] For example, data (also referred to as first data) of the target storage particle in the error row RowN in the storage bank Bank0 of the storage array DRAM 1 may be extracted from the error-corrected read data and stored in the data buffer.

[0116] For example, the first data may be stored in the space occupied by the released existing access request, so that there is no need to allocate a backup storage space for backing up the first data, and there is no need to introduce an additional storage device in the memory.

[0117] In some embodiments of the present disclosure, in the backup process, if the number of data bits of the read data is too large, that is, the number of columns (Column) of the storage particles in the storage array DRAM 0-DRAM 4 in the channel CHA exceeds the number of columns that the storage controller can process at one time, because the storage controller cannot access so many bits at the same time in a single operation, it can be processed by a partial column access (Partial Column Access) method of reading a part of the number of columns at a time. For example, the number of bits of the read data is 64. In the above embodiment, a read command can be sent to first read the data of columns 0-15, then read the next 16-31 columns, then read columns 32-47, and finally read columns 48-63. Thus, by reading multiple times in a cycle, all columns (that is, all bits) of the read data are covered, thereby completing the backup of the first data.

[0118] It should be noted that the above description is based on an example in which the memory is a DDR5 DIMM structure, but it does not limit the memory structure type disclosed in the present invention; the above description is based on an example in which the memory includes two channels, but it does not limit the number of channels of the memory; the above description is based on an example in which one channel includes 5 storage arrays, but it does not limit the number of storage arrays in the memory.

[0119] The above embodiments of the present disclosure are described by taking an error row in a storage body in a storage array as an example. If there are multiple storage bodies in the storage array including multiple error locations or one error location including multiple error rows, the backup process for any error row is the same as the above example.

[0120] It should be noted that, in the above example, the data backup process when an error occurs in any storage array in the channel CHB is the same as the data backup process in the channel CHA, which will not be described in detail in the present disclosure.

[0121] Step S41: after the target storage unit is replaced by the replacement storage unit, restore the first data to the replacement storage unit.

[0122] For example, after the target storage unit is replaced with a replacement storage unit, data (eg, first data) of the previously replaced target storage unit (also referred to as a target storage granule) needs to be restored to the replacement storage unit.

[0123] In some embodiments of the present disclosure, step S41 includes step S410.

[0124] Step S410: reorganize the first data corresponding to the error position and the second data written in parallel with the first data, and perform a write operation on the reorganized data to restore the first data to the replacement storage unit.

[0125] Figure 3 A data recovery schematic diagram provided by at least one embodiment of the present disclosure is shown.

[0126] like Figure 3 As shown, in this embodiment, the memory adopts the structure of a dual in-line memory module of DDR5 memory technology. In the illustrated DDR5 memory, each DIMM has two channels, such as channel CHA and channel CHB as shown in the figure. For example, channel CHA and channel CHB respectively have control logic corresponding to their channels. For example, each channel of channel CHA and channel CHB has the same number of storage arrays. Channel CHA and channel CHB can work in parallel, thereby significantly improving the bandwidth of the memory and also improving the data transmission rate.

[0127] For example, each channel in channel CHA and channel CHB includes five memory arrays DRAM 0, DRAM 1, DRAM 2, DRAM 3 and DRAM 4. Each memory array (Bank Group) includes multiple memory banks (Bank). For example, each memory array in the five memory arrays DRAM 0-DRAM 4 includes multiple memory banks Bank 0-Bank N, where N is a positive integer.

[0128] Take the channel CHA adopting the memory interleaving technology as an example. For example, the control logic corresponding to the channel CHA includes data reorganization and recovery complete write data logic, data recovery control logic and a data buffer.

[0129] First, after a target storage unit (also referred to as a target storage cell) is replaced with a replacement storage unit, a read instruction is sent to the replaced channel CHA.

[0130] Subsequently, channel CHA responds to the read instruction to read out the data of the replaced storage cell in the storage array DRAM 1 and the data (also referred to as the second data) in other storage arrays read out in parallel with the storage array DRAM 1. For example, the read data read out in parallel include: the data of row Row N in the storage bank Bank 0 of the storage array DRAM 0, the data of the replaced storage cell in the storage bank Bank 0 of the storage array DRAM 1, the data of row Row N in the storage bank Bank 0 of the storage array DRAM 2, the data of row Row N in the storage bank Bank 0 of the storage array DRAM 3, and the data of row Row N in the storage bank Bank 0 of the storage array DRAM 4.

[0131] Subsequently, the data of the error row Row N (ie, the target storage unit) in the storage body Bank 0 of DRAM 1 (hereinafter also referred to as "first data") is extracted from the data buffer.

[0132] Afterwards, the first data and the second data need to be reorganized to restore the complete written data. It should be noted that the second data is data written in parallel with the first data.

[0133] For example, the data of the replacement storage unit in the read data can be replaced with the first data through data reorganization, so as to reorganize the first data and the second data to restore the complete write data. For example, in the process of data reorganization, the data of the replacement storage unit in the storage body Bank 0 of the storage array DRAM 1 in the read data can be replaced with the first data to restore the complete write data.

[0134] For example, the restored complete write data is: data of row Row N in memory bank Bank0 of memory array DRAM 0, the first data, data of row Row N in memory bank Bank 0 of memory array DRAM 2, data of row Row N in memory bank Bank 0 of memory array DRAM 3, and data of row Row N in memory bank Bank 0 of memory array DRAM 4. Here, the second data includes other data in the write data except the first data.

[0135] After the data recovery control logic sends a write instruction to channel CHA, the control writes the reorganized data to the storage array DRAM 0-DRAM 4 of channel CHA. For example, the first data is written to the replacement storage unit in the storage body Bank0 of the storage array DRAM 1, and the second data is written to the storage array DRAM 0, the storage array DRAM 2, the storage array DRAM 3 and the storage array DRAM 4 respectively.

[0136] By reorganizing the read data and the first data in the multiple storage arrays, for a memory using the memory interleaving technology, the normal data of other storage arrays will not be overwritten or destroyed due to the error of restoring one storage array among the multiple storage arrays.

[0137] In some embodiments of the present disclosure, step S41 includes step S411.

[0138] Step S411: operating a corresponding data mask to mask the operation of writing the second data in parallel with the first data corresponding to the error position, and restoring the first data to the replacement storage unit.

[0139] For example, the memory supports a data mask function, so when restoring the data (also called the first data) in the target storage unit to the replacement storage unit, the data mask can be used to shield the operation of writing the second data in parallel with the first data corresponding to the error position, so that there is no need to reorganize the data, and the first data can be directly restored to the replacement storage unit. The data mask method does not require the aforementioned read-modify-write (RMW) process, that is, it is not necessary to first send a read request to read the read data written in parallel (i.e., read), then reorganize the data (i.e., modify), and then write the reorganized write data (i.e., write), which can further optimize the recovery process of post-packaging repair and shorten the time consumption of post-packaging repair.

[0140] For example, Figure 3 The five storage arrays DRAM 0-DRAM 4 in the channel CHA shown have data mask bits corresponding to them respectively. For example, the target storage unit at the error position in the storage body Bank 0 of the storage array DRAM 1 has been replaced with a replacement storage unit. Although the memory adopts the memory interleaving technology and the five storage arrays need to be read and written in parallel, the data mask bits can be set so that the storage arrays DRAM 0, DRAM 2, DRAM 3 and DRAM 4 are shielded, so that the storage array DRAM 1 can be operated. In this way, after reading the first data in the data buffer, the operation of the second data that needs to be written in parallel with the first data corresponding to the error position can be shielded, and the first data can be directly restored to the replacement storage unit.

[0141] It should be noted that, in the case where the first data, read data and write data in the recovery process of the storage array are too large, that is, when the number of columns (Column) of the storage particles in the storage array DRAM 0-DRAM 4 or DRAM 1 in the channel CHA exceeds the number of columns that the storage controller can process at one time, a partial column access (Partial Column Access) method can also be used to process the first data, read data or write data, through multiple cycles of processing until all columns (that is, all bits) of the first data, read data and write data are covered, thereby completing the recovery of the first data.

[0142] It should be noted that, in the above example, the data recovery process of any storage array in the channel CHB is the same as the data recovery process in the channel CHA, which will not be described in detail in the present disclosure.

[0143] In some embodiments of the present disclosure, the memory operation method further includes step S33.

[0144] Step S33: In response to the completion of the post-packaging repair process, a compensated refresh command is sent.

[0145] By sending a compensated refresh command, the memory can compensate for the refresh operation that cannot be performed during the post-package repair (PPR) process after the PPR process is completed.

[0146] For example, a compensated refresh command may be sent after restoring the first data to the replacement memory cell.

[0147] By sending the compensation refresh command, the integrity of the data in the memory will not be affected by charge leakage caused by the lack of refresh during the PPR process, and the stability of the data in the memory is maintained.

[0148] In some embodiments of the present disclosure, the memory operation method further includes step S34.

[0149] Step S34: In response to a reset operation or an initialization operation on the memory, a hard repair of the memory array is triggered to replace the target memory cell at the error location in the memory array of the memory with the repair result of the replacement memory cell in the memory array used for the post-packaging repair process to fix it.

[0150] For example, the above-mentioned post-packaging repair process may be a post-packaging soft repair (sPPR) that takes a shorter time. In order to fix the repair result of the above-mentioned post-packaging repair process, the repair result may be recorded in advance. When the memory is reset or initialized, the hard repair of the storage array is triggered according to the recorded repair result (i.e., the replacement relationship of replacing the target storage unit at the error position with the replacement storage unit). For example, the hard repair may be a post-packaging hard repair (hPPR) to fix the repair result in the storage array of the memory by physically changing the storage particles in the storage array.

[0151] Figure 4 An exemplary flowchart of a memory operation method provided by at least one embodiment of the present disclosure is shown.

[0152] like Figure 4 As shown, the process of the memory operation method may be to issue an access request to the memory to access the memory, detect an error in a storage array of the memory in a working state of the memory, and determine an error position in the storage array.

[0153] Afterwards, the soft post-packaging repair (sPPR) process is initiated to notify the processor to stop generating new access requests.

[0154] Afterwards, the storage controller is notified to clear the existing access requests in the memory, release the data buffer occupied by the existing access requests, and send a precharge command to wait for the storage array to enter the idle state.

[0155] After entering the idle state, if you need to wait at this time, you can clear the pending refresh command, send a self-refresh command to let the storage array enter the first self-refresh state, and switch the control of the storage array to the repair module in the first self-refresh state; if you do not need to wait at this time, you can directly switch the control of the storage array to the repair module in the idle state, thereby entering the post-packaging soft repair process.

[0156] If the control of the storage array is switched to the repair module in the first self-refresh state, it is necessary to exit the first self-refresh state before backing up the first data. If the control of the storage array is switched to the repair module directly in the idle state, the first data can be directly started to be backed up.

[0157] Afterwards, a command sequence for starting the SPPR process is sent, and the SPPR process is executed on the target storage unit at the error position in the storage array, and the target storage unit is replaced with a replacement storage unit.

[0158] Afterwards, the first data is restored to the replacement storage unit, and a compensating refresh command is sent after the restoration process is completed.

[0159] If waiting is required at this time, a self-refresh command can be sent to put the storage array into a second self-refresh state, and control of the storage array can be switched to the storage controller in the second self-refresh state. If waiting is not required, control of the storage array can be directly switched to the storage controller.

[0160] If the control right of the storage array is switched to the storage controller in the second self-refresh state, the storage controller may send a self-refresh exit command to make the storage array exit the second self-refresh state, and send a compensation refresh command.

[0161] By restoring the memory as described above, the error in the storage array of the memory is repaired, thereby restoring normal access to the storage.

[0162] The technical effects of the above embodiments of the present disclosure are the same as the technical effects of the above memory operation method, and therefore will not be described in detail.

[0163] Figure 5 A block diagram of a memory provided by at least one embodiment of the present disclosure is shown.

[0164] like Figure 5 As shown, at least one embodiment of the present disclosure further provides a memory 600 , which includes a storage array 610 , an operation control module 620 , a storage controller 630 , and a repair module 640 .

[0165] The memory controller 630 is configured to read and write data to the memory array 610 in a working state.

[0166] The repair module 640 is configured to perform a repair operation on the storage array 610 .

[0167] The operation control module 620 is configured to: in response to detecting an error in the storage array 610 of the memory 600 in the working state of the memory 600, determine the error location of the error in the storage array 610, and after the memory 600 enters the idle state, control the memory 600 to start the repair module 640 to perform a post-packaging repair process.

[0168] The repair module 640 is further configured to replace the target storage unit at the error location with a replacement storage unit in the storage array 610 for the post-packaging repair process according to the error location; after the post-packaging repair process, the memory 600 is switched back to the working state, so that the storage controller 630 uses the replacement storage unit to replace the target storage unit for operation.

[0169] For example, the memory 600 may be a memory, and correspondingly the storage controller 630 may be a memory controller.

[0170] For example, the memory controller 630 is also configured to manage refresh operations of the memory array 610 .

[0171] For example, the repair module 640 is configured to control sending a series of PPR instruction sequences to the storage array 610 in the post-packaging repair process to start the PPR process.

[0172] In some embodiments of the present disclosure, the operation control device includes a selector 6201 and a permission switching module 6202 .

[0173] The selector 6201 is, for example, a multiple-select-one selector. The input end of the selector 6201 is connected to the storage controller 630 and the repair control module, and the output end of the selector 6201 is connected to the storage array 610 .

[0174] The permission switching module 6202 is configured to provide a control signal to the selector 6201 so that the selector 6201 switches the storage array 610 from the working mode to the repairing mode, or switches from the repairing mode back to the working mode.

[0175] In some embodiments of the present disclosure, the memory 600 further includes a data buffer 650. The data buffer 650 is configured to provide a cache space required by the storage array 610 in a working mode or a repair mode. For example, the data buffer 650 is configured to be a cache space for temporarily storing read and write data in a working state of the memory. For example, the data buffer 650 is configured to provide a cache space for backing up the first data corresponding to the error position in the repair mode of the memory.

[0176] For example, in the working mode of the memory, the permission switching module 6202 hands over the control right of the storage array 610 to the storage controller 630 through the selector 6201. At this time, the storage controller 630 can normally respond to the read and write requests issued by the processor, and the data buffer 650 can temporarily store the read and write data; when the memory needs to perform a repair operation on the storage array 610, the control switching process is started. When the memory 600 clears the existing access request and allows the storage array 610 to enter the first self-refresh state, the permission switching module 6202 hands over the control right of the storage array 610 to the repair module 640 through the selector 6201, and then starts to execute the post-packaging repair process. At this time, the data buffer 650 is configured to temporarily store the error row data (first data). After the post-packaging repair process is completed, the permission switching module 6202 hands over the control right of the storage array 610 to the storage controller 630 through the selector 6201, and restores the storage array 610 to a normal state.

[0177] In some embodiments of the present disclosure, the memory 600 further includes a repair status register 660. The repair status register 660 is configured to record whether there are available repair resources at the error location.

[0178] In some embodiments of the present disclosure, the operation control module 620 may include a repair control register (not shown in the figure).

[0179] In some embodiments of the present disclosure, the memory controller 630 is further configured to stop receiving new access requests to the memory 600 and clear existing access requests in the memory 600 to make the memory 600 enter an idle state.

[0180] In some embodiments of the present disclosure, the storage controller 630 is further configured to release the space of the data buffer 650 occupied by the existing access request.

[0181] In some embodiments of the present disclosure, the storage controller 630 is also configured to clear the refresh commands to be sent in the memory 600, so that the storage array 610 enters a first self-refresh state; the operation control module 620 is also configured to switch the storage array 610 from a working mode to a repair mode in the first self-refresh state.

[0182] In some embodiments of the present disclosure, the repair module 640 is further configured to back up the first data corresponding to the error location in response to the end of the first self-refresh state, and restore the first data to the replacement storage unit after the target storage unit is replaced with the replacement storage unit.

[0183] In some embodiments of the present disclosure, the repair module 640 is further configured to back up the first data after processing it using an error correction algorithm.

[0184] In some embodiments of the present disclosure, the repair module 640 is further configured to back up the first data corresponding to the error position to the redundant space of the data buffer 650 space.

[0185] In some embodiments of the present disclosure, the repair module 640 is further configured to reorganize the first data corresponding to the error location and the second data written in parallel with the first data, and perform a write operation on the reorganized data to restore the first data to the replacement storage unit.

[0186] In some embodiments of the present disclosure, the storage array 610 is configured to support data masking, and the repair module 640 is further configured to restore the first data to the replacement storage unit by operating the corresponding data mask to mask the operation of writing the second data in parallel with the first data corresponding to the error position.

[0187] In some embodiments of the present disclosure, the memory controller 630 is further configured to send a compensated refresh command in response to completion of the post-packaging repair process.

[0188] In some embodiments of the present disclosure, the operation control module 620 is further configured to switch the memory array 610 from the repair mode to the working mode in the second self-refresh state in response to completion of the repair mode.

[0189] In some embodiments of the present disclosure, the storage controller 630 is further configured to read the repair status register 660 corresponding to the error location to determine whether there are available repair resources.

[0190] In some embodiments of the present disclosure, the repair module 640 is also configured to trigger a hard repair of the storage array 610 in response to a reset operation or an initialization operation of the memory 600, so as to replace the target storage cell at the error location in the storage array 610 of the memory 600 with the repair result of the replacement storage cell in the storage array used for the post-packaging repair process to fix it.

[0191] The operation control module 620, the repair module 640, the permission switching module 6202, etc. in the above embodiment of the present disclosure can be implemented by hardware, software, firmware, or any combination thereof, such as by digital circuits. The technical effect of the memory in the above embodiment of the present disclosure is the same as the technical effect of the above memory operation method, so it is not repeated here.

[0192] At least one embodiment of the present disclosure further provides an electronic device, wherein the electronic device includes the memory described in at least one of the above embodiments.

[0193] Figure 6 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0194] The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 6 The electronic device 1000 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0195] For example, refer to Figure 6 In some examples, the electronic device 1000 includes a processing device (e.g., a central memory, a graphics memory, etc.) 1001, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1008 to a random access memory (RAM) 1003. Various programs and data required for the operation of the computer system are also stored in the RAM 1003; for example, the RAM 1003 can be a memory described in at least one of the above embodiments of the present disclosure, and the processing device 1001, the ROM 1002, and the RAM 1003 are connected to each other via an Internet 1004. An input / output (I / O) interface 1005 is also connected to the Internet 1004.

[0196] For example, the following components may be connected to the I / O interface 1005: an input device 1006 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1008 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1009 may allow the electronic device 1000 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive 1010 is also connected to the I / O interface 1005 as needed. Removable media 1011, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 1010 as needed, so that the computer program read therefrom can be installed into the storage device 1008 as needed. Although Figure 6 The electronic device 1000 is shown to include various devices, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0197] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1009 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0198] For example, the electronic device 1000 can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or it can be a combination of any memory operating device and hardware, and the embodiments of the present disclosure are not limited to this.

[0199] At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitorily stores computer executable instructions. For example, when the computer executable instructions are executed by a memory, the memory operation method provided by at least one embodiment of the present disclosure is implemented.

[0200] Figure 7 is a schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure. Figure 7 As shown, the non-transitory storage medium 900 can store computer executable instructions 910 non-transitorily. When the computer executable instructions 910 are executed by a computer, the memory operation method provided by any embodiment of the present disclosure is implemented.

[0201] There are a few points to note about this disclosure:

[0202] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0203] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0204] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory operation method, comprising: In response to detecting an error in a memory array of the memory during an operating state of the memory, determining an error location of the error in the memory array; After the memory enters an idle state, controlling the memory to start a post-packaging repair process, and replacing a target storage unit at the error location with a replacement storage unit in the storage array for the post-packaging repair process according to the error location; After the post-packaging repair process, the memory is switched back to the working state, and the replacement memory unit is used to replace the target memory unit for operation.

2. The memory operation method according to claim 1, wherein: After the memory enters the idle state, controlling the memory to start a post-packaging repair process includes: After the memory enters the idle state, the storage array is switched from the working mode to the repair mode, so that the memory starts the post-packaging repair process.

3. The memory operation method according to claim 2, further comprising: Receiving new access requests to the memory is stopped and existing access requests in the memory are flushed, so that the memory enters the idle state.

4. The memory operation method according to claim 3, wherein: Before the memory enters the idle state, the memory operation method further includes: The space of the data buffer occupied by the existing access request is released.

5. The memory operation method according to claim 4, wherein: After the memory enters the idle state, the memory operation method further includes: Clearing the refresh commands to be sent in the memory, so that the storage array enters a first self-refresh state; In the first self-refresh state, the control over the storage array is switched from the working mode to the repair mode.

6. The memory operation method according to claim 5, wherein: The post-packaging repair process includes: In response to the first self-refresh state ending, the first data corresponding to the error position is backed up, and after the target storage unit is replaced by the replacement storage unit, the first data is restored to the replacement storage unit.

7. The memory operation method according to claim 6, wherein: The backing up of the first data corresponding to the error position includes: The first data is backed up after being processed by an error correction algorithm.

8. The memory operation method according to claim 6, wherein: The backing up of the first data corresponding to the error position also includes: The first data corresponding to the error position is backed up to the redundant space of the data buffer space.

9. The memory operation method according to claim 6, wherein: The restoring the first data to the replacement storage unit includes: The first data corresponding to the error position and the second data written in parallel with the first data are reorganized, and a write operation is performed on the reorganized data to restore the first data to the replacement storage unit.

10. The memory operation method according to claim 6, wherein: The storage array is configured to support data masking, The restoring the first data to the replacement storage unit includes: The corresponding data mask is operated to mask the operation of writing the second data in parallel with the first data corresponding to the error position, so as to restore the first data to the replacement storage unit.

11. The memory operation method according to claim 5, further comprising: In response to the completion of the post-packaging repair process, a compensated refresh command is sent.

12. The memory operation method according to claim 5, further comprising: In response to completion of the repair mode, control over the memory array is switched from the repair mode to the operating mode in a second self-refresh state.

13. The memory operation method according to claim 1, wherein: Before starting the post-packaging repair process, the memory operation method further includes: The repair status register corresponding to the error position is read to determine whether there are available repair resources.

14. The memory operation method according to claim 1, further comprising: In response to a reset operation or an initialization operation on the memory, a hard repair of the memory array is triggered to replace the target memory cell at the error location in the memory array of the memory with a repair result of a replacement memory cell in the memory array used for the post-packaging repair process to fix the repair result.

15. A memory comprising a storage array, an operation control module, a storage controller and a repair module; The storage controller is configured to read and write the storage array in a working state; The repair module is configured to perform a repair operation on the storage array; The operation control module is configured to: In response to detecting an error in a memory array of the memory during an operation state of the memory, determining an error location of the error in the memory array, After the memory enters the idle state, the memory is controlled to start the repair module to perform a post-packaging repair process, wherein: The repair module is further configured to replace the target storage unit at the error location with a replacement storage unit in the storage array for the post-packaging repair process according to the error location; After the post-packaging repair process, the memory is switched back to the working state, whereby the memory controller uses the replacement memory unit to replace the target memory unit for operation.

16. The memory of claim 15, wherein: The operation control device comprises: A selector, wherein an input end of the selector is connected to the storage controller and the repair control module, and an output end of the selector is connected to the storage array; The permission switching module is configured to provide a control signal to the selector so that the selector switches the control right over the storage array from the working mode to the repair mode, or switches from the repair mode back to the working mode.

17. The memory of claim 15, further comprising: The data buffer is configured to provide a buffer space required by the storage array in the working mode or the repair mode.

18. The memory of claim 15, further comprising: The repair status register is configured to record whether there are available repair resources at the error location.

19. An electronic device comprising the memory according to any one of claims 15 to 18.

20. A non-transitory storage medium that non-transitorily stores computer-executable instructions, wherein: When the computer executable instructions are executed by at least one processor, the memory operation method according to any one of claims 1 to 14 is implemented.

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