Semiconductor package

Abstract

A semiconductor package includes: a substrate; a platform die disposed on the substrate; a memory die disposed on the platform die; and a processor die disposed on the platform die and disposed adjacent to the memory die, where the platform die includes a memory controller configured to control data communication between the memory die and the processor die.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0134562 filed with the Korean Intellectual Property Office on October 4, 2024 and Korean Patent Application No. 10-2025-0002838 filed with the Korean Intellectual Property Office on January 8, 2025, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates to a semiconductor package and a method for manufacturing the semiconductor package. Background Technology

[0004] Modern electronic devices demand high performance and efficiency, and semiconductor integrated circuit (IC) technology is constantly evolving to meet this need. Specifically, the rapid development of high-performance computing devices, artificial intelligence (AI) processors, graphics processing units (GPUs), data centers, and mobile devices may require higher processing speeds and more powerful data processing capabilities.

[0005] To meet these needs, multi-die or system-on-a-chip (SoC) technology has been widely used in the semiconductor technology field. These technologies, by integrating and operating multiple processors, memories, and various functional blocks into a single package, can help increase space efficiency in addition to improving performance.

[0006] However, signal integrity and power consumption may remain significant challenges in achieving efficient interconnection and communication between dies. Specifically, in high-performance systems, maintaining reliability while optimizing data transfer rates between multiple processors and memory can be critical. This may require new packaging technologies and power management solutions.

[0007] Furthermore, the miniaturization and high-density integration of semiconductor devices increase the precision and complexity of manufacturing processes, thereby increasing manufacturing costs. Therefore, innovative design and packaging technologies are needed to maintain high performance while also being cost-effective. Summary of the Invention

[0008] One or more aspects of this disclosure relate to a semiconductor package and a method of manufacturing the semiconductor package.

[0009] According to one aspect of this disclosure, a semiconductor package is provided, comprising: a substrate; a platform die disposed on the substrate; a memory die disposed on the platform die; and a processor die disposed on the platform die and configured to be adjacent to the memory die; wherein the platform die includes a memory controller configured to control data communication between the memory die and the processor die.

[0010] The memory die can be configured to transmit data through a direct connection with the memory controller.

[0011] The memory die includes a memory stack including stacked memory dies, a number of data lines between the memory dies of the memory stack can be the same as a number of data lines between the memory stack and the memory controller.

[0012] The platform die can include a buffer configured to condition signals between the memory die and the memory controller.

[0013] The memory controller can share the system bus with the processor die.

[0014] The processor die can include a plurality of processor cores, and the memory controller can be connected to the plurality of processor cores via the system bus.

[0015] The memory controller can be connected to the system bus based on a hybrid bond.

[0016] The processor die can include a first interface circuit, the platform die can include a second interface circuit, the first interface circuit can be configured to serialize data received from the system bus and deserialize data received from the second interface circuit, and the second interface circuit can be configured to serialize data received from the memory controller and deserialize data received from the first interface circuit.

[0017] The memory controller can include a bus having a different protocol than the system bus, and the processor die can include a bridge module configured to coordinate communication between the bus of the memory controller and the system bus.

[0018] The platform die can include a communication module configured to communicate between the processor die and another processor die.

[0019] The communication module can share the system bus with the processor die.

[0020] The platform die can include a test module.

[0021] The platform die can include a voltage regulator.

[0022] The platform die can include a static random access memory (SRAM), and the SRAM can be configured to operate as a cache for the processor die.

[0023] The memory die can include a plurality of memory stacks including stacked memory dies, and the processor die can include a structure connected to each of the plurality of memory stacks to communicate with the same.

[0024] According to another aspect of the disclosure, there is provided a semiconductor package including a wafer-level platform chip, a plurality of memory dies disposed on the wafer-level platform chip, and a plurality of processor dies disposed on the wafer-level platform chip, wherein the wafer-level platform chip includes a memory controller configured to control data communication between the plurality of memory dies and the plurality of processor dies, and a communication module configured to communicate with the plurality of processor dies.

[0025] The memory controller and the communication module share a system bus with the plurality of processor dies.

[0026] The memory controller and the communication module can be directly connected to each other in the wafer-level platform chip.

[0027] The wafer-level platform chip can include an external communication module configured to communicate with devices external to the wafer-level platform chip, and the communication module can be connected to the external communication module.

[0028] Each of the plurality of memory dies can include a memory stack including stacked memory dies.

[0029] Other features and aspects will become apparent from the following detailed description, drawings and claims. BRIEF DESCRIPTION OF DRAWINGS

[0030] Embodiments of the disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a perspective view of a 2.5D high bandwidth memory (HBM) chiplet structure of the prior art.

[0032] Figure 2 is a front view of a cross-section of a 2.5D HBM chiplet structure of the prior art, for illustrating a data transfer scheme in the 2.5D HBM chiplet structure of the prior art.

[0033] Figure 3 is a front view of a cross-section of a 2.5D HBM chiplet structure of the prior art, for providing a description of a data transfer limitation of the 2.5D HBM chiplet structure of the prior art.

[0034] Figure 4 is a top view of a cross-section of a 2.5D HBM chiplet structure of the prior art, for illustrating a data transfer limitation occurring in the 2.5D HBM chiplet structure of the prior art.

[0035] Figure 5 is a perspective view of a semiconductor package structure according to an embodiment.

[0036] Figure 6 is a front perspective view of a semiconductor package to illustrate a system bus structure and communication modules in a semiconductor package according to an embodiment.

[0037] Figure 7 is a diagram showing an example of a semiconductor package according to an embodiment.

[0038] Figure 8 is a front view of a cross section of a semiconductor package structure to illustrate an advantage of a semiconductor package structure according to an embodiment.

[0039] Figure 9 is a diagram showing a method of connecting a memory controller to a system bus.

[0040] Figure 10 is a diagram showing a method of connecting a memory controller to a system bus using serializer / deserializer (SerDes) technology.

[0041] Figure 11 is a diagram showing a method of using a bridge circuit to resolve protocol differences between a memory controller and a system bus.

[0042] Figure 12 is a diagram showing a structure in which a test module and a voltage regulator in a semiconductor package according to an embodiment are disposed on a platform die 220.

[0043] Figure 13 is a perspective view of a semiconductor package including a plurality of processor dies according to an embodiment.

[0044] Figure 14 is a front view of a cross section of a semiconductor package including a plurality of platform dies according to an embodiment.

[0045] Figure 15 is a perspective view of a semiconductor package in which four memory stacks are connected to one processor die according to an embodiment.

[0046] Figure 16 is a perspective view of a semiconductor package in which a plurality of processor dies and a plurality of memory stacks are disposed on a wafer according to an embodiment.

[0047] Figure 17 is a front view of a cross section of a semiconductor package according to an embodiment.

[0048] Figure 18 and Figure 19is a diagram illustrating a structure of a memory controller and a network-on-chip (NoC) communication module sharing a processor die and a system bus in a semiconductor package according to an embodiment.

[0049] Figure 20 is a perspective view of a semiconductor package 600 according to an embodiment of applying a wafer-level platform.

[0050] Figure 21 is a diagram illustrating a structure of a semiconductor package according to an embodiment.

[0051] Figure 22 is a diagram illustrating an example of implementing a wafer-based rack structure in a semiconductor package according to an embodiment.

[0052] Figure 23 is a perspective view of a semiconductor package structure according to an embodiment.

[0053] Figure 24 is a perspective front view of a semiconductor package for describing a system bus structure and a communication module in a semiconductor package according to an embodiment.

[0054] Figure 25 is a perspective view of a semiconductor package according to an embodiment, in which a plurality of processor dies and memory dies are disposed on a wafer-level platform chip.

[0055] Figure 26 is a sectional front view of a semiconductor package according to an embodiment.

[0056] Throughout the drawings and the detailed description, unless otherwise described or specified, the same reference numerals will be understood to refer to the same elements, features, and structures. The drawings can not be to scale, and the relative dimensions, proportions, and depiction of elements in the drawings can be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0057] The following description of the structure or function of examples disclosed herein is merely for the purpose of describing examples and can be implemented in various forms. The examples are not intended to be limiting, but are intended to cover various modifications, equivalents, and alternatives within the scope of the claims.

[0058] Although terms of "first" or "second" are used to explain various components, the components are not limited by these terms. These terms should be used only to distinguish one component from another component. For example, within the scope of the right of the idea according to the present disclosure, a "first" component can be referred to as a "second" component, or similarly, a "second" component can be referred to as a "first" component.

[0059] It should be noted that if a component is described as being "connected," "coupled," or "joined" to another component, a third component can be "connected," "coupled," and "joined" between the first and second components directly or indirectly, and may

[0060] The singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0061] According to one or more embodiments, various operations and / or functions described herein can be implemented in a method of hardware. For example, according to some embodiments, the methods described below can be implemented by an electronic device configured to perform one or more operations or functions described. The electronic device can include blocks, which can be referred to herein as managers, units, modules, hardware components, "…er" terms, etc., can be physically implemented by analog and / or digital circuits (e.g., logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive and active electronic elements, optical elements, hardwired circuits, etc.), and can be optionally driven by firmware. These circuits can be, for example, implemented in one or more semiconductor chips, or on a substrate such as a printed circuit board. The circuits constituting the blocks can be implemented by dedicated hardware or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware for performing some functions of the block and a processor for performing other functions of the block. Each block of the embodiments can be physically separated into two or more interacting and discrete blocks without departing from the scope of the disclosure. Similarly, blocks of the embodiments can be physically combined into more complex blocks without departing from the scope of the disclosure. However, the disclosure is not limited thereto, and thus, the blocks referred to herein as managers, units, modules, etc. can be software modules implemented by software code, program code, software instructions, etc. The software modules can be executed on one or more processors. According to embodiments, a "module" can be a minimum unit of a component integrally formed or a part thereof. The "module" can be a minimum unit for performing one or more functions or a part thereof. The "module" can be implemented in a mechanical manner or an electronic manner.

[0062] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this example belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0063] Examples can be implemented as various types of product such as a personal computer (PC), a laptop computer, a tablet computer, a smart phone, a television (TV), a smart home appliance, a smart vehicle, a kiosk, and / or a wearable device. Hereinafter, examples will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals are used for like elements.

[0064] Figure 1 is a perspective view of a prior art 2.5D high bandwidth memory (HBM) chiplet structure.

[0065] Referring to Figure 1 The prior art 2.5D HBM chiplet 100 can include a substrate 110, an interposer 120, a buffer die 130, a memory stack 140, and a processor die 150. The memory stack 140 can include memory dies 140-1, 140-2, 140-3, and 140-4. The interposer 120 can be disposed on the substrate 110, the buffer die 130 can be disposed on the interposer 120, and the memory dies 140-1, 140-2, 140-3, and 140-4 can be stacked on the buffer die 130. The processor die 150 can be disposed adjacent to the memory dies on the interposer 120.

[0066] The interposer 120 of the prior art 2.5D HBM chiplet 100 can be a passive component for providing electrical connections, and can provide a physical wire path for communication between the memory dies and the processor die. That is, the interposer 120 can be used only for transferring electrical signals, and can not include any active circuit.

[0067] The memory stack 140 can include multiple layers of memory dies 140-1, 140-2, 140-3, and 140-4, and each of the memory dies 140-1, 140-2, 140-3, and 140-4 can be used to store data and transmit the data to the processor die 150 through the buffer die 130.

[0068] In the prior art 2.5D HBM chiplet 100, the buffer die 130 plays an important role in relaying data transmission between the memory stack 140 and the processor die 150. Data generated by the memory dies 140-1, 140-2, 140-3, and 140-4 cannot be directly transmitted to the processor die 150 and can be transmitted to the processor die 150 via the buffer die 130. In this way, the buffer die 130 can improve the stability and accuracy of the signal by temporarily storing the data signal and transmitting the signal by regenerating the signal. In addition, the buffer die 130 can improve the data processing speed of the entire system by minimizing the delay and signal distortion that can occur during the data transmission process. The buffer die 130 can be referred to as a base die.

[0069] In a high-speed data transmission environment, the presence of the buffer die 130 can be particularly important as signal loss and delay can increase as the physical distance between the memory stack 140 and the processor die 150 increases. The buffer die 130 can alleviate the above-mentioned problems and can facilitate smoother communication between the memory and the processor. Accordingly, the buffer die 130 can play a key role in maintaining data transmission reliability as well as maximizing system performance in the prior art 2.5D HBM chiplet 100 structure.

[0070] The processor die 150 can process data transmitted from the memory stack 140 and can include various processor cores (e.g., central processing units (CPUs), graphics processing units (GPUs), and neural processing units (NPUs)). The processor cores can be designed to efficiently perform high-performance computing tasks and can smoothly process data transmission with the memory stack 140.

[0071] Figure 2 is a front view of a cross-section of a prior art 2.5D HBM chiplet structure to illustrate a data transmission scheme in the prior art 2.5D HBM chiplet structure. Reference is made to Figure 1 The description provided can also be applied to Figure 2 .

[0072] Reference is made to Figure 2 In the prior art 2.5D HBM chiplet 100 structure, as the memory stack 140 and the processor die 150 are physically spaced apart from each other (e.g., less than or equal to 2 mm), electrical loss can occur when transmitting a signal. To compensate for this deficiency, the buffer die 130 and the processor die 150 can require physical layer (PHY) circuits 131 and 151, respectively, which can be used to maintain the accuracy and stability of the signal.

[0073] Data generated by the memory stack 140 can pass through the buffer die 130 and can be transmitted to the processor die 150 through the PHY circuit 131 included in the buffer die 130. Also, the PHY circuit 151 can be included in the processor die 150 and can process signals transmitted from the memory stack 140 through the PHY circuit 151.

[0074] In the processor die 150, a memory controller (MC) 152 configured to process data from the memory stack 140 and a die-to-die (D2D) communication module 153 configured to communicate with other chips can be installed. The MC 152 can manage data transmission with the memory stack 140 and the communication module 153 can be used to exchange data between the processor die 150 and other dies.

[0075] The silicon bridge 121 can be used to achieve more efficient electrical connection between the memory stack 140 and the processor die 150. Since the silicon bridge 121 has a high wire density, the silicon bridge 121 can be used to reduce signal loss that can occur during data transmission and can increase transmission rate. In another example, data transmission can be performed through the interposer 120 without using the silicon bridge 121, in which case the interposer 120 can be a passive element for providing simple electrical wires and can not perform an active signal processing function. However, in this case, the possibility of signal loss or distortion occurring in signal transmission between the memory stack 140 and the processor die 150 can increase. To address this issue, the silicon bridge 121 as well as the PHY circuits 131 and 151 can be required in the prior art 2.5D HBM chiplet 100 structure.

[0076] However, the use of the PHY circuits 131 and 151 can cause some drawbacks. For example, the PHY circuits 131 and 151 can cause additional power consumption and signal delay to process physical transmission of signals. Also, the PHY circuits 131 and 151 can need to be disposed on a boundary line, i.e., an edge of the buffer die 130 and the processor die 150, in order to be physically connected at the shortest distance. This can limit the available space in the processor die 150, and the available space in the processor die 150 can be even more limited especially since the MC 152 and the communication module 153 can need to be disposed in the processor die 150. Such a limitation can increase design complexity of the processor die 150 and can limit the final data rate.

[0077] Figure 3 is a front view of a cross-section of a prior art 2.5D HBM chiplet structure to illustrate data transmission limitations of the prior art 2.5D HBM chiplet structure. Reference is made to Figure 1 andFigure 2 The description provided can also be applied to Figure 3 .

[0078] Referring to Figure 3 , since the interposer 120 is used only as a simple wire, signal loss and distortion can occur in the process of signal transmission between the memory stack 140 and the processor die 150. To compensate for the signal loss and / or signal distortion, the memory stack 140 and the processor die 150 can require PHY circuits 131 and 151, respectively.

[0079] In this case, the PHY circuits 131 and 151 can need to be connected with a minimum distance between the memory stack 140 and the processor die 150 to minimize signal loss and distortion. Accordingly, the PHY circuits 131 and 151 can be disposed at a position closest to each other. In other words, the PHY circuits 131 and 151 can be disposed at a boundary corresponding to edges of the buffer die 130 and the processor die 150. The interposer 120 and the silicon bridge 121 can need to provide as many wires as possible in a physical space, and in the process, a spacing (e.g., pitch size) between the wires can be an important factor. However, since the pitch size is limited, it can not be possible to connect all data lines provided by the memory stack 140 to the processor die 150, but only some data lines can be used.

[0080] Figure 4 is a top view of a cross-section of a prior art 2.5D HBM chiplet structure to illustrate data transmission limitations that are present in the prior art 2.5D HBM chiplet structure. Referring to Figures 1 to 3 The description provided can also be applied to Figure 4 .

[0081] As described above with reference to Figure 3 , due to the physical limitations of the 2.5D HBM chiplet structure, it can not be possible to connect all data lines provided by the memory stack 140 to the processor die 150, but only some data lines can be used.

[0082] Referring to Figure 3 , the buffer die 130 can transfer some data lines provided by the memory stack 140 to the PHY circuit 131 through a multiplexer (MUX) 132. For example, the multiplexer 132 can be an N:1 multiplexer (e.g., N is 2, 4, or 8), and the multiplexer 132 can transfer 1 / N of the data lines provided by the memory stack 140 to the PHY circuit 131. This can result in underutilization of the high bandwidth of the memory controller, which can degrade the performance of the entire system. As shown in Figure 4 , the buffer die 130 can include a through silicon via (TSV) region.

[0083] As described below, the semiconductor package according to the embodiment can use a platform die including active circuits instead of an interposer to remove the buffer die 130 required for the 2.5D HBM chiplet 100 structure of the related art and can implement the functions performed by the buffer die 130 in the platform die. Additionally, since the memory controller (MC) is disposed on the platform die instead of the processor die, the PHY circuits 131 and 151 can not be required. Since the active circuits of the platform die perform the roles of the physical layer (PHY) circuits 131 and 151, the physical limitations (e.g., the problem of not being able to connect all the data lines provided by the memory stack 140 to the processor die 150) due to the PHY circuits 131 and 151 can be naturally solved by removing the PHY circuits 131 and 151. Through the structural improvement made by adopting the platform die according to the embodiment, system performance can be improved, and a method of connecting the MC to the processor die to implement the structure can be proposed. Hereinafter, the semiconductor package can be a physical structure in which semiconductor chips are attached to a substrate and connected to external circuits. The semiconductor package can also be referred to as a semiconductor structure or a semiconductor device.

[0084] Figure 5 is a perspective view of a semiconductor package structure according to an embodiment.

[0085] Referring to Figure 5 , the semiconductor package 200 according to the embodiment can include a platform die 220 disposed on a substrate 210. Unlike the interposer 120 of the 2.5D HBM chiplet structure of the related art, the platform die 220 can include active circuits. For example, the platform die 220 can be configured to function as a buffer die. According to the embodiment, a main circuit such as a memory controller (MC) can be disposed on the platform die 220. A memory die can be disposed on the platform die 220. The memory die can include a memory stack in which a plurality of memory dies are stacked. Although Figures 5 to 22The memory die is shown as a memory stack 240, but the memory die is not limited thereto, and thus, the memory die can be implemented by various memory devices. For example, the memory die can be implemented by a volatile memory device or a non-volatile memory device. The volatile memory device can be implemented by a dynamic random access memory (DRAM), a static RAM (SRAM), a thyristor RAM (T-RAM), a zero capacitor RAM (Z-RAM), or a dual transistor RAM (TTRAM). The non-volatile memory device can be implemented by an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM (MRAM), a spin transfer torque-MRAM (STT-MRAM), a conductive bridge RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM, a polymer RAM (PoRAM), a nano floating gate memory (NFGM), a holographic memory, a molecular electronic memory device, or an insulator resistance change memory. The type of the memory die is not limited thereto.

[0086] The memory stack 240 can be disposed on the platform die 220, and the memory stack 240 can include a plurality of memory dies 240-1, 240-2, 240-3, and 240-4. For example, the memory die can be implemented as an HBM, and can provide a high data transfer rate and bandwidth. However, the memory stack 240 is not limited thereto. In addition to the HBM device, the memory stack 240 can be implemented as a low power double data rate (LPDDR) device, a graphics double data rate (GDDR) device, or a double data rate (DDR) device.

[0087] The platform die 220 can be a kind of semiconductor chip, can be implemented as a semiconductor device (e.g., silicon), and can be referred to as an active interposer. Unlike the interposer 120 of the related art, the platform die 220 can include an active circuit, and a main circuit (e.g., MC) can be disposed on the platform die. The platform chip 220 can manage and optimize data transmission between the memory stack 240 and the processor die 250. The number of data lines between the stacked memory dies 240-1, 240-2, 240-3, and 240-4 of the memory stack 240 can be the same as the number of data lines between the memory stack 240 and the memory controller (MC).

[0088] According to an embodiment, since the memory controller (MC) is disposed on the platform die 220, data transmission between the memory stack 240 and the processor die 250 can be efficiently managed. The processor die 250 can be directly connected to the MC disposed on the platform die 220. Accordingly, the PHY circuit of the prior art 2.5D HBM chiplet structure can not be required. Further, since the PHY circuit is not required, the limitations (e.g., signal loss or distortion, power consumption, and signal delay problems) due to the PHY circuit can be naturally resolved.

[0089] The processor die 250 can include various types of processors (e.g., CPU, GPU, and NPU). For example, the various types of processors can allow efficient execution of high-performance computing tasks (e.g., machine learning tasks including artificial intelligence (AI) and deep neural network (DNN)). The computing system including the semiconductor package 200 can perform various high-performance computing tasks including machine learning. Machine learning can also be used in various application fields other than AI and DNN (e.g., data analysis, image processing, and natural language processing).

[0090] Figure 6 is a front perspective view of a semiconductor package to illustrate a system bus structure and a communication module in a semiconductor package according to an embodiment. Reference is made to Figure 5 The description provided can also be applied to Figure 6 .

[0091] Reference is made to Figure 6 According to an embodiment, the system bus 251 in the semiconductor package 200 can manage data transmission between the processor die 250 and the platform die 220. The system bus 251 can also be referred to as an on-chip bus (or on-chip network), and can support communication between various processor cores. The system bus 251 can use an Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) bus as the system bus 251. The AMBA AXI can be a bus that provides high bandwidth and low latency, and can enable high-speed data transmission between slave devices and multiple master devices. However, the system bus 251 is not limited thereto. Accordingly, according to another embodiment, the architecture and / or protocol of the system bus can be different from the AMBA AXI.

[0092] The processor die 250 can include a plurality of processor cores (e.g., CPU, GPU, and NPU), and the cores can be connected to each other via the system bus 251. This structure can support efficient communication of the processor cores with the MC 221 and other important circuits. For example, the CPU can perform a task of reading or writing data in the memory stack 240 through the MC 221, and the task can be performed quickly via the system bus 251.

[0093] The semiconductor package 200 can further include a communication module 222. The communication module 222 can be used to manage data transmission between the processor die 250 and other processor dies. The communication module 222 can include a die-to-die (D2D) communication module or a chip-to-chip (C2C) communication module. The communication module can use a standard interface (e.g., universal chiplet interconnect express (UCIe) or peripheral component interconnect express (PCIe)). For example, the D2D communication module can use a UCIe standard interface, and the C2C communication module can use a PCIe standard interface. The UCIe can be a latest interface standard for high-speed data transmission between chiplets, and can enable efficient communication in a chiplet-based design. The UCIe can provide low latency and high data processing throughput required for a high-performance computing environment. The PCIe can be a widely used high-speed data transmission interface, and can support data transmission between internal devices and external devices of a computer. The PCIe can significantly increase data transmission rates using a serial communication scheme, and can provide scalability and flexibility by adjusting the number of links.

[0094] Figure 7 FIG. 1 is a diagram illustrating an example of a semiconductor package according to an embodiment. Referring to FIG. 1, Figure 5 and Figure 6 The description provided above can also be applied to Figure 7 .

[0095] Referring to Figure 7 , according to an embodiment, each memory die (240-1 to 240-4) of the memory stack 240 can be physically connected to the platform die 220 via a via 241. The via 241 can transmit electrical signals by penetrating the inside of the memory die vertically, and can efficiently transmit data of the memory stack 240 to the platform die 220. Since the data lines of the memory dies 240-1, 240-2, 240-3, and 240-4 are connected to the platform die 220 by using the via 241, the data lines of the memory dies 240-1, 240-2, 240-3, and 240-4 can be connected to the platform die 220. The via 241 can be a through silicon via (TSV) that penetrates a silicon substrate. The TSV can provide a high-speed path for quickly transmitting data generated by the memory stack 240 to the platform die 220 without loss of data, and can maintain signal integrity in the package.

[0096] For example, the electrical connection between the memory stack 240 and the platform die 220 can vary according to a set direction of the wiring layer of the platform die 220. An active area of the platform die 220 can be formed below a surface of a wafer in which active components (e.g., transistors) are disposed, and can perform data operations and processing. A wiring layer area (back end of line (BEOL) area) formed above the active area can include multiple layers of metal wiring, and can be used to transmit signals generated in the active area.

[0097] In the example case where the wiring layer of the platform die 220 is disposed on the upper side (e.g., face-to-face connection or front-to-front connection), since the wiring layer area of the platform die 220 is disposed on the upper portion, the wiring layer area of the platform die 220 can be in direct contact with the wiring layer area of the memory stack 240, and can be connected to the wiring layer area of the memory stack 240. In this case, the platform die 220 can be connected to the external circuit by forming a via 241 on the lower portion to be connected to the outside.

[0098] In the example case where the wiring layer of the platform die 220 is disposed on the lower side (e.g., face-to-back connection or front-to-back connection), the wiring layer area of the platform die 220 can be disposed on the lower portion, and cannot be directly connected to the memory stack 240. In this case, the via 241 can penetrate the platform die 220, and can be connected to the memory stack 240 on the upper portion. The signal generated in the memory stack 240 can be transmitted to the wiring layer area of the platform die 220 via the via 241, and the wiring layer of the lower portion of the platform die 220 can be directly connected to the external circuit without the via 241.

[0099] The electrical connection between the memory stack 240 and the platform die 220 can be implemented not only with the via 241, but also with a micro bump. The micro bump can provide contact between the memory stack 240 and the platform die 220, and can ensure stable transmission of data signals. The data signal transmitted through the micro bump can be directly connected to the MC 221 in the platform die 220, and thus can simplify the data transmission path, and can minimize signal delay. However, the present disclosure is not limited thereto, and thus the micro bump is only an example of a data pin, and other types of data pins can be used. For example, other bumps (e.g., copper (Cu) bumps or solder bumps) can be used as pins for data transmission. According to another embodiment, a hybrid bonding scheme that directly connects a die to a die can be used. According to an embodiment, a solder bump 211 can be disposed between the substrate 210 and the platform die 220. The solder bump 211 can be disposed to facilitate interconnection between wiring in the platform die 220 and wiring in the substrate 210.

[0100] For example, in the semiconductor package 200, since the data line of the memory stack 240 is directly connected to the platform die 220, the need for a PHY circuit in the prior art structure can be eliminated. Since data can be quickly and efficiently processed by directly connecting the data line to the MC 221, the data transmission rate can be improved, and the overall performance of the system can be optimized. This design is particularly advantageous in the field of high-performance computing and memory-intensive applications.

[0101] Figure 8 is a front view of a cross-section of a semiconductor package structure to illustrate advantages of a semiconductor package structure according to an embodiment. Reference is made to Figures 5 to 7 the description of Figure 8 .

[0102] According to an embodiment, the semiconductor package 200 structure can include a platform die 220 having an active circuit. Accordingly, data lines can be directly connected to the MC 221, a data transmission path can be simplified, and signal delay and loss can be minimized. Data lines provided by the memory stack 240 can be directly connected to the platform die 220, and data transmission rate and system performance can be improved.

[0103] For example, since the platform die 220 can directly receive data lines of the memory stack 240, a bottleneck phenomenon occurring during a data transmission process can be eliminated. For example, data lines provided by the memory stack 240 can be directly connected to the platform die 220, and thus data transmission rate can be improved. This structural advantage can play an important role in high-performance computing and massive data processing.

[0104] By providing the MC 221 on the platform die 220 rather than on the processor die 250, the semiconductor package 200 according to an embodiment can secure free space in the processor die 250, and additional cores or modules can be provided in the space for performance improvement. However, since the memory speed can be significantly faster than the speed of the system bus 251, many data lines can be required for a data transmission path between the MC 221 and the system bus 251. Hereinafter, a method of effectively solving the above-described problem will be described with reference to Figures 9 to 11 .

[0105] Figure 9 A method of connecting a memory controller to a system bus is illustrated. Reference is made to Figures 5 to 8 the description provided can also be applied to Figure 9 .

[0106] Referring to Figure 9 , the processor die 250 can include a plurality of processor cores, and the processor cores can be connected to the system bus 251 to exchange data. For example, the processor die 250 can include processor cores 250-1, 250-2, to 250-n, where n is a natural number greater than or equal to 2.

[0107] A plurality of data lines can be connected between the MC 221 and the system bus 251 to quickly transfer data generated by the MC 221 to the system bus 251. For example, a plurality of data lines can be directly connected between the MC 221 and the system bus 251. According to an embodiment, a hybrid bonding technique can be used to facilitate data transmission between the MC 221 and the system bus 251. For example, the hybrid bonding technique is a method of arranging data lines at a high density in a die-to-die connection, and can physically extend a data transmission path between the MC 221 and the system bus 251. This can increase a data transmission rate and minimize latency.

[0108] In addition, the communication module 222 can be connected to the system bus 251 in a similar manner to the MC 221, enabling efficient data transmission with other processor dies.

[0109] Figure 10 is a diagram illustrating a method of connecting a memory controller to a system bus using a serializer / deserializer (SerDes) technique. Referring to Figures 5 to 8 The description provided can also be applied to Figure 10 .

[0110] Referring to Figure 10 , the semiconductor package 200 according to an embodiment can include SerDes circuits 252 and 223 to efficiently transmit data read by a memory die to the system bus 251 via the MC 221, or to transmit data from the system bus 251 to the memory die via the MC 211. For example, SerDes is a technique for converting (serializing) parallel data into serial data and restoring (deserializing) serial data into parallel data. The semiconductor package 200 can use the SerDes circuits 252 and 223 to reduce the number of data lines while maintaining a high data transmission rate.

[0111] The SerDes circuit 223 can be used to perform data transmission between the MC 221 and the system bus 251. In the example case where data read by the memory die can be transmitted to the SerDes circuit 223 via the MC 221 and can be serialized, the serialized data can be transmitted to the system bus 251, the data arriving at the system bus 251 can be deserialized by the SerDes circuit 252, and can be transmitted to the plurality of processor cores 250-1 to 250-n of the processor die 250. In the example case where data is transmitted from the system bus 251 to the MC 221, the SerDes circuit 252 can serialize and transmit the data, and the SerDes circuit 223 can deserialize and transmit it to the MC 221. In this process, the SerDes circuits can minimize signal distortion or loss, and can maximize data transmission efficiency. As described above, the MC 221 can perform efficient bidirectional data transmission with the system bus 251 via the SerDes circuits 223 and 252.

[0112] Additionally, the communication module 222 can also be bidirectionally connected to the system bus 251 via the SerDes circuits 224 and 253.

[0113] Data read by another processor die can be transmitted to the SerDes circuit 224 via the communication module 222, and can be serialized. In the example case where the serialized data can be transmitted to the system bus 251, the data arriving at the system bus 251 can be deserialized via the SerDes circuit 253, and can be transmitted to the plurality of processor cores 250-1 to 250-n of the processor die 250. In the example case where data is transmitted from the system bus 251 to another processor die, the SerDes circuit 253 can serialize and transmit the data, and the SerDes circuit 224 can deserialize and transmit it to the communication module 222. As described above, the communication module 222 can perform efficient bidirectional data transmission with the system bus 251 via the SerDes circuits 224 and 253.

[0114] Figure 11 A method of solving protocol differences between a memory controller and a system bus using a bridge circuit is shown. Referring to Figures 5 to 8 The description provided can also be applied to Figure 11 .

[0115] According to embodiments, MC 221 can handle data using a unique bus protocol that is different from system bus 251, and bridge circuit 254 can be used to make the data compatible with system bus 251. According to embodiments, bridge circuit 254 can also be used to convert data transmitted from system bus 251 into a format that MC 221 can understand. For example, bridge circuit 254 and MC 221 can be connected via bus 261.

[0116] Bridge circuit 254 can act as a coordinator that converts data between two different protocols between MC 221 and system bus 251. For example, MC 221 can use a specific high-speed memory protocol, while system bus 251 can use a different protocol (e.g., AMBA AXI bus). In this case, bridge circuit 254 can convert data transmitted from MC 221 into a format that system bus 251 can understand, and vice versa, can convert data transmitted from system bus 251 into a format that MC 221 can handle.

[0117] In addition, communication module 222 can be connected to system bus 251 via bridge circuit 255. According to embodiments, communication module 222 can use a unique protocol when transmitting data with other processor dies. For example, the unique protocol can not be compatible with system bus 251. In this case, bridge circuit 255 can convert data transmitted from communication module 222 into a format that system bus 251 can understand, and vice versa, can convert data transmitted from system bus 251 into a format that communication module 222 can handle to coordinate communication. For example, bridge circuit 255 and communication module 222 can be connected to each other via bus 262.

[0118] According to embodiments, using bridge circuits 254 and 255 can allow MC 221 and communication module 222 to communicate efficiently with system bus 251, and can improve data transmission efficiency of the system while maintaining compatibility between various protocols. This can enable smooth data transmission between memory and processors, and can optimize performance of the entire system.

[0119] Figure 12 FIG. 3 is a diagram illustrating a structure in which a test module and a voltage regulator in a semiconductor package are disposed on a platform die 220 according to an embodiment. Referring to FIG. 3, platform die 220 can include a test module 310, a voltage regulator 320, and a bridge circuit 330. Figures 5 to 11 The description provided above can also be applied to Figure 12 .

[0120] The buffer die of the prior art 2.5D HBM chiplet can be used to regulate signals between the memory stack and the MC. For example, to regulate signals between the memory stack and the MC, various circuits for stabilizing and amplifying the signals can be provided on the buffer die. However, the semiconductor package 200 according to an embodiment can remove the buffer die and simplify the design by integrating the functions into the platform die 220. However, the present disclosure is not limited thereto, and thus, according to an embodiment, the platform die 220 can include a buffer circuit that can be used to directly regulate data between the memory stack 240 and the MC 221. For example, the buffer circuit of the platform die 220 can buffer signals between the memory stack 240 and the MC 221 to independently maintain the size of each signal. In another example, a plurality of signals can be transmitted at different speeds, and the buffer circuit can be used to align and transmit the signals in time sequence so that they leave at the same time. In other words, the semiconductor package 200 can minimize signal loss or distortion via the buffer circuit of the platform die 220, and can improve the reliability and speed of data transmission.

[0121] Referring to Figure 12 A test module can be provided on the platform die 220. The test module can be, for example, a design for test (DFT) module 225. The DFT module 225 can perform various functions for testing the semiconductor device, and since the DFT module 225 is provided on the platform die 220, the test efficiency of the entire chip can be improved. For example, the DFT module 225 can test a communication path between the memory stack 240, the MC 221, and the processor die 250 to detect defects early in the production phase and ensure the reliability of the entire system.

[0122] In addition, a voltage regulator can be provided on the platform die 220. The voltage regulator can include, for example, integrated voltage regulator (IVR) modules 226 and 227. The IVR modules 226 and 227 can be circuits that play an important role in regulating voltage and optimizing power management. For example, the IVR module 226 can manage the memory stack 240, can stably supply power required by the memory stack, and / or can regulate voltage. The IVR module 227 can manage the processor die 250, can regulate voltage according to the power requirement of the processor die, and / or can ensure efficient power supply. In the prior art, the power management circuit is physically separated from the memory stack or the processor die, which can reduce power efficiency. However, by providing the IVR modules 226 and 227 on the platform die, the semiconductor package 200 can achieve power management closely related to the memory stack and the processor die. This can reduce power loss, improve the stability of power supply, and optimize the power efficiency of the entire system.

[0123] According to an embodiment, a static random access memory (SRAM) can also be provided on the platform die 220. The SRAM can be used as a cache connected to the processor die 250. The cache can play an important role in improving the processing rate of the processor by storing data most frequently accessed by the processor core. Since the SRAM is provided on the platform die 220, the cache can be placed close to the processor die 250, so that the access speed can become faster, and the overall system performance can be improved.

[0124] Although Figure 12 Although the MC 221 is shown positioned below the processor die 250, the location of the MC 221 is not limited thereto. For example, the MC 221 can be positioned below the memory stack 240. In addition, the communication module 222 (e.g., D2D 222) can be positioned as close to the boundary of the platform die as possible. In this way, the communication module 222 can facilitate die-to-die communication with minimal latency, optimizing system performance and optimizing communication with other processor dies.

[0125] With the above structural improvement, the semiconductor package 200 can simplify the design and can maximize the performance and efficiency of the system by integrating various functions performed by the buffer die of the related art into the platform die 220.

[0126] Figure 13 is a perspective view of a semiconductor package including a plurality of processor dies according to an embodiment. Referring to Figures 5 to 12 The description provided above can also be applied to Figure 13 .

[0127] Although Figure 13 Although an example of a semiconductor package 300 including two platform dies 320-1 and 320-2 is shown, the semiconductor package 300 is not limited thereto and can include a plurality of platform dies.

[0128] Referring to Figure 13 , the semiconductor package 300 according to an embodiment can include two platform dies 320-1 and 320-2 provided on a substrate 310. For example, processor dies 350-1 and 350-2 can be provided on the platform dies 320-1 and 320-2, respectively, and the processor dies can include processor cores (e.g., CPUs, GPUs, or NPUs). The processor dies 350-1 and 350-2 can be used to perform high-performance operation tasks and data processing, and can be interconnected to optimize system performance.

[0129] The platform dies 320-1 and 320-2 can be connected to each other via a communication module. In addition, the memory stacks 340-1 and 340-2 can be stacked on the platform dies 320-1 and 320-2, respectively, to store and process data by being directly connected to the corresponding platform dies. The memory stacks can use HBM or other memory technology.

[0130] According to embodiments of the disclosure, the number of platform dies is not limited to two and can include multiple platform dies as needed. Since the platform dies are interconnected via a communication module, the scalability and performance of the system can be maximized. This structure is advantageous in improving the efficiency of parallel processing and high-performance computing tasks.

[0131] Figure 14 is a front view of a section of a semiconductor package including multiple platform dies according to embodiments. Reference is made to Figures 5 to 13 the description of Figure 14 .

[0132] Reference is made to Figure 14 , two platform dies 320-1 and 320-2 are arranged side by side on a substrate 310, and processor dies 350-1 and 350-2 are arranged on the platform dies 320-1 and 320-2, respectively.

[0133] The substrate 310 can serve as the basis of the semiconductor package, and all components can be fixed thereto. The substrate 310 can provide electrical connections and can be used to transfer power and signals within the package.

[0134] The platform dies 320-1 and 320-2 can be arranged on the substrate 310, and the processor dies 350-1 and 350-2 can be arranged on the platform dies 320-1 and 320-2, respectively. The processor dies 350-1 and 350-2 can include processor cores (e.g., CPUs, GPUs, or NPUs) and can perform high-performance computing and data processing. Data transmission between the processor dies 350-1 and 350-2 can be performed via communication modules 322-1 and 322-2 arranged on the platform dies 320-1 and 320-2, respectively. The communication modules 322-1 and 322-2 can be designed to quickly and efficiently transmit data between the processor dies 350-1 and 350-2, can minimize the delay that occurs during data transmission, and can maximize the transmission rate.

[0135] The memory stacks 340-1 and 340-2 can be stacked on the platform dies 320-1 and 320-2, respectively, and the memory stacks can store and process data. The memory stacks 340-1 and 340-2 can use HBM technology and can be directly connected to the platform dies 320-1 and 320-2 via MCs 321-1 and 321-2, respectively.

[0136] The number of platform dies of the semiconductor package 300 according to the embodiments is not limited to two, and can include a plurality of platform dies. The semiconductor package structure described above can maximize the scalability and performance of a system, and can have a great advantage especially in an environment requiring parallel processing and high-performance computation. Since a plurality of platform dies are efficiently connected via a communication module, the data processing speed and efficiency of the entire system can be improved.

[0137] Figure 15 is a perspective view of a semiconductor package in which four memory stacks are connected to one processor die according to the embodiments. Referring to Figures 5 to 14 The description provided above can also be applied to Figure 15 .

[0138] Referring to Figure 15 , the semiconductor package 400 according to the embodiments can include a platform die 420 disposed on a substrate 410, a plurality of memory stacks 440-1, 440-2, 440-3, and 440-4 stacked thereon, and a processor die 450 connected to the memory stacks.

[0139] According to the embodiments, a memory controller (MC) can be disposed on the platform die 420, and the MC can be used to control data communication between the plurality of memory stacks 440-1, 440-2, 440-3, and 440-4 and the processor die 450. Data generated by the memory stacks 440-1, 440-2, 440-3, and 440-4 can pass through the MC disposed on the platform die 420 and then can be transmitted to the processor die 450. This structure can enable efficient data transmission between the memory and the processor.

[0140] The memory stacks 440-1, 440-2, 440-3, and 440-4 can use a memory technology such as HBM, and each memory stack can be used to store data and transmit the data to the processor die 450 via the MC disposed on the platform die 420. The number of memory stacks is not limited to four, and more memory stacks can be connected to one processor die as needed.

[0141] The processor die 450 can process data transmitted from the memory stacks 440-1, 440-2, 440-3, and 440-4. The processor die 450 can include various processor cores (e.g., CPU, GPU, or NPU), and can perform high-performance computation tasks through efficient connection with the MC.

[0142] The semiconductor package 400 according to embodiments can be advantageous for application fields requiring high-bandwidth data transmission. In the example case where multiple memory stacks are connected to one processor die, each memory stack can efficiently communicate with the processor die via the MC of the platform die. This can allow maximization of the performance and scalability of the system, and can provide significant advantages especially in parallel data processing and high-performance computing tasks.

[0143] Figure 16 is a perspective view of a semiconductor package according to embodiments, in which multiple processor dies and multiple memory stacks are disposed on a wafer-level platform chip. Reference is made to Figures 5 to 15 The description provided can also apply to Figure 16 .

[0144] Reference is made to Figure 16 The semiconductor package 500 according to embodiments of a wafer-level platform structure can include a wafer-level platform chip 520. The wafer-level platform chip 520 can include active circuits, and reference is made to Figures 5 to 15 The functions of the platform die described can be scaled up at the wafer level. Since the wafer-level platform chip 520 of the semiconductor package 500 is wafer-level, all the wiring can be performed on the wafer. Thus, the semiconductor package 500 can not require a separate substrate. The wafer-level platform chip 520 can include active circuits (e.g., MC, network-on-chip (NoC) communication modules, and wafer-to-wafer (W2W) communication modules), and through these active circuits, data communication between the multiple memory stacks 540-1 and 540-2 and the processor dies 550-1 through 550-n can be efficiently managed. Each of the memory stacks 540-1 and 540-2 can use HBM technology, and can be used for storing and transmitting data. Although Figure 16 An example of the semiconductor package 500 including two memory stacks 540-1 and 540-2 is shown, but the semiconductor package 500 is not limited thereto.

[0145] According to embodiments, not all of the processor dies 550-1 through 550-n can be directly connected to the memory stacks. Some of the processor dies 550-1 through 550-n (e.g., 550-1 and 550-2) can be directly connected to the memory stacks 540-1 and 540-2 via the MC, but other processor dies (e.g., 550-n) can perform separate tasks without being directly connected to the memory dies. In this case, these processor dies (e.g., 550-n) can communicate with other processor dies and memory stacks via the NoC communication modules.

[0146] Figure 17 is a front view of a section of a semiconductor package according to embodiments. Reference is made to Figures 5 to 16The provided description can also apply to Figure 17 .

[0147] Referring to Figure 17 , the semiconductor package 500 can illustrate a structure in which a plurality of processor dies 550-1 to 550-n and memory stacks 540-1 and 540-2 are disposed on a wafer-level platform chip 520.

[0148] The MCs 521-1 and 521-2, the NoC communication modules 522-1 to 522-n, and the wafer-to-wafer (W2W) communication module 523 can be disposed on the wafer-level platform chip 520. The MCs 521-1 and 521-2 can manage data communication between the memory stacks 540-1 and 540-2 and the processor dies 550-1 and 550-2, respectively. For example, the processor dies 550-1 and 550-2 can be connected to the MCs 521-1 and 521-2 and the NoC communication modules 522-1 and 522-2, respectively, and the connection can be performed by sharing the same bus (e.g., system buses 551-1 and 551-2). For example, the processor die 550-1 can be connected to the MC 521-1 and the NoC communication module 522-1, and in this case, the connection can share the system bus 551-1.

[0149] However, a processor die (e.g., the processor die 550-n) can not be directly connected to a memory stack as described above and can operate independently. The processor die 550-n can be connected to the NoC communication module 522-n, and in this case, the connection can share the system bus 551-n. The processor die (e.g., the processor die 550-n) can communicate with other processor dies and memory stacks via the NoC communication module 522-n connected thereto. The NoC communication modules 522-1 to 522-n can support data transmission with the processor dies 550-1 to 550-n in the wafer, and can significantly improve the flexibility and scalability of the system. The NoC structure in the wafer-level platform chip 520 can allow each processor die to transfer data with other processor dies or memory stacks as needed. Accordingly, the system can efficiently process complex computation tasks and can exhibit optimal performance in various application programs.

[0150] In addition, the W2W communication module 523 can support wafer-to-wafer communication and can enable data synchronization and communication with various wafers. Through the W2W communication module 523, the semiconductor package 500 can perform efficient data transmission and cooperative tasks in a multi-wafer expansion system.

[0151] The semiconductor package 500 according to an embodiment can optimize the efficiency of data transmission and can be advantageous in a high-performance computing environment requiring a large amount of parallel computation.

[0152] Figure 18 and Figure 19 are diagrams illustrating structures of a memory controller and a network-on-chip (NoC) communication module sharing a processor die and a system bus in a semiconductor package according to an embodiment. Reference is made to Figures 5 to 17 the description of Figure 18 and Figure 19 .

[0153] Referring to Figure 18 , in a semiconductor package 500 according to an embodiment, MCs 521-1 and 521-2 and NoC communication modules 522-1 and 522-2 can be connected to processor dies 550-1 and 550-2 via system buses 551-1 and 551-2, respectively.

[0154] In the example case where the MCs 521-1 and 521-2 and the NoC communication modules 522-1 and 522-2 are connected to the system buses 551-1 and 551-2, the method of connecting the MCs and the communication modules to the system buses described with reference to Figures 9 to 11 may be applied. For example, in the example case where the MC 521-1 is connected to the processor die 550-1 via the system bus 551-1, the connection can be implemented by directly connecting data lines, or can be implemented by serializing or deserializing data using SerDes circuits. In addition, communication between different protocols can be coordinated by setting a bridge circuit between the MC and the NoC communication module using their own protocols.

[0155] In a processor die (e.g., the processor die 550-1) according to an embodiment, in order to retrieve data from a memory die (e.g., the memory die 540-2) that is not connected to the processor die, intervention of a processor die (e.g., the processor die 550-2) connected to the memory die 540-2 can be required. For example, in order to retrieve data from the memory die 540-2 in the processor die 550-1, the processor die 550-1 can access the memory die 540-2 in the order of the NoC communication module 522-1 connected to the processor die 550-1, the NoC communication module 522-2 connected to the memory die 540-2, the processor die 550-2, and the MC 521-2.

[0156] Referring to Figure 19According to embodiments, MCs 521-1 and 521-2 and NoC communication modules 522-1 and 522-2 can be directly connected to each other via wires 552-1 and 552-2, respectively. NoC communication modules 522-1 and 522-2 can include direct memory access (DMA) functionality. Thereby, in a processor die (e.g., processor die 550-1), in an example case of retrieving data from a memory die (e.g., memory die 540-2) that is not connected to the processor die, the processor die (e.g., processor die 550-1) can directly access MC 521-2 without the intervention of a processor die (e.g., processor die 550-2) that is connected to the memory die. For example, to retrieve data from memory die 540-2 in processor die 550-1, processor die 550-1 can access memory die 540-2 in the order of NoC communication module 522-1 connected to processor die 550-1, NoC communication module 522-2 connected to memory die 540-2, and MC 521-2.

[0157] According to embodiments, as shown in FIG. 6, a direct connection scheme can maximize data transfer efficiency in a high-performance computing environment, and can provide a great advantage especially for systems that frequently perform parallel operations. Figure 18 and Figure 19

[0158] Figure 20 is a perspective view of a semiconductor package 600 that applies a wafer-level platform according to embodiments.

[0159] Referring to Figure 20 In a wafer-level platform structure according to embodiments, a plurality of memory stacks 640-1 through 640-4 and a plurality of processor dies 650-1 through 650-n can be disposed on a wafer 620 of semiconductor package 600.

[0160] A wafer-level platform structure according to embodiments can be based on the concept of disposing as many dies as possible on a single wafer to maximize performance, rather than manufacturing small chips in a reticle-by-reticle manner based on the related art. The wafer-level platform structure can achieve large-scale die integration using the entire wafer 620. Figure 16 A basic form in which processor dies are arranged in a single row is shown, while Figure 20 Features of the wafer-level platform are more intuitively shown.

[0161] Referring to Figure 16 ​Compared to the described semiconductor package 500, semiconductor package 600 may have a structure in which memory stacks 640-1 to 640-4 and processor dies 650-1 to 650-n are arranged in an extended form in multiple rows, instead of arranging the memory stacks and processor dies in a single row on wafer 620. Although Figure 20 An example of a semiconductor package 600 including four memory stacks 640-1, 640-2, 640-3 and 640-4 is shown, but the semiconductor package 600 is not limited thereto.

[0162] Chip 620 may include active circuitry and may include MC and NoC communication modules. Similarly, in Figure 20 In the semiconductor package 600, multiple processor dies 650-1, 650-2, 650-3, 650-4 to 650-n can be interconnected via a NoC communication module. The NoC communication module can transmit data between the processor dies and control the data flow between them. Through this NoC structure, the processor dies can transmit data at high speed and low latency, and the overall system performance can be maximized.

[0163] Additionally, the MC (Memory Management Module) located in chip 620 manages data communication between each memory stack and each processor die, and can be connected to the system bus to transfer data processed by the memory stack to the processor die, or transfer data from the processor die to the memory stack. The MC and NoC (No-Channel Communication Module) can cooperate with each other to optimize data transfer and improve data flow efficiency in the system.

[0164] Because multiple processor dies and memory stacks are configured simultaneously. Figure 20 The semiconductor package 600, with its extended wafer-level platform architecture, delivers superior performance in high-performance computing environments. Because multiple processor dies 650-1 to 650-n are connected via a NoC communication module, flexible and efficient data processing and high-speed computation can be achieved within the chip 620. This architecture offers significant advantages for applications requiring parallel processing and big data analytics.

[0165] Figure 21 This is a diagram illustrating the structure of a semiconductor package according to an embodiment. (Reference) Figures 5 to 20 The description can also be applied to Figure 21 .

[0166] refer to Figure 21 The semiconductor package 700 according to the embodiment can be a new concept of semiconductor packaging, which is based on a wafer-level platform to achieve large-scale integration beyond the system-on-chip (SoC).

[0167] The semiconductor package 700 can include a plurality of mask tiles 720-1 and 720-2. The semiconductor package 700 according to an embodiment is an example of the semiconductor package 500 having a wafer-level platform structure, and the plurality of mask tiles 720-1 and 720-2 can be implemented on a wafer-level platform chip (e.g., the wafer-level platform chip 520) of Figure 16 . The plurality of mask tiles 720-1 and 720-2 can be implemented on one wafer and can be connected to each other without physical cutting.

[0168] The plurality of AI accelerators 731 and 733 and a processor die 732 (e.g., a CPU) can be disposed on the mask tile 720-1. The plurality of memory stacks 734 and 736 (e.g., HBM memory stacks) and a processor die 735 (e.g., a CPU) can be disposed on the mask tile 720-2.

[0169] The two mask tiles 720-1 and 720-2 can be connected to each other via a communication module, and this can enable efficient data transmission between components disposed on each mask tile. In addition, the AI accelerators 731 and 733 and the CPUs 732 and 735 disposed on the mask tiles 720-1 and 720-2, respectively, can be connected to each other via a communication module (e.g., a NoC communication module) in a wafer.

[0170] A voltage regulator VR can be disposed on each of the mask tiles 720-1 and 720-2, and can supply stable power to the processor dies and the AI accelerators through the voltage regulator. Power management can be performed through a power communication network between the mask tiles and a substrate (not shown), and this integrated power management structure can improve the energy efficiency of the system.

[0171] Figure 22 is a diagram illustrating an example of implementing a wafer-based rack structure in a semiconductor package according to an embodiment. Referring to Figures 5 to 21 the description provided above in connection with Figure 22 may also be applied to

[0172] The wafer-based rack structure according to an embodiment can be implemented by integrating a rack-based data center architecture of the related art into a single wafer. Referring to Figure 22 , a plurality of compute blocks 820 can be integrated into a single wafer 810. Each compute block 820 can include modules including a plurality of processor dies, memory stacks, and AI accelerators described with reference to Figures 5 to 21 , and these modules can be arranged at a wafer level. For example, the compute block 820 can include a memory M, a CPU C, and an AI accelerator A. The connection between the components in each compute block 820 can be made through a communication module (e.g., a NoC communication module) as described with reference to Figure 21The described NoC communication module or other custom interconnect is implemented to perform. For example, the memory, CPU, and AI accelerator can be connected by referring to Figure 21 The described NoC communication module or other custom interconnect is connected to each other. For example, the connection between the components in each computing block 820 can enable high-speed data transfer between the processor, memory, and AI accelerator in the computing block 820, and efficient communication with other blocks. Accordingly, the wafer-based rack structure can provide superior performance in a high-performance computing environment requiring a large number of parallel operations.

[0173] According to an embodiment, the wafer-based rack structure can provide a great advantage for application fields requiring large data processing, such as AI operations, machine learning, and big data analysis. Since each computing block can transfer data at high speed, operation efficiency can be maximized, and the response time of the entire system can be reduced.

[0174] According to an embodiment, the wafer-based rack structure can be a completely new architecture that overcomes the physical limitations of the existing data center, and can significantly improve performance by integrating a plurality of high-performance computing elements into a single wafer 810, while reducing the size and power consumption of the data center.

[0175] Figure 23 is a perspective view of a semiconductor package structure according to an embodiment.

[0176] Referring to Figure 23 , the semiconductor package 900 according to an embodiment can include a platform die 920 disposed on a substrate 910. The platform die 920 can include an active circuit and one or more master circuits. For example, the active circuit can serve as a buffer die, and the one or more master circuits can include a memory controller disposed on the platform die 920. A memory die 940 can be disposed on the platform die 920. The memory die can be implemented by a volatile memory device or a non-volatile memory device. The volatile memory device can be implemented by DRAM, SRAM, T-RAM, Z-RAM, or TTRAM. The non-volatile memory device can be implemented by EEPROM, flash memory, MRAM, STT-MRAM, CBRAM, FeRAM, PRAM, RRAM, nanotube RRAM, PoRAM, NFGM, holographic memory, molecular electronic memory device, or insulator resistance change memory. The type of the memory die 940 is not limited thereto.

[0177] The platform die 920 can be a kind of semiconductor chip. The platform die 920 can be implemented by a semiconductor device, and can be referred to as an active interposer. For example, the semiconductor device can be a silicon semiconductor device. Unlike the interposer of the related art, the platform die 920 can include an active circuit and a main circuit (e.g., a memory controller). The platform die 920 can manage and optimize data transmission between the memory die 940 and the processor die 950.

[0178] The memory controller can be disposed on the platform die 920 to efficiently manage data transfer between the memory die 940 and the processor die 950. The processor die 950 can be directly connected to the memory controller disposed on the platform die 920. Also, since the memory controller is disposed on the platform die 920, the processor die 950 does not need to be changed to correspond to the memory die 940 even in the example case where the type of the memory die 940 is changed.

[0179] The processor die 950 can include various processors (e.g., CPU, GPU, and NPU). One or more of the various processors included in the processor die 950 can allow the processor die 950 to efficiently perform high-performance computing tasks, especially machine learning tasks (e.g., AI and DNN). The computing system including the semiconductor package 900 can perform various high-performance computing tasks including machine learning. Machine learning can be used in various application fields including AI, DNN, data analysis, image processing, and natural language processing.

[0180] Figure 24 is a perspective front view of a semiconductor package for describing a system bus structure and a communication module in the semiconductor package according to an embodiment. Reference is made to Figure 23 The description provided can be applied to Figure 24 the description of

[0181] Reference is made to Figure 24 According to an embodiment, the system bus 951 in the semiconductor package 900 can manage data transfer between the processor die 950 and the platform die 920. The system bus 951 can also be referred to as an on-chip bus (or on-chip network), and can support communication between various processor cores. The system bus 951 can use the AMBA AXI bus as the system bus 951. The AMBA AXI can be a bus that provides high bandwidth and low latency, and can allow high-speed data transfer between a plurality of master and slave devices. However, the system bus 951 is not limited thereto.

[0182] The processor die 950 can include a plurality of processor cores (e.g., CPUs, GPUs, and NPUs), and the cores can be connected to each other via a system bus 951. The system bus 951 can support efficient communication of the processor cores with the memory controller 921 and other components or circuits. For example, a CPU can read or write data in the memory die 940 via the memory controller 921, and the task (e.g., reading or writing data task) can be performed quickly via the system bus 951.

[0183] According to an embodiment, the communication module 922 can be included in the semiconductor package 900. The communication module 922 can be used to manage data transfer between the processor die 950 and other processor dies. The communication module 922 can include a D2D communication module or a C2C communication module. The communication module can use a standard interface (e.g., UCIe or PCIe). For example, the D2D communication module can use a UCIe standard interface, and the C2C communication module can use a PCIe standard interface. UCIe can be a latest interface standard for high-speed data transfer between small chips, and can enable efficient communication in a small chip-based design. UCIe can provide low latency and high data processing throughput required for a high-performance computing environment. PCIe can be a widely used high-speed data transfer interface, and can support data transfer between internal devices and external devices of a computer. PCIe can use a serial communication scheme to significantly increase data transfer rates, and can provide scalability and flexibility by adjusting the number of links.

[0184] Figure 25 is a perspective view of a semiconductor package according to an embodiment in which a plurality of processor dies and a memory die are disposed on a wafer-level platform chip. Referring to Figures 5 to 24 The description provided can be applied to Figure 25 the description of

[0185] Referring to Figure 25 According to an embodiment, the semiconductor package 1000 having a wafer-level platform structure can include a wafer-level platform chip 1020. The wafer-level platform chip 1020 can include active circuits, and can be regarded as a wafer-level platform chip according to Figures 5 to 15The functionality of the described platform die is extended at the wafer level. Since the wafer level platform chip 1020 of the semiconductor package 1000 is wafer level, all the wiring can be set on the wafer. Therefore, the semiconductor package 1000 can not need a separate substrate. The wafer level platform chip 1020 can include a memory controller and active circuits (e.g., a NoC communication module and a W2W communication module). These components can allow the wafer level platform chip 1020 to efficiently manage data communication between the plurality of memory dies 1040-1 and 1040-2 and the processor dies 1050-1, 1050-2, through 1050-n (where n is an integer). Each of the memory dies 1040-1 and 1040-2 can use HBM technology and can perform data storage and transmission. Although Figure 25 An example of the semiconductor package 1000 including two memory dies 1040-1 and 1040-2 is shown, but the semiconductor package 1000 is not limited thereto. Accordingly, according to another embodiment, the number of memory dies can be different from two.

[0186] Not all of the processor dies 1050-1 through 1050-n can be directly connected to the memory dies. Some of the processor dies (e.g., 1050-1 and 1050-2) can be directly connected to the memory dies 1040-1 and 1040-2 via the memory controller, but some other processor dies (e.g., 1050-n) can not be directly connected to the memory dies and can perform separate tasks. In this case, the processor dies (e.g., 1050-n) can communicate with other processor dies and the memory dies via the NoC communication module.

[0187] Figure 26 is a cross-sectional elevation view of a semiconductor package according to an embodiment. Referring to Figures 5 to 25 The description provided can be applied to Figure 26 the description of

[0188] Referring to Figure 26 , the semiconductor package 1000 can show a structure in which a plurality of processor dies 1050-1 through 1050-n and memory dies 1040-1 and 1040-2 are disposed on a wafer level platform chip 1020.

[0189] The memory dies 1040-1 and 1040-2 can be implemented by volatile memory devices or non-volatile memory devices. The volatile memory devices can be implemented by DRAM, SRAM, T-RAM, or TTRAM. The non-volatile memory devices can be implemented by EEPROM, flash memory, MRAM, STT-MRAM, CBRAM, FeRAM, RRAM, nanotube RRAM, PoRAM, NFGM, holographic memory, molecular electronic devices, or resistive random-access memory. The types of the memory dies 1040-1 and 1040-2 are not limited thereto.

[0190] The memory controllers 1021-1 and 1021-2, the NoC communication modules 1022-1 to 1022-n, and the W2W communication module 1023 can be disposed on the wafer-level platform chip 1020. The memory controllers 1021-1 and 1021-2 can manage data communication between the memory dies 1040-1 and 1040-2 and the processor dies 1050-1 and 1050-2. For example, the processor dies 1050-1 and 1050-2 can be connected to the memory controllers 1021-1 and 1021-2 and the NoC communication modules 1022-1 and 1022-2, respectively, and the connection can be performed by sharing the same bus (e.g., system buses 1051-1 and 1051-2). For example, the processor die 1050-1 can be connected to the memory controller 1021-1 and the NoC communication module 1022-1, and the connection can share the system bus 1051-1. For example, the processor die 1050-1 can be connected to both the memory controller 1021-1 and the NoC communication module 1022-1 via the same system bus 1051-1.

[0191] However, as described above, a certain processor die (e.g., 1050-n) can not be directly connected to the memory dies and can operate independently. The processor die 1050-n can be connected to the NoC communication module 1022-n, and the connection can share the system bus 1051-n. The processor die (e.g., 1050-n) can communicate with other processor dies and memory dies via the NoC communication module 1022-n connected thereto. The NoC communication modules 1022-1 to 1022-n can support data transfer between the processor dies 1050-1 to 1050-n in the wafer, and can significantly improve the flexibility and scalability of the system. The NoC structure in the wafer-level platform chip 1020 can allow each processor die to transmit data to and receive data from other processor dies or memory dies as needed. Accordingly, the system can efficiently process complex computing tasks and can achieve optimal performance in various application programs.

[0192] In addition, the W2W communication module 1023 can support wafer-to-wafer communication, and can enable data synchronization and communication between a plurality of wafers. Through the W2W communication module 1023, the semiconductor package 1000 can efficiently perform data transfer and cooperative tasks even in an extended system across a plurality of wafers.

[0193] The structure of the semiconductor package 1000 according to the embodiments can maximize the efficiency of data transfer, and can be advantageous in a high-performance computing environment requiring massive parallel computing.

[0194] The embodiments described herein can be implemented using hardware components, software components, and / or combinations thereof. The processing device can be implemented using one or more general-purpose or special purpose computers (e.g., processors, controllers and arithmetic logic units (ALUs), DSPs, microcomputers, FPGAs, programmable logic units (PLUs), microprocessors, or any other devices capable of responding to and executing instructions in a defined manner). The processing device can run an operating system (OS) and one or more software applications running on the OS. The processing device can also access, store, manipulate, process, and create data in response to the execution of software. For simplicity, the processing device is described singularly; however, one of ordinary skill in the art will appreciate that the processing device can include multiple processing elements and multiple types of processing elements. For example, the processing device can include multiple processors or a processor and a controller. In addition, different processing configurations are possible (e.g., parallel processor).

[0195] The software can include a computer program, code, instructions, or combinations thereof for independently or collectively instructing or configuring the processing device to operate as desired. The software and data can be permanently or temporarily stored in any type of machine, component, physical or virtual storage device, computer storage medium or device, or propagated signal waves capable of providing instructions or data to the processing device or being interpreted by the processing device, permanently or temporarily. The software can also be distributed over network-coupled computer systems so that the software is stored and executed in a distributed fashion. The software and data can be stored by one or more non-transitory computer-readable recording mediums.

[0196] The methods according to the above-described examples can be recorded in non-transitory computer-readable media including program instructions to implement various operations embodied by the methods according to the above-described examples. The media can also include, alone or in combination with the program instructions, data files, data structures, and the like. The program instructions recorded on the media can be those specially designed and constructed for the purposes of the examples, or they can be of the type well known and available to those having skill in computer software

[0197] While the present disclosure includes specific examples, it will be apparent to one of ordinary skill in the art, having the benefit of this disclosure, that many modifications, embodiments, and variations of these specific examples can be made in light of this disclosure without departing from the scope of the claims and their equivalents. The examples described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects in each example should be considered to apply to other examples as well, unless the context explicitly dictates otherwise. Where appropriate, singular forms such as "a," "an," and "the" include plural referents unless the context clearly dictates otherwise.

Claims

1. A semiconductor package, comprising: Substrate; The platform die is disposed on the substrate; A memory die is disposed on the platform die; as well as A processor die is disposed on the platform die and is configured to be adjacent to the memory die; The platform die includes a memory controller configured to control data communication between the memory die and the processor die.

2. The semiconductor package according to claim 1, wherein, The memory die is configured to transmit data via a direct connection to the memory controller.

3. The semiconductor package according to claim 1, wherein, The memory die includes a memory stack, and the memory stack includes stacked memory dies.

4. The semiconductor package according to claim 3, wherein, The number of data lines between the stacked memory dies of the memory stack is the same as the number of data lines between the memory stack and the memory controller.

5. The semiconductor package according to claim 1, wherein, The platform die includes a buffer configured to regulate the signal between the memory die and the memory controller.

6. The semiconductor package according to claim 1, wherein, The memory controller shares a system bus with the processor die.

7. The semiconductor package according to claim 6, wherein, The processor die includes multiple processor cores, and The memory controller is connected to the plurality of processor cores via the system bus.

8. The semiconductor package according to claim 6, wherein, The memory controller is connected to the system bus via hybrid bonding.

9. The semiconductor package according to claim 6, wherein: The processor die includes a first interface circuit. The platform die includes a second interface circuit. The first interface circuit is configured to serialize data received from the system bus and deserialize data received from the second interface circuit. The second interface circuit is configured to serialize data received from the memory controller and deserialize data received from the first interface circuit.

10. The semiconductor package according to claim 6, wherein, The memory controller includes a bus with a different protocol than the system bus, and The processor die includes a bridge module configured to coordinate communication between the bus of the memory controller and the system bus.

11. The semiconductor package according to claim 1, wherein, The platform die includes a communication module configured to communicate between the processor die and another processor die.

12. The semiconductor package of claim 11, wherein, The communication module shares the system bus with the processor die.

13. The semiconductor package according to claim 1, wherein, The platform die includes a test module.

14. The semiconductor package according to claim 1, wherein, The platform die includes a voltage regulator.

15. The semiconductor package according to claim 1, wherein, The platform die includes static random access memory (SRAM), and The SRAM is configured to function as a cache for the processor die.

16. A semiconductor package, comprising: Wafer-level platform chips; as well as Multiple memory dies are disposed on the wafer-level platform chip; as well as Multiple processor dies are mounted on the wafer-level platform chip; The wafer-level platform chip includes: A memory controller is configured to control data communication between the plurality of memory dies and the plurality of processor dies; and The communication module is configured to communicate with the plurality of processor dies.

17. The semiconductor package of claim 16, wherein, The memory controller and the communication module share a system bus with the plurality of processor dies.

18. The semiconductor package of claim 16, wherein, The memory controller and the communication module are directly connected to each other in the wafer-level platform chip.

19. The semiconductor package of claim 16, wherein, The wafer-level platform chip includes an external communication module configured to communicate with devices outside the wafer-level platform chip, and The communication module is connected to the external communication module.

20. The semiconductor package of claim 16, wherein, Each of the plurality of memory dies includes a memory stack, the memory stack comprising stacked memory dies.

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