An imaging device, a method for powering an imaging device, and related apparatus

Abstract

The application provides an imaging device, a method for powering the imaging device and related equipment. The imaging device comprises a semiconductor substrate, two sides of the semiconductor substrate are provided with a first well and a second well, a surface of the first well is sequentially provided with a first insulating medium layer and a control gate electrode, and a size of a voltage applied to the control gate electrode is in a positive correlation with a number of charges stored in the first well. Different sizes of voltages can be applied to the control gate electrode in different light intensity environments, and the greater the voltage applied to the control gate electrode, the greater the capacitance of the first well, so that the full well capacity of the imaging device can meet different light environments.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to an imaging device, a method for powering the imaging device and related equipment. BACKGROUND

[0002] An image sensor is a device for converting photoelectrons into electrical signals, and the following will describe the partial structure of an imaging device for composing a sensor provided by the prior art. Figure 1

[0003] The imaging device includes a semiconductor substrate 100, an N buried layer 101 is formed by implanting N impurities at the outer edge of the semiconductor substrate 100, and the N buried layer 101 and the semiconductor substrate 100 close to the N buried layer 101 form a photodiode (PD) 103. When external incident light irradiates on the PD 103, the PD 103 generates photoelectrons corresponding to the incident light, and the photoelectrons can be transferred into a floating diffusion node 104 to generate an electrical signal for obtaining a corresponding image.

[0004] However, as the size of the image sensor is continuously reduced, the area of the PD 103 of a single imaging device is reduced, so that the N buried layer 101 after the area reduction cannot provide sufficient full well capacity (FWC) for the imaging device, and the reduction of the full well capacity reduces the signal-to-noise ratio, sensitivity and the like of the imaging device. SUMMARY

[0005] The present application provides an imaging device, a method for powering the imaging device and related equipment, which has a full well capacity matched with the light intensity, so that the full well capacity of the imaging device can meet different light intensities.

[0006] The first aspect of the embodiment of the present application provides an imaging device, including a semiconductor substrate, the two sides of the semiconductor substrate are respectively provided with a first well and a second well by ion implantation doping, the semiconductor substrate and the second well have a first doping type, and the first well has a second doping type; the surface of the first well is sequentially provided with a first insulating medium layer and a control gate electrode, and the size of the voltage applied to the control gate electrode and the number of charges stored in the first well are in a positive correlation relationship.

[0007] ​It can be understood that different voltages can be applied to the control gate electrode in different light intensity environments, that is, the stronger the light in the light environment where the imaging device is located, the greater the voltage applied to the control gate electrode. In the case where the control gate electrode is applied with a voltage, the first well becomes a capacitor for storing charges, and the greater the voltage applied to the control gate electrode, the greater the capacitance of the first well, that is, the size of the voltage applied to the control gate electrode and the number of charges that can be stored in the first well are positively correlated. It can be seen that when the light intensity is relatively large, a high voltage can be applied to the control gate electrode, so that the first well can accommodate more charges, thereby improving the full well capacity of the imaging device; when the light intensity is relatively weak, a weak voltage can be applied to the control gate electrode, so that the full well capacity of the first well can meet the demand under weak light, thereby avoiding waste of power consumption.

[0008] Based on the first aspect of the embodiment of the present application, in an optional implementation manner of the first aspect of the embodiment of the present application, the control gate electrode is provided with a second insulating medium layer facing the surface of the semiconductor substrate, a containing cavity is formed between the first insulating medium layer and the second insulating medium layer, and a floating gate for storing charges is arranged in the containing cavity.

[0009] It can be understood that in the imaging device, the floating gate for storing charges is increased, thereby improving the full well capacity of the imaging device and improving the number of charges that can be stored in the imaging device.

[0010] Based on the first aspect of the embodiment of the present application, in an optional implementation manner of the first aspect of the embodiment of the present application, a channel region is formed between the first well and the second well along the transverse direction of the imaging device, and the surface of the channel region is sequentially provided with the first insulating medium layer and a charge transfer transistor in a direction away from the channel region. The charge transfer transistor is used to enable the charges in the first well to be transmitted to a floating diffusion node in the second well via the channel region.

[0011] Since the floating diffusion node is arranged in the second well, the second well can effectively isolate the floating diffusion node, effectively avoiding the entry of charges into the floating diffusion node during exposure, avoiding the interference of charges on the floating diffusion node during exposure, and thereby effectively improving the accuracy of the number of read charges to improve the quality of the generated image.

[0012] Based on the first aspect of the embodiment of the present application, in an optional implementation manner of the first aspect of the embodiment of the present application, the first insulating medium layer is provided with at least one window, the floating gate and the first well are connected through the window, and the charge transfer transistor is further used to enable the charges in the floating gate to be transmitted to the floating diffusion node via the channel region.

[0013] Based on the first aspect of the embodiment of the present application, in an optional implementation of the first aspect of the embodiment of the present application, along a direction perpendicular to the imaging device, the window includes a first opening and a second opening arranged oppositely, the first opening is located on a surface of the first insulating medium layer facing the floating gate, the second opening is located on a surface of the first insulating medium layer facing the first well, and the first opening and the second opening are in conduction.

[0014] Based on the first aspect of the embodiment of the present application, in an optional implementation of the first aspect of the embodiment of the present application, the floating gate extends to the second opening along the guide of the window via the first opening, and the floating gate at the second opening and the first well are connected.

[0015] It can be understood that, in the case of setting the first insulating medium layer, the window can be directly set through the first insulating medium layer, and then the floating gate can be directly deposited on the surface of the first insulating medium layer by a method such as chemical vapor deposition (CVD), so that the floating gate deposited in the window is directly connected with the first well.

[0016] Based on the first aspect of the embodiment of the present application, in an optional implementation of the first aspect of the embodiment of the present application, the first well extends to the first opening along the guide of the window via the second opening, and the floating gate at the first opening and the first well are connected.

[0017] Based on the first aspect of the embodiment of the present application, in an optional implementation of the first aspect of the embodiment of the present application, the floating gate extends to the inside of the window via the first opening, the first well extends to the inside of the window via the second opening, and the floating gate in the inside of the window and the first well are connected.

[0018] It can be understood that, the direct connection of the first well and the floating gate is realized via the window, the full well capacity of the imaging device is improved, and then the efficiency of charge transfer and the quality of the obtained image are improved. Via the window, the first insulating medium layer is not damaged in the process of charge transfer, so that the requirement for the thickness of the first insulating medium layer is reduced. As the damage to the first insulating medium layer is effectively avoided, the accuracy of the number of read charges and the quality of the image are effectively improved, and in the process of use, the service life of the imaging device is improved, so that the reliability of the imaging device is improved.

[0019] In an optional implementation of the first aspect of the embodiments of the present application, a separation medium layer is arranged between the first well and the first insulating medium layer in a direction perpendicular to the imaging device, and the separation medium layer is a high-density P ion implantation medium.

[0020] It can be understood that, because the separation medium layer is arranged between the first well and the first insulating medium layer, the first well and the first insulating medium layer are effectively separated, the generation of dark current is reduced, the influence of the dark current on reading the number of charges stored in the floating gate is avoided, the accuracy of reading the number of charges is improved, and thus the quality of the image is improved.

[0021] In an optional implementation of the first aspect of the embodiments of the present application, the cross-sectional area of the first well is greater than the cross-sectional area of the second well in a lateral direction of the imaging device.

[0022] It can be understood that, because the cross-sectional area of the first well is greater than the cross-sectional area of the second well, the photosensitive area for generating charges during an exposure time period is effectively increased, and it can be seen that, in the case of increasing the photosensitive area of the imaging device, the photosensitive sensitivity of the imaging device is effectively increased.

[0023] In an optional implementation of the first aspect of the embodiments of the present application, the first well and the second well have a first distance therebetween in a lateral direction of the imaging device, and the first insulating medium layer and the second well have a second distance therebetween, and the first distance is less than the second distance.

[0024] It can be understood that, because the first distance is less than the second distance, the success rate and the transfer rate of the charges stored in the floating gate transferred to the floating diffusion node via the first well are increased, and the case that the charges stored in the floating gate cannot be successfully transferred to the floating diffusion node is effectively avoided.

[0025] In an optional implementation of the first aspect of the embodiments of the present application, the first doping type is n-type impurity doping, and the second doping type is p-type impurity doping; or, the first doping type is p-type impurity doping, and the second doping type is n-type impurity doping.

[0026] The second aspect of the embodiments of the present application provides a method for powering an imaging device, the method being used for a logic control circuit, the logic control circuit being electrically connected with the imaging device, and the method comprising the following steps.

[0027] The logic control circuit adjusts the voltage applied to the control gate electrode of the imaging device according to the charge stored in the imaging device, wherein the magnitude of the voltage applied to the control gate electrode is positively correlated with the amount of charge stored in the imaging device.

[0028] It can be understood that the amount of charge that can be stored by the phototransistor due to the photoelectric effect is positively correlated with the intensity of the light, that is, the greater the light intensity in the light environment in which the phototransistor is located, the greater the amount of charge that the phototransistor needs to store, and the weaker the light intensity in the light environment in which the phototransistor is located, the smaller the amount of charge that the phototransistor needs to store. The logic control circuit can adjust the magnitude of the voltage applied to the control gate electrode according to the intensity of the light in the light environment in which the phototransistor is located, so that the method provided in this embodiment can match the amount of charge that can be stored by the imaging device to the needs in different light environments.

[0029] Based on the second aspect of the embodiments of the present application, in an optional implementation manner of the second aspect of the embodiments of the present application, the method specifically comprises:

[0030] The logic control circuit obtains a target amount of charge stored in the imaging device in a first exposure time period; and adjusts the voltage applied to the control gate electrode of the imaging device in a second exposure time period according to the target amount, wherein the magnitude of the voltage applied to the control gate electrode is positively correlated with the target amount, and the first exposure time period is earlier than the second exposure time period.

[0031] It can be understood that if the logic control circuit determines that the phototransistor is in a strong light environment in the first exposure time period, the logic control circuit can increase the voltage applied to the control gate electrode, thereby increasing the capacitance of the first well, so that the first well can accommodate more charge in the second exposure time period, thereby enabling the full-well capacity of the phototransistor to meet the needs of strong light; if the logic control circuit determines that the phototransistor is in a weak light environment in the first exposure time period, the logic control circuit can reduce the voltage applied to the control gate electrode, thereby reducing the capacitance of the first well, so that the ability of the first well to accommodate charge in the second exposure time period matches the current light, effectively saving the power consumption of the voltage applied to the control gate electrode, and avoiding waste of power consumption in the case that the full-well capacity of the phototransistor meets the needs of the current light environment.

[0032] In an optional implementation of the second aspect of the embodiments of the present application, the adjusting the voltage applied to the control gate electrode of the imaging device in the second exposure time period according to the target number includes: if the target number is greater than or equal to a preset value, increasing the voltage applied to the control gate electrode of the imaging device in the second exposure time period.

[0033] It can be understood that, in the case where the logic control circuit determines that the target number is greater than or equal to the preset value, the logic control circuit can determine that the imaging device is in a strong light environment in the first exposure time period, and the logic control circuit can increase the voltage applied to the control gate electrode, thereby increasing the capacitance of the first well, so that the first well can accommodate more charges in the second exposure time period, thereby enabling the full-well capacity of the phototransistor to meet the requirement of strong light.

[0034] In an optional implementation of the second aspect of the embodiments of the present application, the adjusting the voltage applied to the control gate electrode of the imaging device in the second exposure time period according to the target number includes: if the target number is less than a preset value, reducing the voltage applied to the control gate electrode of the imaging device in the second exposure time period.

[0035] It can be understood that, in the case where the logic control circuit determines that the target number is less than the preset value, the logic control circuit can determine that the imaging device is in a weak light environment in the first exposure time period, and the logic control circuit can reduce the voltage applied to the control gate electrode, so that the full-well capacity of the first well in the second exposure time period can meet the requirement of the weak light environment, thereby avoiding waste of power consumption.

[0036] In an optional implementation of the second aspect of the embodiments of the present application, the method further includes: obtaining a preset voltage adjustment list, the preset voltage adjustment list including a corresponding relationship between different charge quantity ranges and different voltage values; and the adjusting the voltage applied to the control gate electrode of the imaging device in the second exposure time period according to the target number includes: determining a target voltage corresponding to the target number according to the preset voltage adjustment list; and applying the target voltage to the control gate electrode of the imaging device in the second exposure time period.

[0037] It can be understood that the dynamic adjustment of the target voltage applied to the control gate electrode through the preset voltage adjustment list enables the imaging device to match more diverse illumination environments, improves the matching degree of the imaging device and the illumination environment, and enables the full well capacity of the imaging device to meet the requirements of the current illumination environment after the logic control circuit applies the target voltage to the control gate electrode.

[0038] The third aspect of the embodiments of the present application provides a logic processing circuit, which is electrically connected with an imaging device, and includes an adjustment unit configured to adjust a voltage applied to a control gate electrode of the imaging device according to a charge stored in the imaging device, wherein the size of the voltage applied to the control gate electrode and the number of the charge stored in the imaging device are in a positive correlation.

[0039] Based on the third aspect of the embodiments of the present application, in an optional implementation manner of the third aspect of the embodiments of the present application, the logic processing circuit further includes an acquisition unit configured to acquire a target number of the charge stored in the imaging device in a first exposure time period; and the adjustment unit is further configured to adjust the voltage applied to the control gate electrode of the imaging device in a second exposure time period according to the target number, wherein the size of the voltage applied to the control gate electrode and the target number are in a positive correlation, and the first exposure time period is earlier than the second exposure time period.

[0040] Based on the third aspect of the embodiments of the present application, in an optional implementation manner of the third aspect of the embodiments of the present application, the adjustment unit is specifically configured to: if the target number is greater than or equal to a preset value, increase the voltage applied to the control gate electrode of the imaging device in the second exposure time period.

[0041] Based on the third aspect of the embodiments of the present application, in an optional implementation manner of the third aspect of the embodiments of the present application, the adjustment unit is specifically configured to: if the target number is less than a preset value, decrease the voltage applied to the control gate electrode of the imaging device in the second exposure time period.

[0042] Based on the third aspect of the embodiments of the present application, in an optional implementation manner of the third aspect of the embodiments of the present application, the adjustment unit is specifically configured to: acquire a preset voltage adjustment list, the preset voltage adjustment list including a corresponding relationship between different charge number ranges and different voltage values; determine a target voltage corresponding to the target number according to the preset voltage adjustment list; and apply the target voltage to the control gate electrode of the imaging device in the second exposure time period.

[0043] The fourth aspect of the embodiments of the present application provides an image sensor, the image sensor comprising a pixel array and a logic control circuit, the pixel array comprising at least one imaging device, the imaging device being electrically connected with the logic control circuit, the imaging device being as shown in the first aspect, and the logic control circuit being as shown in the third aspect, and details are not repeated here.

[0044] The fifth aspect of the embodiments of the present application provides an electronic device, the electronic device comprising a processor and an image sensor, the image sensor being as shown in the fourth aspect, and the processor being configured to acquire the image from the image sensor.

[0045] The sixth aspect of the embodiments of the present application provides a storage medium, the storage medium storing computer instructions, when the computer instructions are called by a logic control circuit, the logic control circuit is caused to execute the method shown in the second aspect.

[0046] The seventh aspect of the embodiments of the present application provides a computer program product, the computer program product comprising computer program codes, when the computer program codes are called by a logic control circuit, the logic control circuit is caused to execute the method shown in the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 An example structure diagram of an imaging device provided by the prior art;

[0048] Figure 2 An example structure diagram of an electronic device provided by the present application;

[0049] Figure 3 An example structure diagram of a pixel array provided by the present application;

[0050] Figure 4 Another example structure diagram of an imaging device provided by the prior art;

[0051] Figure 5 An example side view cross-sectional structure diagram of a phototransistor provided by the present application;

[0052] Figure 6 An example side view cross-sectional structure diagram of an imaging device provided by the present application;

[0053] Figure 7 Another example side view cross-sectional structure diagram of an imaging device provided by the present application;

[0054] Figure 8 Another example side view cross-sectional structure diagram of an imaging device provided by the present application;

[0055] Figure 9 A transfer example diagram of one embodiment of optoelectronics provided in the present application;

[0056] Figure 10 An embodiment procedure flow chart of powering an imaging device provided in the present application;

[0057] Figure 11 An embodiment procedure flow chart of powering an imaging device provided in the present application;

[0058] Figure 12 An embodiment procedure flow chart of powering an imaging device provided in the present application;

[0059] Figure 13 An embodiment structure schematic diagram of a logic control circuit provided in the present application. DETAILED DESCRIPTION

[0060] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0061] The term "and / or" appearing in the present application can be a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that there are three cases of A alone, A and B together, and B alone. In addition, the character " / " in the present application generally represents that the front and rear associated objects are in an "or" relationship.

[0062] The terms "first", "second", and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or modules does not necessarily limit to those steps or modules clearly listed, but can include other steps or modules not clearly listed or inherent to these processes, methods, products or devices.

[0063] The present application provides an imaging device. In order to better understand the imaging device provided in the present application, the structure of an electronic device containing the imaging device will be exemplarily described as follows:

[0064] AsFigure 2 As shown, the electronic device 20 can be any electronic device equipped with a camera, including but not limited to a smartphone, a mobile computer, a tablet computer, a personal digital assistant (PDA), and the like. As shown, the electronic device 20 includes, but is not limited to, an image sensor 200, a processor 210, a display 220, a communication unit 260, a storage unit 270, a radio frequency circuit 240, a power supply 250, and the like. Figure 2 As shown, the electronic device 20 includes, but is not limited to, an image sensor 200, a processor 210, a display 220, a communication unit 260, a storage unit 270, a radio frequency circuit 240, a power supply 250, and the like.

[0065] Optionally, the processor 210 can be one or more of a central processing unit (CPU), an image signal processor (ISP), a graphics processing unit (GPU), and a digital signal processor (DSP).

[0066] The image sensor 200 can include a pixel array 201 and a logic control circuit 202. Specifically, the pixel array 201 can be composed of individual imaging devices, each of which can correspond to one or more pixels in an image displayed on the display 230, wherein each imaging device in the pixel array 201 can be independent of each other. Specifically, when external light shines on the pixel array 201, the imaging devices located on the pixel array 201 will undergo photoelectric effect, generating corresponding electric charges in each imaging device, and the logic control circuit 202 obtains an image according to the corresponding electric charges generated in each imaging device. More specifically, the logic control circuit 202 is used to control and exchange data with the pixel array 201, such as sending a command to reset each imaging device included in the pixel array 201 before the image sensor is exposed to light, and then the logic control circuit 202 exposes the pixel array 201. After the exposure is completed, the logic control circuit 202 reads and analyzes the amount of charge of each imaging device of the pixel array 201 to obtain an image.

[0067] The logic control circuit 202 can be provided with a processing device for controlling the pixel array to generate charges and generate corresponding images. The processing device can be one or more field-programmable gate arrays (FPGA), application specific integrated circuits (ASIC), system on chips (SoC), central processing units (CPU), network processors (NP), digital signal processors (DSP), micro controller units (MCU), programmable logic devices (PLD), or other integrated chips, or any combination of the above chips or processors, etc.

[0068] Specifically, the imaging device can be a three-tube active pixel (3T-APS), a clamping diode four-tube active pixel (4T-APS), a clamping diode five-tube active pixel (5T-APS), and the present application takes the 4T-APS as an example for illustrative description.

[0069] The image sensor 200 can be controlled by the processor 210, which can output the image sensed and output by the image sensor 200 to the display 230. The display 230 can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), a field emission display (FED), or the like.

[0070] The storage unit 270 is used to store codes and data, and the codes are run by the processor 210. In the present embodiment, the storage unit 270 can include a volatile memory and can also include a non-volatile memory.

[0071] Communication unit 260 is used to establish a communication channel, enabling electronic devices to connect to a remote server through the communication channel and download media data from the remote server. Communication unit 260 may include communication modules such as a wireless local area network (WLAN) module, a Bluetooth module, and a baseband module, as well as radio frequency (RF) circuits corresponding to the communication modules, for performing WLAN communication, Bluetooth communication, infrared communication, and / or cellular communication system communication.

[0072] Radio frequency (RF) circuit 240 is used to receive and transmit signals during information transmission or calls. For example, it receives downlink information from the base station and processes it with processor 210; additionally, it transmits uplink data to the base station. Typically, the RF circuit 240 includes known circuitry for performing these functions, including but not limited to antenna systems, RF transceivers, one or more amplifiers, tuners, one or more oscillators, digital signal processors, codec chipsets, subscriber identification modules (SIM) cards, memory, etc. Furthermore, the RF circuit 240 can also communicate wirelessly with networks and other devices.

[0073] Power supply 250 is used to supply power to various components of an electronic device to maintain its operation. Generally understood, power supply 250 can be a built-in battery, such as a common lithium-ion battery or nickel-metal hydride battery, or an external power source that directly supplies power to the electronic device, such as an alternating current (AC) adapter. In some embodiments of the invention, power supply 250 can also be defined more broadly, for example, including a power management system, a charging system, a power fault detection circuit, a power converter or inverter, a power status indicator (such as a light-emitting diode), and any other components associated with the generation, management, and distribution of electrical energy in the electronic device.

[0074] The following combination Figure 3 The following is an exemplary description of the specific structure of the pixel array provided in this application, wherein, Figure 3 This is a top view of an embodiment of the pixel array provided in this application.

[0075] like Figure 3 As shown, the pixel array 300 includes multiple imaging devices 301, and further includes a word line set 310, a bit line set 320, and a source line set. The source line set includes multiple source lines, and any one of the source lines is perpendicular to the pixel array 300. Figure 3The source lines are not shown. The word line set 310 includes multiple word lines, such as... Figure 3 The word lines 3101, 3102, 3103, and 310y shown are not limited in number (y) of the word lines in the word line set 310 in this embodiment, as long as y is a positive integer greater than 1; the bit line set 320 includes multiple bit lines, such as... Figure 3 The bit lines 3201, 3202, and 320x shown in the figure are not limited in number (x) of the bit line set 320 in this embodiment, as long as x is a positive integer greater than 1. Specifically, any one of the multiple source lines is connected to an imaging device included in the pixel array 300, any one of the word lines included in the word line set 310 is connected to an imaging device included in the pixel array 300, and any one of the bit lines in the bit line set 320 is connected to an imaging device included in the pixel array 300. Thus, any imaging device included in the pixel array 300 is connected to a bit line in the bit line set 302, a word line in the word line set 310, and any one of the source lines in the source line set. Each imaging device is coupled to a logic control circuit through the bit lines, word lines, and source lines. The logic control circuit can then control the imaging device to generate charges through the bit lines, word lines, and source lines, and acquire the corresponding image based on the charges generated by the imaging device.

[0076] The following combination Figure 4 The diagram illustrates the structure of an existing imaging device. Figure 4 Left side Figure 4 a and Figure 4 Right side Figure 4 b represents two structures of the imaging device, such as Figure 4 As shown in Figure a, the vertical depth of the N-buried layer 401 is L1. To improve the full-well capacity of the imaging device, so that even with a reduction in the area of ​​the imaging device, the signal-to-noise ratio and sensitivity of the imaging device can still be improved, then... Figure 4 As shown in b, the longitudinal depth of the N-buried layer 402 is L2, and the length of L2 is greater than the length of L1. Therefore, Figure 4 b relative to Figure 4 Increasing the vertical depth of the N-layer results in Figure 4 The full-well capacity of the imaging device of b is greater than Figure 4 The full-well capacity of the imaging device of a.

[0077] but, Figure 5 The N-buried layer 402 of b has a deeper vertical depth, which makes it more difficult for photoelectrons in the N-buried layer 402 to transfer to the floating diffusion node 404. This results in low efficiency of photoelectron transfer from the N-buried layer 402 to the floating diffusion node 404, which can easily cause image degradation, such as image trailing.

[0078] The structure of the imaging device provided in the present application is exemplarily illustrated below. The imaging device shown in the present application can effectively guarantee the image quality and relieve the image smearing while improving the full well capacity of the imaging device. The imaging device provided in the present application comprises a phototransistor and a reading unit. Specifically, the phototransistor comprises a semiconductor substrate provided with a first well. The surface of the first well is sequentially provided with a first insulating medium layer and a control gate electrode. Specifically, when the incident light irradiates on the semiconductor substrate and the first well, photoelectric effect occurs to generate charges. The first well is used to transfer the generated charges to the reading unit. The reading unit is used to obtain the corresponding image according to the charges from the first well. In the embodiment, when the control gate electrode is applied with a voltage, the first well becomes a capacitor capable of accommodating charges. The greater the voltage applied to the control gate electrode, the greater the capacitance of the first well, so that the number of charges that can be accommodated by the first well is greater. It can be seen that the widening of the capacitance of the first well is realized by applying the voltage to the control gate electrode, so that the full well capacity of the phototransistor can meet the demand of strong light.

[0079] For better understanding, the structure of the imaging device is specifically illustrated below in combination with Figure 6 and Figure 5 , wherein Figure 6 is an example of the cross-sectional structure of an embodiment of the imaging device provided in the present application, Figure 6 is an example of the cross-sectional structure of an embodiment of the imaging device provided in the present application.

[0080] Specifically, the process of the phototransistor 500 generating corresponding charges according to incident light is illustrated below:

[0081] The phototransistor 500 shown in the embodiment comprises a photodiode (PD). The photodiode comprised in the phototransistor 500 is used to generate corresponding charges according to incident light. More specifically, the photodiode for light sensing shown in the embodiment comprises a semiconductor substrate 501 and a first well 502.

[0082] The semiconductor substrate 501 is first specifically illustrated below:

[0083] The semiconductor substrate 501 shown in this embodiment has a first doping type, which is optionally n-type impurity doping, specifically, the material of the semiconductor substrate 501 is pure silicon crystal, and a pentavalent element (such as phosphorus) is doped in the silicon crystal, so that the doped phosphorus replaces the position of silicon atoms in the semiconductor substrate 501, forming an n-type semiconductor substrate, which is an impurity semiconductor with a free electron concentration much higher than a hole concentration, and the more impurities doped in the semiconductor substrate 501, the higher the free electron concentration of the semiconductor substrate 501, and the stronger the conductivity. Alternatively, the first doping type is p-type impurity doping, specifically, the material of the semiconductor substrate 501 is pure silicon crystal, and a trivalent element (such as boron) is doped in the silicon crystal, so that the doped boron replaces the position of silicon atoms in the semiconductor substrate 501, forming a p-type semiconductor substrate, which is an impurity semiconductor with a hole concentration greater than a free electron, and the more impurities doped in the semiconductor substrate 501, the higher the hole concentration of the semiconductor substrate 501, and the stronger the conductivity. This embodiment takes silicon as an example to illustrate the material of the semiconductor substrate 501, which is not limited, and in other examples, the material of the semiconductor substrate 501 can also be germanium, and this embodiment takes the semiconductor substrate 501 as a p-type semiconductor substrate as an example to illustrate.

[0084] The first well 502 is illustrated as follows:

[0085] Alternatively, if the semiconductor substrate 501 is a p-type semiconductor substrate, the charge generated by the photodiode is a photoelectron, and if the semiconductor substrate 501 is an n-type semiconductor substrate, the charge generated by the photodiode is a hole, and this embodiment takes the charge generated by the photodiode as a photoelectron as an example to illustrate:

[0086] As shown in this embodiment, first ion implantation doping can be performed on the first side of the semiconductor substrate 501 to form a first well (WELL) 502, so that Figure 3 For example, taking the left side of the semiconductor substrate 501 as the first side as an example to illustrate, first ion implantation doping can be performed on the left side of the semiconductor substrate 501 to form a first well 502;

[0087] Specifically, if the first ion is a trivalent element (such as boron), the formed first well 502 is a PWELL; if the first ion is a pentavalent element (such as phosphorus), the formed first well 502 is an NWELL. In this embodiment, to form the photodiode capable of photosensitivity, if the first doping type of the semiconductor substrate 501 is a p-type semiconductor substrate, the first ion is a boron ion; if the first doping type of the semiconductor substrate 501 is an n-type semiconductor substrate, the first ion is a phosphorus ion. This embodiment uses a p-type semiconductor substrate as an example for illustrative purposes.

[0088] The following is an exemplary description of the location of the control gate electrode 504 included in the photosensitive transistor 500 shown in this embodiment:

[0089] Specifically, the first well 502, the first insulating dielectric layer 503, and the control gate electrode 504 are sequentially disposed above the semiconductor substrate 501.

[0090] The first insulating dielectric layer 503 shown in this embodiment has an insulating function. This embodiment does not limit the specific material of the first insulating dielectric layer 503, as long as it is a dielectric with a high dielectric constant. For example, the material of the first insulating dielectric layer 503 is one or a combination of silicon oxide, silicon oxynitride (SiON), silicon nitride, and aluminum oxide.

[0091] The control gate electrode 504 shown in this embodiment can be made of polycrystalline silicon, metal, or other conductive materials; the specific material is not limited in this embodiment. The control gate electrode 504 shown in this embodiment is used to connect to a logic control circuit, which applies a voltage to the control gate electrode 504. This embodiment does not limit the specific connection method between the control gate electrode 504 and the logic control circuit; for example, the control gate electrode 504 can be connected via… Figure 6 The word lines or bit lines shown are connected to the logic control circuit. For example, the control gate electrode 504 can be connected to the logic control circuit via a separate wire.

[0092] The function of the control gate electrode 504 provided in this embodiment will be described below:

[0093] Specifically, the logic control circuit can apply a voltage to the control gate electrode 504 during the exposure time period, so that the first well 502 becomes a capacitor for storing photoelectrons. The greater the voltage applied to the control gate electrode 504, the greater the capacitance of the first well 502. That is, the magnitude of the voltage applied to the control gate electrode 504 is positively correlated with the number of photoelectrons that the first well 502 can store.

[0094] The specific structure of the photosensitive transistor 500 of the imaging device is exemplarily illustrated above. The specific structure of the read unit 600 is exemplarily illustrated below Figure 6 It should be noted that the specific structure of the read unit 600 illustrated in the embodiment is an optional example. For example, the read unit illustrated in the embodiment can be a metal-oxide-semiconductor field-effect transistor (MOSFET), a v-groove metal-oxide semiconductor (VMOS), a vertical double-diffused MOSFET (VDMOSFET), or a lateral double-diffused MOSFET (LDMOSFET).

[0095] The specific structure of the read unit 600 illustrated in the embodiment is exemplarily illustrated below Figure 6

[0096] The read unit 600 includes a floating diffusion node 603, a charge transfer transistor 604, a reset transistor 605, a source follower transistor 606, and a row select transistor 607. First, the specific setting position of the floating diffusion node 603 is exemplarily illustrated below:

[0097] Optionally, the floating diffusion node 603 illustrated in the embodiment is arranged in the second well 602 of the semiconductor substrate 501. The second well 602 is exemplarily illustrated below Figure 6

[0098] In the embodiment, the second ion implantation doping can be performed on the second side of the semiconductor substrate 501 to form the second well 602. In the above example, the first side is the left side of the semiconductor substrate 501. Therefore, the second side illustrated in the example is the right side of the semiconductor substrate 501. For example, as illustrated in Figure 6

[0099] ​​​Specifically, the first well 502 and the second well 602 are of different doping types. If the first ion is a trivalent element (e.g., boron) and the first well 502 is a PWELL, the second ion is a pentavalent element (e.g., phosphorus) and the second well 602 is a NWELL. If the first ion is phosphorus and the first well 502 is a NWELL, the second ion is boron and the second well 502 is a PWELL. In this embodiment, the first well 502 is a NWELL, and the second well 602 is a PWELL. The doping type of the first well 502 is different from that of the second well 602, so that the photoelectrons generated by the photodiode cannot enter the second well 602, thereby avoiding the influence of the photoelectrons flowing to the second well 602 on the accuracy of the number of photoelectrons read by the read unit 600.

[0100] Continue to combine Figure 6 The figure shows how the floating diffusion node 603 is arranged in the second well 602;

[0101] The floating diffusion node 603 is formed by ion implantation on the surface of the second well 602, and the doping type of the floating diffusion node 603 is different from that of the second well 602, i.e., the doping type of the floating diffusion node 603 is the first doping type. For specific description of the first doping type, please refer to the above description.

[0102] The following exemplary description is made of the electrical connection relationship between the components included in the read unit 600:

[0103] The drain of the reset transistor 605 and the drain of the source follower transistor 606 are connected to a power supply voltage VDD to be connected to a logic control circuit. The source of the source follower transistor 606 is connected to the drain of a row selection transistor 607, and the source of the row selection transistor 607 is connected to the logic control circuit. The source of the reset transistor 605 and the gate of the source follower transistor 606 are connected to the floating diffusion node 603, and the charge transfer transistor 604 is connected to the logic control circuit.

[0104] The following exemplary description is made of the specific working process of the read unit 600:

[0105] The logic control circuit in this embodiment is pre-set to have an imaging period, which includes a reset time period, an exposure time period, a transfer time period, and a read time period arranged in sequence. The duration of each time period is not limited in this embodiment, and will be described in detail below:

[0106] First, the first step is to reset. The reset transistor 605 is used to reset the photodiode. Specifically, the logic control circuit simultaneously turns on the charge transfer transistor 604 and the reset transistor 605, so that the electrons inside the first well 502 are depleted. At this time, the first well 502 is in an empty well state, while the floating diffusion node 603 is at a high potential. The potential of the floating diffusion node 603 at this time is read out by the source follower transistor 606 and the row select transistor 607 and output to the bus as the first signal of the correlated double sample (CDS).

[0107] The second step is exposure. Specifically, the logic control circuit turns off the charge transfer transistor 604 and the reset transistor 605. The photosensitive transistor 500 generates photoelectrons under the excitation of the incident light. After the exposure period, the photosensitive transistor 500 accumulates enough photoelectrons.

[0108] Specifically, during the exposure period, a depletion layer is formed within the first well 502. When external incident light irradiates the depletion layer, a photoelectric effect occurs, where photons of the incident light are absorbed to generate photoelectrons. This embodiment does not limit the direction of the external incident light irradiating the pixel array; alternatively, such as... Figure 6 As indicated by arrow 608, the light sequentially passes through the control gate electrode 504 and the first insulating dielectric layer 503 before illuminating the photodiode; optionally, it continues as follows... Figure 6 As indicated by arrow 609, the light directly illuminates the photodiode. The number of photoelectrons generated by the photodiode is positively correlated with the intensity of the incident light and / or the duration of illumination.

[0109] The third step is the transfer of photoelectrons. To better understand the specific process of this photoelectron transfer, please refer to the following. Figure 3 As shown, along the lateral direction of the imaging device, a channel region 610 is formed between the first well 502 and the second well 602. Along the direction away from the channel region 610, the surface of the channel region 610 is sequentially provided with the first insulating dielectric layer 503 and the charge transport transistor 604.

[0110] The logic control circuit turns on the charge transfer transistor 604 during the transfer time period and reduces the voltage of the control gate electrode 504 to the reset voltage, so that the photoelectrons in the first well 502 can be completely transferred to the floating diffusion node 603 through the channel region 610.

[0111] As can be seen, in this embodiment, the charge transfer transistor 604 is used to transfer photoelectrons in the first well 502 to the floating diffusion node 603 via the channel region 610. Therefore, the charge transfer transistor 604 needs to be disposed above the channel region 610 in a direction perpendicular to the imaging device. When the charge transfer transistor 604 is turned on by the logic control circuit, the charge transfer transistor 604 can control the photoelectrons to be completely transferred to the floating diffusion node 603 via the channel region 610.

[0112] The fourth step is reading. Specifically, as photoelectrons are transferred to the floating diffusion node 603, the potential of the floating diffusion node 603 decreases. The floating diffusion node 603 is used to convert the transferred photoelectrons into corresponding electrical signals, and then outputs the optical signals to the logic control circuit through the source follower transistor 606 and the row select transistor 607 in sequence. At this time, the optical signal is output to the logic control circuit as the second signal of the CDS. The logic control circuit calculates the difference between the two CDS signals to obtain the corresponding image.

[0113] Optionally, along the lateral direction of the imaging device, the cross-sectional area of ​​the first well 502 is larger than that of the second well 602, thereby effectively increasing the photosensitive area of ​​the imaging device shown in this embodiment. Furthermore, since the cross-sectional area of ​​the first well 502 is larger than that of the second well 602, the photosensitive sensitivity of the imaging device is increased without reducing the full-well capacitance of the imaging device.

[0114] The following combination Figure 6 and Figure 6 The electrical connection relationships of the pixel array shown in this embodiment are explained below:

[0115] All readout units 600 included in the pixel array 300 shown in this embodiment are interconnected by flash NOR, so that the logic control circuit shown in this embodiment can control the mutually perpendicular bit lines and word lines to perform XY addressing readout of all imaging devices included in the pixel array 300.

[0116] The pixel array 300 shown in this embodiment includes all imaging devices with a common source. During the exposure time period, the logic control circuit controls the common source of all imaging devices included in the pixel array 300 to be grounded, which can effectively prevent the common source readout unit 600 from interfering with the photosensitive transistor 500 during the exposure time period.

[0117] The pixel array 300 shown in the embodiment includes all the phototransistors which are connected by flash NAND, so that each phototransistor 500 of the imaging device is independent, and even if one phototransistor 500 fails, it will not affect the normal operation of other phototransistors 500 in the pixel array.

[0118] Optionally, as shown in Figure 7 , the imaging device is provided with an isolation layer 511 on both sides, and the isolation layer 511 is used to isolate the imaging device from the surrounding imaging devices in the pixel array. The isolation layer 511 can be formed by a shallow trench isolation (STI) method, which means that a shallow trench is formed and filled with oxide or nitride to isolate adjacent imaging devices to prevent interference between them. Alternatively, the isolation layer 511 can also be formed according to the local oxidation of silicon (locos) technology, which is not limited in the embodiment.

[0119] The following will be described in combination with Figure 5 , to illustrate how the imaging device provided by the embodiment effectively reduces the influence of dark current:

[0120] First, referring to Figure 6 and Figure 7 , the dark current is explained. In the phototransistor 500, in the absence of light, the current flowing between the first well 502 and the first insulating medium layer 503 is dark current, which will interfere with the process of obtaining the corresponding electrical signal by the read unit 600 according to the photoelectron. To reduce the influence of dark current on the read unit to obtain the electrical signal, as shown in Figure 8 , the embodiment provides an isolation medium layer 701 between the first well 502 and the first insulating medium layer 503.

[0121] The embodiment does not limit the specific material of the isolation medium layer 701, as long as the isolation medium layer 701 can isolate the first well 502 and the first insulating medium layer 503. For example, the isolation medium layer 701 can be a high-density P ion implantation medium, which can effectively isolate the first well 502 and the first insulating medium layer 503, thereby effectively reducing the interference of the dark current between the first well 502 and the first insulating medium layer 503 on the read unit 600.

[0122] The following will be described in combination with Figure 8As shown, another structure of the imaging device is exemplarily illustrated:

[0123] In the phototransistor 500 shown in the present example, the first well 502, the isolation medium layer 701, the first insulating medium layer 503, the floating gate 800, the second insulating medium layer 801 and the control gate electrode 504 are sequentially arranged above the semiconductor substrate 501. For specific description of the first well 502, the isolation medium layer 701, the first insulating medium layer 503 and the control gate electrode 504, please refer to the above-mentioned embodiments, which are not limited in the present embodiment.

[0124] In the present example, the material of the second insulating medium layer 801 can be the same as or different from that of the first insulating medium layer 503, as long as the second insulating medium layer 801 is also a high dielectric constant medium.

[0125] As shown, Figure 8 As shown, the floating gate 800 is located in the accommodating cavity formed between the first insulating medium layer 503 and the second insulating medium layer 801, so that the first insulating medium layer 503 and the second insulating medium layer 801 can effectively isolate the floating gate 800, so that the photoelectrons are confined in the floating gate 800 to realize the storage function of photoelectrons. The floating gate 800 shown in the present embodiment can be a wide-band semiconductor, such as polysilicon, silicon nitride (Si3N4) or other electronic conductors or semiconductors. The floating gate 800 shown in the present embodiment effectively ensures that photoelectrons can enter the floating gate 800 and be stored in the floating gate 800. It can be seen that the structure shown in the present embodiment can effectively increase the number of photoelectrons that can be stored by the phototransistor, and further improve the full-well capacity of the imaging device.

[0126] To realize that the photoelectrons generated by the photodiode can be stored in the floating gate 800, a window 803 is arranged through the first insulating layer 503 in a direction perpendicular to the imaging device. The present embodiment does not limit the specific number of the window 803, i.e., the number of the window 803 can be one or more. The present embodiment takes Figure 9 As shown, one imaging device includes one window 803. Specifically, the window 803 includes opposite first and second openings 8031 and 8032. The first opening 8031 is located at the end face of the first insulating medium layer 503 towards the floating gate 800, and the second opening 8032 is located at the end face of the first insulating medium layer 503 towards the first well 502. The first and second openings 8031 and 8032 are in communication.

[0127] The embodiment is to realize that the photoelectron generated by the photodiode can be stored into the floating gate 800 through the window 803, so that the light sensing transistor realizes the storage of the photoelectron through the first well 502 and the floating gate 800 at the same time. For the purpose of realizing that the photoelectron generated by the photodiode can be transmitted into the floating gate 800, the first well 502 shown in the embodiment can be connected with the floating gate 800 through the window 803, and the specific connection mode is exemplarily described below.

[0128] Mode 1

[0129] The medium of the floating gate 800 extends to the second opening 8032 along the guide of the window 803 through the first opening 8031, and realizes the connection between the floating gate 800 and the first well 502 at the second opening 8032.

[0130] Mode 2

[0131] The medium of the first well 502 extends to the first opening 8031 along the guide of the window 803 through the second opening 8032, and realizes the connection between the floating gate 800 and the first well 502 at the first opening 8031.

[0132] Mode 3

[0133] The medium of the floating gate 800 extends to the inside of the window 803 along the guide of the window 803 through the first opening 8031, and the medium of the first well 502 extends to the inside of the window 803 along the guide of the window 803 through the second opening 8032, so as to connect the floating gate 800 and the first well 502 in the window 803. The mode does not limit the thickness of the floating gate 800 and the thickness of the first well 502 in the window 803, as long as the floating gate 800 and the first well 502 can be connected.

[0134] The image sensor provided in the application can be applied to a terminal, such as a smart phone, and the imaging device can be less than 0.7um. It can be seen that the imaging device shown in the application can meet the full well capacity requirement and also meet the demand for miniaturization of the imaging device.

[0135] The following Figure 8 The process of how the photoelectron in the photodiode is transmitted to the floating gate 800 is described below.

[0136] Specifically, in the exposure time period, a depletion layer 900 is formed in the photodiode. For specific description of the depletion layer 900, please refer to the embodiment described above, which is not repeated in detail in the embodiment.

[0137] When the external incident light is irradiated in the depletion layer 900, the photoelectric effect occurs in the depletion layer 900, that is, the photons of the external incident light are absorbed to generate photoelectrons 901; for specific description of the generated photoelectrons 901, please refer to the above-mentioned embodiments, which are not repeated here.

[0138] During the transfer period, the logic control circuit opens the charge transfer transistor 604 and lowers the voltage of the control gate electrode 504 to the reset voltage, so that the photoelectrons stored in the floating gate 800 can flow to the channel region 610 through the window 803, and the floating gate 800 completely transfers the photoelectrons to the floating diffusion node 603 through the channel region 610; for specific description of the transfer period, please refer to the above-mentioned embodiments, which are not repeated here.

[0139] Optionally, continuing to refer to Figure 10 As shown, along the transverse direction of the imaging device, the first distance L1 between the first well 502 and the second well 602 is less than the second distance L2 between the first insulating medium layer 503 and the second well 602; the structure shown in the embodiment improves the success rate and transfer rate of the photoelectrons stored in the floating gate 800 transferred to the floating diffusion node 603 through the first well 502, effectively avoiding the situation that the photoelectrons stored in the floating gate 800 cannot be successfully transferred to the floating diffusion node 603.

[0140] Based on the above-mentioned description of the structure of the imaging device, the present application further provides a method for powering the imaging device; for specific description of the imaging device, please refer to the above-mentioned embodiments, which are not repeated here.

[0141] The method specifically includes: the logic control circuit adjusts the voltage applied to the control gate electrode of the imaging device according to the charge stored in the imaging device, wherein the size of the voltage applied to the control gate electrode and the number of the charge stored in the imaging device are in a positive correlation.

[0142] Specifically, the amount of charge that can be stored by the phototransistor due to the photoelectric effect is positively correlated with the intensity of the light, that is, the stronger the light in the light environment in which the phototransistor is located, the greater the amount of charge that the phototransistor needs to store, and the weaker the light in the light environment in which the phototransistor is located, the smaller the amount of charge that the phototransistor needs to store. The logic control circuit can adjust the size of the voltage applied to the control gate according to the strength of the light in the light environment in which the phototransistor is located. For example, if the light in the light environment in which the phototransistor is located is stronger, the voltage applied to the control gate is greater, so that the amount of charge that the phototransistor can store is greater. If the light in the light environment in which the phototransistor is located is weaker, the voltage applied to the control gate is smaller, so that the amount of charge that the phototransistor can store is smaller. The method provided in the embodiment can match the amount of charge that the imaging device can store to the needs of different light environments.

[0143] In order to better understand the method provided in the present application, the following will be described in detail in combination with Figure 10 The specific execution process of the method provided in the present application for powering the imaging device is shown in FIG. 10, and the method provided in the embodiment includes the following steps: Figure 11 The specific execution process of the method provided in the present application for powering the imaging device is shown in FIG. 10, and the method provided in the embodiment includes the following steps:

[0144] Step 1001, the logic control circuit acquires a target amount of charge stored by the imaging device in a first exposure time period;

[0145] For a specific description of the logic control circuit, please refer to the above description, which will not be repeated in detail in the present embodiment. The logic control circuit in the present embodiment first determines a first exposure time period. The first exposure time period is a time period in which the imaging device has completed exposure, that is, the phototransistor completes exposure in the first exposure time period and acquires a target amount of charge in the first exposure time period. For a specific description of the target amount of charge acquired by the phototransistor in the exposure time period, please refer to the description of the above embodiment, which will not be repeated in detail in the present embodiment.

[0146] Step 1002, the logic control circuit adjusts the voltage applied to the control gate of the imaging device in a second exposure time period according to the target amount.

[0147] In the present embodiment, the logic control circuit dynamically adjusts the voltage applied to the control gate. Specifically, the logic control circuit adjusts the voltage according to the target amount of charge stored by the phototransistor in the first exposure time period.

[0148] More specifically, the target number of charges that can be stored by the phototransistor due to the photoelectric effect is positively correlated with the intensity of the light, that is, the greater the light intensity in the light environment in which the phototransistor is located during the first exposure time period, the greater the target number of charges stored by the phototransistor, and the weaker the light intensity in the light environment in which the phototransistor is located during the first exposure time period, the smaller the target number of charges stored by the phototransistor. After the logic control circuit determines the light conditions in which the phototransistor is located during the first exposure time period, the voltage applied to the control gate electrode of the imaging device during the second exposure time period can be adjusted accordingly. The first exposure time period is earlier than the second exposure time period, and the second exposure time period is the next time period during which the phototransistor needs to be exposed to light.

[0149] The specific adjustment process can be that, if the logic control circuit determines that the phototransistor is located in a strong light environment during the first exposure time period, the logic control circuit can increase the voltage applied to the control gate electrode, thereby increasing the capacitance of the first well, so that the first well can accommodate more charges during the second exposure time period, thereby enabling the full-well capacity of the phototransistor in the embodiment to meet the requirements of strong light.

[0150] If the logic control circuit determines that the phototransistor is located in a weak light environment during the first exposure time period, the logic control circuit can reduce the voltage applied to the control gate electrode, thereby reducing the capacitance of the first well, so that the ability of the first well to accommodate charges during the second exposure time period matches the current light, effectively saving the power consumption of the voltage applied to the control gate electrode, and avoiding waste of power consumption when the full-well capacity of the phototransistor can meet the current light environment.

[0151] The following will be described in conjunction with Figure 10 to illustrate a specific process of adjusting the size of the voltage applied to the control gate electrode by the logic control circuit:

[0152] Step 1101, the logic control circuit acquires the target number of charges stored by the imaging device during the first exposure time period;

[0153] The specific execution process of step 1101 in the embodiment will be described in detail with reference to Figure 12 The specific execution process of step 1001 is not described in detail in the embodiment.

[0154] Step 1102, the logic control circuit determines whether the target number is greater than or equal to a preset value, if yes, step 1103 is executed, if no, step 1104 is executed.

[0155] Specifically, the logic control circuit in the embodiment can be preset with the preset value. When the target number of charges generated by the imaging device according to photoelectric effect is greater than or equal to the preset value, the logic control circuit determines that the first exposure time period is for exposure in a strong light environment. When the target number of charges generated by the imaging device according to photoelectric effect is less than the preset value, the logic control circuit determines that the first exposure time period is for exposure in a weak light environment.

[0156] Step 1103, the logic control circuit increases the voltage applied to the control gate electrode of the imaging device in the second exposure time period.

[0157] Step 1104, the logic control circuit decreases the voltage applied to the control gate electrode of the imaging device in the second exposure time period.

[0158] The method shown in the embodiment is described below in combination with a specific example:

[0159] Taking the first exposure time period of 10 milliseconds as an example, the incident light in a weak light environment irradiates in the phototransistor 500, and can generate 10,000 charges in the first well 502. The incident light in a strong light environment irradiates in the phototransistor 500, and can generate 100,000 charges in the first well 502. If the capacitance capacity of the first well 502 is fixed, the phototransistor 500 cannot meet the demand of strong light irradiation.

[0160] The logic control circuit in the embodiment determines that the target number (100,000 charges) stored in the phototransistor 500 in the first exposure time period is greater than the preset value (60,000 charges). It can be known that the exposure of the phototransistor 500 is in a strong light environment. The phototransistor 500 is in a strong light environment in the next exposure time period (second exposure time period) of the first exposure time period. The logic control circuit in the embodiment can decrease the voltage applied to the control gate electrode of the imaging device in the second exposure time period, so as to increase the full-well capacity of the first well 502, so that the capacitance value of the photoelectrons that can be accommodated by the first well 502 is also increased, thereby realizing the widening of the charge depletion region of the first well 502, so that the full-well capacity of the phototransistor in the embodiment can meet the demand of strong light.

[0161] The another specific process of adjusting the size of the voltage applied to the control gate electrode by the logic control circuit is described below in combination with the embodiment. Figure 10

[0162] ​In step 1201, the logic control circuit acquires a target quantity of charges stored by the imaging device in a first exposure time period.

[0163] For a specific execution process of step 1201 shown in this embodiment, please see Figure 13 For a specific execution process of step 1001 shown in this embodiment, please see

[0164] In step 1202, the logic control circuit acquires a preset voltage adjustment list.

[0165] The preset voltage adjustment list shown in this embodiment includes a corresponding relationship between different charge quantity ranges and different voltage values. In order to achieve the purpose that the stronger the light irradiating the imaging device is, the greater the capacitance value of the first well is to accommodate more charges, in the preset voltage adjustment list, the greater the range of the quantity of charges is, the greater the corresponding voltage value is.

[0166] In step 1203, the logic control circuit determines a target voltage corresponding to the target quantity according to the preset voltage adjustment list.

[0167] In step 1204, the logic control circuit applies the target voltage to the control gate electrode of the imaging device in a second exposure time period.

[0168] By using the preset voltage adjustment list shown in this embodiment, the dynamic adjustment of the target voltage applied to the control gate electrode is realized, so that the method shown in this embodiment can match more diverse lighting environments, and the matching degree of the imaging device and the lighting environment is improved. After the logic control circuit applies the target voltage to the control gate electrode, the full-well capacity of the imaging device can meet the needs of the current lighting environment.

[0169] The specific structure of the logic control circuit provided in this embodiment will be exemplarily described below ​ in combination with the description of the logic control circuit shown in this embodiment, which is a processing device for executing the corresponding processing and / or steps in any of the above method embodiments. For specific processes, please see the description of the above method embodiments;

[0170] Specifically, the logic control circuit includes:

[0171] The adjustment unit 1301 is configured to adjust a voltage applied to a control gate electrode of the imaging device according to the charges stored by the imaging device, wherein the size of the voltage applied to the control gate electrode and the quantity of the charges stored by the imaging device are in a positive correlation.

[0172] Optionally, the logic control circuit further includes an acquisition unit 1302 configured to acquire a target quantity of charges stored by the imaging device in a first exposure time period.

[0173] The adjusting unit 1301 is further configured to adjust a voltage applied to a control gate electrode of the imaging device in a second exposure time period according to the target number, wherein the voltage applied to the control gate electrode and the target number are in a positive correlation, and the first exposure time period is earlier than the second exposure time period.

[0174] Optionally, the adjusting unit 1301 is specifically configured to increase the voltage applied to the control gate electrode of the imaging device in the second exposure time period if the target number is greater than or equal to a preset value.

[0175] Optionally, the adjusting unit 1301 is specifically configured to decrease the voltage applied to the control gate electrode of the imaging device in the second exposure time period if the target number is less than a preset value.

[0176] Optionally, the adjusting unit 1301 is specifically configured to obtain a preset voltage adjustment list, the preset voltage adjustment list including a corresponding relationship between different charge quantity ranges and different voltage values; determine a target voltage corresponding to the target number according to the preset voltage adjustment list; and apply the target voltage to the control gate electrode of the imaging device in the second exposure time period.

[0177] In a specific application process, the obtaining unit 1302 can be an input / output interface or a transceiver circuit. The input / output interface can include an input interface and an output interface, and the transceiver circuit can include an input interface circuit and an output interface circuit.

[0178] The adjusting unit 1301 can be a processing device, and the functions of the processing device can be partially or entirely implemented by software. Alternatively, the functions of the processing device can be partially or entirely implemented by software. At this time, the processing device can include a memory and a processor, wherein the memory is configured to store a computer program, and the processor is configured to read and execute the computer program stored in the memory to perform the corresponding processing and / or steps in any one of the method embodiments. Alternatively, the processing device can only include the processor. The memory for storing the computer program is located outside the processing device, and the processor is connected with the memory through a circuit / wire to read and execute the computer program stored in the memory. Alternatively, the functions of the processing device can be partially or entirely implemented by hardware, which is not specifically limited in the present embodiment, as long as the processing device can perform the corresponding processing and / or steps in any one of the above method embodiments.

[0179] The embodiment of the present application further provides a storage medium, wherein computer instructions are stored in the storage medium, and when the computer instructions are called by a logic control circuit, the logic control circuit executes corresponding processing and / or steps shown in any method embodiment described above.

[0180] The embodiment of the present application further provides a computer program product, wherein the computer program product comprises computer program codes, and when the computer program codes are called by a logic control circuit, the logic control circuit executes corresponding processing and / or steps shown in any method embodiment described above.

[0181] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0182] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the described device embodiments are merely schematic, and the division of the units is merely a logical function division, and there can be another division manner in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0183] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, that is, can be located in one place, or can be distributed on a plurality of network units. According to actual needs, some or all of the units can be selected to achieve the purpose of the embodiment scheme.

[0184] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be a physically independent unit, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware, or in the form of software functional unit.

[0185] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application, essentially or in other words, the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0186] The above description and the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An imaging device, characterized in that, The semiconductor substrate includes a first well and a second well formed on both sides of the semiconductor substrate by ion implantation doping. The semiconductor substrate and the second well have a first doping type, and the first well has a second doping type. The surface of the first well is sequentially provided with a first insulating dielectric layer and a control gate electrode. The magnitude of the voltage applied to the control gate electrode is positively correlated with the amount of charge stored in the first well.

2. The imaging device according to claim 1, characterized in that, A second insulating dielectric layer is disposed on the surface of the control gate electrode facing the semiconductor substrate, and a receiving cavity is formed between the first insulating dielectric layer and the second insulating dielectric layer. A floating gate for storing charge is disposed in the receiving cavity.

3. The imaging device according to claim 2, characterized in that, A channel region is formed between the first well and the second well. Along the direction away from the channel region, the surface of the channel region is sequentially provided with the first insulating dielectric layer and the charge transfer transistor. The charge transfer transistor is used to enable the charge in the first well to be transferred to the floating diffusion node through the channel region. The floating diffusion node is located in the second well.

4. The imaging device according to claim 3, characterized in that, The first insulating dielectric layer is provided with at least one window, the floating gate and the first well are connected through the window, and the charge transfer transistor is also used to enable the charge in the floating gate to be transferred to the floating diffusion node via the channel region.

5. The imaging device according to claim 4, characterized in that, Along a direction perpendicular to the first insulating dielectric layer of the imaging device, the window includes a first opening and a second opening disposed opposite to each other. The first opening is located on the surface of the first insulating dielectric layer facing the floating grating, and the second opening is located on the surface of the first insulating dielectric layer facing the first well. The first opening and the second opening are connected to each other.

6. The imaging device according to any one of claims 1 to 5, characterized in that, An isolation medium layer, which is a high-density P-ion implantation medium, is disposed between the first well and the first insulating medium layer along a direction perpendicular to the first insulating medium layer of the imaging device.

7. The imaging device according to any one of claims 1 to 5, characterized in that, The cross-sectional area of ​​the first well is larger than that of the second well, and the cross-sectional area is the area parallel to the semiconductor substrate.

8. The imaging device according to any one of claims 1 to 5, characterized in that, There is a first distance between the first well and the second well, and a second distance between the first insulating dielectric layer and the second well, wherein the first distance is less than the second distance.

9. The imaging device according to claim 5, characterized in that, The floating gate extends along the guide of the window through the first opening to the second opening, and the floating gate located at the second opening is connected to the first sink.

10. The imaging device according to claim 5, characterized in that, The first well extends through the second opening along the guide of the window to the first opening, and the floating gate located at the first opening is connected to the first well.

11. The imaging device according to claim 5, characterized in that, The floating grid extends into the window through the first opening, and the first sink extends into the window through the second opening. The floating grid and the first sink located inside the window are connected.

12. The imaging device according to any one of claims 1 to 5, characterized in that, The first doping type is n-type impurity doping, and the second doping type is p-type impurity doping; or, the first doping type is p-type impurity doping, and the second doping type is n-type impurity doping.

13. A method for supplying power to an imaging device, characterized in that, The method is used in a logic control circuit, the logic control circuit being electrically connected to an imaging device, the imaging device being as described in any one of claims 1 to 12, the method comprising: The voltage applied to the control gate electrode of the imaging device is adjusted according to the charge stored in the imaging device, wherein the magnitude of the voltage applied to the control gate electrode is positively correlated with the amount of charge stored in the imaging device.

14. An image sensor, characterized in that, The image sensor includes a pixel array and a logic control circuit. The pixel array includes at least one imaging device, which is electrically connected to the logic control circuit. As described in any one of claims 1 to 12, the logic control circuit is used to adjust the voltage applied to the control gate electrode of the imaging device according to the charge stored in the imaging device, wherein the magnitude of the voltage applied to the control gate electrode is positively correlated with the amount of charge stored in the imaging device.

15. An electronic device, characterized in that, The electronic device includes a processor and an image sensor, as described in claim 14, wherein the processor is configured to acquire the image from the image sensor.

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