Computational circuits and neuromorphic devices

Abstract

An arithmetic circuit includes a resistance change element having three terminals of a first terminal, a second terminal, and a third terminal, capable of changing a resistance value; an input line connected to the first terminal; a capacitor connected to the second terminal, between the second terminal and a reference potential; a first switching element connected to the third terminal; a wiring connected to the third terminal via the first switching element; a second switching element connected to a first end of the wiring; and a third switching element connected to a second end of the wiring.

Description

Technical Field

[0001] This invention relates to computational circuits and neuromorphic devices. Background Technology

[0002] Research and development of neural system models are underway with the aim of improving the electrical performance of neuromorphic devices that perform neural network operations. Examples of such neural system models include spiking neural networks (SNNs).

[0003] As a method for implementing a spiking neural network, a method using a two-terminal resistance-changing element is known (see Patent Document 1). Here, the resistance-changing element is a two-terminal element capable of changing resistance, such as a PCM (Phase Change Memory).

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Publication No. 2018-508922. Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] At present, there is no known method for implementing a pulse neural network using a three-terminal type resistance-changing element.

[0009] Technical means for solving problems

[0010] One aspect of the present invention provides an operational circuit comprising: a resistance changing element having three terminals—a first terminal, a second terminal, and a third terminal—capable of changing the resistance value; an input line connected to the first terminal; a capacitor connected to the second terminal and located between the second terminal and a reference potential; a first switching element connected to the third terminal; a wiring connected to the third terminal via the first switching element; a second switching element connected to a first end of the wiring; and a third switching element connected to a second end of the wiring.

[0011] Invention Effects

[0012] According to the present invention, it is possible to provide an operational circuit and a neuromorphic device that can realize a pulse neural network using a three-terminal type resistance variation element. Attached Figure Description

[0013] Figure 1 This is a diagram showing an example of the smallest unit of the operational circuit in the first embodiment.

[0014] Figure 2 This is a diagram illustrating an example of a neuromorphic device according to the first embodiment.

[0015] Figure 3 This is a diagram showing an example of the waveform of the signal output from the third terminal in an operational circuit.

[0016] Figure 4 This is another example of the waveform of the signal output from the third terminal in an operational circuit.

[0017] Figure 5 This is another example of a waveform representing the signal output from the third terminal in an operational circuit.

[0018] Figure 6 This is a time graph that shows the voltage change over time of multiple units connected to an operational circuit via a wiring connection.

[0019] Figure 7 This is a time graph that shows the voltage change over time of multiple units connected to an operational circuit via a wiring connection.

[0020] Figure 8 This is a diagram illustrating an example of the resistance-changing element in the first embodiment.

[0021] Figure 9 This is a diagram showing an example of an operational circuit 1 constructed on a substrate. Detailed Implementation

[0022] <First Implementation>

[0023] Hereinafter, this embodiment will be described in detail with appropriate reference to the accompanying drawings. In the following description, the drawings used are sometimes enlarged to show characteristic parts for ease of understanding and convenience, and the size ratios of the constituent elements may sometimes differ from the actual dimensions. The materials, dimensions, etc., illustrated in the following description are examples, and the present invention is not limited thereto; appropriate modifications can be made to achieve the effects of the present invention.

[0024] Operational Circuits

[0025] Figure 1 This is a diagram showing an example of the smallest unit of the operational circuit in the first embodiment.

[0026] The operational circuit 1 outputs a spike signal from a pulse neural network. The operational circuit 1 includes, for example, a resistance changing element 11, an input line w1, a wiring w2, a first switching element S1, a second switching element S2, a third switching element S3, a fourth switching element S4, and a capacitor C.

[0027] The resistance changing element 11 is a component capable of changing resistance. Furthermore, the resistance changing element 11 has three terminals: a first terminal TM1, a second terminal TM2, and a third terminal TM3. That is, the resistance changing element 11 is a three-terminal type component. The resistance changing element 11 is, for example, a domain wall moving element. The domain wall moving element is a domain wall moving type magnetoresistive effect element, which will be described in detail later. The resistance changing element is not limited to a domain wall moving element; it can also be other three-terminal type resistance changing elements.

[0028] Input line w1 is the transmission path for transmitting input signals. Wiring w2 is the transmission path for transmitting charging and output signals. The transmission path can be a metal wiring formed on a semiconductor integrated circuit, a conductor printed on a substrate, or a copper wire formed as a line. Input line w1 is connected to the first terminal TM1 of the resistance changing element 11. Wiring w2 is connected to the third terminal TM3 via the first switching element S1.

[0029] The first switching element S1, the second switching element S2, the third switching element S3, and the fourth switching element S4 are switching elements that control the flow of current. When a switching element is in the ON state, it is energized and electrically connected. When a switching element is in the OFF state, it is de-energized and electrically disconnected. Examples of switching elements include field-effect transistors, bidirectional transistors, and bidirectional threshold switches. The following explanation uses a field-effect transistor as an example.

[0030] The first switching element S1 is connected between the third terminal TM3 and the wiring w2. For example, the source of the first switching element S1 is connected to the third terminal TM3, the drain of the first switching element S1 is connected to the wiring w2, and the gate of the first switching element S1 is connected to the control unit 20 described later.

[0031] The second switching element S2 is connected to the first end of the wiring w2. For example, the source of the second switching element S2 is connected to the charging circuit 13 described later, the drain of the second switching element S2 is connected to the wiring w2, and the gate of the second switching element S2 is connected to the control unit 20 described later.

[0032] The third switching element S3 is connected to the second end of the wiring w2. For example, the source of the third switching element S3 is connected to the wiring w2, the drain of the third switching element S3 is connected to the output circuit 14 described later, and the gate of the third switching element S3 is connected to the control unit 20 described later.

[0033] The fourth switching element S4 is connected between the input line w1 and the first terminal TM1. For example, the source of the fourth switching element S4 is connected to the input line w1, the drain of the fourth switching element S4 is connected to the first terminal TM1, and the gate of the fourth switching element S4 is connected to the control unit 20 described later. Alternatively, the fourth switching element S4 may be omitted. Alternatively, a resistor may be provided to replace the fourth switching element S4.

[0034] Capacitor C is positioned between the second terminal TM2 and the reference potential. One plate of capacitor C is connected to the second terminal TM2, and the other plate is grounded to the reference potential. The reference potential is, for example, ground potential.

[0035] <Neuromorphic Devices>

[0036] Figure 2 This is a diagram illustrating an example of the neuromorphic device 100 according to the first embodiment. Figure 2 The neuromorphic device 100 shown includes Figure 1 The smallest unit of the operational circuit 1 shown.

[0037] Figure 2 The neuromorphic device 100 shown includes an arithmetic circuit 10, an input circuit 12, a charging circuit 13, and an output circuit 14.

[0038] The operational circuit 10 of the neuromorphic device 100 includes multiple resistance changing elements 11, multiple input lines w1, multiple wiring w2, multiple first switching elements S1, multiple second switching elements S2, multiple third switching elements S3, multiple fourth switching elements S4, multiple capacitors C, and a control unit 20.

[0039] The operational circuit 10 has multiple units U, each consisting of an input line w1, a resistance changing element 11, a capacitor C, a first switching element S1, and a fourth switching element S4. Multiple units U are connected to a single wiring line w2. In the operational circuit 10, the multiple resistance changing elements 11 are arranged in a matrix. Multiple resistance changing elements 11 are connected to one input line w1, and multiple resistance changing elements 11 are also connected to one wiring line w2.

[0040] The control unit 20 is connected to, for example, a first switching element S1, a second switching element S2, a third switching element S3, and a fourth switching element S4. The control unit 20 is connected to, for example, the gates of the first switching element S1, the second switching element S2, the third switching element S3, and the fourth switching element S4. The control unit 20 controls the switching on and off of the first switching element S1, the second switching element S2, the third switching element S3, and the fourth switching element S4. The control unit 20 may be, for example, a control circuit unit or a microcomputer provided on a semiconductor integrated circuit. The control unit 20 may also be other circuits or other devices capable of controlling the arithmetic circuit 10.

[0041] Input circuit 12 is a circuit that generates an input signal that is input to input line w1. Input circuit 12 is, for example, a neuron in the pre-layer of a neuromorphic device.

[0042] The charging circuit 13 is a circuit used to store charge in the capacitor C, which generates a pulse current that changes the resistance of the resistance-changing element 11. The charging circuit 13 is, for example, a power source. The charging circuit 13 may have a resistor between the power source and the second switching element S2. The charging speed in the capacitor C can be controlled by the resistor. The resistor may also be disposed between the second switching element S2 and the first switching element S1.

[0043] Output circuit 14 is a circuit that outputs the charge stored in capacitor C. Output circuit 14 is, for example, a detector. Output circuit 14 detects spike signals.

[0044] Actions of neuromorphic devices

[0045] Next, regarding Figure 2 The operation of the neuromorphic device 100 shown will be explained. First, the output operation of a spike signal from a unit U will be explained.

[0046] First, the first switching element S1 is turned off, the second switching element S2 is turned off, and the fourth switching element S4 is turned on. The third switching element S3 can be either turned on or off. In this state, an input signal is input from the input circuit 12. The input signal reaches the capacitor C via the fourth switching element S4 and the resistance changing element 11, and the capacitor C is charged. The amount of charge stored in the capacitor C is determined by the resistance value of the resistance changing element 11 and the magnitude of the input signal. For example, if the input signal is a signal representing one of the multiple input parameters of a pulse neural network, the capacitor C stores the charge required to generate a spike signal corresponding to that input parameter and the resistance value of the resistance changing element 11.

[0047] After capacitor C has accumulated a sufficient amount of charge, if the fourth switching element S4 is turned off, capacitor C will maintain the state of having accumulated a sufficient amount of charge.

[0048] Next, the first switching element S1 is turned on. While the third switching element S3 is turned off, it is also turned on simultaneously. If the first switching element S1 is turned on, the charge stored in capacitor C flows in the output circuit 14. A signal corresponding to the discharge current is output from capacitor C. In the pulse neural network, this signal is processed as the aforementioned spike signal.

[0049] Here, Figure 3 This is a diagram showing an example of the waveform of a spike signal output from a unit U in a neuromorphic device 100. Figure 3In the graph shown, the vertical axis represents voltage, and the horizontal axis represents the elapsed time from the moment indicated by the origin. Figure 3 The spike signal is the spike signal when the resistance of the resistance changing element 11 is 0.5MΩ, and the input signal is a pulse signal with a pulse width of 10ns and a pulse height of 0.5V.

[0050] in addition, Figure 4 This is a diagram showing an example of the waveform of a spike signal output from a unit U in a neuromorphic device 100. Figure 4 The graph shown has voltage on the vertical axis and time elapsed since the moment indicated by the origin on the horizontal axis. Figure 4 The spike signal is the spike signal when the resistance of the resistance changing element 11 is 0.5MΩ and the input signal is a pulse signal with a pulse width of 30ns and a wave height of 0.5V.

[0051] in addition, Figure 5 This is a diagram showing an example of the waveform of a spike signal output from a unit U in a neuromorphic device 100. Figure 5 In the graph shown, the vertical axis represents voltage, and the horizontal axis represents the elapsed time from the moment indicated by the origin. Figure 5 The spike signal is the spike signal when the resistance of the resistance changing element 11 is 1MΩ, and the input signal is a pulse signal with a pulse width of 30ns and a wave height of 0.5V.

[0052] like Figures 3-5 As shown, the neuromorphic device 100 can output a signal corresponding to the discharge current of capacitor C as a spike signal of a spiking neural network. Additionally, as... Figures 3-5 As shown, the output spike signal varies according to the resistance value of the resistance changing element 11, the pulse width of the input signal, and the peak height. The spike signal output from the third terminal TM3 is determined by the resistance value of the resistance changing element 11 and the input signal.

[0053] So far, the output operation of the spike signal from one unit U has been explained. Next, the writing operation of changing the resistance value of the resistance changing element 11, which is one of the parameters used to change the spike signal, will be explained. The resistance value of the resistance changing element 11 changes, for example, according to the pulse current flowing between the second terminal TM2 and the third terminal TM3. Specifically, the resistance value of the resistance changing element 11 refers to the resistance value between the first terminal TM1 and the second terminal TM2 that affects the spike signal.

[0054] First, connect. Figure 2 The first switching element S1 shown connects the second switching element S2, turns off the third switching element S3, and turns off the fourth switching element S4. In this case, the charging circuit 13 is connected to the capacitor C, and the capacitor C is charged.

[0055] In the absence of a fourth switching element 4 in the operational circuit 10, for example, the resistance between the first terminal TM1 and the second terminal TM2 of the resistance changing element 11 is greater than the resistance between the second terminal TM2 and the third terminal TM3. By increasing the resistance between the first terminal TM1 and the second terminal TM2, the charge charged to the capacitor C is prevented from discharging to the input circuit 12.

[0056] Furthermore, if a resistor is provided between the first switching element S1 and the second switching element S2, or between the second switching element S2 and the charging circuit 13, the charging of capacitor C is slowed down. If the charging speed of capacitor C is accelerated, a pulse current flows between the second terminal TM2 and the third terminal TM3. The pulse current flowing between the second terminal TM2 and the third terminal TM3 causes a change in the resistance value of the resistance changing element 11. The resistance value of the resistance changing element 11 is controlled by the discharge from capacitor C, which will be described later. If a pulse current is generated when charging capacitor C, the resistance value of the resistance changing element 11 will change unexpectedly. By slowing down the charging of capacitor C, the generation of a pulse current during the charging of capacitor C is avoided. In addition, a power supply capable of controlling the charging speed can also be used in the charging circuit 13.

[0057] After capacitor C has accumulated sufficient charge, if the first switching element S1 is turned off, capacitor C will maintain the state of accumulating charge. At this time, the second switching element S2 can also be turned off.

[0058] Next, the first switching element S1 and the third switching element S3 are turned on. If the first switching element S1 is turned on, the charge stored in the capacitor C flows in the output circuit 14. At this time, a pulse current flows between the second terminal TM2 and the third terminal TM3. If the pulse current flows between the second terminal TM2 and the third terminal TM3, the resistance value of the resistance changing element 11 changes.

[0059] As described above, the neuromorphic device 100 can generate spike signals, enabling the implementation of a pulsed neural network using a three-terminal resistance-changing element. Furthermore, by discharging from the capacitor C, the resistance value of the resistance-changing element 11 can be changed, altering the waveform of the output spike signal. To prevent unexpected fluctuations in the resistance-changing element 11 during spike signal generation, it is desirable that the resistance between the first terminal TM1 and the second terminal TM2 is greater than the resistance between the second terminal TM2 and the third terminal TM3. As a result, a difference can be created between the current value of the spike signal and the magnitude of the discharge pulse during the write operation, preventing erroneous write operations. Preferably, the resistance between the first terminal TM1 and the second terminal TM2 is at least 10 times greater than the resistance between the second terminal TM2 and the third terminal TM3, more preferably at least 100 times greater.

[0060] As described above, a spike signal can be generated from a single unit U. Additionally, as... Figure 2 As shown, when multiple units U are connected to the wiring w2, the control unit 20 controls the operation of the first switching element S1 of each unit U, thereby generating various spike signals. The operation of the first switching element S1 of each unit U can be synchronized or asynchronous through the control unit 20. Hereinafter, the three units connected to the same wiring w2 will be referred to as the first unit, the second unit, and the third unit.

[0061] Figure 6 This is a time diagram showing the synchronization of the operation of the first switching element S1 of the multiple units U connected to wiring w2. The time diagram shows the voltage changes of the first terminal TM1 and the third terminal TM3 over time. Figure 6 The area R1 shown is the time map of the first unit. Figure 6 The region R2 shown is the time map of the second unit. Figure 6 The area R3 shown is the time map of the third unit. Figure 6 The area R4 shown is a time graph representing the change of the output voltage from the output circuit 14 over time.

[0062] Time diagrams IS1, IS2, and IS3 respectively show examples of the voltage change of the first terminal TM1 of each unit over time. Additionally, time diagrams OS1, OS2, and OS3 respectively show examples of the voltage change of the third terminal TM3 of each unit over time. Furthermore, time diagram OS4 shows an example of the output voltage from the output circuit 14 changing over time.

[0063] Figure 6 The periods TS11 and TS12 shown represent the periods during which an input signal is input to the first terminal TM1 of the first unit. For example... Figure 6 As shown, period TS12 is a period that follows period TS11.

[0064] in addition, Figure 6 The periods TS21 and TS22 shown represent the periods during which an input signal is input to the first terminal TM1 of the second unit. For example... Figure 6 As shown, period TS22 is a period that follows period TS21.

[0065] Figure 6 The periods TS31 and TS32 shown indicate the periods during which an input signal is input to the first terminal TM1 of the third unit. For example... Figure 6 As shown, period TS32 is a period that follows period TS31.

[0066] Figure 6Each of the five times T1 to T5 shown represents the time when the state of the first switching element S1 of each of the first to third units changes from the off state to the on state. During each of these five times, the control unit 20 sets the first switching element S1 of each of the first to third units to the off state for a predetermined period of time. After the predetermined period has elapsed, the control unit 20 sets the state of the first switching element S1 to the on state. Thus, during this period, a spike signal corresponding to the discharge current of the capacitor C is output from each of the first to third units. By making the resistance value of wiring w2 approximately 2 to 3 digits smaller than the resistance value of the resistance changing element 11, a spike signal can be output even when the first switching element S1 is on while the input signal is input to the first terminal TM1.

[0067] like Figure 6 As shown, the spike signals output from each of the first to third units are superimposed and output. The spike signal generated by OS4 in the timing diagram is a signal superimposed with the spike signals output from each of the first to third units.

[0068] That is, the neuromorphic device 100 can superimpose the spike signals output from the units U corresponding to each neuron in the spiking neural network, and process the superimposed signal. Here, Figure 6 The "FireThreshold" shown in the timing diagram OS4 represents an example of a threshold for this signal. For example, the neuromorphic device 100 can determine whether the magnitude of the signal exceeds the threshold using a comparator or the like connected to the output of the target device. Furthermore, the neuromorphic device 100 can perform processing corresponding to the determination result.

[0069] Figure 7 This is a time diagram showing the asynchronous operation of the first switching element S1 of multiple units U connected to wiring w2. Figure 7 The area R5 shown is the time map of the first unit. Figure 7 The area R6 shown is the time map of the second unit. Figure 7 The area R7 shown is the time map of the third unit. Figure 7 The area R8 shown is a time graph representing the change of the output voltage to the output circuit 14 over time.

[0070] Time diagrams IS1, IS2, and IS3 respectively show examples of the voltage change of the first terminal TM1 of each unit over time. Additionally, time diagrams OS5, OS6, and OS7 respectively show examples of the voltage change of the third terminal TM3 of each unit over time. Furthermore, time diagram OS8 shows an example of the output voltage output to the output circuit 14 over time.

[0071] Here, in the timing diagram OS5, spike signals are output from the first unit at the end of period TS11 and the end of period TS12, respectively. That is, this means that the control unit 20 controls the first switching element S1 of the first unit synchronously with the time when the end input signal is input to the first terminal TM1 of the first unit. Specifically, this means that the control unit 20 changes the state of the first switching element S1 from a first state to a second state at that time.

[0072] Similarly, in timing diagram OS6, spike signals are output from the second unit at the end of period TS21 and the end of period TS22, respectively. Likewise, in timing diagram OS7, spike signals are output from the third unit at the end of period TS31 and the end of period TS32, respectively.

[0073] Thus, the control unit 20 can also be configured to control the first switching element S1 of the arithmetic circuit 10 synchronously with the time when the input signal to the first terminal TM1 of the arithmetic circuit 10 ends, for each of the first to third units. In other words, the control unit 20 can also be configured to control the first switching elements S1 of each of the first to third units asynchronously. In this case, for example, the neuromorphic device 100 can superimpose a spike signal output from a unit U with high sensitivity to a certain information (or a certain input signal) in the spiking neural network and output it from the output end of the object transmission path. It can also be considered that this superposition of spike signals is closer to the processing performed in the human brain. Therefore, the neuromorphic device 100 can realize a spiking neural network that mimics the processing performed in the human brain to a higher level.

[0074] <Specific examples of resistance-changing elements>

[0075] Furthermore, a domain wall-moving type magnetoresistive effect element, which is one example of a resistance-changing element 11, will be described. The magnetoresistive effect element utilizes the giant magnetoresistive effect, tunnel magnetoresistive effect, etc., as a magnetoresistive effect. The resistance value of the magnetoresistive effect element varies according to the magnetization relationship of the two ferromagnetic layers possessed by the magnetoresistive effect element. For example, the magnetoresistive effect element can change the magnetization relationship of the two ferromagnetic layers according to the spin polarization current. Moreover, the domain wall-moving type magnetoresistive effect element is a magnetoresistive effect element that can change the magnetization relationship of the two ferromagnetic layers by moving the domain wall within one of the two ferromagnetic layers using a spin polarization current.

[0076] Figure 8This is a diagram showing an example of the structure of the resistance changing element 11. In addition to the three terminals TM1, TM2, and TM3, the resistance changing element 11 also includes a resistance changing part B1, a magnetization fixing part B11, and a magnetization fixing part B12.

[0077] The resistance changing section B1 has two ferromagnetic layers. The resistance value of the resistance changing section B1 varies according to the magnetization relationship between these two ferromagnetic layers. Specifically, the resistance changing section B1 includes a ferromagnetic layer L1, a non-magnetic layer L2, and a magnetic recording layer L3. Hereinafter, as an example, the magnetic recording layer L3 will be described in the case where it is a plate-shaped cuboid. However, the shape of the magnetic recording layer L3 can also be other than a plate-shaped cuboid.

[0078] Figure 8 The three-dimensional coordinate system BC shown is a right-handed three-dimensional orthogonal coordinate system in which the long side of the magnetic recording layer L3 is aligned with the X-axis and the short side of the magnetic recording layer L3 is aligned with the Y-axis. Figure 8 The resistance changing element 11 shown is the resistance changing element 11 viewed in the negative direction of the Y-axis in the three-dimensional coordinate system BC. Hereinafter, for ease of explanation, the positive direction of the Z-axis in the three-dimensional coordinate system BC will be referred to as the up or upper direction, and the negative direction of the Z-axis will be referred to as the down or lower direction.

[0079] In the resistance variation section B1, the ferromagnetic layer L1, the nonmagnetic layer L2, and the magnetic recording layer L3 are as follows: Figure 8 As shown, the layers are stacked from bottom to top in the order of magnetic recording layer L3, non-magnetic layer L2, and ferromagnetic layer L1.

[0080] The ferromagnetic layer L1 contains a ferromagnetic material. The ferromagnetic layer L1 is one of the two ferromagnetic layers present in the resistance-changing section B1. In the ferromagnetic layer L1, the direction of magnetization is fixed. Figure 8 The direction of the arrow M1 shown represents an example of the direction of magnetization fixed in the ferromagnetic layer L1. Figure 8 In the example shown, direction M1 is aligned with the positive direction of the X-axis of the three-dimensional coordinate system BC.

[0081] exist Figure 8 In the example shown, the aforementioned first terminal TM1 is disposed on the upper part of the ferromagnetic layer L1. The first terminal TM1 is, for example, an electrode.

[0082] The ferromagnetic material constituting the ferromagnetic layer L1 may be, for example, a metal selected from Cr, Mn, Co, Fe, and Ni, an alloy containing one or more of these metals, or an alloy containing these metals and at least one of the elements B, C, and N. Examples of ferromagnetic layers L1 include Co-Fe, Co-Fe-B, and Ni-Fe.

[0083] The ferromagnetic layer L1 can also contain Hassler alloys. Hassler alloys are half-metals with high spin polarization. They are intermetallic compounds with an XYZ or X2YZ chemical composition. X is a transition metal or noble metal element from the Co, Fe, Ni, or Cu group of the periodic table. Y is a transition metal from the Mn, V, Cr, or Ti group, or an element of X. Z is a typical element from Group III to Group V. Examples of Hassler alloys include Co2FeSi, Co2FeGe, Co2FeGa, Co2MnSi, and Co2Mn. 1-a Fe a Al b Si 1-b Co2FeGe 1-c Ga c .

[0084] When the magnetization of the ferromagnetic layer L1 is oriented along the XY plane (making the ferromagnetic layer L1 an in-plane magnetized film), for example, the ferromagnetic layer L1 is NiFe. This XY plane is a plane parallel to both the X-axis and Y-axis in the three-dimensional coordinate system BC. On the other hand, when the magnetization of the ferromagnetic layer L1 is oriented along the Z-axis (making the ferromagnetic layer L1 a perpendicularly magnetized film), for example, the ferromagnetic layer L1 is a Co / Ni laminate or a Co / Pt laminate. This Z-axis is the Z-axis in the three-dimensional coordinate system BC.

[0085] The ferromagnetic layer L1 may also have a sandblasted layer composed of an antiferromagnetic layer AF1 on the side opposite to the non-magnetic layer L2. IrMn, PtMn, etc. can be used as the material for the antiferromagnetic layer AF1.

[0086] The structure of the ferromagnetic layer L1 can also be a composite structure. In a composite structure, a non-magnetic layer and a ferromagnetic layer are stacked on the surface of the ferromagnetic layer L1 opposite to the non-magnetic layer L2. The magnetization of the ferromagnetic layer L1 is strongly maintained by antiferromagnetic coupling of the magnetization of the two ferromagnetic layers forming the composite structure.

[0087] The non-magnetic layer L2 can be made of known materials. For example, when the non-magnetic layer L2 is made of an insulator (i.e., when the non-magnetic layer L2 is a tunnel barrier layer), materials such as Al2O3, SiO2, MgO, and MgAl2O4 can be used. The non-magnetic layer L2 can also be made of materials in which a portion of Al, Si, and Mg are replaced with Zn, Be, etc. When the non-magnetic layer L2 is made of a metal, materials such as Cu, Au, and Ag can be used. Furthermore, when the non-magnetic layer L2 is made of a semiconductor, materials such as Si, Ge, CuInSe2, CuGaSe2, and Cu(In,Ga)Se2 can be used.

[0088] The magnetic recording layer L3 contains ferromagnetic material. Magnetic recording layer L3 is the other of the two ferromagnetic layers present in the resistance change section B1. Magnetic domain walls DW are present within magnetic recording layer L3. Magnetic domain walls DW are the boundaries between magnetic regions MR1 ​​and MR2, whose magnetization directions are opposite to each other within magnetic recording layer L3. That is, magnetic recording layer L3 contains two magnetic regions, MR1 and MR2. Figure 8 The direction of the arrow M2 shown represents an example of the magnetization direction of the magnetic region MR1. Figure 8 In the example shown, direction M2 is aligned with the positive direction of the X-axis in the three-dimensional coordinate system BC. Figure 8 The direction of the arrow M3 shown represents an example of the magnetization direction of the magnetic region MR2. Figure 8 In the example shown, direction M3 is aligned with the negative direction of the X-axis in the three-dimensional coordinate system BC.

[0089] A magnetization fixing part B11 is provided at the lower part of the end of the magnetic region MR1 side of the end of the magnetic recording layer L3. The second terminal TM2 described above is provided at the lower part of the magnetization fixing part B11. The second terminal TM2 is, for example, an electrode or a circuit wiring.

[0090] The ferromagnetic material constituting the magnetic recording layer L3 can be the same material as that constituting the ferromagnetic layer L1. Alternatively, the ferromagnetic material constituting the magnetic recording layer L3 can be a different ferromagnetic material from those constituting the ferromagnetic layer L1. The magnetic recording layer L3 preferably has at least one element selected from, for example, Co, Ni, Pt, Pd, Gd, Tb, Mn, Ge, and Ga. Furthermore, when perpendicular magnetization is used as the magnetic recording layer L3, examples of ferromagnetic materials constituting the magnetic recording layer L3 include multilayer films of Co and Ni, multilayer films of Co and Pt, multilayer films of Co and Pd, MnGa-type materials, GdCo-type materials, and TbCo-type materials. Subferromagnetic materials such as MnGa-type materials, GdCo-type materials, and TbCo-type materials have low saturation magnetization, which can reduce the threshold current required for the moving domain wall DW. Furthermore, Co and Ni laminates, Co and Pt laminates, and Co and Pd laminates exhibit high coercivity, which can improve device stability. Additionally, they can suppress the migration velocity of magnetic domain walls (DWs).

[0091] The magnetization fixing part B11 contains a ferromagnetic material. In the magnetization fixing part B11, the direction of magnetization is fixed. Figure 8 The direction of the arrow M4 shown indicates an example of the direction of magnetization (or the direction of the spin) fixed in the magnetization fixing part B11. Figure 8 In the example shown, direction M4 is aligned with the positive direction of the X-axis in the three-dimensional coordinate system BC.

[0092] The material constituting the magnetization fixing part B11 can be any material that can form the ferromagnetic layer L1. The magnetization fixing part B11 can also be a composite structure.

[0093] A magnetization fixing part B12 is provided at the lower part of the end on the magnetic region MR2 side of the end of the magnetic recording layer L3. The aforementioned third terminal TM3 is provided at the lower part of the magnetization fixing part B12. The second terminal TM2 is, for example, an electrode or a circuit wiring.

[0094] The magnetization fixing part B12 contains a ferromagnetic material. In the magnetization fixing part B12, the direction of magnetization is fixed. Figure 8 The direction of the arrow M5 shown indicates an example of the magnetization direction fixed in the magnetization fixing part B12. Figure 8 In the example shown, direction M5 is aligned with the negative direction of the X-axis in the three-dimensional coordinate system BC.

[0095] The material constituting the magnetization fixing part B12 can be any material that can form the ferromagnetic layer L1, or any material. The magnetization fixing part B12 can also be a composite structure.

[0096] When current flows from the second terminal TM2 sequentially through the magnetization fixing part B11 and the magnetic recording layer L3 to the third terminal TM3, electrons that are spin-polarized in the same direction as the magnetization direction M5 of the magnetization fixing part B12 flow from the third terminal TM3 toward the second terminal TM2 in the magnetic recording layer L3. Specifically, when a voltage is applied between the second terminal TM2 and the third terminal TM3 such that the potential of the third terminal TM3 is lower than the potential of the second terminal TM2, these electrons flow from the third terminal TM3 side toward the second terminal TM2 side in the magnetic recording layer L3.

[0097] Conversely, when current flows from the third terminal TM3 sequentially through the magnetization fixing part B12 and the magnetic recording layer L3 to the second terminal TM2, electrons that are spin-polarized in the same direction as the magnetization direction M4 of the magnetization fixing part B11 flow from the second terminal TM2 towards the third terminal TM3 in the magnetic recording layer L3. Specifically, when a voltage is applied between the second terminal TM2 and the third terminal TM3 such that the potential of the third terminal TM3 is higher than the potential of the second terminal TM2, these electrons flow from the second terminal TM2 side towards the third terminal TM3 side in the magnetic recording layer L3.

[0098] When the position of the domain wall DW within the magnetic recording layer L3 shifts, the ratio of the volume occupied by magnetic region MR1 to the volume occupied by magnetic region MR2 changes within the magnetic recording layer L3. Figure 8In the example shown, the magnetization direction M1 of the ferromagnetic layer L1 is the same as the magnetization direction M2 of the magnetic region MR1, and opposite to the magnetization direction M3 of the magnetic region MR2.

[0099] When the resistance change section B1 is observed in the negative Z-axis direction of the three-dimensional coordinate system BC, the overlapping area of ​​the ferromagnetic layer L1 and the magnetic region MR1 widens as the domain wall DW moves in the positive X-axis direction of the three-dimensional coordinate system BC. As a result, the resistance value of the resistance change element 11 decreases due to the magnetoresistance effect. On the other hand, when the domain wall DW moves in the negative X-axis direction, this area narrows. As a result, the resistance value of the resistance change element 11 increases due to the magnetoresistance effect.

[0100] Here, as described above, in the resistance change section B1, the magnetic domain wall DW moves due to the pulse current flowing between the second terminal TM2 and the third terminal TM3.

[0101] That is, when current flows from the third terminal TM3 to the second terminal TM2, the magnetic region MR1 expands in the direction of the magnetic region MR2. As a result, the domain wall DW moves in the direction of the magnetic region MR2. On the other hand, in this example, when current flows from the second terminal TM2 to the third terminal TM3, the magnetic region MR2 expands in the direction of the magnetic region MR1. As a result, the domain wall DW moves in the direction of the magnetic region MR1.

[0102] Thus, in the resistance changing section B1, the position of the domain wall DW moves according to the direction and intensity of the current flowing between the second terminal TM2 and the third terminal TM3 (i.e., the direction of the current flowing in the magnetic recording layer L3), and the resistance value of the resistance changing element 11 changes.

[0103] <Methods for constructing operational circuits>

[0104] Figure 9 This diagram shows an example of an operational circuit 1 constructed on a substrate Sub. As described above, the operational circuit 1 includes, for example, a resistance changing element 11, an input line w1, a wiring w2, a first switching element S1, a second switching element S2, a third switching element S3, and a capacitor C.

[0105] The substrate Sub is, for example, a semiconductor substrate. A first switching element S1, a second switching element S2, a third switching element S3, and a fourth switching element S4 are formed on the substrate Sub. The second switching element S2, the third switching element S3, and the fourth switching element S4 are not shown in this cross-section, for example, they are located at arbitrary positions in the Y direction.

[0106] The first switching element S1 is connected to wiring w2, for example, via a path wiring V1. Additionally, the first switching element S1 is connected to the resistance changing element 11, for example, via a path wiring V2. Wiring w2 extends, for example, in the y-direction. The second switching element S2 and the third switching element S3 are connected to wiring w2, for example, via path wiring, at positions different from the y-direction of wiring w2. Wiring w2, the first switching element S1, the second switching element S2, and the third switching element S3 are surrounded by an insulating layer 91.

[0107] Insulating layer 91 is an interlayer insulating film that insulates the wiring between layers and components in multilayer wiring. Insulating layer 91 is, for example, silicon oxide (SiO2). x ), silicon nitride (SiN) x Silicon carbide (SiC), chromium nitride, silicon carbon nitride (SiCN), silicon oxynitride (SiON), aluminum oxide (Al2O3), zirconium oxide (ZrO2) x )wait.

[0108] The resistance changing element 11 is connected to the first switching element S1, for example, via a circuit V2. The resistance changing element 11 is, for example, the aforementioned domain wall moving element. The resistance changing element 11 is covered by an insulating layer 90. The insulating layer 90 is similar to the insulating layer 91.

[0109] The input line w1 is connected to the ferromagnetic layer L1 of the resistance changing element 11. The insulating layer L4 and the electrode L5 are connected to the magnetic recording layer L3 of the resistance changing element 11. The insulating layer L4 and the electrode L5 are connected in the X direction to the ends opposite to the end connected to the pass wiring V2.

[0110] The insulating layer L4 functions as a capacitor C. One of the two plates of the capacitor C is part of the outer periphery of the resistance changing element 11. That is, the outer periphery of the magnetic recording layer L3, which is opposite to the plate L5, functions as a plate of the capacitor C. When the outer periphery of the magnetic recording layer L3 functions as a plate of the capacitor C, the number of parts is reduced, which can suppress the increase in manufacturing costs and make manufacturing easier. In addition, it enables the miniaturization of neuromorphic devices.

[0111] Symbol Explanation

[0112] 1.10 Operational Circuit

[0113] 11 Resistance changing element

[0114] 12 Input Circuit

[0115] 13 Charging Circuit

[0116] 14 Output Circuit

[0117] 20 Control Department

[0118] 100 Neuromorphic Devices

[0119] C capacitor

[0120] DW domain walls

[0121] L1 Ferromagnetic layer

[0122] L2 nonmagnetic layer

[0123] L3 magnetic recording layer

[0124] L5 plate

[0125] S1 First switching element

[0126] S2 Second Switching Element

[0127] S3 Third Switching Element

[0128] S4 Fourth Switching Element

[0129] TM1 First Terminal

[0130] TM2 Second Terminal

[0131] TM3 Third Terminal

[0132] U unit

[0133] w1 input line

[0134] w2 wiring

Claims

1. An operational circuit, comprising: A resistance-changing element has three terminals: a first terminal, a second terminal, and a third terminal, which enables the resistance value to change. An input line, which is connected to the first terminal; A capacitor connected to the second terminal and located between the second terminal and a reference potential; A first switching element is connected to the third terminal; The wiring is connected to the third terminal via the first switching element; A second switching element is connected to the first end of the wiring; A third switching element is connected to the second end of the wiring; and The control unit controls the first switching element, the second switching element, and the third switching element. The control unit turns on the first and second switching elements, stores charge in the capacitor, turns off the second switching element, and turns on the third switching element. The capacitor is directly connected in series with the second terminal. The charge stored in the capacitor is output to the wiring as a spike signal.

2. The operational circuit according to claim 1, wherein, Regarding the resistance changing element, the resistance value between the first terminal and the third terminal changes according to the pulse current flowing between the second terminal and the third terminal.

3. The operational circuit according to claim 1 or 2, wherein, It has a control unit that controls the first switching element, the second switching element, and the third switching element. The control unit, During the period when the input signal is input from the input line, the first switching element is turned off. After the capacitor has accumulated a charge, the first switching element is turned on.

4. The operational circuit according to claim 3, wherein, The signal output from the third terminal by turning on the first switching element is determined by the resistance value of the resistance changing element and the input signal.

5. The operational circuit according to claim 1 or 2, wherein, A resistor is provided between the first switching element and the second switching element.

6. The operational circuit according to claim 1 or 2, wherein, A fourth switching element is also provided between the input line and the first terminal.

7. The operational circuit according to claim 1 or 2, wherein, One of the two plates of the capacitor is part of the outer periphery of the resistance changing element.

8. The operational circuit according to claim 1 or 2, wherein, The wiring connection includes multiple units comprising the input line, the resistance changing element, the capacitor, and the first switching element.

9. The operational circuit according to claim 8, wherein, It has a control unit that controls the first switching element, the second switching element, and the third switching element. The control unit enables at least a portion of the units to control the first switching elements of each other synchronously.

10. The operational circuit according to claim 8, wherein, It has a control unit that controls the first switching element, the second switching element, and the third switching element. The control unit causes at least a portion of the first switching elements of the plurality of units to be controlled asynchronously.

11. The operational circuit according to claim 1 or 2, wherein, The resistance changing element is a domain wall moving type element. The domain wall moving element includes: A magnetic recording layer that connects the second terminal to the third terminal; A non-magnetic layer, which is stacked on the magnetic recording layer; and A ferromagnetic layer, which sandwiches the non-magnetic layer between the magnetic recording layer.

12. A neuromorphic device comprising: The operational circuit according to any one of claims 1 to 11; An input circuit, which is connected to the input line of the arithmetic circuit; A charging circuit, which is connected to the second switching element of the operational circuit; and An output circuit is connected to the third switching element of the operational circuit.

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