A debugging method and device for an AI chip

Abstract

The present invention provides a debugging method and device for an AI chip, including: when an exception occurs during the operation of the AI chip, the AI module notifies the CPU through an interrupt; the CPU checks the interrupt and reads the status register of the AI module; based on the value of the read status register, the approximate time point of the error is determined; through the configuration and operation of the single-step debugging module, the accurate error clock point is determined. The present invention is based on the single-step debugging module (circuit) of the chip AI IP, and quickly locates the problem of AI IP exception at a very low cost, shortening the time for debugging and locating complex problems by more than 50%.

Description

Technical Field

[0001] The present invention relates to the technical field of AI chips, and specifically, to a debugging method and device for an AI chip. Background Art

[0002] With the rapid development of deep learning, AI chips have been widely applied to devices such as personal computers, industrial computers, network video recorders, and servers.

[0003] The design complexity and circuit scale of AI chips are far beyond those of ordinary chips. Among them, the process of debugging and quickly locating anomalies is particularly crucial. From the traditional chip AI module AI IP debugging process, only the finally occurring errors can be seen, and the intermediate process of no errors cannot be seen; thus, it is impossible to know which step or which clock cycle the error occurs, resulting in a long time-consuming for the positioning and solution of AI IP problems, which is not conducive to the rapid market launch of products. Summary of the Invention

[0004] The main purpose of the present invention is to provide a debugging method and device for an AI chip, so as to solve the problems existing in the prior art.

[0005] To achieve the above purpose, the present invention provides a debugging method for an AI chip, including:

[0006] When an anomaly occurs during the operation of the AI chip, the AI module notifies the CPU through an interrupt;

[0007] The CPU views the interrupt and reads the status register of the AI module;

[0008] Based on the value of the read status register, the approximate time point of the error is judged;

[0009] Through the configuration and operation of the single-step debugging module, the accurate error clock point is determined.

[0010] Optionally, the determining the accurate error clock point through the configuration and operation of the single-step debugging module specifically includes:

[0011] Configuring the first expected number of forward clock beats starting from the approximate time point;

[0012] Judging whether the first expected number of forward clock beats is the error clock point;

[0013] If not, configuring the second expected number of forward clock beats starting from the approximate time point;

[0014] Judging whether the second expected number of forward clock beats is the error clock point;

[0015] If not, configuring the third expected number of forward clock beats starting from the approximate time point;

[0016] Determine whether the third expected number of forward clock beats is an incorrect clock point;

[0017] Repeat this process until the accurate incorrect clock point is located.

[0018] Optionally, the determining whether the first expected number of forward clock beats is an incorrect clock point specifically includes: starting from the beginning of program operation, controlling the AI module to work for only the number of clock cycles of the first expected number of forward clock beats, checking whether the AI module notifies the CPU through an interrupt. If so, determine that the first expected number of forward clock beats is an incorrect clock point; otherwise, determine that the first expected number of forward clock beats is not an incorrect clock point.

[0019] Optionally, the method further includes: after determining the accurate incorrect clock point, starting from the accurate incorrect clock point, checking the status register of the module related to the AI module to determine whether it is a problem with the upstream and downstream modules that causes the AI module to malfunction.

[0020] The present invention also provides a debugging device for an AI chip, including:

[0021] An AI module, which is used to notify the CPU through an interrupt when an abnormality occurs during the operation of the AI chip;

[0022] A CPU, which is used to check the interrupt and read the status register of the AI module;

[0023] A judgment module, which is used to judge the approximate time point of the error according to the value of the read status register;

[0024] A single-step debugging module, which is used to determine the accurate incorrect clock point through the configuration and operation of the single-step debugging module.

[0025] Optionally, the single-step debugging module specifically includes a configuration unit and a judgment unit,

[0026] The configuration unit is used to configure the first expected number of forward clock beats starting from the approximate time point;

[0027] The judgment unit is used to judge whether the first expected number of forward clock beats is an incorrect clock point;

[0028] If not, the configuration unit is further used to configure the second expected number of forward clock beats starting from the approximate time point;

[0029] The judgment unit is further used to judge whether the second expected number of forward clock beats is an incorrect clock point;

[0030] If not, the configuration unit is further configured to configure a third expected number of forward clock beats starting from the approximate time point;

[0031] The determination unit is further configured to determine whether the third expected number of forward clock beats is an incorrect clock point;

[0032] Repeat this process until the single-step debugging module locates the accurate incorrect clock point.

[0033] Optionally, the determination unit is specifically configured to: starting from the program run, control the AI module to work only for the number of clock cycles of the first expected number of forward clock beats, check whether the AI module notifies the CPU through an interrupt. If so, determine that the first expected number of forward clock beats is an incorrect clock point; otherwise, determine that the first expected number of forward clock beats is not an incorrect clock point.

[0034] Optionally, the single-step debugging module is further configured to: after determining the accurate incorrect clock point, starting from the accurate incorrect clock point, check the status registers of the modules related to the AI module to determine whether problems in the upstream and downstream modules cause the AI module to malfunction.

[0035] Optionally, the functional mode of the single-step debugging module: set bp_en to 0, and the clock is always on;

[0036] The debugging mode of the single-step debugging module:

[0037] Set bp_en to 1, and the clock is gated;

[0038] Set bp_tar to the expected number of forward clock beats;

[0039] Write 1 (write pulse) to bp_upd, and the clock moves forward to the target set by bp_tar to quickly reproduce and locate the state where the AI IP has problems.

[0040] Optionally, the single-step debugging module consists of a counter and a gating unit.

[0041] The beneficial effects of the present invention are: based on the single-step debugging module (circuit) of the chip AI IP, at a very low cost, quickly locate the problems of AI IP anomalies, and shorten the time for debugging and locating complex problems by more than 50%.

[0042] Other features and advantages of the present invention will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following detailed implementation manners, they are used to explain the present invention, but do not constitute a limitation to the present invention. In the accompanying drawings:

[0044] Figure 1 It is a schematic flowchart of a debugging method for an AI chip according to an embodiment of the present invention;

[0045] Figure 2 It is a circuit architecture diagram of a single-step debugging module according to an embodiment of the present invention;

[0046] Figure 3 It is a schematic structural diagram of a debugging device for an AI chip according to an embodiment of the present invention. Detailed Implementation Manner

[0047] The following will explain in detail the specific implementation manners of the present invention with reference to the accompanying drawings. It should be understood that the specific implementation manners described herein are only used to illustrate and explain the present invention and do not limit the present invention.

[0048] As Figure 1 shown, a schematic flowchart of a debugging method for an AI chip according to an embodiment of the present invention is shown, including:

[0049] S101. During the operation of the AI chip, an exception occurs, and the AI module notifies the CPU through an interrupt;

[0050] S102. The CPU checks the interrupt and reads the status register of the AI module;

[0051] S103. According to the value of the read status register, determine the approximate time point when the error occurred;

[0052] S104. Through the configuration and operation of the single-step debugging module, determine the accurate error clock point.

[0053] Optionally, the determining the accurate error clock point through the configuration and operation of the single-step debugging module specifically includes:

[0054] Configure the first expected number of forward clock beats starting from the approximate time point;

[0055] Judge whether the first expected number of forward clock beats is the error clock point;

[0056] If not, configure the second expected number of forward clock beats starting from the approximate time point;

[0057] Judge whether the second expected number of forward clock beats is the error clock point;

[0058] If not, configure the third expected number of forward clock beats starting from the approximate time point;

[0059] Determine whether the third expected number of forward clock beats is an incorrect clock point;

[0060] Repeat this process until the exact incorrect clock point is located.

[0061] Optionally, the determination of whether the first expected number of forward clock beats is an incorrect clock point specifically includes: starting from the program run, controlling the AI module to work for only the number of clock cycles of the first expected number of forward clock beats, and checking whether the AI module notifies the CPU through an interrupt. If so, determine that the first expected number of forward clock beats is an incorrect clock point; otherwise, determine that the first expected number of forward clock beats is not an incorrect clock point.

[0062] Optionally, the method further includes: after determining the exact incorrect clock point, starting from the exact incorrect clock point, checking the status register of the module related to the AI module to determine whether it is a problem with the upstream and downstream modules that causes the AI module to be abnormal.

[0063] Among them, the first / second / third expected number of forward clock beats can be the same or different, and the specific values can be based on experience, and the subsequent values can be adjusted with reference to the previous results. For example, assuming that the approximate time point of the error is 2000 clock cycles, the first / second / third expected number of forward clock beats can be 1500 clock cycles, 1000, 500, and so on, approaching the error time step by step, or quickly determining it by the dichotomy method. The determination time process depends on the specific situation, but it can be at least 50% faster than the traditional debugging relying on the status register.

[0064] Specifically,

[0065] 1. During the operation of the AI chip, an abnormality occurs, and the AI module notifies the CPU through an interrupt;

[0066] 2. The engineer uses the CPU to view the interrupt generated by the AI IP and reads the status register of the AI module;

[0067] 3. The engineer can roughly know what the error is by reading the register. For example, the FIFO is read empty (resulting in data loss), the FIFO is written full (resulting in data loss, and these problems will all cause data errors), but the engineer does not know the reason for the error;

[0068] 4. Starting from the program run, the AI module notifies the CPU through an interrupt (when an abnormality occurs), and the CPU debugging tool can record the approximate time point of the error (for example, 10000 clock cycles);

[0069] Configure the single-step debugging module and operate through the single-step debugging module:

[0070] Starting from the program run, control the AI module to work only for 5000 clock cycles, and check whether the AI module notifies the CPU through an interrupt. If not;

[0071] Starting from the program run, control the AI module to work only for 7000 clock cycles, and check whether the AI module notifies the CPU through an interrupt. If not;

[0072] Starting from the program run, control the AI module to work only for 8000 clock cycles, and check whether the AI module notifies the CPU through an interrupt. An interrupt occurs;

[0073] Starting from the program run, control the AI module to work only for 7500 clock cycles, and check whether the AI module notifies the CPU through an interrupt. An interrupt occurs, and determine that 7500 clock cycles is the accurate error clock point;

[0074] Starting from this clock point, check the status registers of the modules related to the AI module to see if it is a problem with the upstream and downstream modules that causes the AI module to malfunction. For other problems, it can also be analyzed according to the scenario.

[0075] The interface of the single-step debugging module (clk_bp) is as follows:

[0076]

[0077]

[0078] The single-step debugging module (clk_bp) can be regarded as a clock pulse number management module, which can accurately control the number of clock cycles for the AI module to run.

[0079] Operation steps of the single-step debugging module:

[0080] Function mode: Set bp_en to 0, and the clock is always on;

[0081] Debugging mode:

[0082] Set bp_en to 1, and the clock is gated;

[0083] Set bp_tar to the desired number of clock beats forward;

[0084] Write 1 (write pulse) to bp_upd, and the clock moves forward to the target set by bp_tar to quickly reproduce and locate the state where the AI IP has a problem.

[0085] As Figure 2 shown, it is the circuit architecture diagram of the single-step debugging module of the embodiment of the present invention. The single-step debugging module is composed of a counter and a gating unit:

[0086] When bp_en = 0, after synchronization and then inversion, the clock gating circuit is always open;

[0087] When bp_en = 1, after synchronization and then inversion, the clock gating circuit is controlled by a counter. The initial value of the counter is bp_tar[31:0], and bp_upd updates the initial value of the counter;

[0088] The gating enables the output clock until the counter decrements to 0, at which point the gating is turned off and the clock stops outputting.

[0089] The configured signals bp_en, bp_upd, and bp_tar are signals in the clk_cfg clock domain and need to be synchronized to the clk_in clock domain through a standard synchronization circuit.

[0090] As Figure 3 shown, the present invention also provides a debugging device for an AI chip, including:

[0091] An AI module for notifying the CPU through an interrupt when an exception occurs during the operation of the AI chip;

[0092] A CPU for viewing the interrupt and reading the status register of the AI module;

[0093] A judgment module for judging the approximate time point of the error according to the value of the read status register;

[0094] A single-step debugging module for determining the exact error clock point through the configuration and operation of the single-step debugging module.

[0095] Optionally, the single-step debugging module specifically includes: a configuration unit and a judgment unit,

[0096] The configuration unit for configuring the first desired number of forward clock beats starting from the approximate time point;

[0097] The judgment unit for judging whether the first desired number of forward clock beats is the error clock point;

[0098] If not, the configuration unit is further configured to configure the second desired number of forward clock beats starting from the approximate time point;

[0099] The judgment unit is further configured to judge whether the second desired number of forward clock beats is the error clock point;

[0100] If not, the configuration unit is further configured to configure the third desired number of forward clock beats starting from the approximate time point;

[0101] The determining unit is further configured to determine whether the third expected number of forward clock beats is an incorrect clock point;

[0102] And so on, until the single-step debugging module locates the accurate incorrect clock point.

[0103] Optionally, the determining unit is specifically configured to: since the start of program operation, control the AI module to operate for only the number of clock cycles of the first expected number of forward clock beats, check whether the AI module notifies the CPU through an interrupt. If so, determine that the first expected number of forward clock beats is an incorrect clock point; otherwise, determine that the first expected number of forward clock beats is not an incorrect clock point.

[0104] Optionally, the single-step debugging module is further configured to: after determining the accurate incorrect clock point, starting from the accurate incorrect clock point, check the status registers of the modules related to the AI module to determine whether problems with upstream and downstream modules cause the AI module to exhibit anomalies.

[0105] Optionally, the functional mode of the single-step debugging module: set bp_en to 0, and the clock is always on;

[0106] The debugging mode of the single-step debugging module:

[0107] Set bp_en to 1, and the clock is gated;

[0108] Set bp_tar to the expected number of forward clock beats;

[0109] Write 1 (write pulse) to bp_upd, and the clock moves forward to the target set by bp_tar to quickly reproduce and locate the state where problems occur in the AI IP.

[0110] Optionally, the single-step debugging module is composed of a counter and a gating unit.

[0111] The preferred embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solutions of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0112] In addition, it should be noted that, among the various specific technical features described in the above specific embodiments, they can be combined in any appropriate manner without conflict. To avoid unnecessary repetition, the present invention does not separately describe various possible combination methods.

[0113] Furthermore, any combination can be made between different embodiments of the present invention, as long as it does not violate the idea of the present invention, and it should also be regarded as the content disclosed by the present invention.

Claims

1. A debugging method for an AI chip, characterized in that, it includes: When an exception occurs during the operation of the AI chip, the AI module notifies the CPU through an interrupt; The CPU checks the interrupt and reads the status register of the AI module; Based on the value of the read status register, determine the approximate time point when the error occurred; Through the configuration and operation of the single-step debugging module, determine the accurate error clock point; The determining the accurate error clock point through the configuration and operation of the single-step debugging module specifically includes: Configure the first expected number of forward clock beats starting from the approximate time point; Determine whether the first expected number of forward clock beats is the error clock point; If not, configure the second expected number of forward clock beats starting from the approximate time point; Determine whether the second expected number of forward clock beats is the error clock point; If not, configure the third expected number of forward clock beats starting from the approximate time point; Determine whether the third expected number of forward clock beats is the error clock point; Repeat this process until the accurate error clock point is located.

2. The debugging method according to claim 1, characterized in that, The determining whether the first expected number of forward clock beats is the error clock point specifically includes: starting from the start of program operation, control the AI module to work only for the first expected number of forward clock beats of clock cycles, check whether the AI module notifies the CPU through an interrupt. If so, determine that the first expected number of forward clock beats is the error clock point; otherwise, determine that the first expected number of forward clock beats is not the error clock point.

3. The debugging method according to claim 2, characterized in that, The method further includes: after determining the accurate error clock point, starting from the accurate error clock point, check the status registers of the modules related to the AI module to determine whether it is a problem with the upstream and downstream modules that causes the AI module to have an exception.

4. A debugging device for an AI chip, characterized in that, it includes: An AI module, used for when an exception occurs during the operation of the AI chip, notifying the CPU through an interrupt; A CPU, used for checking the interrupt and reading the status register of the AI module; A judgment module, used for judging the approximate time point when the error occurred according to the value of the read status register; A single-step debugging module, used for determining the accurate error clock point through the configuration and operation of the single-step debugging module; The single-step debugging module specifically includes: a configuration unit and a judgment unit, The configuration unit is used for configuring the first expected number of forward clock beats starting from the approximate time point; The judgment unit is used for judging whether the first expected number of forward clock beats is the error clock point; If not, the configuration unit is further used for configuring the second expected number of forward clock beats starting from the approximate time point; The judgment unit is further used for judging whether the second expected number of forward clock beats is the error clock point; If not, the configuration unit is further used for configuring the third expected number of forward clock beats starting from the approximate time point; The judgment unit is further used for judging whether the third expected number of forward clock beats is the error clock point; Repeat the above steps until the single-step debugging module locates the exact error clock point.

5. The debugging device according to claim 4, wherein, the judgment unit is specifically configured to: starting from the start of program operation, control the AI module to work only for the first expected number of forward clock cycles, check whether the AI module notifies the CPU through an interrupt. If so, judge that the first expected number of forward clock cycles is the error clock point; otherwise, judge that the first expected number of forward clock cycles is not the error clock point.

6. The debugging device according to claim 5, wherein, the single-step debugging module is further configured to: after determining the exact error clock point, view the status registers of the modules related to the AI module from the exact error clock point, and judge whether it is a problem of the upstream and downstream modules that causes the AI module to be abnormal.

7. The debugging device according to claim 6, wherein, the function mode of the single-step debugging module: set bp_en to 0, and the clock is always on; the debugging mode of the single-step debugging module: set bp_en to 1, and the clock is gated; set bp_tar to the expected number of forward clock cycles; write 1 (write pulse) to bp_upd, and the clock moves forward to the target set by bp_tar, quickly reproduce and locate the state where the AI IP has problems.

8. The debugging device according to any one of claims 4-7, wherein, the single-step debugging module consists of a counter and a gating unit.

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