Method and system for downloading and debugging RISC-V processor based on FPGA-JTAG (Field Programmable Gate Array-Joint Test Action Group) interface

Abstract

The invention provides an FPGA-JTAG (Field Programmable Gate Array-Joint Test Action Group) interface-based RISC-V processor downloading debugging method and system, and the method comprises the steps: modifying a boundary scan configuration code related to an FPGA chip in an upper computer source code based on the address and bit width of a boundary scan register; modifying a cfg configuration code of the upper computer based on the boundary scan register, and configuring the cfg configuration code into a boundary scan mode; a data packet containing a boundary scan register address, a debugging instruction and debugging data is constructed through an upper computer, and is transmitted to a data analysis module through an FPGA-JTAG interface; and the TDI signal is analyzed according to the format of the data packet, and the state of the TAP state machine is switched by controlling the TMS signal, so that the debugging of the RISC-V processor is realized. The FPGA-JTAG interface is reused for debugging, the debugging efficiency and reliability are improved, the hardware design is simplified, and the system cost is reduced.

Description

Technical Field

[0001] This application belongs to the technical field of processor debugging design, and particularly relates to a method and system for downloading and debugging a RISC-V processor based on the FPGA-JTAG interface. Background Art

[0002] RISC-V, that is, the fifth-generation Reduced Instruction Set Computer architecture, is an open instruction set architecture (ISA) proposed in 2010. Compared with traditional instruction sets such as ARM and X86, the advantage of RISC-V lies in its patent-free openness, which greatly reduces the threshold for processor innovation and enables more developers to participate in the design and application of processors. At the same time, RISC-V also allows users to customize instruction set extensions according to specific needs, so as to customize processors for different application scenarios.

[0003] In the RISC-V ecosystem, debugging technology is crucial for processor design and software development. The debugging system endows developers with the ability to deeply observe and control the processor state, including but not limited to setting breakpoints, stepping through instructions, viewing and modifying register and memory contents. These functions greatly facilitate developers to discover and modify potential errors.

[0004] However, currently, the RISC-V processor soft core running on an FPGA (Field Programmable Gate Array) chip has certain inconveniences during the debugging process. Specifically, the existing download and debugging methods rely on external IO connections, which leads to frequent hot plugging operations during the debugging process, not only increasing the complexity of debugging but also potentially damaging the device. Therefore, a solution is needed to address the inconveniences in the existing debugging process to improve the debugging efficiency.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely explaining the technical solutions of this application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of this application. Summary of the Invention

[0006] This application discloses a method and system for downloading and debugging a RISC-V processor based on the FPGA-JTAG interface. By reusing the FPGA-JTAG interface, it is possible to avoid the problems of waste of external IO resources and complex debugging processes, and improve the debugging efficiency and reliability.

[0007] Other objectives and advantages of the present application can be further understood from the technical features disclosed in the present application.

[0008] To achieve one or part or all of the above objectives or other objectives, in a first aspect, the present application provides a method for downloading and debugging a RISC-V processor based on an FPGA-JTAG interface. The method includes: Based on the boundary scan register address and bit width of the FPGA chip, modify the boundary scan configuration code related to the FPGA chip in the source code of the host computer; Based on the boundary scan register of the FPGA chip, modify the cfg configuration code of the host computer to configure the host computer in the boundary scan mode; Construct a data packet containing the boundary scan register address, debug instruction, and debug data through the host computer, and transmit it to the data parsing module through the FPGA-JTAG interface; Parse the TDI signal according to the format of the data packet to obtain a parsing result, and control the TMS signal to switch the state of the TAP state machine according to the parsing result to achieve debugging of the RISC-V processor.

[0009] Further, the modification of the cfg configuration code of the host computer at least includes: defining the access method of the boundary scan register, setting the chain order, and configuring the length of the scan chain in the cfg configuration code.

[0010] Further, when the host computer is in the boundary scan mode, transmit a data packet to the boundary scan register through the FPGA-JTAG interface, parse the data type and bit width based on the TDI signal, and control the change of the TMS signal according to the data type and bit width to switch the state of the TAP state machine.

[0011] Further, when the TAP state machine is in the shift instruction register state, input the boundary scan register address through the TDI signal and transmit it to the boundary scan register through the FPGA-JTAG interface.

[0012] Further, when the TAP state machine is in the shift data register state, the TDI signal transmits the configuration information of the debug instruction and the debug data to the data parsing module through the FPGA-JTAG interface.

[0013] Further, when the TAP state machine is in the shift instruction register state or the shift data register state, the TMS signal remains zero; judge whether the data sent to the TAP state machine is the data register or the instruction register according to the TDI signal, and calculate the number of clock cycles for which the TMS signal needs to remain zero by obtaining the data bit width.

[0014] Further, the data parsing module parses the debug instruction according to the instruction register mode and parses the debug data according to the data register mode.

[0015] In a second aspect, the present application provides a RISC-V processor download and debug system based on an FPGA-JTAG interface. The system at least includes a host computer, a boundary scan register, a data parsing module, a debug module, and an FPGA-JTAG interface. The system is used to execute the RISC-V processor download and debug method based on the FPGA-JTAG interface according to any one of the first aspects; The host computer is used to modify the boundary scan configuration code related to the FPGA-JTAG interface in the source code based on the boundary scan register address and bit width of the FPGA chip; the host computer is used to modify the cfg configuration code of the host computer based on the boundary scan register of the FPGA chip and configure the host computer to the boundary scan mode; a data packet including the boundary scan register address, debug instruction, and debug data is constructed by the host computer and transmitted to the data parsing module through the FPGA-JTAG interface; The data parsing module parses the TDI signal according to the data packet format to obtain a parsing result; the data parsing module controls the TMS signal according to the parsing result to switch the state of the TAP state machine in the debug module, so as to implement the debugging of the RISC-V processor.

[0016] In a third aspect, the present application provides a computer-readable storage medium. Program codes are stored in the computer-readable storage medium, and the program codes are called by a processor to execute the RISC-V processor download and debug method based on the FPGA-JTAG interface according to any one of the first aspects.

[0017] In a fourth aspect, the present application further provides an electronic device, including one or more processors; a memory; one or more application programs, wherein one or more application programs are stored in the memory and configured to be executed by one or more processors, and one or more application programs are configured to execute the RISC-V processor download and debug method based on the FPGA-JTAG interface according to any one of the first aspects.

[0018] The above RISC-V processor download and debugging method, system, computer-readable storage medium, and electronic device based on the FPGA-JTAG interface avoid adding additional hardware connections for debugging using general-purpose IO pins by multiplexing the FPGA-JTAG interface as dedicated test and debugging pins, saving valuable IO resources; this application simplifies the hardware design by multiplexing the FPGA-JTAG interface for debugging, without the need to add additional debugging interfaces or modify the hardware circuit; by reducing the introduction of additional debugging lines, system noise and interference are reduced, and the data transmission stability during debugging and the overall system reliability are improved; this application can achieve processor debugging using only the FPGA-JTAG interface, simplifying the board design and reducing test or development overhead.

[0019] To make the above and other purposes, features, and advantages of this application more obvious and understandable, the following specifically presents preferred embodiments and, in conjunction with the accompanying drawings, provides detailed descriptions as follows. Brief Description of the Drawings

[0020] To more clearly illustrate the technical solutions in the specific embodiments of this application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the following-described drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0021] Figure 1 It is a schematic flowchart of the RISC-V processor download and debugging method based on the FPGA-JTAG interface of this application.

[0022] Figure 2 It is a timing schematic diagram of the data parsing module of this application.

[0023] Figure 3 It is a schematic diagram of the TAP state machine of this application.

[0024] Figure 4 It is a system framework diagram of the RISC-V processor download and debugging system based on the FPGA-JTAG interface of this application. Detailed Embodiments

[0025] The foregoing and other technical contents, features, and effects of this application will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. The terms "first", "second", etc. in the description and claims of this application and the above drawings are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing the embodiments of this application.

[0026] Reference Figure 1 In the embodiments of the present application, a method for downloading and debugging a RISC-V processor based on an FPGA-JTAG interface is provided. The RISC-V Debug system of the present application complies with the RISC-V External Debug Support Version 0.13 protocol. The method specifically includes the following steps: Step S1: Modify the boundary scan configuration code related to the FPGA chip in the source code of the host computer based on the address and bit width of the boundary scan register of the FPGA chip.

[0027] Among them, the JTAG interface (Joint Test Action Group) is a protocol for in-chip testing. In this article, the FPGA-JTAG interface is also simply referred to as the JTAG interface.

[0028] The boundary scan (Boundary SCAN, BSCAN) register is a special register inside the FPGA chip for boundary scan testing. They are located in the JTAG boundary scan chain of the FPGA chip. These registers allow access and control of the boundary scan chain of the FPGA chip through the FPGA-JTAG interface. Each boundary scan register has a unique address used to identify and access the register in the JTAG protocol. The register bit width represents the data width of the register (such as 6 bits, 8 bits, and 32 bits, etc.), which determines the amount of data that the register can store and transmit. The address and bit width of the boundary scan register of the chip can be obtained through the data manual of the FPGA chip and related technical documents. According to this parameter, modify the boundary scan configuration part related to the FPGA-JTAG interface in the source code of the host computer such as OpenOCD (Open On-Chip Debugger) so that the host computer can correctly identify and process it.

[0029] Step S2: Modify the cfg configuration code of the host computer accordingly based on the boundary scan register of the FPGA chip to make it in the boundary scan mode.

[0030] Exemplarily, the boundary scan mode is an operating mode of the FPGA chip under the FPGA-JTAG interface. In this mode, the boundary scan chain of the FPGA chip is activated, allowing testing and debugging of the input / output pins, internal signals, etc. of the FPGA chip through the FPGA-JTAG interface. The host computer communicates with the FPGA chip through the FPGA-JTAG interface, identifies the IDCODE of the chip to confirm the type of the target device, and the host computer configures, debugs, and tests the FPGA through JTAG protocol communication, including operations such as reading and writing registers and accessing memory.

[0031] Optionally, modifying the cfg configuration code of the host computer includes: defining the access method of the boundary scan register in the cfg configuration code, setting the chain order, configuring the length of the scan chain, etc. These modifications enable it to support the boundary scan mode of the FPGA chip, so as to improve the accuracy of the host computer's identification and operation of the boundary scan register of the FPGA chip through the FPGA-JTAG interface, laying a foundation for subsequent debugging work.

[0032] Step S3: The host computer constructs a data packet containing the boundary scan register address, debug instruction, and debug data, and transmits it to the data parsing module through the FPGA-JTAG interface.

[0033] After configuring the host computer, a data packet containing the boundary scan register address, debug instruction, and debug data is constructed and transmitted to the data parsing module through the FPGA-JTAG interface for processing.

[0034] Optionally, after receiving the debug instruction from the host computer through the FPGA-JTAG interface, multiple tests can be performed to verify the stability of the communication connection and ensure error-free data transmission.

[0035] Step S4: Parse the TDI signal according to the data packet format to obtain the parsing result, and control the TMS signal to switch the state of the TAP state machine according to the parsing result to achieve the debugging of the RISC-V processor.

[0036] The data parsing module parses the TDI signal according to the data format, and determines whether the data is sent to the data register or the instruction register of the TAP state machine. Subsequently, by obtaining the bit width of the data, the number of clock cycles for which the TMS signal needs to be kept at zero is calculated to ensure the accurate reception of the data. By controlling the TMS signal to switch the state of the TAP state machine, the debugging of the RISC-V processor is achieved.

[0037] The debugging module is the core component of the RISC-V processor debugging, used to provide the ability to debug and control the CPU running state, allowing the debugger to control the execution of the RISC-V processor, such as: single-step execution, setting breakpoints, reading / writing registers and memory, so as to achieve the debugging of the RISC-V processor. In this embodiment, the data parsing module is used to parse the data packet, and then the debug information in the parsing result is accurately transmitted to the debug transport module (DebugTransport Module, DTM) in the debugging module to achieve the debugging of the RISC-V processor.

[0038] Step S5: After completing the debugging, disconnect the connection between the host computer and the FPGA-JTAG interface, restore the default configuration, and release the occupied resources.

[0039] According to the above description, the RISC-V processor download and debugging method based on the FPGA-JTAG interface of the present application modifies the source code and cfg configuration code of the host computer through configuration, and reuses the FPGA-JTAG interface as dedicated test and debugging pins, avoiding the addition of extra hardware connections by using general-purpose IO pins, saving precious IO resources, eliminating the inconvenience caused by frequent hot-plugging of external IO pins in traditional debugging, and significantly improving the stability and reliability of the debugging process. At the same time, by reusing the FPGA-JTAG interface for debugging, there is no need to add extra debugging interfaces or change the hardware circuit, simplifying the board design and reducing the test or development overhead. Moreover, by reducing the introduction of extra debugging lines, the system noise and interference are reduced, enabling efficient debugging of the RISC-V processor, and improving the data transmission stability during the debugging process and the overall reliability of the system.

[0040] In one implementation, referring to Figure 2 , when the host computer is in the boundary scan mode, the boundary scan register address is first sent. When the FPGA-JTAG interface receives the boundary scan register address, communication can be established with the RISC-V debugging system through the boundary scan register of the FPGA. The debugging instructions and debugging data related to the RISC-V processor debugging are embedded in the data register. Since these instructions need to be parsed during the debugging process, the debugging information is processed and extracted by the data parsing module of the present application and accurately transmitted to the debugging module. This method supports advanced debugging operations on the processor, such as batch reading and writing of registers, block operations on memory, flexible setting of breakpoints, etc., enriching the means and functions of debugging.

[0041] Furthermore, the data parsing module parses the TDI signal transmitted through the boundary scan register to obtain the data type and bit width, and controls the change of the TMS signal according to the parsing result, which can ensure the accurate switching of the TAP state machine between the instruction register (IR) and data register (DR) modes, thereby accurately parsing the debugging instructions and debugging data in the data packet and achieving precise debugging of the RISC-V processor. Specifically, referring to Figure 2 , when the TAP state machine is in the shift instruction register state, the boundary scan register address is input through the TDI signal and transmitted to the boundary scan register through the FPGA-JTAG interface; when the TAP state machine is in the shift data register state, the TDI signal transmits the configuration information of the debugging instructions and debugging data to the data parsing module through the FPGA-JTAG interface. Thus, by reusing the FPGA-JTAG interface for debugging, the hardware design is simplified, there is no need to add extra debugging interfaces or change the hardware circuit, and the introduction of extra debugging lines is reduced, reducing the system noise and interference, and improving the data transmission stability during the debugging process and the overall reliability of the system.

[0042] As shown in Table 1 and Table 2 below, Table 1 includes the data format of the execution instruction register mode, and Table 2 includes the data format of the execution data register mode.

[0043] Table 1 Table 2 Specifically, first, the TDI signal sends 1 bit flag ("0" or "1") to select whether to enter the instruction register mode or the data register mode. 0 of 1 bit (bit) means entering the instruction register mode to transmit instructions, and 1 of 1 bit means entering the data register mode to transmit data. After entering the instruction register mode or the data register mode, then send the instruction bit width and data information of the instruction. 7 bits represent the corresponding bit width, and IR Width bits or DR Width bits represent the corresponding width bits. In the shift instruction register state or the shift data register state, the TMS signal remains 0 continuously to ensure that the TAP state machine performs instruction transmission or data transmission. The data parsing module parses the TDI signal according to the data packet format to determine whether the data is sent to the data register or the instruction register of the TAP state machine. Subsequently, by obtaining the data bit width, calculate the number of clock cycles for which the TMS signal needs to remain zero to ensure accurate reception of the data. After the transmission is completed, 0 of 3 bits will be sent continuously, causing the TAP state machine to re-enter the test run idle state to prepare for subsequent operations.

[0044] In summary, the RISC-V processor download and debugging method based on the FPGA-JTAG interface of the present application can save external IO resources, improve debugging efficiency and system stability, simplify the design of test or application boards, and reduce costs. Specifically, the present application multiplexes the FPGA-JTAG interface as dedicated test and debugging pins instead of the general IO pins of the FPGA, avoiding adding additional hardware connections for debugging and saving valuable IO resources; the present application simplifies the hardware design by multiplexing the FPGA-JTAG interface for debugging, without the need to add additional debugging interfaces or change the hardware circuit; by reducing the introduction of additional debugging lines, the system noise and interference are reduced, and the data transmission stability during debugging and the overall reliability of the system are improved; the present application can implement the function of debugging the processor while only using the FPGA-JTAG interface, simplify the board design, and reduce test or development overhead.

[0045] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0046] In one embodiment, referring to Figure 4 , the present application also provides a download and debugging system framework for a RISC-V processor based on the FPGA-JTAG interface. The system framework at least includes a host computer, a boundary scan register, a data parsing module, a debugging module, and an FPGA-JTAG interface. This system is used for the download and debugging method of the RISC-V processor based on the FPGA-JTAG interface in any of the above embodiments. Specifically, the host computer is used to modify the boundary scan configuration code related to the FPGA-JTAG interface in the host computer source code based on the boundary scan register address and bit width of the FPGA chip; the host computer is used to modify the cfg configuration code of the host computer based on the boundary scan register of the FPGA chip to make it in the boundary scan mode; the host computer constructs a data packet containing the boundary scan register address, debugging instruction, and debugging data, and transmits it to the data parsing module through the FPGA-JTAG interface; the data parsing module parses the TDI signal according to the data packet format to obtain a parsing result; the data parsing module controls the TMS signal according to the parsing result to switch the state of the TAP state machine in the debugging module, so as to realize the debugging of the RISC-V processor.

[0047] In one embodiment, the present application also provides a computer-readable storage medium, in which program code is stored, and the program code is called by a processor to execute the download and debugging method of the RISC-V processor based on the FPGA-JTAG interface in any of the above embodiments.

[0048] In one embodiment, the present application also provides an electronic device, which includes one or more processors; a memory; one or more application programs, where one or more application programs are stored in the memory and are configured to be executed by one or more processors, and one or more application programs are configured to execute the download and debugging method of the RISC-V processor based on the FPGA-JTAG interface in any of the above items.

[0049] It should be noted that for those of ordinary skill in the art, without departing from the principles of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the scope of protection of the claims of this application. It should be understood that certain features of the present disclosure described in the context of separate embodiments for clarity can also be provided in a single embodiment by combination. Conversely, the various features of the present disclosure described in the context of a single embodiment for clarity can also be provided individually or in any suitable combination or as any other described embodiment of the present disclosure.

Claims

1. A RISC-V processor download and debugging method based on FPGA-JTAG interface, characterized in that: The method comprises: Based on the boundary scan register address and bit width of the FPGA chip, modify the boundary scan configuration code related to the FPGA chip in the host computer source code; Based on the boundary scan register of the FPGA chip, modify the cfg configuration code of the host computer to configure the host computer to the boundary scan mode; The host computer constructs a data packet including a boundary scan register address, a debug instruction and debug data, and transmits the data packet to a data analysis module through an FPGA-JTAG interface; The TDI signal is parsed according to the format of the data packet to obtain a parsing result, and the TMS signal is controlled to switch the state of the TAP state machine according to the parsing result to implement debugging of the RISC-V processor.

2. A RISC-V processor download and debugging method based on FPGA-JTAG interface according to claim 1, characterized in that: The modifying of the cfg configuration code of the host computer at least includes: defining the access mode of the boundary scan register, setting the chain sequence and configuring the length of the scan chain in the cfg configuration code.

3. The RISC-V processor download and debugging method based on FPGA-JTAG interface according to claim 1, characterized in that: When the host computer is in boundary scan mode, a data packet is transmitted to the boundary scan register through the FPGA-JTAG interface, the data type and bit width are obtained based on TDI signal analysis, and the change of the TMS signal is controlled according to the data type and bit width to switch the state of the TAP state machine.

4. The download and debugging method of a RISC-V processor based on an FPGA-JTAG interface according to claim 3, characterized in that: When the TAP state machine is in the shift instruction register state, the boundary scan register address is input through the TDI signal and transmitted to the boundary scan register through the FPGA-JTAG interface.

5. The download and debugging method of a RISC-V processor based on FPGA-JTAG interface according to claim 3, characterized in that: When the TAP state machine is in the shift data register state, the TDI signal transmits the debugging instruction and the configuration information of the debugging data to the data analysis module through the FPGA-JTAG interface.

6. The download and debugging method of a RISC-V processor based on FPGA-JTAG interface according to claim 3, characterized in that: When the TAP state machine is in the shift instruction register state or the shift data register state, the TMS signal remains zero; according to the TDI signal, it is determined whether it is sent to the data register or the instruction register of the TAP state machine, and by obtaining the data bit width, the number of clock cycles that the TMS signal needs to remain zero is calculated.

7. The download and debugging method of a RISC-V processor based on FPGA-JTAG interface according to claim 1, characterized in that: The data parsing module parses the debugging instruction according to the instruction register mode, and parses the debugging data according to the data register mode.

8. A RISC-V processor download and debug system based on FPGA-JTAG interface, characterized in that: The system at least includes a host computer, a boundary scan register, a data parsing module, a debugging module and an FPGA-JTAG interface, and the system is used to execute the RISC-V processor download and debugging method based on the FPGA-JTAG interface according to any one of claims 1 to 7; The host computer is used to modify the boundary scan configuration code related to the FPGA-JTAG interface in the host computer source code based on the boundary scan register address and bit width of the FPGA chip; the host computer is used to modify the cfg configuration code of the host computer based on the boundary scan register of the FPGA chip, and configure the host computer to the boundary scan mode; the host computer constructs a data packet containing the boundary scan register address, debug instructions and debug data, and transmits it to the data analysis module through the FPGA-JTAG interface; The data parsing module parses the TDI signal according to the data packet format to obtain a parsing result; the data parsing module controls the TMS signal according to the parsing result, switches the state of the TAP state machine in the debugging module, and realizes debugging of the RISC-V processor.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code, and the program code is called by a processor to execute the RISC-V processor download and debugging method based on the FPGA-JTAG interface as described in any one of claims 1 to 7.

10. An electronic device, characterized in that: comprising one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the RISC-V processor download and debugging method based on the FPGA-JTAG interface as described in any one of claims 1 to 7.

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