BMC debugging method and monitoring method, system, device, equipment, and medium

Abstract

The present application discloses a baseboard management controller debugging method, device and system, a baseboard management controller monitoring method, device and system, an electronic device, and a readable storage medium. The method includes pre-connecting the output pins and buses of the BMC through a programmable logic device containing multiple debugging buses. The received BMC debugging instruction is sent to the programmable logic device, and the bus to be debugged is connected to the debugging bus corresponding to the programmable logic device, while the physical connection between the bus to be debugged and the component to be debugged through the output bus of the programmable logic device is cut off; the debugging instruction includes a debugging protocol and a bus to be debugged. Based on the BMC debugging instruction, switch to the bus to be debugged and receive data information of the bus to be debugged. Call the debugging protocol to parse the data information, and obtain the corresponding target debugging data according to the parsing result to respond to the BMC debugging instruction. The present application can effectively shorten the software development cycle and reduce the software development and debugging costs.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a baseboard management controller debugging method, device and system, a baseboard management controller monitoring method, device and system, an electronic device, and a readable storage medium. Background Art

[0002] With the continuous advancement of computer technology, servers are increasingly being used in various technological fields, from the internet to finance, from mobile communications to education, funding, and scientific research. As server applications and scenarios diversify, customer demands for servers also vary, with an increasing demand for customization. This leads to an increasing number of components and information that the baseboard management controller (BMC), as a baseband management system, must monitor, placing higher and higher demands on BMC performance.

[0003] In the prior art, during the BMC development process, debugging of components, such as hard drives, can only be performed if the required components meet the debugging requirements, are introduced in a timely manner, and the required software and hardware environments are in place. However, if the components to be tested are not introduced in a timely manner, are difficult to obtain, or if the testing hardware is limited, debugging cannot be performed. This results in long software development cycles and high R&D costs.

[0004] In view of this, how to shorten the software development cycle and reduce software development and debugging costs is a technical problem that technical personnel in the relevant field need to solve. Summary of the Invention

[0005] The present application provides a baseboard management controller debugging method, device and system, a baseboard management controller monitoring method, device and system, an electronic device, and a readable storage medium, which can effectively shorten the software development cycle and reduce software development and debugging costs.

[0006] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0007] An embodiment of the present invention provides a baseboard management controller debugging method, including:

[0008] The output pins and output bus of the BMC are pre-connected through a programmable logic device; the programmable logic device also includes multiple debug buses;

[0009] Sending the received BMC debugging instruction to the programmable logic device to connect the bus to be debugged to the debug bus corresponding to the programmable logic device, and simultaneously severing the physical connection between the bus to be debugged and the component to be debugged through the output bus of the programmable logic device; the BMC debugging instruction includes a debugging protocol and the bus to be debugged;

[0010] Based on the BMC debugging instruction, switching to the bus to be debugged to receive data information of the bus to be debugged;

[0011] The debugging protocol is called to parse the data information, and corresponding target debugging data is obtained according to the parsing result to respond to the BMC debugging instruction.

[0012] Optionally, before obtaining corresponding target debugging data according to the parsing result, the method further includes:

[0013] When receiving the debugging data configuration command of the component to be debugged, determining whether there is original debugging data of the component to be debugged;

[0014] If original debugging data of the component to be debugged exists, updating the original debugging data according to the debugging data configuration command;

[0015] If the original debugging data of the component to be debugged does not exist, debugging data is generated for the component to be debugged.

[0016] Optionally, after obtaining corresponding target debugging data according to the parsing result, the method further includes:

[0017] In response to the data verification instruction, a data verification page is displayed to check the accuracy of the debugging data configured for the component to be debugged and the debugging data obtained;

[0018] The data verification page includes all debugging data of the component to be debugged and the target debugging data.

[0019] Optionally, the BMC is built into the server, and sending the received BMC debugging instruction to the programmable logic device includes:

[0020] When BMC debugging is required and the component to be debugged meets the debugging conditions, a bus debugging instruction is output through the BMC, and the bus debugging instruction is sent to the editable logic device at the same time;

[0021] Based on the bus debugging instruction, the working mode of the bus to be debugged of the BMC and the debugging bus corresponding to the bus to be debugged on the programmable logic device is set to a debugging mode.

[0022] Optionally, the step of setting the operating mode of the bus to be debugged of the BMC and the debug bus corresponding to the bus to be debugged on the programmable logic device to a debug mode based on the bus debug instruction includes:

[0023] If the debugging condition of the component to be debugged is restart or power off, based on the bus debugging instruction, without performing a restart operation or a power off operation, the working mode of the bus to be debugged of the BMC and the debugging bus of the programmable logic device corresponding to the bus to be debugged is set to debug mode.

[0024] An embodiment of the present invention further provides a baseboard management controller debugging device, comprising:

[0025] A pre-deployment module is used to pre-connect the output pins and output buses of the BMC through a programmable logic device; the programmable logic device also includes multiple debug buses;

[0026] a debugging instruction issuing module, configured to send a received BMC debugging instruction to the programmable logic device to connect the bus to be debugged to the debug bus corresponding to the programmable logic device, and simultaneously cut off the physical connection between the bus to be debugged and the component to be debugged through the output bus of the programmable logic device; the BMC debugging instruction includes a debugging protocol and the bus to be debugged;

[0027] A hardware interface switching module is used to switch to the bus to be debugged based on the BMC debugging instruction to receive data information of the bus to be debugged;

[0028] A data parsing module, configured to call the debugging protocol to parse the data information;

[0029] The debugging module is used to obtain corresponding target debugging data according to the analysis result to respond to the BMC debugging instruction.

[0030] The embodiment of the present invention further provides a baseboard management controller debugging system, comprising a BMC, a programmable logic device, and a component to be debugged;

[0031] The output pins and output bus of the BMC are connected to the input pins of the programmable logic device, and the output bus of the programmable logic device is connected to the component to be debugged;

[0032] The BMC is used to call a computer program stored in a memory to execute the steps of the baseboard management controller debugging method as described in any of the preceding items on the component to be debugged.

[0033] Optionally, the programmable logic device includes a first type of output pin and a second type of output pin;

[0034] The first type of output pins are connected to each component to be debugged via a corresponding output bus;

[0035] The second type of output pins are connected to the input pins of the BMC via corresponding output buses.

[0036] Optionally, a conversion chip is also included;

[0037] The output pin of the programmable logic device is connected to the conversion chip;

[0038] If the BMC is in debugging mode, the conversion chip is connected to the input pin of the BMC;

[0039] If the BMC is not in the debugging mode, the conversion chip is connected to each component to be debugged.

[0040] Another embodiment of the present invention provides a baseboard management controller monitoring method, including:

[0041] When a BMC monitoring anomaly is detected, the BMC is set to enter a debugging mode, and the target component is debugged using any of the above baseboard management controller debugging methods;

[0042] Obtaining feedback information when the BMC is in the debugging mode;

[0043] If the feedback information is normal, it is determined that the information acquisition logic, information processing logic and underlying driving functions of the BMC are normal.

[0044] An embodiment of the present invention further provides a baseboard management controller monitoring device, comprising:

[0045] A debugging module, configured to, upon detecting a BMC monitoring anomaly, set the BMC to enter a debugging mode and debug a target component using any of the above baseboard management controller debugging methods;

[0046] An information acquisition module, configured to acquire feedback information when the BMC is in the debugging mode;

[0047] The fault diagnosis module is configured to determine whether the information acquisition logic, information processing logic and underlying driver functions of the BMC are normal if the feedback information is normal.

[0048] An embodiment of the present invention further provides a baseboard management controller monitoring system, comprising a server, a programmable logic device, and a component to be debugged;

[0049] The server has a built-in BMC, the output pins and output bus of the SOC chip running the BMC are connected to the input pins of the programmable logic device, and the output bus of the programmable logic device is connected to the component to be debugged;

[0050] The BMC is used to implement the steps of the baseboard management controller monitoring method as described above when executing the computer program stored in the memory.

[0051] An embodiment of the present invention also provides an electronic device, including a processor and a memory, wherein the processor is configured to implement the steps of the baseboard management controller debugging method and / or the baseboard management controller monitoring method as described above when executing a computer program stored in the memory.

[0052] Finally, an embodiment of the present invention further provides a readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the baseboard management controller debugging method as described in any of the above items and / or the baseboard management controller monitoring method as described above are implemented.

[0053] The advantage of the technical solution provided by this application is that debugging data for virtual components corresponding to each component to be debugged is pre-configured within the BMC. The programmable logic device can be connected to the component to be debugged and the BMC at the same time. Whether the programmable logic device is connected to the actual component or interacts with the virtual component within the BMC is determined based on actual needs. Therefore, during the BMC development process, when the component to be tested does not yet meet the test conditions, it can be used as a means of self-testing. At least, the accuracy of the developed code, such as the processing logic of the upper-layer application and the underlying driver, can be guaranteed. This is concise, convenient, and easy to execute, which can effectively shorten the software development cycle and reduce software development and debugging costs.

[0054] In addition, the embodiment of the present invention also provides corresponding implementation devices, electronic devices and readable storage media for the baseboard management controller debugging method, further making the method more practical, and the devices, electronic devices and readable storage media have corresponding advantages.

[0055] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions of the embodiments of the present invention or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0057] Figure 1 A schematic diagram of a flow chart of a baseboard management controller debugging method provided by an embodiment of the present invention;

[0058] Figure 2 A schematic diagram of the BMC framework structure provided by an embodiment of the present invention;

[0059] Figure 3 A flow chart of a baseboard management controller monitoring method provided by an embodiment of the present invention;

[0060] Figure 4 A structural diagram of a specific implementation of a baseboard management controller debugging device provided by an embodiment of the present invention;

[0061] Figure 5 A structural diagram of a specific implementation of a baseboard management controller monitoring device provided by an embodiment of the present invention;

[0062] Figure 6 A structural diagram of a specific implementation of an electronic device provided by an embodiment of the present invention;

[0063] Figure 7 A structural diagram of a specific implementation of a baseboard management controller debugging system provided by an embodiment of the present invention;

[0064] Figure 8 This is a structural diagram of a specific implementation of the baseboard management controller monitoring system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0065] In order to enable those skilled in the art to better understand the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0066] In the specification, claims, and drawings of this application, the terms "first," "second," "third," "fourth," and so on are used to distinguish between different items, not to describe a specific order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements and may include steps or elements that are not listed.

[0067] After introducing the technical solutions of the embodiments of the present invention, various non-limiting implementation methods of the present application are described in detail below.

[0068] See first Figure 1 , Figure 1 A flowchart of a baseboard management controller debugging method provided by an embodiment of the present invention may include the following contents:

[0069] In order to debug physical components that do not meet the debugging conditions, this application will pre-build a self-test system process module in the BMC, and support the baseboard management controller debugging method described in the following embodiment through the self-test system process module. The software architecture of the self-test system process module is as follows: Figure 2 As shown, the self-test system process module is used to implement the relevant functions of the virtual component, and its architecture may include a protocol layer, a hardware interface layer, a debugging information interface layer, and a command control interface. Figure 2 Taking the programmable logic device as a CPLD (Complex Programmable Logic Device) as an example, the actual components shown in the figure are the components to be debugged, such as hard disks. In the CPLD, the bus input interface and the bus output interface are the external interfaces of the programmable logic device CPLD. The bus input interface interacts with the BMC, and the bus output interface is connected to the actual components. The CPLD control conversion logic is used to control the CPLD to be in debug mode or non-debug mode. The so-called debug mode is to interact with the virtual components inside the BMC, and the so-called non-debug mode means that the connection and interaction between the BMC and the actual components are carried out through the CPLD. The control command input interface is used to receive control commands sent by the BMC.

[0070] In the BMC, the control command module is used to control the BMC's sending of control commands to the CPLD and to process external input commands. The database can be a Redis database, which is used to store pre-configured debugging data. The hardware interface layer primarily implements the interaction and switching of specific buses. For example, the buses used to monitor the same component with the same protocol can also be different. For example, RAID monitoring can use either the i2c (Inter-Integrated Circuit) bus or the PCIE (Peripheral Component Interconnect Express) bus, which are differentiated and shielded at the hardware interface layer. This module will switch to the corresponding bus based on the specific commands issued by the user to receive the corresponding data and information. The protocol layer is used to implement different protocols and may include the reception and parsing of protocol frames. For example, the monitoring of different components may use MCTP (Management Component Transport Protocol) Over PCIE, or may use i2c, or directly respond to the corresponding data according to the spec (Standard Performance Evaluation Corporation) of the hardware chip. For example, to read the temperature of EMC1413 and other functions, it is necessary to develop and debug the relevant protocols according to the chip manual of EMC1413; and parse the received data using the various protocols supported by the protocol layer. The debugging information interface layer is used to implement the configuration function of the actual component debugging data. When reading the information of different components, different test data needs to be configured for the components. This embodiment can configure the relevant data through the web or redfis interface or IPMI (Intelligent Platform Management Interface) command, and these data will be written to the database such as Figure 2In the Redis database shown, when the hardware interface layer receives the data fed back by the programmable logic device and parses it through the protocol layer, it will go to the database to obtain the relevant debugging data and frame it in response. The command control interface is used to receive control commands issued from the outside, such as commands issued by the user. It mainly implements a series of IPMI commands and restful (Representational State Transfer) interface commands. In this embodiment, the user, such as the developer, decides whether to enter the debugging mode, the debugging protocol used, and the bus that needs to be debugged. Then the BMC will notify the programmable logic device, such as the CPLD, to cut off the connection of the corresponding actual component and connect to the debugging bus corresponding to the BMC. Start the debugging process of the BMC, control the hardware interface layer to use the correct bus, bus protocol, debugging data, etc. Through the above-mentioned BMC architecture, there is no need to frequently modify the code for the programmable logic device of a specific model. It only needs to make corresponding connections according to the server bus type and bus conditions, without worrying about the actual component type and interaction protocol.

[0071] S101: pre-connect the output pins and output bus of the BMC through a programmable logic device.

[0072] In this embodiment, the BMC is not directly connected to the actual components, but is switched through a programmable logic device. Taking into account the cost and implementation complexity, the programmable logic device can be a CPLD. The programmable logic device of the present application may also include multiple debug buses in addition to input pins and output pins. All output pins and output buses of the BMC are connected to the input pins of the programmable logic device, that is, the pins and buses presented to the outside by the BMC, such as the I2C bus, SPI (Serial Peripheral Interface) bus, LPC (Low Pin Count Bus) bus, PCIE bus, SIO (Super Input and Output Chip) and ordinary GPIO (General-purpose input / output), etc., are all used as inputs of programmable logic devices such as CPLD. The output pins are used to connect to the actual components through the output bus, or to connect to the input pins of the BMC.

[0073] S102: Send the received BMC debugging instruction to the programmable logic device to connect the bus to be debugged with the debugging bus corresponding to the programmable logic device, and simultaneously cut off the physical connection between the bus to be debugged and the component to be debugged through the output bus of the programmable logic device.

[0074] In this embodiment, to debug a specific component, the user issues a BMC debug command to the BMC. The BMC debug command specifies the debug protocol, the bus to be debugged, the component to be debugged, the debug time, and other information. When not in debug mode, the programmable logic device (PLD) is physically connected to the actual component via an output bus. However, when in debug mode, the PLD interacts with virtual components within the BMC, requiring the physical connection between the bus to be debugged and the component to be debugged via the PLD's output bus to be disconnected. The programmable logic device (CPLD) can configure corresponding output buses based on the number and type of input buses, where the output buses are connected to specific external devices. Furthermore, the CPLD pre-sets another type of debug bus output, which is routed according to commands sent by the BMC. When the CPLD enters BMC debug mode, it connects the corresponding bus to the corresponding debug bus according to the BMC's commands. For example, if the BMC's I2C2 function needs to be debugged, the CPLD connects the I2C2 bus input to the debug I2C bus and simultaneously disconnects the I2C2 from the actual connected component.

[0075] S103: Based on the BMC debugging instruction, switch to the bus to be debugged to receive data information of the bus to be debugged.

[0076] After the connection between the programmable logic device and the BMC is completed in the above steps, the BMC performs bus switching at the hardware interface layer and switches to the bus to be debugged, so as to receive data fed back by the programmable logic device through the bus to be debugged.

[0077] S104: Invoke the debugging protocol to parse the data information, and obtain corresponding target debugging data according to the parsing result to respond to the BMC debugging instruction.

[0078] Based on the data information fed back by the programmable logic device in the previous step, the corresponding debugging protocol is invoked to parse the data and obtain the data analysis results. Based on the analysis results, the debugging data of the component to be debugged is obtained from the BMC. Specifically, the debugging data of each component can be pre-configured and stored in a database. In this way, the debugging data of the component to be debugged can be directly obtained from the database in this step. The target debugging data in this step is the debugging data of the component to be debugged obtained from the BMC. It may or may not be the same as the pre-configured debugging data. If it is different, it indicates that the BMC data acquisition logic is incorrect.

[0079] In the technical solution provided by the embodiment of the present invention, debugging data for virtual components corresponding to each component to be debugged is pre-configured within the BMC. The programmable logic device can be connected to the component to be debugged and the BMC simultaneously. Whether the programmable logic device is connected to the actual component or interacts with the virtual component within the BMC is determined based on actual needs. This allows for self-testing during BMC development when the component to be tested does not yet meet test conditions. This ensures the accuracy of the developed code, such as the processing logic of upper-layer applications and underlying drivers. This is concise, convenient, and easy to execute, effectively shortening the software development cycle and reducing software development and debugging costs.

[0080] In order to further improve debugging convenience and reduce debugging costs, based on the above embodiment, before obtaining corresponding target debugging data according to the analysis result, the following steps may be further included:

[0081] When receiving a debugging data configuration command for a component to be debugged, determining whether there is original debugging data for the component to be debugged;

[0082] If there is original debugging data of the component to be debugged, the original debugging data is updated according to the debugging data configuration command;

[0083] If the original debugging data of the component to be debugged does not exist, debugging data is generated for the component to be debugged.

[0084] In this embodiment, the original debugging data refers to the debugging data configured for the component to be debugged before the current moment. The debugging data configuration command can be debugging data for a newly added physical component, or can be modification or deletion of the original debugging data.

[0085] It is understandable that the target debugging data obtained based on the analysis results may not be completely identical to the debugging data pre-configured in the BMC for the component to be debugged. For example, errors may occur in the BMC's data reading logic. Based on this, the present application further provides an embodiment of accuracy checking, which may include the following:

[0086] In response to the data verification instruction, the data verification page is displayed to check the accuracy of the debugging data configured for the debugged component and the debug data obtained;

[0087] The data verification page includes all debugging data of the component to be debugged and target debugging data.

[0088] In this embodiment, the data verification instruction is issued by the user, and the data verification page can be a web page or a BMC management page, which does not affect the implementation of this application. The debugging data configured for the component to be debugged refers to the debugging data pre-configured in the BMC, and the debug data obtained is the data obtained by executing step S104. The debugging data of the virtual component in the BMC has a strong human-computer interaction interface, allowing the configuration of relevant data through a series of interfaces such as the web and IPMI. It can also perform accuracy checks based on the configured data and the data obtained by the BMC, thereby improving debugging accuracy.

[0089] The above embodiment is for debugging operations performed on actual components by the BMC during BMC development. However, for a BMC that has been developed and built into a server, the process of sending received BMC debugging instructions to a programmable logic device may include:

[0090] When BMC debugging is required and the component to be debugged meets the debugging conditions, the bus debugging instruction is output through the BMC and sent to the programmable logic device at the same time; based on the bus debugging instruction, the working mode of the BMC's bus to be debugged and the debugging bus corresponding to the bus to be debugged in the programmable logic device is set to debugging mode.

[0091] In this embodiment, a normally operating server does not need to start the BMC debugging process, nor does a programmable logic device (CPLD) need to enter debug mode. This means that this function does not affect the normal operation of the server or the BMC's monitoring of various physical components. Only when debugging is required and the debugging conditions are met will the BMC issue a bus debug command, notifying the programmable logic device (CPLD) to enter debug mode on the BMC and the corresponding bus of the programmable logic device. The "debugging conditions" refer to the presence of the software and hardware environment (e.g., versions, protocols, and physical connections) of the component to be debugged. Entering debug mode does not affect the normal monitoring and operation of other non-debugging buses, thus minimizing the impact on the server and ensuring stable server operation.

[0092] In addition, some probabilistic problems and phenomena will disappear after the BMC is restarted. Such problems and phenomena cannot be well captured and reproduced. Moreover, the monitoring of many components requires debugging after power is turned off. This situation not only increases the difficulty of BMC debugging, but also wastes a lot of manpower, material and financial resources to solve the problem, increasing the debugging cost of the entire BMC. Based on this, the present application also provides another embodiment, including:

[0093] If the debugging condition of the component to be debugged is restart or power off, based on the bus debugging instruction, the working mode of the bus to be debugged of the BMC and the debug bus corresponding to the bus to be debugged in the programmable logic device is set to debug mode without performing the restart operation or power off operation.

[0094] In this embodiment, in order to address the situation where a restart or power outage is required to replace components and perform component debugging, this embodiment allows a bus to be forced into debugging mode during normal operation. After entering the debugging mode, debugging can be performed by reading relevant information from the virtual components in the BMC, which has little impact on the entire server and can reduce the debugging cost and difficulty of the BMC.

[0095] Understandably, the various operating components in servers currently use different manufacturers and diverse interaction protocols. Even different models of components from the same manufacturer have different protocols. To accommodate this diversity, the BMC's internal monitoring code logic has become increasingly complex. Even with a highly scalable and redundant architecture, various component interaction issues can arise during field operation, especially when component firmware versions are inconsistent, upgrades are made, or even when components fail. This can lead to BMC monitoring issues. When customers report BMC monitoring anomalies, the BMC is unable to clearly determine or obtain evidence to confirm whether the anomaly is caused by inconsistent component versions, a component problem causing the associated symptoms, or a problem with the BMC's monitoring logic or driver. Resolving these issues requires significant human and material investment in analyzing and debugging the BMC. This process ultimately leads to the identification of a component or other related issue, even though the BMC logic is operating flawlessly. Alternatively, component developers may invest significant effort but ultimately identify a BMC issue. This results in inefficient troubleshooting and fault location after monitoring failures, hindering stable server operation. Based on this, this application also provides a baseboard management controller monitoring method, please

[0096] See also Figure 3 , Figure 3 This is a flow chart of a baseboard management controller monitoring method provided by an embodiment of the present invention. The embodiment of the present invention can be applied to a server where a BMC is located, and specifically may include the following contents:

[0097] When designing a server, all output pins and buses of the SOC chip running the BMC are transferred through a programmable logic device such as a CPLD. That is, the external pins and buses of the processor where the BMC is located, such as the I2C bus, are used as inputs of the programmable logic device.

[0098] S301: When a BMC monitoring abnormality is detected, the BMC is set to enter a debugging mode.

[0099] S302: Debug the target component using the method steps in any of the above baseboard management controller debugging method embodiments.

[0100] S303: Acquire feedback information when the BMC is in debugging mode.

[0101] S304: If the feedback information is normal, determine whether the information acquisition logic, information processing logic, and underlying driver functions of the BMC are normal.

[0102] In this embodiment, the target component can be any hardware that has the debugging conditions and is monitored by the BMC. If the BMC monitoring is abnormal, the method proposed in this embodiment can be used to prove one's innocence and troubleshoot the problem. When in debugging mode, the virtual component feedback information implemented by the BMC is normal, which at least shows that there is no problem with the BMC's information acquisition and processing logic, including the underlying driver, which means that the monitoring anomaly caused by the BMC logic anomaly has been ruled out. This requires the component developer to intervene for analysis and debugging. When in debugging mode, the virtual component feedback information implemented by the BMC is abnormal, which means that there is a problem with the BMC's information acquisition and processing logic, including the underlying driver. The BMC can be prioritized for anomaly detection, reducing the manpower, material and financial resources for debugging and troubleshooting, thereby improving the server's troubleshooting efficiency and improving the server's fault repair efficiency.

[0103] It should be noted that there is no strict order in which the steps in this application are performed. As long as they comply with the logical order, these steps can be performed simultaneously or in a predetermined order. Figure 1 and Figure 3 This is just a schematic and does not mean that this is the only execution order.

[0104] In order to make those skilled in the art more clearly understand the technical solution of the present application, the present application also provides an illustrative example to illustrate the above technical solution, which may include:

[0105] When it is detected that the BMC reports an error when monitoring RAID (Redundant Arrays of Independent Disks) through the PCIE bus, the RAID needs to be debugged. Accordingly, the bus to be debugged is the PCIE bus. The user sends a debugging instruction to the BMC to turn on the debugging mode function and specify the debugging protocol and the bus to be debugged. The BMC then enters the debugging mode and switches the current bus to the PCIE bus through the hardware interface layer, and sends the debugging instruction to the CPLD. At this time, the first output bus of the CPLD is connected to the RAID. After receiving the debugging instruction, the CPLD enters the debugging mode, cuts off the physical connection between the first output bus and the hard disk, and connects the PCIE bus to the corresponding debugging bus in the CPLD. The CPLD feeds back data to the BMC through the debugging bus. The BMC calls the corresponding protocol of the protocol layer to parse the received data and reads the debugging data of the RAID in the database based on the parsing results.

[0106] As can be seen from the above, the embodiments of the present invention can effectively shorten the software development cycle and reduce software development and debugging costs.

[0107] The embodiments of the present invention also provide a corresponding apparatus for the baseboard management controller debugging method, further enhancing the practicality of the method. The apparatus can be described from the perspective of functional modules and hardware. The following describes the baseboard management controller debugging apparatus provided by the embodiments of the present invention. The baseboard management controller debugging apparatus described below can be used in conjunction with the baseboard management controller debugging method described above.

[0108] From the perspective of functional modules, see Figure 4 , Figure 4 A structural diagram of a baseboard management controller debugging device provided in an embodiment of the present invention in a specific implementation manner, the device may include:

[0109] The pre-deployment module 401 is used to pre-connect the output pins and output buses of the BMC through a programmable logic device; the programmable logic device also includes multiple debugging buses.

[0110] The debugging instruction sending module 402 is used to send the received BMC debugging instruction to the programmable logic device to connect the bus to be debugged with the debugging bus corresponding to the programmable logic device, and at the same time cut off the physical connection between the bus to be debugged and the component to be debugged through the output bus of the programmable logic device; the BMC debugging instruction includes a debugging protocol and a bus to be debugged.

[0111] The hardware interface switching module 403 is configured to switch to the bus to be debugged based on the BMC debugging instruction to receive data information of the bus to be debugged.

[0112] The data analysis module 404 is used to call the debugging protocol to analyze the data information.

[0113] The debugging module 405 is used to obtain corresponding target debugging data according to the analysis result to respond to the BMC debugging instruction.

[0114] Optionally, in some implementations of this embodiment, the above-mentioned device may further include a data configuration module, which is used to determine whether the original debugging data of the component to be debugged exists when receiving the debugging data configuration command of the component to be debugged; if the original debugging data of the component to be debugged exists, update the original debugging data according to the debugging data configuration command; if the original debugging data of the component to be debugged does not exist, generate debugging data for the component to be debugged.

[0115] Optionally, in some other implementations of this embodiment, the above-mentioned device may also include a verification module, for example, for responding to a data verification instruction and displaying a data verification page to check the accuracy of the debugging data configured for the component to be debugged and the debugging data obtained; wherein the data verification page includes all debugging data of the component to be debugged and the target debugging data.

[0116] Optionally, in some other implementations of this embodiment, the above-mentioned debugging instruction sending module 402 can be further used for: the BMC is built into the server, and when BMC debugging is required and the component to be debugged meets the debugging conditions, the bus debugging instruction is output through the BMC, and the bus debugging instruction is sent to the editable logic device at the same time; based on the bus debugging instruction, the working mode of the BMC's bus to be debugged and the debugging bus corresponding to the bus to be debugged in the programmable logic device is set to debugging mode.

[0117] As an optional implementation of the above embodiment, the above debugging instruction issuing module 402 can also be further used for: if the debugging condition of the component to be debugged is restart or power off, based on the bus debugging instruction, without performing a restart operation or a power off operation, the working mode of the BMC's bus to be debugged and the debugging bus corresponding to the bus to be debugged in the programmable logic device is set to debugging mode.

[0118] In addition, this embodiment also provides a baseboard management controller monitoring device, Figure 5 A structural diagram of a baseboard management controller debugging device provided in an embodiment of the present invention in a specific implementation manner, the device may include:

[0119] The debugging module 501 is used to set the BMC to enter a debugging mode when a BMC monitoring anomaly is detected, and to debug a target component using any of the above baseboard management controller debugging methods.

[0120] The information acquisition module 502 is used to obtain feedback information when the BMC is in debugging mode.

[0121] The fault diagnosis module 503 is configured to determine whether the information acquisition logic, information processing logic and underlying driver functions of the BMC are normal if the feedback information is normal.

[0122] The functions of the functional modules of the baseboard management controller debugging device and the baseboard management controller monitoring device in the embodiment of the present invention can be specifically implemented according to the method in the above method embodiment. The specific implementation process can refer to the relevant description of the above method embodiment and will not be repeated here.

[0123] As can be seen from the above, the embodiments of the present invention can effectively shorten the software development cycle and reduce software development and debugging costs.

[0124] The baseboard management controller debugging device mentioned above is described from the perspective of functional modules. Furthermore, the present application also provides an electronic device, which is described from the perspective of hardware. Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application in one embodiment. Figure 6 As shown, the electronic device includes a memory 60 for storing computer programs; a processor 61 for implementing the steps of the baseboard management controller debugging method and / or baseboard management controller monitoring method mentioned in any of the above embodiments when executing the computer program.

[0125] The processor 61 may include one or more processing cores, such as a 4-core processor or an 8-core processor. The processor 61 may also be a controller, a microcontroller, a microprocessor, or other data processing chip. The processor 61 may be implemented in at least one hardware form selected from the group consisting of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). The processor 61 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 61 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 61 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0126] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In some embodiments, the memory 60 may be an internal storage unit of an electronic device, such as a hard disk of a server. In other embodiments, the memory 60 may also be an external storage device of an electronic device, such as a plug-in hard disk equipped on a server, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. Furthermore, the memory 60 may also include both an internal storage unit of an electronic device and an external storage device. The memory 60 can not only be used to store application software installed on the electronic device and various types of data, such as the code of the program that executes the vulnerability handling method, but can also be used to temporarily store data that has been output or is to be output. In this embodiment, the memory 60 is used to store at least the following computer program 601, wherein, after being loaded and executed by the processor 61, the computer program can implement the relevant steps of the baseboard management controller debugging method and / or baseboard management controller monitoring method disclosed in any of the aforementioned embodiments. In addition, the resources stored in memory 60 may also include an operating system 602 and data 603, which may be stored in a temporary or permanent manner. Operating system 602 may include Windows, Unix, Linux, etc. Data 603 may include, but is not limited to, baseboard management controller debugging results and / or data corresponding to baseboard management controller monitoring results.

[0127] In some embodiments, the electronic device may further include a display screen 62, an input / output interface 63, a communication interface 64 or a network interface, a power supply 65 and a communication bus 66. Among them, the display screen 62 and the input / output interface 63 such as a keyboard belong to the user interface, and the optional user interface may also include a standard wired interface, a wireless interface, etc. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, and an OLED (Organic Light-Emitting Diode) touch device, etc. The display may also be appropriately referred to as a display screen or a display unit, which is used to display information processed in the electronic device and to display a visual user interface. The communication interface 64 may optionally include a wired interface and / or a wireless interface, such as a WI-FI interface, a Bluetooth interface, etc., which is generally used to establish a communication connection between the electronic device and other electronic devices. The communication bus 66 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0128] Those skilled in the art will understand that Figure 6 The structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure, for example, it may also include a sensor 67 to realize various functions.

[0129] The functions of the functional modules of the electronic device in the embodiment of the present invention can be specifically implemented according to the method in the above method embodiment. The specific implementation process can refer to the relevant description of the above method embodiment, which will not be repeated here.

[0130] As can be seen from the above, the embodiments of the present invention can effectively shorten the software development cycle and reduce software development and debugging costs.

[0131] It is understandable that if the baseboard management controller debugging method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium and executes all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, multimedia card, card-type memory (such as SD or DX memory, etc.), magnetic memory, removable disk, CD-ROM, magnetic disk or optical disk, etc. Various media that can store program code.

[0132] Based on this, an embodiment of the present invention further provides a readable storage medium storing a computer program. When the computer program is executed by a processor, the steps of the baseboard management controller debugging method and / or the baseboard management controller monitoring method in any of the above embodiments are performed.

[0133] The present invention also provides a baseboard management controller debugging system, see Figure 7 , which may include:

[0134] The baseboard management controller debugging system may include a BMC 71, a programmable logic device 72, and a component to be debugged 73. The output pins and output bus of the BMC 71 are connected to the input pins of the programmable logic device 72, and the output bus of the programmable logic device 72 is connected to the component to be debugged 73.

[0135] The BMC 72 is used to call a computer program stored in a memory to execute the steps of any of the above baseboard management controller debugging method embodiments on the component to be debugged.

[0136] The bus switching method of the programmable logic device 72 can include internal switching and external switching, depending on the type of output pins. In the first method, the programmable logic device includes first-class output pins and second-class output pins. The first-class output pins are connected to each component to be debugged via corresponding output buses, while the second-class output pins are connected to the input pins of the BMC via corresponding output buses. In the second method, the programmable logic device includes only one type of output pin, and the entire system may also include a conversion chip. The output pins of the programmable logic device are connected to the conversion chip. If the BMC is in debug mode, the conversion chip is connected to the BMC input pins. If the BMC is not in debug mode, the conversion chip is connected to each component to be debugged.

[0137] Finally, the embodiment of the present invention also provides a baseboard management controller management system, see Figure 8 , which may include:

[0138] A baseboard management controller monitoring system may include a server 81, a programmable logic device 82, and a component to be debugged 83. Server 81 has a built-in BMC. The output pins and output bus of the SOC chip running the BMC are connected to the input pins of the programmable logic device. The output bus of the programmable logic device 82 is connected to the component to be debugged 83. The BMC is used to implement the steps of the aforementioned baseboard management controller monitoring method embodiment when executing a computer program stored in a memory.

[0139] In this embodiment, a programmable logic device (CPLD) also includes two bus control methods. One method is to internally control the bus path. Specifically, the CPLD includes two types of pins: input pins and output pins. There is only one set of input pins (which may include the I2C bus, PECI bus, etc.), and two sets of output pins: one set connected to actual component devices (this set also includes the I2C bus, PECI bus, etc.), and the other set connected to the input pins of the BMC. In actual use, whether the CPLD output interacts with actual components or with internal BMC modules is controlled by the CPLD, and the CPLD's control instructions are issued by the BMC. A second solution involves connecting a specific chip external to the CPLD to control the bus path. That is, the CPLD includes two types of pins, one is input pins and the other is output pins. There is only one group of input pins (including i2c bus, peci bus, etc.), and the output pins include a group (this group also includes i2c bus, peci bus, etc.). This group of output buses is connected to a specific conversion chip. The chip implements the interaction between the bus and the components or the control of the interaction with the debugging components of the BMC. The chip is controlled by sending instructions through the CPLD, and the CPLD is controlled by sending instructions through the BMC.

[0140] The functions of the various functional modules of the above-mentioned system in the embodiment of the present invention can be specifically implemented according to the method in the above-mentioned method embodiment. The specific implementation process can refer to the relevant description of the above-mentioned method embodiment, which will not be repeated here.

[0141] As can be seen from the above, the embodiments of the present invention can effectively shorten the software development cycle and reduce software development and debugging costs.

[0142] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. References to the same or similar parts between the various embodiments are sufficient. The hardware disclosed in the embodiments, including devices and electronic devices, is described briefly because it corresponds to the methods disclosed in the embodiments. For relevant details, refer to the method description.

[0143] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0144] The above is a detailed introduction to a baseboard management controller debugging method, device and system, baseboard management controller monitoring method, device and system, electronic device, and readable storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of this application.

Claims

1. A baseboard management controller debugging method, characterized in that: include: Transfer the BMC output pins and output bus through programmable logic devices in advance; The programmable logic device further comprises a plurality of debug buses; Sending the received BMC debugging instruction to the programmable logic device to connect the bus to be debugged to the debug bus corresponding to the programmable logic device, and at the same time cutting off the physical connection between the bus to be debugged and the component to be debugged through the output bus of the programmable logic device; The BMC debugging instruction includes a debugging protocol and a bus to be debugged; Based on the BMC debugging instruction, switching to the bus to be debugged to receive data information of the bus to be debugged; The debugging protocol is called to parse the data information, and corresponding target debugging data is obtained according to the parsing result to respond to the BMC debugging instruction.

2. The baseboard management controller debugging method according to claim 1, characterized in that: Before obtaining the corresponding target debugging data according to the analysis result, the method further includes: When receiving the debugging data configuration command of the component to be debugged, determining whether there is original debugging data of the component to be debugged; If original debugging data of the component to be debugged exists, updating the original debugging data according to the debugging data configuration command; If the original debugging data of the component to be debugged does not exist, debugging data is generated for the component to be debugged.

3. The baseboard management controller debugging method according to claim 2, characterized in that: After obtaining the corresponding target debugging data according to the analysis result, the method further includes: In response to the data verification instruction, a data verification page is displayed to check the accuracy of the debugging data configured for the component to be debugged and the debugging data obtained; The data verification page includes all debugging data of the component to be debugged and the target debugging data.

4. The baseboard management controller debugging method according to any one of claims 1 to 3, characterized in that: The BMC is built into the server, and sending the received BMC debugging instruction to the programmable logic device includes: When BMC debugging is required and the component to be debugged meets the debugging conditions, a bus debugging instruction is output through the BMC, and the bus debugging instruction is sent to the programmable logic device at the same time; Based on the bus debugging instruction, the working mode of the bus to be debugged of the BMC and the debugging bus corresponding to the bus to be debugged on the programmable logic device is set to a debugging mode.

5. The baseboard management controller debugging method according to claim 4, characterized in that: The step of setting the operating mode of the bus to be debugged of the BMC and the corresponding debug bus of the programmable logic device to a debug mode based on the bus debug instruction includes: If the debugging condition of the component to be debugged is restart or power off, based on the bus debugging instruction, without performing a restart operation or a power off operation, the working mode of the bus to be debugged of the BMC and the debugging bus of the programmable logic device corresponding to the bus to be debugged is set to debug mode.

6. A baseboard management controller debugging device, characterized in that: include: Pre-deployment module, used to pre-connect the BMC output pins and output bus through programmable logic devices; The programmable logic device further comprises a plurality of debug buses; a debugging instruction issuing module, configured to send the received BMC debugging instruction to the programmable logic device to connect the bus to be debugged to the debug bus corresponding to the programmable logic device, and simultaneously cut off the physical connection between the bus to be debugged and the component to be debugged through the output bus of the programmable logic device; The BMC debugging instruction includes a debugging protocol and a bus to be debugged; A hardware interface switching module is used to switch to the bus to be debugged based on the BMC debugging instruction to receive data information of the bus to be debugged; A data parsing module, configured to call the debugging protocol to parse the data information; The debugging module is used to obtain corresponding target debugging data according to the analysis result to respond to the BMC debugging instruction.

7. A baseboard management controller debugging system, characterized in that: Including BMC, programmable logic devices and components to be debugged; The output pins and output bus of the BMC are connected to the input pins of the programmable logic device, and the output bus of the programmable logic device is connected to the component to be debugged; The BMC is used to call a computer program stored in a memory to execute the steps of the baseboard management controller debugging method according to any one of claims 1 to 5 on the component to be debugged.

8. The baseboard management controller debugging system according to claim 7, characterized in that: The programmable logic device includes a first type of output pin and a second type of output pin; The first type of output pins are connected to each component to be debugged via a corresponding output bus; The second type of output pins are connected to the input pins of the BMC via corresponding output buses.

9. The baseboard management controller debugging system according to claim 7, characterized in that: Also includes conversion chips; The output pin of the programmable logic device is connected to the conversion chip; If the BMC is in debugging mode, the conversion chip is connected to the input pin of the BMC; If the BMC is not in the debugging mode, the conversion chip is connected to each component to be debugged.

10. A baseboard management controller monitoring method, characterized in that: include: When a BMC monitoring anomaly is detected, setting the BMC to enter a debugging mode, and debugging the target component using the baseboard management controller debugging method according to any one of claims 1 to 5; Obtaining feedback information when the BMC is in the debugging mode; If the feedback information is normal, it is determined that the information acquisition logic, information processing logic and underlying driving functions of the BMC are normal.

11. A baseboard management controller monitoring device, characterized in that: include: a debugging module, configured to, when detecting a BMC monitoring anomaly, set the BMC to enter a debugging mode and debug a target component using the baseboard management controller debugging method according to any one of claims 1 to 5; An information acquisition module, configured to acquire feedback information when the BMC is in the debugging mode; The fault diagnosis module is configured to determine whether the information acquisition logic, information processing logic and underlying driver functions of the BMC are normal if the feedback information is normal.

12. A baseboard management controller monitoring system, characterized in that: Including servers, programmable logic devices and components to be debugged; The server has a built-in BMC, the output pins and output bus of the SOC chip running the BMC are connected to the input pins of the programmable logic device, and the output bus of the programmable logic device is connected to the component to be debugged; The BMC is used to implement the steps of the baseboard management controller monitoring method as claimed in claim 10 when executing the computer program stored in the memory.

13. An electronic device, characterized in that: The system comprises a processor and a memory, wherein the processor is configured to implement the steps of the baseboard management controller debugging method according to any one of claims 1 to 5 and / or the baseboard management controller monitoring method according to claim 10 when executing the computer program stored in the memory.

14. A readable storage medium, characterized in that The readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the baseboard management controller debugging method according to any one of claims 1 to 5 and / or the baseboard management controller monitoring method according to claim 10.

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