Memory, memory control method and system

Abstract

Disclosed are a memory, a memory control method, and a corresponding system. The memory includes: a memory cell array; and a memory cell array operation module, including: a read operation module, enabled in response to the memory receiving a memory cell array read instruction, and used to read the memory cell array; an erase operation module, enabled in response to the memory receiving a memory cell array erase instruction, and used to erase the memory cell array; and a program operation module, enabled in response to the memory receiving a memory cell array program instruction, and used to program the memory cell array. By independently setting up the read operation, program operation, and erase operation control modules, and enabling them only when the corresponding instructions are received and executed, the present invention can reduce the number of logic control circuits that need to be enabled when executing memory array operation instructions, thereby reducing the overall power consumption of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of memory, and in particular to a memory, a memory control method, and a corresponding system. Background Art

[0002] Flash memory, with its high storage density, high reliability, and low power consumption, is increasingly being used today. Flash memory includes NAND flash memory and NOR flash memory. NOR flash memory, also known as code-type memory, is typically used with microcontrollers, supports in-chip execution (XIP, eXecute In Place), and is widely used in automotive electronics, wearable devices, smart home appliances, home medical devices, and other areas. NAND flash memory is widely used in various large-capacity devices such as memory cards, USB flash drives, SSDs, and eMMCs. With the improvement of device performance and integration, as well as the characteristics of distributed applications, battery replacement or frequent charging will bring many inconveniences. Therefore, how to extend battery life and reduce device power consumption is a major challenge currently facing flash memory applications. Summary of the Invention

[0003] The present disclosure addresses a technical problem by providing an improved memory, memory control method, and corresponding system. The memory of the present invention can include independently configured read, program, and erase operation modules, each of which is enabled only upon receiving a corresponding instruction. This reduces the number of logic control circuits required to execute memory array operation instructions, thereby lowering the overall power consumption of the memory.

[0004] According to a first aspect of the present disclosure, a memory is provided, comprising: a memory cell array; and a memory cell array operation module, the operation module comprising: a read operation module, which is enabled in response to the memory receiving a memory cell array read instruction, and is used to perform a read operation on the memory cell array; an erase operation module, which is enabled in response to the memory receiving a memory cell array erase instruction, and is used to perform an erase operation on the memory cell array; and a program operation module, which is enabled in response to the memory receiving a memory cell array program instruction, and is used to perform a program operation on the memory cell array.

[0005] Optionally, the read operation module is disabled in response to completion of the read operation, the erase operation module is disabled in response to completion of the erase operation, and the program operation module is disabled in response to completion of the program operation.

[0006] Optionally, the read operation module includes: a read voltage pump, used to generate a voltage required for the read operation; and a read control circuit, used to control the data read operation of the memory cell array.

[0007] Optionally, the read control circuit includes: a read operation enable signal circuit, used to enable control of a voltage used in a read operation.

[0008] Optionally, the read voltage pump is enabled in a verify sub-operation of an erase operation and / or a program operation.

[0009] Optionally, the programming operation module includes: a programming voltage pump for generating a voltage required for the programming operation; and a programming control circuit for controlling the data programming operation of the memory cell array.

[0010] Optionally, the erase operation module includes: an erase voltage pump for generating a voltage required for the erase operation; and an erase control circuit for controlling the data erase operation of the memory cell array.

[0011] Optionally, the programming voltage pump is enabled in a soft programming sub-operation of the erase operation.

[0012] Optionally, the memory further includes: a power manager; and an instruction decoder,

[0013] Among them, the power manager is capable of supplying power to the instruction decoder in standby mode, the power manager supplies power to the read operation module in response to the storage cell array read instruction, the power manager supplies power to the programming operation module in response to the storage cell array programming instruction, and the power manager supplies power to the erase operation module in response to the storage cell array erase instruction.

[0014] Optionally, the power manager is used to: in response to receiving a low power state instruction, stop powering the instruction decoder to enter a low power state; and in response to receiving a chip selection signal, resume powering the instruction decoder to return to the standby state.

[0015] According to a second aspect of the present disclosure, a memory control method is provided, comprising: enabling a read operation module in a memory cell array operation module after the memory receives a memory cell array read instruction, the read operation module performing a read operation on the memory cell array; enabling a program operation module in the memory cell array control module after the memory receives a memory cell array program instruction, the program operation module performing a program operation on the memory cell array; and enabling an erase operation module in the memory cell array control module after the memory receives a memory cell array erase instruction, the erase operation module performing an erase operation on the memory cell array.

[0016] According to a third aspect of the present disclosure, a system is provided, comprising: a host controller; an interface bus; and the memory according to the first aspect, coupled to the host controller via the interface bus.

[0017] Therefore, the memory of the present invention reduces the size of the circuit required to execute each storage array operation instruction by using independently set read, program and erase operation modules that can be independently enabled and disabled, thereby further reducing the overall power consumption of the memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, wherein like reference numerals generally represent like components in the exemplary embodiments of the present disclosure.

[0019] Figure 1 A simplified schematic diagram of a system incorporating a memory according to one embodiment of the present invention is shown.

[0020] Figure 2 A schematic diagram showing the composition of a memory in the related art is shown.

[0021] Figure 3 A schematic diagram showing the composition of a memory according to an embodiment of the present invention is shown.

[0022] Figure 4 FIG. 4 shows a schematic diagram of memory state switching according to an embodiment of the present invention.

[0023] Figure 5 FIG. 2 shows a timing diagram of entering a read state from a standby state according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0025] Various embodiments will be described in more detail with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, like reference numerals represent like parts throughout the various figures and embodiments of the present invention.

[0026] Note that the drawings are simplified schematic diagrams and are not necessarily drawn to scale. In some cases, parts of the drawings may have been exaggerated to more clearly illustrate certain features of the illustrated embodiments.

[0027] It is further noted that in the following description, specific details are set forth to facilitate understanding of the present invention, however, the present invention may be practiced without some of these specific details. In addition, it is noted that well-known structures and / or processes may be described only briefly or not at all to avoid obscuring the present disclosure with unnecessary well-known details.

[0028] It should also be noted that in some cases, it will be apparent to those skilled in the relevant art that elements (also referred to as features) described in relation to one embodiment may be used alone or in combination with other elements of another embodiment unless specifically stated otherwise.

[0029] The various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figure 1 Describe the application environment of the present invention.

[0030] Figure 1 FIG2 is a simplified diagram of a system including a nonvolatile memory according to an embodiment of the present invention. The system 10 may be implemented as an electronic device, and the device 10 may include a host 200 and a memory 300 as shown in the figure, and communicate via a bus 100 .

[0031] Here, the host 200 refers to the part that realizes the key functions of the device 10, that is, the main part of the device 10, and the host 200 (or the device 10) can be any appropriate electronic device. In one embodiment, the device 10 can be an electronic device, including but not limited to portable electronic devices such as mobile phones, tablets, wearable devices (such as TWS headphones) and laptop computers, or non-portable electronic devices such as desktop computers, game consoles, televisions, set-top boxes and projectors, and even industrial Internet of Things devices such as independently set sensors. In this case, the memory 300 can be a device that provides storage services for independent electronic devices.

[0032] In other embodiments, the device 10 may also be an electronic device with relatively independent functions (these electronic devices are usually key components of electronic devices), such as independently sold smart screens, main control chips, camera components, etc. These electronic devices usually need to be assembled, for example, a smart screen must be assembled into a mobile phone before it can provide services to consumers (e.g., users who purchase mobile phones). In this case, the memory 300 can be a device that provides the necessary storage services for the electronic device.

[0033] Here, the host 200 may be implemented as or include a microcontroller, a microprocessor, an application-specific integrated circuit (ASIC), or an application-specific standard product (ASSP), and is coupled to a memory 300 as a slave device via a bus 100 as shown. Here, the bus 100 may be implemented as, for example, a serial peripheral interface (SPI) bus, and include a plurality of connection lines 101-104 as shown in the figure to implement the transmission of instructions, addresses, and data, thereby reading and executing the code stored in the memory 300, and erasing and writing when necessary, such as performing firmware over-the-air upgrades.

[0034] In the illustrated example, bus 100 may include at least a data input line 101, a data output line 102, a clock line 103, and a chip strobe line 104. Data input line 101 transmits data signals generated by host 200 and received by memory 300. These data signals may include instructions and address sequences. Data output line 102 transmits signals generated by memory 300 and received by host 200, such as data read from memory 300, or code executable on host 200. Clock line 103 is used to transmit the clock signal generated by host 200 to memory 300, thereby achieving synchronous data transmission between the two parties. When data transmission is required between host 200 and memory 300, the chip strobe signal on chip strobe line 104 is set to an active level, such as a low level. When data transmission is complete, the chip strobe signal on chip strobe line 104 is set to an inactive level, such as a high level. Although not shown in the figure, it should be understood that the bus 100 can also realize the connection between the host 200 and other slave or peripheral devices, and other chip enable lines will be provided for these devices.

[0035] The host 200 and the memory 300 may each include pins for making the above connections. In a preferred embodiment, the memory 300 may be implemented as a flash memory device having an SPI interface, particularly a NOR flash memory and a NAND flash memory, capable of sequentially accessing data via a serial interface (pins) and suitable for many applications such as voice, image, program code, and data storage. Specifically, the memory 300 can be enabled by a chip select signal received on a chip select (CS) pin (e.g., a specified valid "assertion" signal), and can implement data access via a data input (SI) pin, a data output (SO) pin, and a clock (CLK) pin.

[0036] The memory circuit 300 may include an input / output interface connected to the outside, the input / output interface including a data input interface, a data output interface, a clock interface, and a chip strobe interface. The input / output interface may generally be implemented as a pin including an SI pin, an SO pin, a CLK pin, and a CS pin, wherein the SI pin corresponds to the data input interface, the SO pin corresponds to the data output interface, the CLK pin corresponds to the clock interface, and the CS pin corresponds to the chip strobe pin / interface. The above pins may each be used Figure 1 The bus 100 shown, in particular the SPI bus includes a data input line 101, a data output line 102, a clock line 103 and a chip selection line 104 for exchanging data with the outside, such as a host, thereby realizing data reading, erasing or writing under the control of the host.

[0037] It can be understood that although the SI pin, SO pin, CLK pin and CS pin are collectively referred to as input and output interfaces, in actual operation, the SI pin, CLK pin and CS pin can be designated to obtain external signals; the SO pin is designated to output data to the outside, such as the program code read from the memory 300, or the status signal stored in the internal register of the memory 300. Furthermore, the SI pin, CLK pin and CS pin are each used to obtain signals of different properties from the outside. Specifically, the instruction sent by the host 200 to the memory 300 can be an operator, and the operator includes multiple bits (for example, 8 bits), and the SI pin sequentially obtains the operator. The instruction obtained by the SI pin cannot usually be used directly to control the memory, but needs to be decoded by a decoding device (for example, via Figure 2 The instruction decoder 331 in the memory is used to convert the instruction into a control instruction recognizable in the memory. The CLK pin is used to receive the host's clock signal (e.g., a clock pulse of a specific frequency) to facilitate synchronous data transmission. For example, at the rising edge of the clock signal, the host 200 sends data and the memory 300 receives data. The CS pin obtains the chip select signal from the host 200. The chip select signal can be a select pulse or an active level that lasts for a predetermined time (e.g., when the chip select signal is low, the memory 300 can receive the clock and data from the host 200; when the chip select signal is high, the memory 300 ignores the clock and data on the clock line 103 and the data input line 101). The internal operation of the memory can usually be changed directly based on the chip select signal.

[0038] Figure 2A schematic diagram of the composition of a memory device in the related art is shown. Memory 300 includes an input / output buffer 211, a power manager 221, a voltage pump 222, an ID register 251, an instruction decoder 231, a controller 232, a memory array 241, a column decoder 242, a row decoder 243, and a readout circuit 245. Memory array 241 includes multiple memory cells arranged in an array and addressable via word lines and bit lines. A memory cell can be a transistor having a floating gate or an insulating layer capable of trapping charge. The memory cell also includes a substrate, a source, a drain, and a control gate. The floating gate and substrate are separated by a tunneling insulating layer, and the floating gate and control gate are separated by an insulating layer. The threshold voltage of the transistor is related to the amount of charge trapped in the floating gate. When the floating gate has a large amount of charge trapped, the memory cell stores a logic 0; when the floating gate has no charge trapped, the memory cell stores a logic 1. The row decoder 243 is used to select a word line based on the address. The column decoder 242 is used to select a bit line based on the address. The read circuit 245 is used to perform read and verify operations on the memory array 241. The power manager 221 is used to power the voltage pump 222, the instruction decoder 231, the controller 232, the memory array 241, the column decoder 242, the row decoder 243, and the read circuit 245. The ID register 251 is used to store information such as the memory ID and the memory manufacturer ID. The memory 300 also includes an internal clock for providing a clock signal for the operation of the memory array 241. Accordingly, the clock signal on the clock line 103 can be referred to as an external clock. The charge pump 222 is used to provide voltage for the operation of the memory array 241. The charge pump 222 may include multiple charge pump circuits, each used to generate the voltage required for the read operation, the programming operation, and the erase operation.

[0039] With the further miniaturization of portable and wearable devices, as well as the prevalence of distributed devices such as those used in IoT applications, it is expected that memories will be able to further reduce power consumption. Common memories (e.g., low-power NOR flash memory) utilize the same controller to execute all memory array operation instructions, including read instructions, program instructions, and erase instructions. Because the control module needs to have the ability to control read, program, and erase operations simultaneously, it is implemented as a logic control circuit that includes a large number of devices. When the logic control circuit is executing instruction operations, the devices included in the circuit will still have a certain amount of leakage current even if they are not enabled, resulting in increased power consumption of the memory.

[0040] To this end, the present invention proposes a memory device comprising independently configured read, program, and erase control modules. These modules can be enabled only when corresponding commands are received and disabled at other times. This reduces the number of logic control circuits required to execute memory array operation commands, thereby lowering the overall power consumption of the memory device.

[0041] Figure 3 A schematic diagram showing the composition of a memory according to an embodiment of the present invention is shown. Figure 3 The memory 300 shown includes an input / output buffer 311, a power manager 321, an operation module, an ID register 351, an instruction decoder 331, a storage array 341, a column decoder 342, a row decoder 343 and a readout circuit 345. Figure 2 Yes, Figure 3 In the memory shown in FIG, the operation module includes a read operation module, an erase operation module and a program operation module respectively set for the read operation, the erase operation and the program operation. The above operation module as a whole can play a role, for example, Figure 2 The controller 332 and the voltage pump 322 are shown to function and may each include a control circuit portion and a voltage pump portion.

[0042] The memory array 341 includes multiple memory cells arranged in an array and addressable via word lines and bit lines. A row decoder 343 is used to select a word line based on an address. A column decoder 342 is used to select a bit line based on an address. A read circuit 345 is used to perform read and verify operations on the memory array 341. Data received from the input / output interface can be temporarily stored in the input / output buffer 311 and then transmitted to the instruction decoder 331. The data input line 101 and the data output line 102 support a serial protocol. For example, during a read operation, data received via the data input line 101 to be written to the memory array 341 is first stored in the shift register of the input / output buffer 311 and then shifted to the data register. Instructions received via the data input line 101 are first stored in the shift register of the input / output buffer 311 and then provided to the instruction decoder 331.

[0043] In some embodiments, the signals obtained from the SI pin, the CLK pin, and the CS pin may be buffered in a data input buffer, a clock buffer, and a chip strobe signal buffer, respectively, in the input / output buffer 311. Accordingly, the input / output buffer 311 may further include a data output buffer for buffering data to be output via the SO pin.

[0044] The instruction decoder 331 reads instruction signals received by the SI pin from the data input buffer of the input / output buffer 311 and decodes them into internal instructions that the memory can execute. The internal instructions send control signals to the power manager 321. In response to the control signals, the power manager 321 supplies power to the read operation module, the erase operation module, and the program operation module.

[0045] Although not shown in the figure, the memory 300 may include a power interface for receiving an external power source, such as a pin for receiving an external voltage VCC (e.g., a first voltage). This pin may, for example, receive power from a power supply device in the system (e.g., electronic device 10). Furthermore, the memory 300 may also include a pin connected to the system ground. The input and output interfaces of the memory 300 may typically operate directly at the external voltage VCC, while the operation module, instruction decoder 331, memory array 341, column decoder 342, row decoder 343, and readout circuit 345 typically operate at a voltage different from VCC (i.e., the memory's operating voltage VDD, e.g., a second voltage). VDD is typically lower than VCC, thus requiring a power manager 321 to provide the operating voltage VDD to the components in the memory. In other embodiments, the external voltage VCC may be the same as the memory's operating voltage VDD. The power manager 321 can be used to power the various components operating at the VDD voltage.

[0046] like Figure 3 As shown, the read operation module can read the memory cell array ( Figure 3 A read operation is performed on the memory module in the memory array 341, for example, with the help of the column decoder 342, the row decoder 343 and the read circuit 345 of the memory module, data at a specified position of the memory array 341 is read out.

[0047] The read operation module may include a read control circuit 3321 and a read voltage pump 3221. The read control circuit 3321 may be used to control the data read operation of the memory cell array. Specifically, during the read operation, when the voltage is applied, when the application stops, and the timing of the voltage require enable signal control. To this end, the read control circuit 3321 may include a read operation enable signal circuit for enabling control of the voltage used in the read operation, that is, providing these enable signals. Furthermore, the read control circuit 3321 includes a state machine that implements the logic control of each step of the read operation. Furthermore, during the read operation, parameters such as the data read rate also need to be configured. To this end, the read control circuit 3321 may also include a read operation parameter selection circuit for configuring the parameters of the read operation.

[0048] The read voltage pump 3221 can be used to generate the voltages required for read operations. For example, the read voltage pump 3221 can generate a read voltage applied to a selected word line, a pass voltage (for NAND flash memory), or a negative voltage (for NOR flash memory) applied to unselected word lines.

[0049] The program operation module can program the memory cell array ( Figure 3For example, with the help of the column decoder 342 and the row decoder 343 of the storage module, data is written to a specified position of the storage array 341.

[0050] The programming operation module may include a programming control circuit 3322 and a programming voltage pump 3222. The programming control circuit 3322 may be used to control the data write operation of the memory cell array. Specifically, in the programming operation, the magnitude and timing of the applied voltage also require enable signal control. To this end, the programming control circuit 3322 may include a programming operation enable signal circuit for enabling control of the voltage used in the programming operation. Furthermore, the programming control circuit 3322 also includes a state machine for implementing the logic control of each step of the programming operation. Furthermore, in the programming operation, parameters such as how many bytes to program at a time may also be configured. The programming control circuit 3322 may also include a programming operation parameter selection circuit for configuring parameters for the programming operation.

[0051] The programming voltage pump 3222 can be used to generate the voltage required for the programming operation. More specifically, programming a memory cell also involves the participation of multiple voltages. For example, in a NOR flash memory programming operation, a word line programming voltage is applied to the selected word line and a bit line programming voltage is applied to the selected bit line, thereby achieving the writing of 0 to the target memory cell. In a NAND flash memory programming operation, a programming voltage is applied to the word line corresponding to the target page (the selected word line), that is, a positive voltage (for example, 20V) can be applied to the control gates of all transistors in the page, and a programming turn-on voltage is applied to the unselected word lines. Accordingly, according to the distribution of the target data 0 and 1, a programming enable voltage (for example, a ground voltage) and a programming inhibit voltage (for example, a positive voltage of 2.5V) are applied to the selected bit line and the unselected bit line, respectively. After the programming enable voltage is applied to the bit line corresponding to the memory cell, electrons are attracted by the positive voltage applied to the control gate and enter the floating gate through the insulating layer, completing the writing of 0 to the memory cell. In both NOR and NAND implementations, the programming voltage pump 3222 can be used solely to generate wordline programming voltages, bitline programming voltages, programming on-voltages, and programming inhibit voltages. In some embodiments, the programming operation also includes a verification sub-operation after the programming voltage application step, for example, reading the programmed memory cells to verify that the data was correctly stored. In this case, the read charge pump 3221 is also called upon to generate the required voltages on the selected wordline and unselected wordlines, thereby completing the verification sub-operation included in the programming operation.

[0052] The operation module also includes an erase operation module, which can perform an erase operation on the memory cell array based on the memory cell array erase instruction. For example, with the help of the column decoder 342 and the row decoder 343 of the memory module, data at a specified position of the memory array 341 can be erased.

[0053] The erase operation module may include an erase control circuit 3323 and an erase voltage pump 3223. The erase control circuit 3323 may be used to control the data erase operation of the memory cell array. Specifically, the erase operation also involves the selection of the magnitude and application time of the erase voltage and the setting of related parameters. To this end, the erase control circuit 3323 may include an erase operation enable signal circuit for enabling the voltage used in the erase operation, and an erase operation parameter selection circuit for configuring the parameters of the erase operation. Furthermore, the erase control circuit 3323 also includes a state machine for implementing the logic control of each step of the erase operation.

[0054] The erase voltage pump 3223 is used to generate the voltages required for the erase operation. For example, for NAND flash memory, the erase voltage pump 3223 is used to generate a positive voltage of up to 20V applied to the substrate. For NOR flash memory, the erase voltage pump 3223 includes a positive voltage pump and a negative voltage pump. The positive voltage pump generates the positive voltage applied to the substrate, while the negative voltage pump generates the negative voltage applied to the word lines. In some embodiments, the erase operation also includes a verification sub-operation after the erase voltage application step. For example, reading erased memory cells to verify whether the memory cells are in the erased state. In this case, the read charge pump 3221 is also called upon to generate the required voltages for the selected and unselected word lines, thereby completing the verification sub-operation included in the programming operation. Furthermore, in some NOR flash memory implementations, the erase operation also requires verification of whether the memory cells are over-erased, that is, whether the threshold voltage of the memory cell is less than 0. If the threshold voltage of the memory cell is less than 0, the threshold voltage needs to be raised to greater than 0 through soft programming. To this end, the erase operation of NOR flash memory may also include a soft programming sub-operation. At this time, the programming charge pump 3222 needs to be called to generate the required voltage, such as the word line programming voltage.

[0055] Figure 3 The read control circuit 3321, program control circuit 3322 and erase control circuit 3323 shown can realize Figure 2 The equivalent functions of the controller shown, the read voltage pump 3221, the program voltage pump 3222 and the erase voltage pump 3223 can achieve Figure 2 The charge pump shown in the figure has the same function, but the difference is that the above circuits / voltage pumps are set up independently. In other words, they can not be enabled at the same time. As a result, the memory can only enable the corresponding modules for operation according to specific instructions received from the outside, avoiding leakage current caused by enabling unnecessary circuits, thereby reducing the power consumption level of the memory chip.

[0056] It will be appreciated that the read control circuit 3321, the program control circuit 3322, and the erase control circuit 3323 may be a general-purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general-purpose processor may be a microprocessor, but in an alternative embodiment, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration).

[0057] Figure 4 FIG2 is a schematic diagram showing the state switching of a memory according to an embodiment of the present invention. As shown in the figure, the operating state of the memory 300 may include a standby state, a low power state (PWD), and three independent active states: a read state (READ), a program state (PGM), and an erase state (ERASE).

[0058] The following table lists the enable and disable conditions of various components in the memory 300 corresponding to various states.

[0059]

[0060]

[0061] Table 1

[0062] "Enable" means that a component is in a state where it can be used. "Disable" means that a component is in a state where it cannot be used. For example, you can enable a component by supplying power, and disable it by stopping the supply.

[0063] In the standby state, the memory 300 can recognize any command from the host 200. In the standby state, if there is no data transmission between the host 200 and the memory 300, the chip selection signal remains at an inactive level. Compared with the prior art, the memory of the present invention has fewer modules enabled in the standby state, and its voltage pump and control circuit (for example, Figure 3 The read, program, and erase control modules (shown in the figure) can all be disabled, leaving only the command decoder, input / output buffers, and ID register powered. In standby mode, some instructions that don't require the memory array can be executed directly, such as the READID instruction used to retrieve information from the ID register.

[0064] When the memory further receives an operation instruction for the memory cell array in the standby state, it can enter the corresponding read state (READ), program state (PGM) and erase state (ERASE) according to the type of the received instruction.

[0065] When the host 200 needs to send an operation instruction of the memory cell array to the memory 300, the host 200 sets the chip selection signal to a valid level, the memory 300 receives the instruction or data through the data input line SI and sets the busy signal to valid, and according to the decoding result of the instruction decoder 331, the power manager 321 enables the corresponding operation module, thereby entering one of the read state (READ), programming state (PGM) and erase state (ERASE).

[0066] The following will be combined Figure 3-4 , and the subsequent state transition timing diagram, describe the various states and state transitions involved in the memory of the present invention.

[0067] As shown in Table 1 above, in the standby state, the read operation module (read control circuit 3321 and read charge pump 3221), the program operation module (program control circuit 3322 and program charge pump 3222) and the erase operation module (erase control circuit 3323 and erase charge pump 3223) are all disabled.

[0068] In the standby state, when the chip selection signal is valid (for example, pulled low) and an instruction for the memory cell array is received on the data input pin, the memory can enter the corresponding operation state from the standby state to perform operations on the memory cell array.

[0069] Figure 5 The timing diagram of entering the read state from the standby state according to one embodiment of the present invention is shown. First, a low-level chip selection signal is received on the CS pin of the memory, and then an 8-bit input instruction is received on the SI pin. The instruction is cached by the input and output buffer 311 and sent to the instruction decoder 331. The instruction decoder 331 then decodes the received 8-bit instruction, identifies that the input instruction is a read instruction read_cmd for performing a memory cell array read operation, and sends the identification result to the power manager 321. Based on the identification result, the power manager 321 decides to enable the storage module, the read control circuit 3321 and the read charge pump 3221, and supplies power to them. Figure 5 As shown, after t R After the processing time, the read control circuit 3321 and the read charge pump 3221 enter the working state, whereby the memory enters the read state, and the current flowing into the memory increases from I CC1 I changes to read state CC3Subsequently, the read control circuit 3321 and the read charge pump 3221 control the storage array 341, the column decoder 342, the row decoder 343 and the read circuit 345 to perform corresponding operations according to the above read instruction (and subsequent related instructions, if any), thereby realizing the reading of the target storage content. After completing the execution of the above instruction, the memory returns to the standby mode, the read control circuit 3321 and the read charge pump 3221 are disabled again, and the current is also reduced from I CC3 Fall back to I CC1 .

[0070] Similarly, after the memory receives the memory cell array programming instruction, the programming operation module (programming control circuit 3322 and programming charge pump 3222) is enabled under the control of the power manager 321 based on the decoding recognition result, thereby the memory enters the programming state, and the current flowing into the memory is reduced from I CC1 I becomes the programming state CC4 . The enabled programming control circuit 3322 and programming charge pump 3222 are used to perform programming operations on the memory cell array. As mentioned above, the programming operation may involve a verification sub-operation. In this verification sub-operation, the read voltage pump 3221 can be enabled separately to generate the corresponding voltage. Therefore, in Table 1, the read voltage pump 3221 is shown as being enabled in the programming state. The above-mentioned enablement can be enabled throughout the entire programming operation, but is preferably enabled only in the corresponding verification sub-operation. After completing all the programming operations, the memory returns to standby mode, and the programming control circuit 3322 and the programming charge pump 3222 (and the optionally enabled read voltage pump 3221) are disabled again.

[0071] After the memory receives the memory cell array erase instruction, the erase operation module (erase control circuit 3323 and erase charge pump 3223) is enabled under the control of the power manager 321 based on the decoding recognition result, thereby the memory enters the erase state, and the current flowing into the memory is increased from I in the standby state to CC1 I becomes erased CC5. The enabled erase control circuit 3323 and erase charge pump 3223 are used to perform an erase operation on the memory cell array. As mentioned above, the erase operation may involve a verification sub-operation. In the verification sub-operation, the read voltage pump 3221 can be enabled separately to generate the corresponding voltage. Further, in the application scenario of NOR flash memory, the erase operation may involve a soft programming sub-operation. In the soft programming sub-operation, the programming voltage pump 3222 can be enabled separately to generate the corresponding voltage. Therefore, in Table 1, the read voltage pump 3221 and the programming voltage pump 3222 are shown as being enabled in the erase state. The above-mentioned enablement can be enabled in the entire erase operation, but it is preferably enabled only in various corresponding verification sub-operations and soft programming sub-operations. After completing all the erase operations, the memory returns to standby mode, and the erase control circuit 3323 and the erase charge pump 3223 (and the optionally enabled read voltage pump 3221 and programming voltage pump 3222) are disabled again.

[0072] Furthermore, if Figure 4 As shown in FIG. 1 , in the standby state, the memory 300 can directly enter the low power state according to the low power state instruction PWD_cmd. In the low power state, the power manager 321 can disable the memory module, namely the memory array 341, the column decoder 342, the row decoder 343 and the read circuit 345 (and the page buffer in some embodiments), thereby reducing the power consumption of the memory chip, and the current flowing into the memory is reduced from I CC1 Change to low power state with lower I CC2 .

[0073] After transitioning to a low-power state, any signal on the SI pin will be ignored. When a valid chip select signal is received on the CS pin, such as a low-level active signal (i.e., CS is pulled low), the memory in the low-power state can respond to the chip select signal, thereby leaving the low-power state and returning to the standby state.

[0074] Although Figure 3 Each operation module is shown as including both a control circuit and a voltage pump, but it should be understood that in some embodiments, only the logic control circuit can be divided while still using a combined charge pump. For example, the read operation module only includes a read control circuit and does not include a separate read charge pump. The above changes are still within the scope defined by the present invention.

[0075] The present invention can also be implemented as a memory control method, comprising: enabling a read operation module in a memory cell array operation module after the memory receives a memory cell array read instruction, and the read operation module performs a read operation on the memory cell array; enabling a programming operation module in the memory cell array control module after the memory receives a memory cell array programming instruction, and the programming operation module performs a programming operation on the memory cell array; and enabling an erase operation module in the memory cell array control module after the memory receives a memory cell array erase instruction, and the erase operation module performs an erase operation on the memory cell array.

[0076] Furthermore, the present invention can also be implemented as a system, for example Figure 1 The electronic device shown includes a host, an interface bus, and the memory described above. The memory is coupled to the host via its input / output interface (eg, SPI interface) connected to the interface bus.

[0077] The memory, the memory control method, and the memory control system according to the present invention have been described above in detail with reference to the accompanying drawings.

[0078] The present disclosure updates the internal structure of memory circuits (especially flash memory chips) from the perspective of reducing power consumption, and divides the control circuits based on instruction types. For different instructions, only the specific circuits required to complete the instruction are turned on, and other operating circuits are disabled, ensuring that no unnecessary circuits of the memory operating device are turned on, thereby reducing memory leakage current and power consumption in the working state. Furthermore, the detailed division of the above-mentioned activation state avoids the need to turn on the charge pump and control circuit in the standby state, thereby further reducing standby power consumption and increasing battery life.

[0079] While various embodiments of the present invention have been described above, the foregoing description is intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A memory comprising: memory cell array; as well as A memory cell array operation module, the operation module comprising: a read operation module, enabled in response to the memory receiving a memory cell array read instruction, and configured to perform a read operation on the memory cell array; a programming operation module, enabled in response to the memory receiving a memory cell array programming instruction, and configured to perform a programming operation on the memory cell array; and an erasing operation module, enabled in response to the memory receiving a memory cell array erasing instruction, and configured to perform an erasing operation on the memory cell array, wherein, in response to the completion of the read operation, the read operation module is disabled; disabling the program operation module in response to completion of the program operation execution, and The erase operation module is disabled in response to completion of the erase operation execution.

2. The memory according to claim 1, wherein The read operation module includes: a read voltage pump for generating a voltage required for a read operation; and A read control circuit is used to control the data reading operation of the memory cell array.

3. The memory according to claim 2, wherein The read control circuit includes: The read operation enable signal circuit is used to enable the voltage used in the read operation.

4. The memory according to claim 2, wherein The read voltage pump is enabled in a verify sub-operation of an erase operation and / or a program operation.

5. The memory according to claim 1, wherein The programming operation module includes: a programming voltage pump for generating a voltage required for a programming operation; and The programming control circuit is used to control the data programming operation of the memory cell array.

6. The memory according to claim 5, wherein The program voltage pump is enabled in a soft program sub-operation of an erase operation.

7. The memory according to claim 1, wherein The erase operation module includes: an erase voltage pump for generating a voltage required for an erase operation; and The erase control circuit is used to control the data erase operation of the memory cell array.

8. The memory of claim 1 , further comprising: Power Manager; as well as Instruction decoder, Among them, the power manager is capable of supplying power to the instruction decoder in standby mode, the power manager supplies power to the read operation module in response to the storage cell array read instruction, the power manager supplies power to the programming operation module in response to the storage cell array programming instruction, and the power manager supplies power to the erase operation module in response to the storage cell array erase instruction.

9. The memory according to claim 8, wherein The power manager is used to: In response to receiving a low power state instruction, stopping power supply to the instruction decoder to enter a low power state; as well as In response to receiving a chip strobe signal, power supply to the instruction decoder is restored to return to the standby state.

10. A memory control method, comprising: After the memory receives a memory cell array read instruction, enabling a read operation module in a memory cell array operation module, the read operation module performs a read operation on the memory cell array; After the memory receives a memory cell array programming instruction, enabling a programming operation module in the memory cell array control module, the programming operation module performs a programming operation on the memory cell array; as well as After the memory receives a memory cell array erase instruction, the erase operation module in the memory cell array control module is enabled, and the erase operation module performs an erase operation on the memory cell array. And the method further includes: disabling the read operation module in response to completion of the read operation; disabling the program operation module in response to completion of the program operation execution, and The erase operation module is disabled in response to completion of the erase operation execution.

11. A system comprising: Host controller; Interface bus; as well as The memory of claims 1-9, coupled to a host controller via the interface bus.

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