Semiconductor memory device and method of operating the same

Abstract

The present application relates to a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory string and control logic. The memory string is connected between a common source line and a bit line, and includes at least one first select transistor, a plurality of memory cells, and a plurality of second select transistors. The control logic is configured to apply a first voltage to a first group of a plurality of second select lines connected to the plurality of second select transistors, respectively, float a second group of the plurality of second select lines, and then apply an erase voltage to the common source line during an erase operation.

Description

Technical Field

[0001] This disclosure relates to an electronic device, and more specifically, to a semiconductor device and a method of operating the same. Background Technology

[0002] Semiconductor memory devices can be formed as a two-dimensional structure in which strings are arranged horizontally on a semiconductor substrate, or as a three-dimensional structure in which strings are stacked vertically on a semiconductor substrate. Three-dimensional memory devices have been designed to overcome the integration limitations of two-dimensional memory devices and can include multiple memory cells stacked vertically on a semiconductor substrate. Summary of the Invention

[0003] The embodiments of this disclosure are intended to provide a semiconductor memory device with improved erase operation speed and erase reliability, and a method for operating the semiconductor memory device.

[0004] A semiconductor memory device according to an embodiment of the present disclosure includes a memory string and control logic. The memory string is connected between a common source line and a bit line and includes at least one first selection transistor, a plurality of memory cells, and a plurality of second selection transistors. The control logic is configured to apply a first voltage to a first group of a plurality of second selection lines respectively connected to the plurality of second selection transistors during an erase operation, causing a second group of the plurality of second selection lines to float, and then apply an erase voltage to the common source line.

[0005] In one implementation, the first voltage can generate a gate-induced drain leakage (GIDL) current in a second selection transistor connected to a second selection line in the first group.

[0006] In one implementation, as an erase voltage is applied to the common source line, the voltage of the second group of multiple second select lines can be increased through coupling.

[0007] In one implementation, the voltage of the second selection line of the second group is increased to a level that turns on the second selection transistor connected to the second selection line of the second group.

[0008] In an implementation, the second selection line of the second group can be positioned adjacent to the common source line.

[0009] In one implementation, during the erase operation, the control logic can also be configured to precharge the second group to a second voltage higher than the first voltage. The control logic can then float the second group after performing the precharge operation.

[0010] In one implementation, during the erase operation, the control logic can also be configured to precharge the second and third groups of the plurality of second selection lines to a second voltage higher than the first voltage. The control logic can then float the second group after performing the precharge operation.

[0011] In an implementation, among multiple second selection lines, the third group can be located between the first group and the second group.

[0012] In one implementation, during the erase operation, the control logic can also be configured to apply a first voltage to a third group of the plurality of second select lines. The control logic can also be configured to float the third group after the application operation is performed. The control logic can apply an erase voltage to the common source line after floating the second and third groups.

[0013] In an implementation, among the multiple second selection lines, the third group can be located between the first group and the second group.

[0014] A method of operating a semiconductor memory device according to another embodiment of the present disclosure, the semiconductor memory device including a cell string including a first drain select transistor and a second drain select transistor sequentially connected between a bit line and a common source line, a plurality of memory cells, a first source select transistor and a second source select transistor, the method including: applying a first voltage to a first source select line connected to the first source select transistor; floating a second source select line connected to the second source select transistor; and increasing the voltage of the second source select line by applying an erase voltage to the common source line.

[0015] In an implementation, the method may further include applying a first voltage to the second source selection line before performing a floating operation.

[0016] In an implementation, the method may further include applying a second voltage greater than the first voltage to the second source selection line before performing the floating operation.

[0017] In an implementation, the first voltage may be the ground voltage.

[0018] In one implementation, a first voltage may be applied to the first source select line while the second source select line is floated and an erase voltage is applied to the common source line.

[0019] In one implementation, the voltage of the second source selection line can be increased to a level that turns on the second source selection transistor.

[0020] In an implementation, the method may further include: floating the first source select line after applying a first voltage to the first source select line connected to the first source select transistor.

[0021] In an implementation, the method may further include: applying a first voltage to a first drain select line connected to a first drain select transistor before floating the second source select line; floating the second drain select line connected to a second drain select transistor; and increasing the voltage of the second drain select line by applying an erase voltage to the bit line.

[0022] According to another embodiment of the present disclosure, a method for operating a semiconductor memory device includes a cell string comprising a drain selection transistor, a plurality of memory cells, and a plurality of source selection transistors sequentially connected between a bit line and a common source line. The source selection transistors are grouped into an upper source selection transistor group, an intermediate source selection transistor group, and a lower source selection transistor group. The method includes: applying a first voltage to an upper source selection line group connected to the upper source selection transistor group; floating a lower source selection line group connected to the lower source selection transistor group; and increasing the voltage of the lower source selection line group by applying an erase voltage to the common source line.

[0023] In one implementation, the lower source select line group can be positioned adjacent to the common source line. The method may further include applying a second voltage greater than the first voltage to the lower source select line group before performing a floating operation.

[0024] In one implementation, the intermediate source select line group connected to the intermediate source select transistor group can be located between the upper source select line group and the lower source select line group. The method may further include applying a second voltage to the intermediate source select line group before performing a floating operation.

[0025] In one implementation, a second voltage may be applied to the intermediate source select line group while the lower source select line group connected to the lower source select transistor group is floating and an erase voltage is applied to the common source line.

[0026] In one implementation, the intermediate source select line group connected to the intermediate source select transistor group can be located between the upper source select line group and the lower source select line group. The method may further include applying a first voltage to the intermediate source select line group before performing a floating operation.

[0027] In an implementation, the method may further include: floating the intermediate source selection line group before performing the voltage increase operation.

[0028] According to another embodiment of the present disclosure, a method of operating a semiconductor memory device includes a cell string comprising a first drain select transistor and a second drain select transistor, a plurality of memory cells, and a source select transistor sequentially connected between a bit line and a common source line. The method includes: applying a first voltage to a first drain select line and a second drain select line connected to the first drain select transistor and the second drain select transistor; floating the first drain select line adjacent to the bit line; and increasing the voltage of the first drain select line by applying an erase voltage to the bit line.

[0029] A semiconductor memory device according to an embodiment of the present disclosure includes a memory block and circuitry. The memory block includes a plurality of memory strings, each memory string having a group of memory cells, a near group, and a far group connected in series. Each of the near and far groups is configured with one or more select transistors connected in series. The near group is positioned closer to an erase voltage line than the far group, and the erase voltage line is one of a common source line and a bit line respectively connected to the memory string. The circuitry is configured to: initialize the select line connected to the far group, float the select line connected to the near group, and provide an erase voltage to the erase voltage line to erase the memory block.

[0030] This technology can provide a semiconductor memory device with improved erase operation speed and erase reliability, as well as a method for operating the semiconductor memory device. Attached Figure Description

[0031] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0032] Figure 2 This is an example Figure 1 A block diagram of an embodiment of the memory cell array 110.

[0033] Figure 3 This is an example Figure 2 A circuit diagram of an implementation of any one of the storage blocks BLK1 to BLKz, BLKa.

[0034] Figure 4 This is an example Figure 2 A circuit diagram of another embodiment of storage block BLKb, any one of storage blocks BLK1 to BLKz.

[0035] Figure 5 This is an example Figure 1 A circuit diagram illustrating an implementation of any one of the memory blocks BLK1 to BLKz, BLKc, included in the memory cell array 110.

[0036] Figure 6This is a circuit diagram illustrating the structure of a unit string.

[0037] Figure 7 This is a cross-sectional view illustrating different overlapping cell strings between the source selection line and the common source line.

[0038] Figure 8 This is a circuit diagram illustrating the structure of a cell string included in a semiconductor memory device according to an embodiment of the present disclosure.

[0039] Figure 9 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0040] Figure 10 This is a timing diagram illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0041] Figure 11 This is a diagram illustrating the effects of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0042] Figure 12 This is a flowchart illustrating a method of operating a semiconductor memory device according to another embodiment of the present disclosure.

[0043] Figure 13 This is a timing diagram illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0044] Figure 14 This is a circuit diagram illustrating the structure of a cell string included in a semiconductor memory device according to yet another embodiment of the present disclosure.

[0045] Figure 15 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0046] Figure 16 This is a timing diagram illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0047] Figure 17 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0048] Figure 18 This is a timing diagram illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0049] Figure 19 This is a circuit diagram illustrating the structure of a cell string included in a semiconductor memory device according to yet another embodiment of the present disclosure.

[0050] Figure 20 This is an example Figure 19 The circuit diagram includes an example of the connection structure of the source selection transistor.

[0051] Figure 21 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0052] Figure 22 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0053] Figure 23 This is an example Figure 19 The circuit diagram shows another example of the connection structure of the source selection transistor included in the circuit.

[0054] Figure 24 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0055] Figure 25 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0056] Figure 26 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0057] Figure 27 This is a timing diagram illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0058] Figure 28 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0059] Figure 29 This example includes Figure 1 A block diagram of a memory system for a semiconductor memory device.

[0060] Figure 30 This is an example Figure 29 A block diagram illustrating an application example of a memory system.

[0061] Figure 31 This illustrates the example including references. Figure 30 A block diagram of the computing system describing the memory system. Detailed Implementation

[0062] The specific structural and functional descriptions provided herein are for the purpose of describing embodiments of this disclosure. However, the invention can be implemented in various forms and in various ways. Therefore, the invention is not limited to any of the disclosed embodiments, nor is it limited by any of the disclosed embodiments, nor is it limited to any of the specific details provided herein. Throughout the specification, references to "implementation," "another embodiment," etc., do not necessarily refer to only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment. When the term "implementation" is used herein, it does not necessarily refer to all embodiments.

[0063] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0064] Reference Figure 1 The semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read / write circuit 130, control logic 140, and a voltage generator 150.

[0065] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz connected to the address decoder 120 via word lines WL. The multiple memory blocks BLK1 to BLKz are connected to the read / write circuitry 130 via bit lines BL1 to BLm. Each of the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In one embodiment, the multiple memory cells are non-volatile memory cells and can be configured as non-volatile memory cells with a vertical channel structure. The memory cell array 110 can be configured as a two-dimensional memory cell array. According to another embodiment, the memory cell array 110 can be configured as a three-dimensional memory cell array. Each of the multiple memory cells included in the memory cell array can store at least one bit of data. Each of the multiple memory cells in the memory cell array 110 can be a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a three-level cell (TLC) storing three bits of data, or a four-level cell (QLC) storing four bits of data. According to another embodiment, the memory cell array 110 can include multiple memory cells each storing five or more bits of data.

[0066] Address decoder 120, read / write circuitry 130, and voltage generator 150 operate as peripheral circuitry driving memory cell array 110. The peripheral circuitry operates under the control of control logic 140. Address decoder 120 is connected to memory cell array 110 via word line WL. Address decoder 120 is configured to operate in response to control logic 140. Address decoder 120 receives addresses through an input / output buffer (not shown) within semiconductor memory device 100.

[0067] Address decoder 120 is configured to decode block addresses among received addresses. Address decoder 120 selects at least one memory block based on the decoded block address. Additionally, during a read operation, address decoder 120 applies a read voltage Vread generated in voltage generator 150 to the selected word line of the selected memory block and applies a pass voltage Vpass to the remaining unselected word lines. Furthermore, during a programming verification operation, address decoder 120 applies a verification voltage generated in voltage generator 150 to the selected word line of the selected memory block and applies a pass voltage Vpass to the remaining unselected word lines.

[0068] Address decoder 120 is configured to decode the column address in the received address. Address decoder 120 sends the decoded column address to read / write circuit 130.

[0069] Read and programming operations of the semiconductor memory device 100 are performed on a page-by-page basis. The address received when requesting a read or programming operation includes a block address, a row address, and a column address. The address decoder 120 selects a memory block and a word line based on the block and row addresses. The column address is decoded by the address decoder 120 and provided to the read / write circuitry 130.

[0070] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0071] The read / write circuit 130 includes multiple page buffers PB1 to PBm. The read / write circuit 130 can operate as a "read circuit" during read operations of the memory cell array 110 and as a "write circuit" during write operations of the memory cell array 110. The multiple page buffers PB1 to PBm are connected to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, in order to sense the threshold voltage of the memory cells, the multiple page buffers PB1 to PBm continuously supply sensing current to the bit lines connected to the memory cells while sensing changes in the amount of current flowing according to the programming state of the corresponding memory cells through sensing nodes, and latch the sensed changes as sensed data. The read / write circuit 130 operates in response to page buffer control signals output from control logic 140.

[0072] During a read operation, the read / write circuit 130 senses the data in the memory cell, temporarily stores the read data, and outputs the data DATA to the input / output buffer (not shown) of the semiconductor memory device 100. In an embodiment, in addition to a page buffer (or page register), the read / write circuit 130 may also include a column select circuit, etc.

[0073] Control logic 140 is connected to address decoder 120, read / write circuitry 130, and voltage generator 150. Control logic 140 receives commands CMD and control signals CTRL via input / output buffers (not shown) of semiconductor memory device 100. Control logic 140 is configured to control the overall operation of semiconductor memory device 100 in response to control signal CTRL. Additionally, control logic 140 outputs control signals for adjusting the precharge potential levels of sensing nodes in multiple page buffers PB1 to PBm. Control logic 140 can control read / write circuitry 130 to perform read operations on memory cell array 110. Control logic 140 controls voltage generator 150 to generate various voltages used during programming operations of memory cell array 110. Furthermore, control logic 140 controls address decoder 120 to transmit the voltage generated by voltage generator 150 to the local lines of the memory block to be operated via global lines. During a read operation, control logic 140 controls read / write circuit 130 to read data from the selected page of the memory block via bit lines BL1 to BLm and store the data in page buffers PB1 to PBm. Conversely, during a programming operation, control logic 140 controls read / write circuit 130 to program the data from page buffers PB1 to PBm into the selected page.

[0074] Voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation in response to a control signal output from control logic 140. To generate multiple voltages with various voltage levels, voltage generator 150 may include multiple pump capacitors that receive an internal power supply voltage and selectively activate the multiple pump capacitors in response to control by control logic 140 to generate multiple voltages.

[0075] The address decoder 120, read / write circuit 130, and voltage generator 150 can be used as "peripheral circuitry" to perform read, write, and erase operations on the memory cell array 110. The peripheral circuitry performs read, write, and erase operations on the memory cell array 110 based on the control logic 140.

[0076] Figure 2 This is an example Figure 1 A block diagram of an embodiment of the memory cell array 110.

[0077] Reference Figure 2 The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. Each memory block has a three-dimensional structure. Each memory block includes multiple memory cells stacked on a substrate. These multiple memory cells are arranged along the +X, +Y, and +Z directions. (Refer to...) Figure 3 and Figure 4 Describe the structure of each storage block in more detail.

[0078] Figure 3 This is an example Figure 2 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0079] Reference Figure 3 The storage block BLK comprises multiple cell strings CS11 to CS1m and CS21 to CS2m. In an implementation, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m can be formed in a "U" shape. In the storage block BLK, m cell strings are arranged in the row direction (i.e., the +X direction). Figure 3 In this example, two unit strings are arranged in the column direction (i.e., the +Y direction). This is for clarity purposes; however, three or more unit strings can be arranged in the column direction.

[0080] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a tube transistor PT, and at least one drain selection transistor DST.

[0081] The selected transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. In an embodiment, each of the selected transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunnel insulating film, a charge storage film, and a barrier insulating film. In an embodiment, pillars for providing the channel layer may be provided in each cell string. In an embodiment, pillars for providing at least one of the channel layer, tunnel insulating film, charge storage film, and barrier insulating film may be provided in each cell string.

[0082] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCp.

[0083] In one implementation, source selection transistors of cell strings arranged in the same row are connected to source selection lines extending in the row direction, and source selection transistors of cell strings arranged in different rows are connected to different source selection lines. Figure 3 In the first row, the source selection transistors of cell strings CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors of cell strings CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0084] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0085] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0086] The first memory cells MC1 to the nth memory cell MCn can be divided into first memory cells MC1 to the pth memory cells MCp and (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first memory cells MC1 to the pth memory cells MCp are arranged sequentially in the direction opposite to the +Z direction and connected in series between the source selection transistor SST and the transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn are arranged sequentially in the +Z direction and connected in series between the transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cells MCp and the (p+1)th memory cells MCp+1 to the nth memory cells MCn are connected to each other via the transistor PT. The gates of the first memory cells MC1 to the nth memory cells MCn in each cell string are respectively connected to the first word line WL1 to the nth word line WLn.

[0087] The gate of the tubular transistor PT in each cell string is connected to the pipeline PL.

[0088] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. The DST of cell strings arranged in the row direction is connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0089] The cell string arranged in the column direction is connected to the bit line extending in the column direction. Figure 3 In the diagram, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

[0090] Memory cells connected to the same word line in a cell string arranged in the row direction constitute a page. For example, memory cells connected to the first word line WL1 in cell strings CS11 to CS1m in the first row constitute one page. Memory cells connected to the first word line WL1 in cell strings CS21 to CS2m in the second row constitute another page. A cell string arranged in a row direction can be selected by selecting either drain select line DSL1 or DSL2. A page in the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0091] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Additionally, the even-numbered cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the even-numbered bit lines, and the odd-numbered cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the odd-numbered bit lines.

[0092] In this implementation, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. The more dummy memory cells provided, the higher the operational reliability of the memory block BLKa; however, the size of the memory block BLKa increases. Conversely, the smaller the number of dummy memory cells provided, the smaller the size of the memory block BLKa can be; however, the operational reliability of the memory block BLKa may decrease.

[0093] To effectively control at least one dummy memory cell, each dummy memory cell can have a set threshold voltage. Programming operations can be performed on all or part of the dummy memory cells before or after an erase operation on the memory block BLKa. When an erase operation is performed after a programming operation, the dummy memory cell can have a set threshold voltage by controlling the voltage applied to the dummy word line connected to the corresponding dummy memory cell.

[0094] Figure 4 This is an example Figure 2 A circuit diagram of another embodiment of any one of the storage blocks BLK1 to BLKz, BLKb.

[0095] Reference Figure 4 The memory block BLKb includes multiple cell strings CS11′ to CS1m′ and CS21′ to CS2m′. Each of the multiple cell strings CS11′ to CS1m′ and CS21′ to CS2m′ extends along the +Z direction. Each of the multiple cell strings CS11′ to CS1m′ and CS21′ to CS2m′ includes at least one source selection transistor SST, a first memory cell MC1 to an nth memory cell MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) beneath the memory block BLKb.

[0096] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. The source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. In another embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' may be connected to a single source select line.

[0097] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0098] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0099] As a result, in addition to excluding the tubular transistor PT from each cell string, Figure 4 The storage block BLKb has the same characteristics as Figure 3 The equivalent circuit of the storage block BLKa is similar to the equivalent circuit.

[0100] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Additionally, the even-numbered cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction can be connected to the even-numbered bit lines, and the odd-numbered cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction can be connected to the odd-numbered bit lines respectively.

[0101] In this implementation, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. The more dummy memory cells provided, the higher the operational reliability of the memory block BLKb; however, the size of the memory block BLKb increases. Conversely, the smaller the number of dummy memory cells provided, the smaller the size of the memory block BLKb can be; however, the operational reliability of the memory block BLKb may decrease.

[0102] To effectively control at least one dummy memory cell, each dummy memory cell can have a set threshold voltage. Programming operations can be performed on all or part of the dummy memory cells before or after an erase operation on the memory block BLKb. When an erase operation is performed after a programming operation, the dummy memory cell can have a set threshold voltage by controlling the voltage applied to the dummy word line connected to the corresponding dummy memory cell.

[0103] Figure 5 This is an example Figure 1 A circuit diagram of an implementation of any one of the memory blocks BLK1 to BLKz included in the memory cell array 110, namely BLKc.

[0104] Reference Figure 5 The memory block BLKc includes multiple cell strings CS1 to CSm. The multiple cell strings CS1 to CSm can be connected to multiple bit lines BL1 to BLm respectively. Each of the cell strings CS1 to CSm includes at least one source selection transistor SST, a first memory cell MC1 to an nth memory cell MCn, and at least one drain selection transistor DST.

[0105] The selector transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. In an embodiment, each of the selector transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunnel insulating film, a charge storage film, and a barrier insulating film. In an embodiment, pillars for providing the channel layer may be provided in each cell string. In an embodiment, pillars for providing at least one of the channel layer, tunnel insulating film, charge storage film, and barrier insulating film may be provided in each cell string.

[0106] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn.

[0107] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0108] The drain selection transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn.

[0109] Memory cells connected to the same word line constitute a page. Cell strings CS1 to CSm can be selected by choosing the drain select line DSL. A page within the selected cell string can be selected by choosing any one of the word lines WL1 to WLn.

[0110] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit lines BL1 to the m-th bit lines BLm. The even-numbered cell strings CS1 to CSm can be connected to the even-numbered bit lines, while the odd-numbered cell strings can be connected to the odd-numbered bit lines respectively.

[0111] like Figures 2 to 4 As shown, the memory cell array 110 of the semiconductor memory device 100 can be configured as a three-dimensional memory cell array. Additionally, as... Figure 5 As shown, the memory cell array 110 of the semiconductor memory device 100 can be configured as a two-dimensional memory cell array.

[0112] Figure 6 This is a circuit diagram illustrating the structure of a unit string. (Refer to...) Figure 6 The cell string CSa is connected between the bit line BL and the common source line CSL. Additionally, the cell string CSa includes a drain selection transistor DST, multiple memory cells MC1 to MCn, and a source selection transistor SST connected in series. In this embodiment, Figure 6 The unit string shown can be Figure 3 Any one of the cell strings CS11 to CS1m and CS21 to CS2m. In this case, although not shown in the figures, the cell string CSa may also include a tubular transistor PT located between the plurality of memory cells MC1 to MCn. In another embodiment, Figure 6 The unit string shown can be Figure 4 Any one of the unit strings CS11′ to CS1m′ and CS21′ to CS2m′.

[0113] Word lines WL1 to WLn are connected to the gates of memory cells MC1 to MCn, respectively. Drain select line DSL is connected to the gate of drain select transistor DST and controls the connection between control string CSa and bit line BL. Source select line SSL is connected to the gate of source select transistor SST and controls the connection between control string CSa and common source line CSL.

[0114] exist Figure 6 In one implementation, the cell string CSa includes one DST and one SST. However, in another implementation, the cell string may include multiple drain-select transistors and multiple source-select transistors. In this case, the number of source-select transistors (SSTs) and the number of drain-select transistors (DSTs) included in a cell string may be the same or different. The number of source-select transistors (SSTs) may be greater than the number of drain-select transistors (DSTs), or the number of drain-select transistors (DSTs) may be greater than the number of source-select transistors (SSTs). For example, a cell string may include seven source-select transistors (SSTs) and three drain-select transistors (DSTs).

[0115] Figure 7 This is a cross-sectional view illustrating different junctions between the source selection line and the common source line. (Refer to...) Figure 7 The example shows a cross-sectional view of the first cell string Str1 and the second cell string Str2 in the selected memory block. Figure 7 The unit strings Str1 and Str2 shown can be Figure 4 The three-dimensional storage block BLKb shown includes any one of the cell strings CS11′ to CS1m′ and CS21′ to CS2m′.

[0116] Reference Figure 7 A post is formed on the common source line CSL to configure the first unit string Str1 and the second unit string Str2, and the source select line SSL, word lines WL1 to WL8, and drain select line DSL are formed around the post. Figure 7 For clarity, the charge trapping layer, channel layer, and insulating layer formed between them have been omitted. Figure 7 In this implementation, each unit string is connected to eight word lines. That is, Figure 7 Each unit string shown may include eight memory units. However, the invention is not limited thereto; a unit string may include any suitable number of memory units.

[0117] Reference Figure 7 Source junctions SLJ1 and SLJ2 are formed at the junctions between the first cell string Str1 and the second cell string Str2 and the common source line CSL, respectively. Source junctions SLJ1 and SLJ2 may be unintentionally formed during the process of forming the common source line CSL and the respective pillars of cell strings Str1 and Str2. For each of cell strings Str1 and Str2, source junctions SLJ1 and SLJ2 may be formed differently. Figure 7In the example, the source junction SLJ1 of the first unit string Str1 is weakly formed. That is, the first unit string Str1 has weak junction overlap. The source junction SLJ2 of the second unit string Str2 is strongly formed. That is, the second unit string Str2 has strong junction overlap.

[0118] During the erase operation of a memory block including the first unit string Str1 and the second unit string Str2, the problem is: for each unit string, the erase speed depends on... Figure 7 The overlap of the corresponding strings differs. In the case of weak overlap in the first cell string Str1, the oxide layer between the source select line SSL and the common source line CSL is relatively thicker than the oxide layer in the second cell string Str2, which has strong overlap. Therefore, the electric field formed between the source select line SSL and the common source line CSL is relatively weaker in the first cell string Str1 than in the second cell string Str2. In this case, during the erase operation, the gate-induced drain leakage (GIDL) current generated in the source select transistor SST of the first cell string Str1 is relatively smaller than the GIDL current generated in the SST of the second cell string Str2. As a result, the erase speed of the first cell string Str1 becomes slower than that of the second cell string Str2, and the different erase speeds become a factor that reduces the erase operation speed of the semiconductor memory device.

[0119] A semiconductor memory device 100 according to an embodiment of the present disclosure includes a plurality of cell strings in each memory block of a memory cell array 110. Each cell string includes a plurality of source select transistors. During an erase operation of a memory block, after floating one of the multiple source select lines connected to the cell strings included in the target erase memory block, which is adjacent to a common source line, an erase voltage is applied to the common source line. As the erase voltage is applied to the common source line, the voltage of the source select line adjacent to the common source line increases. Therefore, the source select transistor adjacent to the common source line among the multiple source select transistors of the cell string belonging to the target erase memory block is turned on. Therefore, a high electric field is formed up to the vicinity of the source select transistor adjacent to the common source line. This results in the effect of forming a dummy source near the source select transistor adjacent to the common source line.

[0120] A ground voltage can be applied to a source selection transistor that is not adjacent to the common source line. Therefore, a GIDL current is generated in the source selection transistor that is not adjacent to the common source line. In this way, the difference between the erase speed of the first cell string Str1 with weak junction overlap and the erase speed of the second cell string Str2 with strong junction overlap can be reduced. As a result, the reliability of the erase operation of the semiconductor memory device can be improved.

[0121] Figure 8 This is a circuit diagram illustrating the structure of a cell string included in a semiconductor memory device according to an embodiment of the present disclosure.

[0122] Reference Figure 8 The cell string CSb is connected between the bit line BL and the common source line CSL. Additionally, the cell string CSb includes an upper drain select transistor DSTu and a lower drain select transistor DSTd connected in series, multiple memory cells MC1 to MCn, and an upper source select transistor SSTu and a lower source select transistor SSTd. In this embodiment, Figure 8 The unit string shown can be Figure 3 Any one of the cell strings CS11 to CS1m and CS21 to CS2m. In this case, although not shown in this figure, the cell string CSb may also include a tubular transistor PT located between the plurality of memory cells MC1 to MCn. In another embodiment, Figure 8 The unit string shown can be Figure 4 Any one of the unit strings CS11′ to CS1m′ and CS21′ to CS2m′.

[0123] In addition to the cell string CSb including two drain-select transistors DSTu and DSTd and two source-select transistors SSTu and SSTd, Figure 8 The unit string CSb shown can have the same characteristics as... Figure 6 The cell string CSa shown has a basically the same structure. Word lines WL1 to WLn are connected to the gates of memory cells MC1 to MCn, respectively. The upper drain select line DSLu is connected to the gate of the upper drain select transistor DSTu, and the lower drain select line DSLd is connected to the gate of the lower drain select transistor DSTd. The upper source select line SSLu is connected to the gate of the upper source select transistor SSTu, and the lower source select line SSLd is connected to the gate of the lower source select transistor SSTd.

[0124] exist Figure 8 The diagram illustrates an implementation where the number of drain-select transistors DSTu and DSTd, and the number of source-select transistors SSTu and SSTd in a cell string CSb are each two. However, a cell string may include three or more drain-select transistors and source-select transistors. In this case, the number of source-select transistors and drain-select transistors in a cell string may be the same or different.

[0125] Figure 9 This is a flowchart illustrating a method for operating a semiconductor memory device to erase memory cells in a selected memory block according to an embodiment of the present disclosure. (See also...) Figure 9The method of operating a semiconductor memory device includes: applying a first voltage to a first source select line and a second source select line (S110), floating the second source select line adjacent to a common source line (S130), and applying an erase voltage to the common source line (S150).

[0126] In operation S110, the source selection line connected to the memory block to be erased (e.g., ...) is sent to the source selection line. Figure 8 A first voltage is applied to the upper source select line SSLu and the lower source select line SSLd. Figure 9 In the middle, the first source selection line can be Figure 8 The upper source selection line SSLu, and the second source selection line can be Figure 8 The lower source select line SSLd. The first voltage can be the voltage applied to the gate of the source select transistor to generate the GIDL current. In an embodiment, the first voltage can be ground voltage.

[0127] In operation S130, the second source selection line among the multiple source selection lines, positioned adjacent to the common source line CSL, is made floating. That is, it allows... Figure 8 The lower source selection line SSLd is floated. In operation S130, the first source selection line (i.e., not adjacent to the common source line CSL) is floated. Figure 8 The upper source select line (SSLu) is not floating, and a first voltage can still be applied to the first source select line.

[0128] Subsequently, in operation S150, an erase voltage is applied to the common source line CSL. As the erase voltage, as a high voltage, is applied to the common source line CSL, the second source selection line (i.e., Figure 8 The voltage of the lower source select line (SSLd) can also be increased through coupling. Therefore, the lower source select transistor SSTd connected to the lower source select line SSLd can be turned on. In operation S150, a first voltage can still be applied to the first source select line (i.e., the upper source select line SSLu). Therefore, a GIDL current can be generated in the upper source select transistor SSTu. Therefore, the memory cells MC1 to MCn included in the cell string CSb can be erased.

[0129] Figure 10 This is a timing diagram illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure. (See also...) Figure 9 and Figure 10 To describe this method.

[0130] Reference Figure 10At the first time point t1, a first voltage V1 is applied to the upper source select line SSLu and the lower source select line SSLd (S110). As described above, the first voltage V1 is the voltage used to generate the GIDL current and can be the ground voltage GND. At the first time point t1, the ground voltage GND can be applied to the first word line WL1 to the nth word line WLn and the common source line CSL.

[0131] At the second time point t2, the lower source selection line SSLd, which is located adjacent to the common source line CSL, is floated (S130). Figure 10 In this process, the lower source selection line SSLd is floated at the second time point t2, but the present invention is not limited to this specific timing. That is, the lower source selection line SSLd can be floated at any time point between the first time point t1 and the second time point t2.

[0132] At the second time point t2, the erase voltage VERS (S150) is applied to the common source line CSL. The voltage of the common source line CSL can increase from the second time point t2 to the third time point t3. As the voltage of the common source line CSL increases, the voltage of the lower source select line SSLd begins to increase through coupling.

[0133] At time point t3, the voltage of the common source line CSL reaches the erase voltage VERS. At time point t3, the voltage of the lower source select line SSLd increases from the first voltage by the coupling voltage Vcpl. At time point t3, the lower source select transistor SSTd can be turned on by the voltage V1+Vcpl of the lower source select line SSLd.

[0134] Subsequently, the voltage on the common source line CSL can be maintained until the fourth time point t4. The voltage V1+Vcpl on the lower source select line SSLd can also be maintained until the fourth time point t4. Therefore, a GIDL current is generated in the upper source select transistor SSTu, and the memory cell erase operation is performed.

[0135] according to Figure 10In the illustrated implementation, the time period between the first time point t1 and the second time point t2 can be defined as an initialization operation, and the time period between the second time point t2 and the fourth time point t4 can be defined as an erase operation. During the initialization operation, the voltages of word lines WL1 to WLn, the upper source select line SSLu, the lower source select line SSLd, and the common source line CSL can be initialized. At the end of the initialization period, the lower source select line SSLd can be floated. Subsequently, during the erase operation, an erase voltage VERS is applied to the common source line CSL. Furthermore, the voltage of the lower source select line SSLd increases through coupling, thus turning on the lower source select transistor SSTd. Since the voltage of the upper source select line SSLu remains at the first voltage V1, a GIDL current can be generated in the upper source select transistor SSTu, thereby erasing the memory cell.

[0136] according to Figure 9 and Figure 10 The diagram illustrates an erase method in which a GIDL current is generated in the first source select transistor SST1. However, according to another embodiment, GIDL can be generated not only in the first source select transistor SST1 but also in each of the drain select transistors DST1 and DST2 to erase memory cells MC1 to MCn. In this case, an erase voltage can be applied to the bit line BL.

[0137] Reference Figure 10 This illustrates an embodiment in which the voltage of the upper source select line SSLu is maintained at a first voltage V1. According to another embodiment of this disclosure, after applying the first voltage V1 to the upper source select line SSLu, the upper source select line SSLu can be floated. For example, the upper source select line SSLu can be floated between a first time point t1 and a second time point t2. In this case, the first source select line can be floated between operations S110 and S130.

[0138] As another example, the upper source selection line SSLu can be floated between the second time point t2 and the third time point t3. In this case, the first source selection line can be floated between operations S130 and S150.

[0139] Figure 11 This is a diagram illustrating the effect of operating a semiconductor memory device according to an embodiment of the present disclosure. (Refer to...) Figure 11 The first unit string Str1 has weak junction overlap, while the source junction SLJ2 of the second unit string Str2 is strongly formed. That is, the second unit string Str2 can have strong junction overlap. Figure 10As shown, the floating lower source select line SSLd can be connected to the common source line CSL. As the voltage on the common source line CSL increases, the voltage on the lower source select line SSLd also increases. Therefore, the lower source select transistor SSTd turns on. Consequently, a high electric field is formed up to the vicinity of the lower source select transistor SSTd adjacent to the common source line CSL. Therefore, the effect of virtual sources VS1 and VS2 can be formed near the lower source select transistor SSTd adjacent to the common source line CSL, as... Figure 11 As shown by the dashed lines, essentially the same effect can occur in the first unit string Str1 with weak knot overlap and the second unit string Str2 with strong knot overlap.

[0140] A first voltage V1 (e.g., ground voltage GND) can be applied to the upper source selection line SSLu, which is connected to the upper source selection transistor SSTu and is not adjacent to the common source line CSL. This generates a GIDL current in the upper source selection transistor SSTu. In this way, the difference between the erase speed of the first cell string Str1 with weak junction overlap and the erase speed of the second cell string Str2 with strong junction overlap can be reduced. As a result, the reliability of the erase operation of the semiconductor memory device can be improved.

[0141] Figure 12 This is a flowchart illustrating a method for operating a semiconductor memory device to erase memory cells in a selected memory block according to another embodiment of the present disclosure. (See also...) Figure 12 The method of operating a semiconductor memory device includes: applying a first voltage to a first source select line and a second source select line (S210), applying a second voltage greater than the first voltage to the second source select line adjacent to a common source line (S230), causing the second source select line to float (S250), and applying an erase voltage to the common source line (S270).

[0142] In operation S210, the source selection line connected to the memory block to be erased (e.g., ...) is sent to the source selection line. Figure 8 A first voltage is applied to the upper source select line SSLu and the lower source select line SSLd. Figure 12 In the middle, the first source selection line can be Figure 8 The upper source selection line SSLu, and the second source selection line can be Figure 8 The lower source select line SSLd. The first voltage can be the voltage applied to the gate of the source select transistor to generate the GIDL current. In an embodiment, the first voltage can be ground voltage.

[0143] In operation S230, a second voltage greater than the first voltage is applied to the second source selection line among the multiple source selection lines that is positioned adjacent to the common source line CSL. That is, in operation S230, a second voltage can be applied to... Figure 8 The lower source select line SSLd is pre-charged. During operation S230, a first voltage can still be applied to the first source select line.

[0144] In operation S250, the second source selection line is made to float. That is, it can make... Figure 8 The lower source selection line SSLd is floated. In operation S250, the first source selection line (i.e., not adjacent to the common source line CSL) is floated. Figure 8 The upper source select line (SSLu) can be left unfloated, and a first voltage can still be applied to the first source select line.

[0145] Subsequently, in operation S270, an erase voltage is applied to the common source line CSL. As the erase voltage, as a high voltage, is applied to the common source line CSL, the second source selection line (i.e., Figure 8 The voltage of the lower source select line (SSLd) can also be increased through coupling. Therefore, the lower source select transistor SSTd connected to the lower source select line SSLd can be turned on. In operation S270, the first voltage can still be applied to the first source select line (i.e., the upper source select line SSLu). Therefore, a GIDL current can be generated in the upper source select transistor SSTu. Therefore, the memory cells MC1 to MCn included in the cell string CSb can be erased.

[0146] Figure 13 This is a timing diagram illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure. (See also...) Figure 12 and Figure 13 To describe this method.

[0147] Reference Figure 13 At the fifth time point t5, a first voltage V1 is applied to the upper source select line SSLu and the lower source select line SSLd (S210). As described above, the first voltage V1 is the voltage used to generate the GIDL current and can be the ground voltage GND. At the fifth time point t5, the ground voltage GND can be applied to the first word line WL1 to the nth word line WLn and the common source line CSL.

[0148] At the sixth time point t6, a second voltage V2 is applied to the lower source selection line SSLd, which is positioned adjacent to the common source line CSL (S230). The second voltage V2 is a voltage greater than the first voltage V1. Therefore, the lower source selection line SSLd is pre-charged.

[0149] At time point t7, the lower source selection line SSLd is floated (S250). Figure 13 In this invention, the lower source selection line SSLd is floated at the seventh time point t7, but the invention is not limited to a specific timing. That is, the lower source selection line SSLd can be floated at any time point between the sixth time point t6 and the seventh time point t7.

[0150] At time point t7, the erase voltage VERS (S270) is applied to the common source line CSL. The voltage of the common source line CSL can increase from time point t7 to time point t8. As the voltage of the common source line CSL increases, the voltage of the lower source select line SSLd begins to increase through coupling.

[0151] At time point t8, the voltage of the common source line CSL reaches the erase voltage VERS. At time point t8, the voltage of the lower source select line SSLd increases from the second voltage by the coupling voltage Vcpl. At time point t8, the lower source select transistor SSTd can be turned on by the voltage V2+Vcpl of the lower source select line SSLd.

[0152] Subsequently, the voltage on the common source line CSL can be maintained until the ninth time point t9. The voltage V2+Vcpl on the lower source select line SSLd can also be maintained until the ninth time point t9. Therefore, a GIDL current is generated in the upper source select transistor SSTu, thereby performing the erase operation of the memory cell.

[0153] according to Figure 13 In the illustrated implementation, the time period between the fifth time point t5 and the sixth time point t6 can be defined as an initialization operation, the time period between the sixth time point t6 and the seventh time point t7 can be defined as a precharge operation, and the time period between the seventh time point t7 and the ninth time point t9 can be defined as an erase operation. During the initialization operation, the voltages of word lines WL1 to WLn, the upper source select line SSLu and the lower source select line SSLd, and the common source line CSL can be initialized. During the precharge operation, the voltage of the lower source select line SSLd can be precharged to the second voltage V2. The lower source select line SSLd can be floated at the end of the precharge period. Subsequently, during the erase operation, an erase voltage VERS is applied to the common source line CSL. Furthermore, the voltage of the lower source select line SSLd increases through coupling, thus turning on the lower source select transistor SSTd. Since the voltage of the upper source select line SSLu remains at the first voltage V1, a GIDL current is generated in the upper source select transistor SSTu, thus erasing the memory cell.

[0154] Will Figure 10 and Figure 13 Compared with the implementation method, in Figure 10 In one implementation, the lower source select line SSLd is floated when the voltage of the lower source select line SSLd is a first voltage V1. In contrast, in... Figure 13 In this implementation, after pre-charging the voltage of the lower source select line SSLd to the second voltage V2, the lower source select line SSLd is floated. Therefore, compared with... Figure 10 Compared to the implementation method, in Figure 13 In this implementation, the lower source select line SSLd can be increased to a higher voltage level depending on the coupling voltage.

[0155] Figure 14 This is a circuit diagram illustrating the structure of a cell string included in a semiconductor memory device according to yet another embodiment of the present disclosure.

[0156] Reference Figure 14 The cell string CSc is connected between the bit line BL and the common source line CSL. Furthermore, the cell string CSc includes an upper drain select transistor DSTu, a middle drain select transistor DSTm, and a lower drain select transistor DSTd connected in series, multiple memory cells MC1 to MCn, and an upper source select transistor SSTu, a middle source select transistor SSTm, and a lower source select transistor SSTd. In this embodiment, Figure 14 The unit string shown can be Figure 3 Any one of the cell strings CS11 to CS1m and CS21 to CS2m. In this case, although not shown in this figure, the cell string CSc may also include a tubular transistor PT located between the plurality of memory cells MC1 to MCn. In another embodiment, Figure 14 The unit string shown can be Figure 4 Any one of the unit strings CS11′ to CS1m′ and CS21′ to CS2m′.

[0157] In addition to the cell string CSc comprising three drain-select transistors DSTu, DSTm, and DSTd, and three source-select transistors SSTu, SSTm, and SSTd, Figure 14 The unit string CSc shown can have the same characteristics as... Figure 8The cell string CSb shown has essentially the same structure. Word lines WL1 to WLn are connected to the gates of memory cells MC1 to MCn, respectively. The upper drain select line DSLu is connected to the gate of the upper drain select transistor DSTu, the middle drain select line is connected to the gate of the middle drain select transistor DSTm, and the lower drain select line DSLd is connected to the gate of the lower drain select transistor DSTd. The upper source select line SSLu is connected to the gate of the upper source select transistor SSTu, the middle source select line SSLm is connected to the gate of the middle source select transistor SSTm, and the lower source select line SSLd is connected to the gate of the lower source select transistor SSTd.

[0158] exist Figure 14 In one implementation, the cell string CSc includes three drain-select transistors (DSTu, DSTm, and DSTd) and three source-select transistors (SSTu, SSTm, and SSTd). However, a cell string may include four or more drain-select transistors and four or more source-select transistors. In this case, the number of source-select transistors and the number of drain-select transistors included in a cell string may be the same or different.

[0159] Figure 15 This is a flowchart illustrating a method for operating a semiconductor memory device to erase memory cells in a selected memory block according to another embodiment of the present disclosure. (See also...) Figure 15 The method of operating a semiconductor memory device includes: applying a first voltage to a first source select line, a second source select line, and a third source select line (S310); applying a second voltage greater than the first voltage to the third source select line and the second source select line adjacent thereto (S330); floating the third source select line adjacent to the common source line (S350); and applying an erase voltage to the common source line (S370).

[0160] In operation S310, the source selection line connected to the memory block to be erased (e.g., ...) is sent to the source selection line. Figure 14 A first voltage is applied to the upper source select line SSLu, the middle source select line SSLm, and the lower source select line SSLd. Figure 15 In the middle, the first source selection line can be Figure 14 The upper source selection line SSLu, and the second source selection line can be Figure 14 The intermediate source selection line is SSLm. The third source selection line can be... Figure 14 The lower source select line SSLd. The first voltage can be the voltage applied to the gate of the source select transistor to generate the GIDL current. In an embodiment, the first voltage can be ground voltage.

[0161] In operation S330, a second voltage is applied to the third source selection line among the multiple source selection lines, which is positioned adjacent to the common source line CSL. That is, a second voltage can be applied to... Figure 14 A second voltage is applied to the lower source select line SSLd. In operation S330, the second voltage is similarly applied to the second source select line adjacent to the third source select line. That is, it can be applied to... Figure 14 A second voltage is applied to the intermediate source select line SSLm. In operation S330, a second voltage can still be applied to the first source select line (i.e., the one not adjacent to the third source select line) among the multiple source select lines. Figure 14 A first voltage is applied to the upper source selection line (SSLu).

[0162] In operation S350, the third source selection line (i.e., Figure 14 The lower source select line (SSLd) is floated. In operation S350, the first source select line and the second source select line may not be floated. That is, in operation S350, a second voltage can still be applied to the second source select line, and a first voltage can still be applied to the first source select line.

[0163] Subsequently, in operation S370, an erase voltage is applied to the common source line CSL. As the erase voltage, as a high voltage, is applied to the common source line CSL, the third source selection line (i.e., Figure 14 The voltage of the lower source select line (SSLd) can also be increased through coupling. Therefore, the lower source select transistor SSTd connected to the lower source select line SSLd can be turned on. In operation S370, a second voltage can still be applied to the second source select line (i.e., the intermediate source select line SSLm), and a first voltage can still be applied to the first source select line (i.e., the upper source select line SSLu). Therefore, a GIDL current can be generated in the upper source select transistor SSTu. In this case, the intermediate source select transistor SSTm can be used as a buffer between the upper source select transistor SSTu and the lower source select transistor SSTd. Therefore, the memory cells MC1 to MCn included in the cell string CSb can be erased.

[0164] Figure 16 This is a timing diagram illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure. (See also...) Figure 15 and Figure 16 To describe this method.

[0165] Reference Figure 16At the tenth time point t10, a first voltage V1 is applied to the upper source select line SSLu, the intermediate source select line SSLm, and the lower source select line SSLd (S310). As described above, the first voltage V1 is the voltage used to generate the GIDL current and can be the ground voltage GND. At the tenth time point t10, the ground voltage GND can be applied to the first word line WL1 to the nth word line WLn and the common source line CSL.

[0166] At time point t11, a second voltage V2 is applied to the lower source selection line SSLd, which is positioned adjacent to the common source line CSL, and the intermediate source selection line SSLm, which is adjacent to the lower source selection line (S330). The second voltage V2 is a voltage greater than the first voltage V1. Therefore, the lower source selection line SSLd and the intermediate source selection line SSLm are pre-charged.

[0167] At time point t12, the lower source selection line SSLd is floated (S350). Figure 16 In this invention, the lower source selection line SSLd is floated at the twelfth time point t12, but the invention is not limited to this specific timing. That is, the lower source selection line SSLd can be floated at any time point between the eleventh time point t11 ​​and the twelfth time point t12.

[0168] At time point t12, an erase voltage VERS (S370) is applied to the common source line CSL. The voltage of the common source line CSL can increase from time point t12 to time point t13. As the voltage of the common source line CSL increases, the voltage of the lower source select line SSLd begins to increase through coupling. Additionally, in this case, the voltage of the intermediate source select line SSLm remains at the second voltage V2, and the voltage of the upper source select line SSLu remains at the first voltage V1.

[0169] At time point t13, the voltage of the common source line CSL reaches the erase voltage VERS. At time point t13, the voltage of the lower source select line SSLd increases from the second voltage by the coupling voltage Vcpl. At time point t13, the lower source select transistor SSTd can be turned on by the voltage V2+Vcpl of the lower source select line SSLd.

[0170] Subsequently, the voltage of the common source line CSL can be maintained until the fourteenth time point t14. The voltage V2+Vcpl of the lower source select line SSLd can also be maintained until the fourteenth time point t14. Therefore, a GIDL current is generated in the upper source select transistor SSTu, and the erase operation of the memory cell is performed. A second voltage V2 is applied to the intermediate source select transistor SSTm, and the intermediate source select transistor SSTm can be used as a buffer between the upper source select transistor SSTu and the lower source select transistor SSTd.

[0171] according to Figure 16 In the illustrated implementation, the time period between the tenth time point t10 and the eleventh time point t11 ​​can be defined as an initialization operation, the time period between the eleventh time point t11 ​​and the twelfth time point t12 can be defined as a pre-charge operation, and the time period between the twelfth time point t12 and the fourteenth time point t14 can be defined as an erase operation. During the initialization operation, the voltages of word lines WL1 to WLn, the upper source select line SSLu, the middle source select line SSLm, the lower source select line SSLd, and the common source line CSL can be initialized. During the pre-charge operation, the voltages of the middle source select line SSLm and the lower source select line SSLd can be pre-charged to a second voltage V2. The lower source select line SSLd can be floated at the end of the pre-charge period. Subsequently, during the erase operation, an erase voltage VERS is applied to the common source line CSL. Furthermore, the voltage of the lower source select line SSLd increases through coupling, thus turning on the lower source select transistor SSTd. Since the voltage of the upper source select line SSLu remains at the first voltage V1, a GIDL current can be generated in the upper source select transistor SSTu, thus allowing the memory cell to be erased.

[0172] Figure 17 This is a flowchart illustrating a method for operating a semiconductor memory device to erase memory cells in a selected memory block according to yet another embodiment of the present disclosure. (See also...) Figure 17 The method of operating a semiconductor memory device includes: applying a first voltage to a first source select line, a second source select line, and a third source select line (S410); applying a second voltage greater than the first voltage to the third source select line (S430); floating the third source select line and the second source select line adjacent to the third source select line (S450); and applying an erase voltage to a common source line (S470).

[0173] In operation S410, the source selection line connected to the memory block to be erased (e.g., ...) is sent to the source selection line. Figure 14 A first voltage is applied to the upper source select line SSLu, the middle source select line SSLm, and the lower source select line SSLd. Figure 17 In the middle, the first source selection line can be Figure 14 The upper source selection line SSLu, and the second source selection line can be Figure 14 The intermediate source selection line is SSLm. The third source selection line can be... Figure 14 The lower source select line SSLd. The first voltage can be the voltage applied to the gate of the source select transistor to generate the GIDL current. In an embodiment, the first voltage can be ground voltage.

[0174] In operation S430, a second voltage is applied to the third source selection line among the multiple source selection lines, which is positioned adjacent to the common source line CSL. That is, a second voltage can be applied to... Figure 14 A second voltage is applied to the lower source select line SSLd. In operation S430, it is still possible to apply a second source select line (i.e., the one adjacent to the third source select line among multiple source select lines) to the second source select line. Figure 14 A first voltage is applied to the intermediate source select line (SSLm). Furthermore, in operation S430, a first voltage can still be applied to the first source select line (i.e., the one adjacent to the second source select line). Figure 14 A first voltage is applied to the upper source selection line (SSLu).

[0175] In operation S450, the third source selection line and the second source selection line (i.e., Figure 14 The lower source select line (SSLd) and the intermediate source select line (SSLm) are floated. In operation S450, the first source select line may not be floated. That is, in operation S450, a first voltage can still be applied to the first source select line.

[0176] Subsequently, in operation S470, an erase voltage is applied to the common source line CSL. As the erase voltage, as a high voltage, is applied to the common source line CSL, the second source select line and the third source select line (i.e., Figure 14 The voltages of the intermediate source select line SSLm and the lower source select line SSLd can also be increased through coupling. Therefore, the lower source select transistor SSTd connected to the lower source select line SSLd can be turned on. In this case, the intermediate source select transistor SSTm can be used as a buffer between the upper source select transistor SSTu and the lower source select transistor SSTd. During operation S470, a first voltage can still be applied to the first source select line (i.e., the upper source select line SSLu). Therefore, a GIDL current can be generated in the upper source select transistor SSTu. Therefore, the memory cells MC1 to MCn included in the cell string CSb can be erased.

[0177] Figure 18 This is a timing diagram illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure. (See also...) Figure 17 and Figure 18To describe this method.

[0178] Reference Figure 18 At the fifteenth time point t15, a first voltage V1 is applied to the upper source select line SSLu, the intermediate source select line SSLm, and the lower source select line SSLd (S410). As described above, the first voltage V1 is the voltage used to generate the GIDL current and can be the ground voltage GND. At the fifteenth time point t15, the ground voltage GND can be applied to the first word line WL1 to the nth word line WLn and the common source line CSL.

[0179] At time point t16, a second voltage V2 is applied to the lower source selection line SSLd, which is positioned adjacent to the common source line CSL (S430). The second voltage V2 is a voltage greater than the first voltage V1. Therefore, the lower source selection line SSLd is pre-charged.

[0180] At time point t17, the intermediate source select line SSLm and the lower source select line SSLd are floated (S450). Figure 16 In this process, the intermediate source selection line SSLm and the lower source selection line SSLd are floated at the seventeenth time point t17, but the present invention is not limited to this specific timing. That is, the intermediate source selection line SSLm and the lower source selection line SSLd can be floated at any time point between the sixteenth time point t16 and the seventeenth time point t17.

[0181] At time point t17 (seventeenth time), the erase voltage VERS (S470) is applied to the common source line CSL. The voltage of the common source line CSL can increase from time point t17 to time point t18 (eighteenth time). As the voltage of the common source line CSL increases, the voltages of the intermediate source select line SSLm and the lower source select line SSLd also begin to increase through coupling. Additionally, in this case, the voltage of the upper source select line SSLu remains at the first voltage V1.

[0182] At time point t18, the voltage of the common source line CSL reaches the erase voltage VERS. At time point t18, the voltages of the intermediate source select line SSLm and the lower source select line SSLd are increased by the coupling voltage Vcpl from the first voltage and the second voltage, respectively. At time point t18, the lower source select transistor SSTd can be turned on by the voltage V2 + Vcpl of the lower source select line SSLd. At time point t18, the intermediate source select transistor SSTm can be used as a buffer between the upper source select transistor SSTu and the lower source select transistor SSTd by the voltage V1 + Vcpl of the intermediate source select line SSLm.

[0183] Subsequently, the voltage of the common source line CSL can be maintained until the nineteenth time point t19. The voltage V2+Vcpl of the lower source select line SSLd can also be maintained until the nineteenth time point t19. Therefore, a GIDL current is generated in the upper source select transistor SSTu, thereby performing the erase operation of the memory cell. The voltage V1+Vcpl of the intermediate source select line SSLm is also maintained until the nineteenth time point t19.

[0184] according to Figure 18 In the illustrated implementation, the time period between the fifteenth time point t15 and the sixteenth time point t16 can be defined as an initialization operation, the time period between the sixteenth time point t16 and the seventeenth time point t17 can be defined as a precharge operation, and the time period between the seventeenth time point t17 and the nineteenth time point t19 can be defined as an erase operation. During the initialization operation, the voltages of word lines WL1 to WLn, the upper source select line SSLu, the middle source select line SSLm, the lower source select line SSLd, and the common source line CSL can be initialized. During the precharge operation, the voltage of the lower source select line SSLd can be precharged to the second voltage V2. The middle source select line SSLm and the lower source select line SSLd can be floated at the end of the precharge period. Subsequently, during the erase operation, an erase voltage VERS is applied to the common source line CSL. Furthermore, the voltages of the middle source select line SSLm and the lower source select line SSLd increase through coupling, thus turning on the lower source select transistor SSTd. Since the voltage of the upper source select line SSLu remains at the first voltage V1, a GIDL current is generated in the upper source select transistor SSTu, thus allowing the memory cell to be erased.

[0185] Figure 19 This is a circuit diagram illustrating the structure of a cell string included in a semiconductor memory device according to yet another embodiment of the present disclosure.

[0186] Reference Figure 19 The cell string CSd is connected between the bit line BL and the common source line CSL. Furthermore, the cell string CSd includes, in series, the a-th drain select transistors DSTA to DSTp, multiple memory cells MC1 to MCn, and the a-th source select transistors SSTa to SSTq. The a-th drain select line DSLa to the p-th drain select line DSLp are respectively connected to the gates of the a-th drain select transistors DSTA to DSTp. The a-th source select line SSLa to the q-th source select line SSLq are respectively connected to the gates of the a-th source select transistors SSTa to SSTq.

[0187] Region A may include any suitable number of source selection transistors SSTa to SSTq. (See reference...) Figure 20 Provide a more detailed description.

[0188] Figure 20 This is an example Figure 19 A circuit diagram illustrating an example of the connection structure of a source selection transistor. (Refer to...) Figure 20 In region A, the source selection transistors SSTa to SSTq (from the a-th to the q-th source selection transistors) are divided into an upper source selection transistor group GSSTu and a lower source selection transistor group GSSTd. More specifically, the source selection transistors SSTa to SSTi (from the a-th to the q-th source selection transistors SSTq) are included in the upper source selection transistor group GSSTu. The source selection transistors SSTj to SSTq (from the j-th to the q-th source selection transistors SSTq) are included in the lower source selection transistor group GSSTd.

[0189] The source selection lines SSLa to SSLi, which are respectively connected to the gates of the source selection transistors SSTa to SSTi, are included in the upper source selection line group GSSLu, and the source selection lines SSLj to SSLq, which are respectively connected to the gates of the source selection transistors SSTj to SSTq, are included in the lower source selection line group GSSLd.

[0190] Figure 21 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure. (Refer to...) Figure 21 A method for operating a semiconductor memory device includes: applying a first voltage to a first source select line group and a second source select line group (S510), floating the second source select line group adjacent to a common source line (S530), and applying an erase voltage to the common source line (S550). Referring hereafter... Figure 20 and Figure 21 Provide a description.

[0191] In operation S510, the source selection line connected to the memory block to be erased (e.g., ...) is sent to the source selection line. Figure 20 A first voltage is applied to the upper source selection line group GSSLu and the lower source selection line group GSSLd. Therefore, a first voltage is applied to the source selection lines SSLa to SSLq. Figure 21 In the middle, the first source selection line group can be Figure 20 The upper source selection line group GSSLu, and the second source selection line group can be Figure 20The lower source select line group GSSLd. The first voltage can be the voltage applied to the gate of the source select transistor to generate the GIDL current. In an embodiment, the first voltage can be ground voltage.

[0192] In operation S530, among the multiple source selection line groups, the second source selection line group positioned adjacent to the common source line CSL is floated. Therefore, the j-th source selection lines SSLj to q-th source selection lines SSLq included in the lower source selection line group GSSLd can be floated. In operation S530, the first source selection line group (i.e., not adjacent to the common source line CSL) is floated. Figure 20 The source selection lines SSLa to SSLi included in the upper source selection line group GSSLu can be not floated, and a first voltage can still be applied to the source selection lines SSLa to SSLi.

[0193] Subsequently, in operation S550, an erase voltage is applied to the common source line CSL. As the erase voltage, as a high voltage, is applied to the common source line CSL, the second source selection line group (i.e., Figure 20 The voltage of the j-th source selection line SSLj to the q-th source selection line SSLq included in the lower source selection line group GSSLd can also be increased through coupling. Therefore, the j-th source selection transistor SSTj to the q-th source selection transistor SSTq included in the lower source selection transistor group GSSTd can be turned on. In operation S550, a first voltage can still be applied to the first source selection line group (i.e., the upper source selection line group GSSLu). Therefore, a GIDL current can be generated in the a-th source selection transistor SSTa to the i-th source selection transistor SSTi included in the upper source selection transistor group GSSSu. Therefore, the memory cells MC1 to MCn included in the cell string CSd can be erased.

[0194] Figure 22 This is a flowchart illustrating a method for operating a semiconductor memory device to erase memory cells in a selected memory block according to another embodiment of the present disclosure. (See also...) Figure 22 The method of operating a semiconductor memory device includes: applying a first voltage to a first source select line group and a second source select line group (S610), applying a second voltage greater than the first voltage to the second source select line group adjacent to a common source line (S630), causing the second source select line group to float (S630), and applying an erase voltage to the common source line (S670).

[0195] In operation S610, the source selection line connected to the memory block to be erased (e.g., ...) is sent to the source selection line. Figure 20A first voltage is applied to the upper source select line group GSSLu and the lower source select line group GSSLd. Therefore, the first voltage is applied to the source select lines SSLa to SSLq. Figure 21 In the middle, the first source selection line group can be Figure 20 The upper source selection line group GSSLu, and the second source selection line group can be Figure 20 The lower source select line group GSSLd. The first voltage can be the voltage applied to the gate of the source select transistor to generate the GIDL current. In an embodiment, the first voltage can be ground voltage.

[0196] In operation S630, among the multiple source selection line groups, a second voltage greater than the first voltage is applied to the second source selection line group positioned adjacent to the common source line CSL. That is, in operation S630, a second voltage can be applied to... Figure 20 The lower source select line group GSSLd is pre-charged. During operation S630, a first voltage can still be applied to the first source select line group.

[0197] In operating the S650, the second source selection line group is made to float. That is, it can make... Figure 20 The lower source selection line group GSSLd is floating. In operation S650, the first source selection line group (i.e., not adjacent to the common source line CSL) is floating. Figure 20 The upper source select line group (GSSLu) can be left unfloated, and a first voltage can still be applied to the first source select line group (GSSLu).

[0198] Subsequently, in operation S670, an erase voltage is applied to the common source line CSL. As the erase voltage, as a high voltage, is applied to the common source line CSL, the second source selection line group (i.e., Figure 20 The voltage of the j-th source selection line SSLj to the q-th source selection line SSLq included in the lower source selection line group GSSLd can also be increased through coupling. Therefore, the j-th source selection transistor SSTj to the q-th source selection transistor SSTq included in the lower source selection transistor group GSSTd can be turned on. In operation S670, the first voltage can still be applied to the first source selection line group (i.e., the upper source selection line group GSSLu). Therefore, a GIDL current can be generated in the a-th source selection transistor SSTa to the i-th source selection transistor SSTi included in the upper source selection transistor group GSSLu. Therefore, the memory cells MC1 to MCn included in the cell string CSd can be erased.

[0199] Figure 23 This is an example Figure 19 A circuit diagram illustrating another example of the connection structure of a source selection transistor. (Refer to...) Figure 23The source selection transistors SSTa to SSTq shown in region A can be divided into an upper source selection transistor group GSSTu, an intermediate source selection transistor group GSSTm, and a lower source selection transistor group GSSTd. More specifically, among the source selection transistors SSTa to SSTq, the a-th to g-th source selection transistors SSTg are included in the upper source selection transistor group GSSTu. The h-th to k-th source selection transistors SSTk are included in the intermediate source selection transistor group GSSTm. Furthermore, the l-th to q-th source selection transistors SSTq are included in the lower source selection transistor group GSSTd.

[0200] The source selection lines SSLa to SSLg, which are respectively connected to the gates of the source selection transistors SST1 to SSTg, are included in the upper source selection line group GSSLu. The source selection lines SSLh to SSLk, which are respectively connected to the gates of the source selection transistors SST1 to SSTk, are included in the middle source selection line group GSSLm. The source selection lines SSLl to SSLq, which are respectively connected to the gates of the source selection transistors SST1 to SSTq, are included in the lower source selection line group GSSLd.

[0201] Figure 24 This is a flowchart illustrating a method for operating a semiconductor memory device to erase memory cells in a selected memory block according to another embodiment of the present disclosure. (See also...) Figure 24 The method of operating a semiconductor memory device includes: applying a first voltage to a first source select line group, a second source select line group, and a third source select line group (S710); applying a second voltage greater than the first voltage to the third source select line group adjacent to the common terminal and the second source select line group adjacent to the third source select line group (S730); floating the third source select line group (S750); and applying an erase voltage to the common source line (S770).

[0202] In operation S710, the source selection line connected to the memory block to be erased (e.g., ...) is sent to the source selection line. Figure 23 A first voltage is applied to the upper source select line group GSSLu, the middle source select line group GSSLm, and the lower source select line group GSSLd. Therefore, the first voltage is applied to the source select lines SSLa to SSLq. Figure 24 In the middle, the first source selection line group can be Figure 23 The upper source selection line group GSSLu, the second source selection line group can be Figure 23 The intermediate source selection line group GSSLm, and the third source selection line group can be Figure 23 The lower source select line group GSSLd. The first voltage can be the voltage applied to the gate of the source select transistor to generate the GIDL current. In an embodiment, the first voltage can be ground voltage.

[0203] In operation S730, among multiple source select line groups, a second voltage is applied to the third source select line group GSSL3, which is positioned adjacent to the common source line CSL. That is, a voltage can be applied to... Figure 23 A second voltage is applied to the lower source select line group GSSLd. In operation S730, the second voltage is similarly applied to the second source select line group adjacent to the third source select line group. That is, it can be applied to... Figure 23 A second voltage is applied to the intermediate source select line group GSSLm. Among the multiple source select line groups in operation S730, it is still possible to apply a second voltage to the first source select line group that is not adjacent to the third source select line group (i.e., Figure 23 The first voltage is applied to the upper source selection line group (GSSLu).

[0204] In operating the S750, the third source selection line group (i.e., Figure 23 The lower source select line group (GSSLd) is floated. In operation S750, the first source select line group and the second source select line group may not be floated. That is, in operation S750, a second voltage can still be applied to the second source select line group, and a first voltage can still be applied to the first source select line group.

[0205] Subsequently, in operation S770, an erase voltage is applied to the common source line CSL. As the erase voltage, as a high voltage, is applied to the common source line CSL, the third source selection line group (i.e., Figure 23 The voltage of the lower source select line group (GSSLd) can also be increased through coupling. Therefore, the lower source select transistor group (GSSTd) connected to the lower source select line group (GSSLd) can be turned on. In operation S770, a second voltage can still be applied to the second source select line group (i.e., the intermediate source select line group (GSSLm)) and a first voltage can still be applied to the first source select line group (i.e., the upper source select line group (GSSLu)). Therefore, a GIDL current can be generated in the upper source select transistor group (GSSTu). In this case, the intermediate source select transistor group (GSSTm) can be used as a buffer between the upper source select transistor group (GSSTu) and the lower source select transistor group (GSSTd). Therefore, the memory cells MC1 to MCn included in the cell string CSd can be erased.

[0206] Figure 25This is a flowchart illustrating a method for operating a semiconductor memory device to erase memory cells in a selected memory block according to another embodiment of the present disclosure. (See also...) Figure 25 The method of operating a semiconductor memory device includes: applying a first voltage to a first source select line group, a second source select line group, and a third source select line group (S810); applying a second voltage greater than the first voltage to the third source select line group adjacent to the common source line (S830); floating the third source select line group and the second source select line group adjacent to the third source select line group (S850); and applying an erase voltage to the common source line (S870).

[0207] In operation S810, the source selection line connected to the memory block to be erased (e.g., ...) is sent to the source selection line. Figure 23 A first voltage is applied to the upper source selection line group GSSLu, the middle source selection line group GSSLm, and the lower source selection line group GSSLd. Figure 25 In the middle, the first source selection line group can be Figure 23 The upper source selection line group GSSLu, the second source selection line group can be Figure 23 The intermediate source selection line group GSSLm, and the third source selection line group can be Figure 23 The lower source select line group GSSLd. The first voltage can be the voltage applied to the gate of the source select transistor to generate the GIDL current. In an embodiment, the first voltage can be ground voltage.

[0208] In operation S830, among multiple source selection line groups, a second voltage is applied to the third source selection line group positioned adjacent to the common source line CSL. That is, a voltage can be applied to... Figure 23 A second voltage is applied to the lower source select line group GSSLd. Among the multiple source select line groups in operation S830, a second source select line group adjacent to the third source select line group (i.e., Figure 23 A first voltage is applied to the intermediate source select line group (GSSLm). Furthermore, in operation S830, a first voltage can still be applied to the first source select line group (i.e., the one adjacent to the second source select line group). Figure 23 The first voltage is applied to the upper source selection line group (GSSLu).

[0209] In operation S850, the third source selection line group and the second source selection line group (i.e., Figure 23 The lower source select line group (GSSLd) and the middle source select line group (GSSLm) are floated. In operation S850, the first source select line group may not be floated. That is, in operation S850, a first voltage can still be applied to the first source select line group.

[0210] Subsequently, in operation S870, an erase voltage is applied to the common source line CSL. As the erase voltage, as a high voltage, is applied to the common source line CSL, the second source select line group and the third source select line group (i.e., Figure 23 The voltages of the intermediate source select line group GSSLm and the lower source select line group GSSLd are also increased through coupling. Therefore, the lower source select transistor group GSSTd connected to the lower source select line group GSSLd can be turned on. In this case, the intermediate source select transistor group GSSTm can be used as a buffer between the upper source select transistor group GSSTu and the lower source select transistor group GSSTd. During operation S870, a first voltage can still be applied to the first source select line group (i.e., the upper source select line group GSSLTu). Therefore, a GIDL current can be generated in the upper source select transistor group GSSTu. Therefore, the memory cells MC1 to MCn included in the cell string CSd can be erased.

[0211] according to Figures 9 to 25 The embodiment shown applies an erase voltage via the common source line CSL, generating a GIDL current in the source select transistor, thus erasing memory cells MC1 to MCn. However, the invention is not limited to this specific arrangement. An erase voltage can be applied to the bit line BL, generating a GIDL current in the drain select transistor, thus erasing memory cells MC1 to MCn. In the following, reference is made to... Figure 26 and Figure 27 This implementation method is described.

[0212] Figure 26 This is a flowchart illustrating a method for operating a semiconductor memory device to erase memory cells in a selected memory block according to another embodiment of the present disclosure. (See also...) Figure 25 The method of operating a semiconductor memory device includes: applying a first voltage to a first drain select line and a second drain select line (S910), floating the first drain select line adjacent to the bit line (S930), and applying an erase voltage to the bit line (S950).

[0213] In operation S910, the drain selection line connected to the memory block to be erased (e.g., ...) is selected. Figure 8 A first voltage is applied to the upper drain select line DSLu and the lower drain select line DSLd. Figure 26 In the middle, the first drain selection line can be Figure 8 The upper drain selection line of the DSLu, and the second drain selection line can be Figure 8 The lower drain select line DSLd. The first voltage can be the voltage applied to the gate of the drain select transistor to generate the GIDL current. In an embodiment, the first voltage can be ground voltage.

[0214] In operation S930, among multiple drain select lines, the first drain select line positioned adjacent to the bit line BL is floated. That is, it allows... Figure 8 The upper drain select line DSLu is floating. In operation S930, the second drain select line (i.e., not adjacent to the bit line BL) is... Figure 8 The lower drain select line (DSLd) can be left unfloated, and the first voltage can still be applied to the second drain select line.

[0215] Subsequently, in operation S950, an erase voltage is applied to the bit line BL. As the erase voltage, as a high voltage, is applied to the bit line BL, the first drain select line (i.e., Figure 8 The voltage of the upper drain select line (DSLu) can also be increased through coupling. Therefore, the upper drain select transistor DSTu, connected to the upper drain select line DSLu, can be turned on. In operation S950, the first voltage can still be applied to the second drain select line (i.e., the lower drain select line DSLd). Therefore, a GIDL current can be generated in the lower drain select transistor DSTd. Therefore, the memory cells MC1 to MCn included in the cell string CSb can be erased.

[0216] Figure 27 This is a timing diagram illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure. (See also...) Figure 26 and Figure 27 To describe this method.

[0217] Reference Figure 27 At the twentieth time point t20, a first voltage V1 is applied to the upper drain select line DSLu and the lower drain select line DSLd (S910). As described above, the first voltage V1 is the voltage used to generate the GIDL current and can be the ground voltage GND. At the twentieth time point t20, the ground voltage GND can be applied to the first word line WL1 to the nth word line WLn and the bit line BL.

[0218] At time point t21 (21st time), the upper drain selection line DSLu, positioned adjacent to the bit line BL, is floated (S930). Figure 27 In this invention, the upper drain selection line DSLu is floated at the 21st time point t21, but the invention is not limited to this specific timing. That is, the upper drain selection line DSLu can be floated at any time point between the 20th time point t20 and the 21st time point t21.

[0219] At time point t21 (21st time), the erase voltage VERS (S950) is applied to the bit line BL. The voltage of the bit line BL can increase from time point t21 (21st time) to time point t22 (22nd time). As the voltage of the bit line BL increases, the voltage of the upper drain select line DSLu begins to increase through coupling.

[0220] At time t22, the voltage of bit line BL reaches the erase voltage VERS. At time t22, the voltage of upper drain select line DSLu increases from the first voltage by the coupling voltage Vcpl. At time t22, upper drain select transistor DSTu can be turned on by the voltage V1+Vcpl of upper drain select line DSLu.

[0221] Subsequently, the voltage on bit line BL can be maintained until the twenty-third time point t23. The voltage V1+Vcpl on the upper drain select line DSLu can also be maintained until the twenty-third time point t23. Therefore, a GIDL current is generated in the lower drain select transistor DSTd, thereby performing the erase operation of the memory cell.

[0222] Reference Figures 9 to 25 This describes an implementation that applies an erase voltage via the common source line CSL, generates a GIDL current in the source selection transistor, and thereby erases memory cells MC1 to MCn. Furthermore, refer to... Figure 26 and Figure 27 An embodiment is described in which an erase voltage is applied to the bit line BL, generating a GIDL current in the drain select transistor, and thereby erasing memory cells MC1 to MCn. However, the invention is not limited to those specific arrangements. The erase voltage can be applied through the common source line CSL and the bit line BL, generating a GIDL current in the source select transistor and the drain select transistor, thereby erasing memory cells MC1 to MCn. In the following, reference is made to... Figure 28 This implementation method is described.

[0223] Figure 28 This is a flowchart illustrating a method for operating a semiconductor memory device to erase memory cells in a selected memory block according to another embodiment of the present disclosure. (See also...) Figure 28 The method of operating a semiconductor memory device includes: applying a first voltage to a first drain select line and a second drain select line, as well as a first source select line and a second source select line (S1010), floating a second source select line adjacent to a common source line and floating a first drain select line adjacent to a bit line (S1030), and applying an erase voltage to the common source line and the bit line (S1050).

[0224] In operation S1010, the drain selection line connected to the memory block to be erased (e.g., ...) is selected. Figure 8 A first voltage is applied to the upper drain select line DSLu and the lower drain select line DSLd. Figure 28 In the middle, the first drain selection line can be Figure 8 The upper drain selection line of the DSLu, and the second drain selection line can be Figure 8 The lower drain select line DSLd. The first voltage can be the voltage applied to the gate of the drain select transistor to generate the GIDL current. Furthermore, in operation S1010, the source select line (e.g., connected to the memory block to be erased) is... Figure 8 A first voltage is applied to the upper source select line SSLu and the lower source select line SSLd. Figure 28 In the middle, the first source selection line can be Figure 8 The upper source selection line SSLu, and the second source selection line can be Figure 8 The lower source select line SSLd. The first voltage can be the voltage applied to the gate of the source select transistor to generate the GIDL current. In an embodiment, the first voltage can be ground voltage.

[0225] In operation S1030, among multiple source selection lines, the second source selection line, positioned adjacent to the common source line CSL, is floated. That is, Figure 8 The lower source selection line SSLd can be floated. In operation S1030, the first source selection line (i.e., not adjacent to the common source line CSL) is floated. Figure 8 The upper source select line (SSLu) can be left unfloated, and a first voltage can still be applied to the first source select line. In operation S1030, among the multiple drain select lines, the first drain select line positioned adjacent to the bit line BL is floated. That is, Figure 8 The upper drain select line DSLu can be floated. In operation S1030, the second drain select line (i.e., not adjacent to the bit line BL) is... Figure 8 The lower drain select line (DSLd) can be left unfloated, and the first voltage can still be applied to the second drain select line.

[0226] Subsequently, in operation S1050, an erase voltage is applied to the common source line and the bit line BL. As the erase voltage, as a high voltage, is applied to the common source line CSL, the second source select line (i.e., Figure 8The voltage of the lower source select line (SSLd) can also be increased through coupling. Therefore, the lower source select transistor SSTd connected to the lower source select line SSLd can be turned on. In operation S1050, a first voltage can still be applied to the first source select line (i.e., the upper source select line SSLu). Therefore, a GIDL current can be generated in the upper source select transistor SSTu. Furthermore, as a high erase voltage is applied to the bit line BL, the voltage of the first drain select line (i.e., the lower source select line SSLu) can be increased. Figure 8 The voltage of the upper drain select line (DSLu) can also be increased through coupling. Therefore, the upper drain select transistor DSTu, connected to the upper drain select line DSLu, can be turned on. In operation S1050, the first voltage can still be applied to the second drain select line (i.e., the lower drain select line DSLd). Therefore, a GIDL current can be generated in the lower drain select transistor DSTd. Therefore, the memory cells MC1 to MCn included in the cell string CSb can be erased.

[0227] Figure 29 This example includes Figure 1 Block diagram of a memory system 1000 of a semiconductor memory device.

[0228] Reference Figure 29 The memory system 1000 includes a semiconductor memory device 100 and a memory controller 1100. The semiconductor memory device 100 can be compared with a reference... Figure 1 The semiconductor memory device described is the same.

[0229] Memory controller 1100 is connected to a host and semiconductor memory device 100. Memory controller 1100 is configured to access semiconductor memory device 100 in response to requests from the host. For example, memory controller 1100 is configured to control read operations, write operations, erase operations, and background operations of semiconductor memory device 100. Memory controller 1100 is configured to provide an interface between semiconductor memory device 100 and the host. Memory controller 1100 is configured to drive firmware for controlling semiconductor memory device 100.

[0230] The memory controller 1100 includes random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. RAM 1110 serves as any one of the following: operating memory of the processing unit 1120, a cache memory between the semiconductor memory device 100 and the host, and a buffer memory between the semiconductor memory device 100 and the host. The processing unit 1120 controls the overall operation of the memory controller 1100. Furthermore, the memory controller 1100 can temporarily store programming data provided from the host during write operations.

[0231] The host interface 1130 includes protocols for performing data exchange between the host and the memory controller 1100. In some embodiments, the memory controller 1100 is configured to communicate with the host via at least one of the following interface protocols: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Fast (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and / or proprietary protocols.

[0232] The memory interface 1140 is interfaced with the semiconductor memory device 100. For example, the memory interface includes a NAND interface or a NOR interface.

[0233] Error correction block 1150 is configured to use error correction codes (ECC) to detect and correct errors in data received from semiconductor memory device 100. In an embodiment, the error correction block may be configured as a component of memory controller 1100.

[0234] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device. In one embodiment, the memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to configure memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, or micro MMC), SD cards (SD, mini SD, micro SD, or SDHC), and / or universal flash memory (UFS).

[0235] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a semiconductor drive (solid-state drive (SSD)). A semiconductor drive (SSD) includes a storage device configured to store data in the semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of the host connected to the memory system 1000 is significantly improved.

[0236] As another example, the memory system 1000 is configured as one of the components of various electronic devices such as computers, ultra-mobile PCs (UMPCs), workstations, netbooks, personal digital assistants (PDAs), portable computers, network tablets, cordless phones, mobile phones, smartphones, e-books, portable multimedia players (PMPs), portable game consoles, navigation devices, black boxes, digital cameras, 3D televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, and digital video players; a device capable of transmitting and receiving information in a wireless environment; one of the various electronic devices configuring a home network; one of the various electronic devices configuring a computer network; one of the various electronic devices configuring a telematics network; an RFID device; or one of the various components configuring a computing system.

[0237] In implementations, the semiconductor memory device 100 or memory system 1000 can be mounted as any type of package of various kinds. For example, the semiconductor memory device 100 or memory system 1000 can be packaged and mounted in ways such as: package stack (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), wafer in a waffle, wafer-level package, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level fabrication stack-up package (WSP).

[0238] Figure 30 This is an example Figure 29 A block diagram illustrating an application example of a memory system.

[0239] Reference Figure 30 The memory system 2000 includes a semiconductor memory device 2100 and a memory controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups.

[0240] exist Figure 30 In this process, multiple groups communicate with the memory controller 2200 via channels CH1 to CHk, respectively. Each semiconductor memory chip communicates with a reference... Figure 1 The semiconductor memory device 100 described is similarly configured and operated.

[0241] Each group is configured to communicate with the memory controller 2200 via a common channel for that group. The memory controller 2200 and the reference... Figure 29 The memory controller 1100 described is similarly configured and is configured to control multiple memory chips of the semiconductor memory device 2100 via multiple channels CH1 to CHk.

[0242] Figure 31 This illustrates the example including references. Figure 30 A block diagram of the computing system describing the memory system.

[0243] The computing system 3000 includes a central processing unit 3100, random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, and a memory system 2000.

[0244] The memory system 2000 is electrically connected to the central processing unit 3100, RAM 3200, user interface 3300, and power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

[0245] exist Figure 31 In this configuration, semiconductor memory device 2100 is connected to system bus 3500 via memory controller 2200. However, semiconductor memory device 2100 can also be configured to be directly connected to system bus 3500. The functions of memory controller 2200 are performed by central processing unit 3100 and RAM 3200.

[0246] exist Figure 31 The middle provides a reference. Figure 30 The memory system described is 2000. However, it can be referenced... Figure 29 The memory system 1000 described herein replaces the memory system 2000. In an embodiment, the computing system 3000 may be configured to include a reference... Figure 29 and Figure 30 The memory systems 1000 and 2000 are described.

[0247] Although the invention has been illustrated and described in the context of various embodiments, those skilled in the art will understand from this disclosure that various modifications may be made to any of the disclosed embodiments within the spirit and scope of this disclosure. The invention covers all such modifications falling within the scope of the claims.

[0248] Cross-references to related applications

[0249] This application claims priority to Korean Patent Application No. 10-2020-0113410, filed on September 4, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: a memory string connected between a common source line and a bit line and including at least one first select transistor, a plurality of memory cells, and a plurality of second select transistors; and control logic configured to, during an erase operation, apply a first voltage to a first group among a plurality of second select lines respectively connected to the plurality of second select transistors, float a second group among the plurality of second select lines, and then apply an erase voltage to the common source line, wherein, as the erase voltage is applied to the common source line, a voltage of the second group among the plurality of second select lines increases by coupling. The first voltage generates a gate-induced drain leakage (GIDL) current in the second select transistor connected to a second select line in the first group.

2. The semiconductor memory device according to claim 1, wherein, The voltage of the second select line of the second group increases to a level that turns on the second select transistor connected to the second select line of the second group.

3. The semiconductor memory device according to claim 1, wherein, The second select line of the second group is positioned adjacent to the common source line.

4. The semiconductor memory device according to claim 1, wherein, 5. The semiconductor memory device of claim 1, during the erase operation, the control logic is further configured to pre-charge the second group to a second voltage higher than the first voltage, and wherein wherein the control logic floats the second group after performing a pre-charge operation.

6. The semiconductor memory device of claim 1, during the erase operation, the control logic is further configured to pre-charge the second group and a third group among the plurality of second select lines to a second voltage higher than the first voltage, and wherein wherein the control logic floats the second group after performing a pre-charge operation. The third group is positioned between the first group and the second group among the plurality of second select lines.

7. The semiconductor memory device of claim 6, wherein, 8. The semiconductor memory device of claim 1, during the erase operation, the control logic is further configured to apply the first voltage to a third group among the plurality of second select lines, wherein, wherein the control logic is further configured to float the third group after performing an apply operation, and wherein the control logic applies the erase voltage to the common source line after floating the second group and the third group. The third group is positioned between the first group and the second group among the plurality of second select lines.

9. The semiconductor memory device of claim 8, wherein, 10. A method of operating a semiconductor memory device including a cell string including a first drain select transistor and a second drain select transistor, a plurality of memory cells, a first source select transistor, and a second source select transistor connected in series between a bit line and a common source line, the method comprising the steps of: applying a first voltage to a first source select line connected to the first source select transistor; floating a second source select line connected to the second source select transistor; and increasing a voltage of the second source select line by applying an erase voltage to the common source line, ​ ​ wherein the first voltage is applied to the first source select line during the floating of the second source select line and the application of the erase voltage to the common source line.

11. The method of claim 10, further comprising the step of: The first voltage is applied to the second source select line prior to performing the floating operation.

12. The method of claim 10, further comprising the step of: The first voltage is applied to the second source select line prior to performing the floating operation.

13. The method of claim 10, wherein, The first voltage is a ground voltage.

14. The method of claim 10, wherein, The voltage of the second source select line is increased to a level that turns on the second source select transistor.

15. The method of claim 10, further comprising the step of: The first voltage is applied to the first source select line connected to the first source select transistor prior to floating the first source select line.

16. The method of claim 10, further comprising the steps of: The first voltage is applied to a second drain select line connected to the second drain select transistor prior to floating the second source select line; a first drain select line connected to the first drain select transistor is floated; and The voltage of the first drain select line is increased by applying the erase voltage to the bit line.

17. A method of operating a semiconductor memory device, the semiconductor memory device comprising a cell string comprising a drain select transistor, a plurality of memory cells, and a plurality of source select transistors connected in series between a bit line and a common source line, the source select transistors being grouped into an upper source select transistor group, a middle source select transistor group, and a lower source select transistor group, the method comprising the steps of: a first voltage is applied to an upper source select line group connected to the upper source select transistor group; a lower source select line group connected to the lower source select transistor group is floated; and the voltage of the lower source select line group is increased by applying an erase voltage to the common source line, wherein the first voltage is applied to the upper source select line group during the floating of the lower source select line group and the application of the erase voltage to the common source line.

18. The method of claim 17, wherein the lower source select line group is positioned adjacent to the common source line, and the method further comprises the step of applying a second voltage greater than the first voltage to the lower source select line group prior to performing the floating operation.

19. The method of claim 18, wherein a middle source select line group connected to the middle source select transistor group is positioned between the upper source select line group and the lower source select line group, and the method further comprises the step of applying the second voltage to the middle source select line group prior to performing the floating operation.

20. The method of claim 19, wherein, the second voltage is applied to the middle source select line group during the floating of the lower source select line group connected to the lower source select transistor group and the application of the erase voltage to the common source line.

21. The method of claim 18, wherein a middle source select line group connected to the middle source select transistor group is positioned between the upper source select line group and the lower source select line group, and The method further includes the step of applying the first voltage to the intermediate set of source select lines prior to performing the floating operation.

22. The method of claim 21, further comprising the step of: The intermediate set of source select lines is floated prior to performing the increasing voltage operation.

23. A method of operating a semiconductor memory device including a cell string including a first drain select transistor and a second drain select transistor connected in series between a bit line and a common source line, a plurality of memory cells, and a source select transistor, the method comprising the steps of: applying a first voltage to a first drain select line and a second drain select line connected to the first drain select transistor and the second drain select transistor, respectively; floating the first drain select line adjacent to the bit line; and increasing the voltage of the first drain select line by applying an erase voltage to the bit line, wherein the second drain select line is applied with the first voltage during floating the first drain select line and applying the erase voltage to the bit line.

24. A semiconductor memory device comprising: a memory block including a plurality of memory strings, each memory string having a set of memory cells coupled in series, a near set and a far set, each of the near set and the far set configured by one or more select transistors coupled in series, the near set disposed closer to an erase voltage line than the far set, and the erase voltage line being one of a common source line and a bit line each coupled to the memory string; and circuitry configured to: initialize a select line coupled to the far set, float a select line coupled to the near set, and provide an erase voltage to the erase voltage line to erase the memory block, wherein as the erase voltage is applied to the erase voltage line, the voltage of the select line coupled to the near set is increased by coupling.

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