Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, the substrate including a base, a gate structure on the substrate, source / drain doped layers on both sides of the gate structure, and an interlayer dielectric layer on both sides of the gate structure covering the source / drain doped layers; a first dielectric layer covering the gate structure and the interlayer dielectric layer; a first plug and a second plug penetrating the first dielectric layer and the interlayer dielectric layer, the first plug being connected to the source / drain doped layers, and the second plug being connected to the gate structure; the top surface of the first dielectric layer being higher than the top surfaces of the first and second plugs; forming a metal interconnect protection layer covering the sidewalls of the first dielectric layer; and forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a first via exposing the first plug and a second via exposing the second plug. The method improves the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the back-end fabrication of semiconductor devices, a metal interconnect structure formation process is typically required. This metal interconnect structure formation process is usually performed on a semiconductor substrate, which typically has active regions on which semiconductor devices such as transistors and capacitors are formed. The metal interconnect structure usually includes multilayer via interconnect structures and metal interconnects, with multiple layers of metal interconnects electrically connected through the via interconnect structures. When forming a subsequent metal interconnect on a previous layer of via interconnect structure, or vice versa, an interlayer dielectric layer is typically formed first on the previous via interconnect structure or metal interconnect. Then, vias and interconnect trenches are formed in the interlayer dielectric layer. Finally, the vias and interconnect trenches are filled with metal to form the subsequent via interconnect structure or metal interconnect.

[0003] In particular, after forming through holes or interconnecting trenches, and before filling the through holes and trenches with metal, an adhesive layer is usually formed on the bottom surface and sidewalls of the through holes or interconnecting trenches.

[0004] However, devices manufactured using existing semiconductor processes do not perform well. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the electrical performance of the device.

[0006] To address the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising:

[0007] A substrate is provided, the substrate including a substrate, a gate structure on the substrate, source and drain doped layers on both sides of the gate structure, and an interlayer dielectric layer on both sides of the gate structure and covering the source and drain doped layers, a first dielectric layer covering the gate structure and the interlayer dielectric layer, a first plug and a second plug penetrating the first dielectric layer and the interlayer dielectric layer, the first plug being connected to the source and drain doped layers, the second plug being connected to the gate structure, and the top surface of the first dielectric layer being higher than the top surfaces of the first plug and the second plug;

[0008] A metal interconnect protective layer is formed, which covers the sidewall of the first dielectric layer;

[0009] A second dielectric layer is formed on the first dielectric layer, and the second dielectric layer has a first through hole exposing the first plug and a second through hole exposing the second plug.

[0010] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising:

[0011] The substrate includes a substrate, a gate structure on the substrate, source and drain doped layers on both sides of the gate structure, and an interlayer dielectric layer on both sides of the gate structure and covering the source and drain doped layers, a first dielectric layer covering the gate structure and the interlayer dielectric layer, a first plug and a second plug penetrating the first dielectric layer and the interlayer dielectric layer, the first plug being connected to the source and drain doped layers, the second plug being connected to the gate structure, and the top surface of the first dielectric layer being higher than the top surfaces of the first plug and the second plug.

[0012] A metal interconnect protective layer, wherein the metal interconnect protective layer conformally covers the sidewall of the first dielectric layer;

[0013] A second dielectric layer covers the first dielectric layer, and the second dielectric layer has a first through hole exposing the first plug and a second through hole exposing the second plug.

[0014] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0015] In the semiconductor structure formation method provided by this invention, before connecting the first plug connecting the source / drain doped layer and the second plug connecting the gate structure, a metal interconnect protection layer is first formed on the sidewall of a first dielectric layer whose top surface is higher than the top surface of the first and second plugs. Then, a second dielectric layer is formed on the first dielectric layer. The second dielectric layer has a first via exposing the first plug and a second via exposing the second plug. During the etching process of forming the second dielectric layer, the metal interconnect protection layer can serve as an etching stop layer, thereby preventing the first dielectric layer used to isolate the first and second plugs from being etched away. Subsequently, after a third plug is formed in the first and second vias, the metal interconnect protection layer and the first dielectric layer between the metal interconnect protection layers together serve as an isolation structure between the first and second plugs, preventing the third plug from simultaneously connecting the first and second plugs, thereby preventing the third plug from simultaneously connecting the source / drain doped layer and the gate structure, and improving the electrical performance of the semiconductor structure. As can be seen, in the semiconductor structure formation method provided by the embodiments of the present invention, since the metal interconnect protection layer is disposed on the sidewall of the first dielectric layer, when the first through hole and the second through hole are formed on the second dielectric layer covering the first dielectric layer, the metal interconnect protection layer can separate the first plug and the second plug, thereby avoiding the first through hole or the second through hole from being connected to the gate structure and the source / drain doped layer at the same time due to alignment deviation, thereby improving the electrical performance of the device. Attached Figure Description

[0016] Figures 1 to 7 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0017] Figures 8 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0018] The devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0019] Please refer to Figures 1-7 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0020] like Figure 1As shown, a substrate is provided, the substrate including a substrate 100, a gate structure 101 located on the substrate 100, source / drain doped layers 102 located on both sides of the gate structure 101, and an interlayer dielectric layer 103 located on both sides of the gate structure 101 and covering the source / drain doped layers 102, a first dielectric layer 106 covering the gate structure 101 and the interlayer dielectric layer 103, a first plug 107 and a second plug 108 penetrating the first dielectric layer 106 and the interlayer dielectric layer 103, the first plug 107 being connected to the source / drain doped layers 102, the second plug 108 being connected to the gate structure 101, and the top surface of the first dielectric layer 106 being flush with the top surfaces of the first plug 107 and the second plug 108;

[0021] like Figure 2 As shown, a second dielectric material layer 109a is formed, which covers the first dielectric layer 103, the first plug 107, and the second plug 108.

[0022] like Figure 3 As shown, an anti-reflective material layer (not shown) is formed on the second dielectric material layer 109a; a photoresist layer 111 is formed on the anti-reflective material layer; the anti-reflective material layer is etched using the photoresist layer 111 as a mask to form an anti-reflective coating 110.

[0023] Next, as Figure 4 As shown, the second dielectric material layer is etched using the photoresist layer 111 and the anti-reflective coating 110 as masks to form a first through hole 115 exposing the first plug 107 and a second through hole 112 exposing the second plug 108, respectively.

[0024] like Figure 5 As shown, a metal material layer 113 is formed, which fills the first through-hole and the second through-hole and covers the second dielectric layer 109.

[0025] like Figure 6 As shown, the metal material layer 113 is planarized to form a third plug 114 whose top surface is flush with the top surface of the second dielectric layer 109.

[0026] Since the first through-hole 115 and the second through-hole 112 are formed using photolithography and etching processes, during the formation of the first through-hole 115 and the second through-hole 112, due to the problem of overlay shift, the dimensions of the first through-hole 115 and the second through-hole 112 in the fin extension direction are easily offset, such as... Figure 6 As shown, in the fin extension direction, the distance between the first plug and the second plug is relatively close (e.g. Figure 6As shown in circle A), if the alignment deviation between the first through hole 115 and the second through hole 112 is large, it will cause the closely spaced first and second through holes to connect. Then, when the third plug 114 is formed into the first and second through holes, it will cause the third plug 114 formed in the first and second through holes to be electrically connected, thereby causing the first plug 107 and the second plug 108 below it (as shown in circle A) to connect. Figure 7 (As shown in dashed box B) Electrical connection will cause the gate structure 101 and the source / drain doped layer 102 to connect after the device is powered on, resulting in a short circuit and affecting the electrical performance of the device.

[0027] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate, a gate structure located on the substrate, source / drain doped layers located on both sides of the gate structure, and an interlayer dielectric layer located on both sides of the gate structure and covering the source / drain doped layers; a first dielectric layer covering the gate structure and the interlayer dielectric layer; a first plug and a second plug penetrating the first dielectric layer and the interlayer dielectric layer, the first plug being connected to the source / drain doped layers, the second plug being connected to the gate structure, and the top surface of the first dielectric layer being higher than the top surfaces of the first plug and the second plug; forming a metal interconnect protection layer, the metal interconnect protection layer covering the sidewalls of the first dielectric layer; forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a first via exposing the first plug and a second via exposing the second plug.

[0028] In the semiconductor structure formation method provided by this invention, before connecting the first plug connecting the source / drain doped layer and the second plug connecting the gate structure, a metal interconnect protection layer is first formed on the sidewall of a first dielectric layer whose top surface is higher than the top surface of the first and second plugs. Then, a second dielectric layer is formed on the first dielectric layer. The second dielectric layer has a first via exposing the first plug and a second via exposing the second plug. During the etching process of forming the second dielectric layer, the metal interconnect protection layer can serve as an etching stop layer, thereby preventing the first dielectric layer used to isolate the first and second plugs from being etched away. Subsequently, after a third plug is formed in the first and second vias, the metal interconnect protection layer and the first dielectric layer between the metal interconnect protection layers together serve as an isolation structure between the first and second plugs, preventing the third plug from simultaneously connecting the first and second plugs, thereby preventing the third plug from simultaneously connecting the source / drain doped layer and the gate structure, and improving the electrical performance of the semiconductor structure. As can be seen, in the semiconductor structure formation method provided by the embodiments of the present invention, since the metal interconnect protection layer is disposed on the sidewall of the first dielectric layer, when the first through hole and the second through hole are formed on the second dielectric layer covering the first dielectric layer, the metal interconnect protection layer can separate the first plug and the second plug, thereby avoiding the first through hole or the second through hole from being connected to the gate structure and the source / drain doped layer at the same time due to alignment deviation, thereby improving the electrical performance of the device.

[0029] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Figures 8 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0031] like Figures 8-9 As shown, a substrate is provided, the substrate including a substrate 200, a gate structure 201 located on the substrate 200, source / drain doped layers 202 located on both sides of the gate structure 201, and an interlayer dielectric layer 203 located on both sides of the gate structure 201 and covering the source / drain doped layers 202, a first dielectric layer 206 covering the gate structure 201 and the interlayer dielectric layer 203, a first plug 207 and a second plug 208 penetrating the first dielectric layer 206 and the interlayer dielectric layer 203, the first plug 207 being connected to the source / drain doped layers 202, the second plug 208 being connected to the gate structure 201, and the top surface of the first dielectric layer 206 being higher than the top surfaces of the first plug 207 and the second plug 208.

[0032] The substrate provides a process platform for the subsequent formation of semiconductors.

[0033] This embodiment uses a FinFET (Fin Field-Effect Transistor) semiconductor structure as an example. Accordingly, the substrate includes a substrate 200 and fins 204 located on the substrate 200. In other embodiments, the semiconductor structure can also be a planar transistor (MOSFET).

[0034] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0035] When the subsequently formed semiconductor structure is in operation, the fin 204 at the bottom of the gate structure 201 is used as a channel region.

[0036] In this embodiment, the fin 204 is made of silicon. In other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0037] The gate structure 201 spans the fin 204 and covers part of the top wall and part of the side wall of the fin 204.

[0038] The gate structure 201 is used to turn the channel on or off when the semiconductor structure is in operation.

[0039] Specifically, the material of the gate structure 201 includes metal.

[0040] In this embodiment, the gate structure 201 includes a work function layer (not shown in the figure) and a metal gate layer (not shown in the figure) located on the work function layer.

[0041] When a semiconductor structure is in operation, the work function layer is used to regulate the threshold voltage of the transistor.

[0042] In this embodiment, the material of the metal gate layer includes a magnesium-tungsten alloy. In other embodiments, the material of the metal gate layer includes one or more of Co, Ru, and W.

[0043] When the semiconductor structure is in operation, the source and drain doped layers 202 are used to provide stress to the channel and improve the migration rate of charge carriers in the channel.

[0044] In this embodiment, the semiconductor structure is used to form an NMOS (Negative Channel Metal Oxide Semiconductor), and the source / drain doped layer 202 is silicon carbide or silicon phosphide doped with N-type ions. The N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions.

[0045] In other embodiments, the semiconductor structure can also be used to form a PMOS (Positive Channel Metal Oxide Semiconductor). The source and drain doped layers are silicon germanide doped with P-type ions. The P-type ions include one or more of boron ions, gallium ions, and indium ions.

[0046] Interlayer dielectric layer 203 is used for electrical isolation of adjacent devices.

[0047] In this embodiment, the material of the interlayer dielectric layer 203 is an insulating material. Specifically, the material of the interlayer dielectric layer 203 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 203.

[0048] It should be noted that, in the step of providing the substrate, a gate cap layer 205 is formed on the gate structure 201.

[0049] During the subsequent formation of the semiconductor structure, the gate cap layer 205 is used to protect the top of the gate structure 201 from damage.

[0050] In this embodiment, the gate capping layer 205 is also formed on the interlayer dielectric layer 203. In other embodiments, the gate capping layer may be formed only on top of the gate structure 201.

[0051] In this embodiment, the material of the gate cap layer 205 includes one or more of silicon nitride, silicon oxynitride, silicon carbonitride, and boron nitride silicon carbide.

[0052] The first dielectric layer 206 is used to electrically isolate the first plug 207 of the source / drain doped layer 202 and the second plug 208 of the gate structure 201.

[0053] The first dielectric layer 206 covers the gate structure 201 and the interlayer dielectric layer 203. In this embodiment, the gate cap layer 205 covers the gate structure 201 and the interlayer dielectric layer 203. Therefore, the first dielectric layer 206 covers the gate structure 201 and the interlayer dielectric layer 203 by covering the gate cap layer 205.

[0054] In this embodiment, the first dielectric layer 206 is made of an insulating material. Specifically, the material of the first dielectric layer can be one or a combination of at least two of silicon oxide, silicon nitride, or silicon carbide. In one specific embodiment, the material of the first dielectric layer 206 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the difficulty and cost of forming the dielectric layer.

[0055] The first plug 207 is used to connect the source / drain doped layer 102 to the subsequent metal.

[0056] Specifically, the material of the first plug 207 includes one or more of Co, W, Ta, TaN, Ti, and TiN. In this embodiment, the material of the first plug 207 includes W.

[0057] The second plug 208 is used to connect the gate structure 201 to the rear metal section.

[0058] Specifically, the material of the second plug 208 includes one or more of Co, W, Ta, TaN, Ti, and TiN. In this embodiment, the material of the second plug 208 includes W.

[0059] Specifically, please combine Figure 9 refer to Figure 8 In this embodiment, the substrate formation step is as follows:

[0060] An initial substrate is provided, wherein a first initial plug 207a and a second initial plug 208a are formed through the first dielectric layer 206 and the interlayer dielectric layer 203, the first initial plug 207a is connected to the source / drain doped layer 202, and the second initial plug 208a is connected to the gate structure 201, wherein the top of the first dielectric layer 206 is flush with the top of the first initial plug 207a and the top of the second initial plug 208a;

[0061] The first initial plug and the second initial plug of the first thickness are etched back to form the first plug and the second plug, such that the height of the first dielectric layer is greater than the height of the first plug and the second plug.

[0062] The top surface of the first dielectric layer 206 is higher than the top surfaces of the first plug 207 and the second plug 208, providing space for the subsequent formation of a metal interconnect protection layer on the sidewall of the first dielectric layer 206.

[0063] In this embodiment, the top surface of the first dielectric layer 206 is made higher than the top surfaces of the first plug 207 and the second plug 208 through a back-etching process. Back-etching is a dry etching process, which has anisotropic etching characteristics and good control over the etching profile, which is beneficial to ensuring that the final morphology meets the process requirements.

[0064] Of course, in other embodiments, during the process of depositing the first plug and the second plug into the opening of the first dielectric layer, the first plug and the second plug may partially fill the opening of the first dielectric layer, thereby making the top of the first dielectric layer 206 higher than the top of the first plug and the second plug.

[0065] like Figure 8 and Figure 9 As shown, in order to improve the firmness of the first plug 207a and the second plug 208a, the substrate further includes an adhesive layer 214, which surrounds the bottom and sidewalls of the first initial plug 207a and the second initial plug 208a.

[0066] The adhesive layer 214 is used to fix the first plug 207 and the second plug 208, so as to prevent the first plug 207 from detaching from the source / drain doped layer 202 and the second plug 208 from detaching from the gate structure 201 during the planarization process of the first initial plug 207a and the second initial plug 208a.

[0067] In this embodiment, the adhesive layer 214 is made of titanium nitride. In other embodiments, the adhesive layer may also be made of titanium.

[0068] When the adhesive layer 214 is present, the steps of etching back the first initial plug and the second initial plug of the first thickness are as follows:

[0069] Simultaneously, the first initial plug, the second initial plug, and the adhesive layer 214 of the first thickness H are etched.

[0070] It is easy to understand that before forming the first plug 207 and the second plug 208, the first dielectric layer 206 and the interlayer dielectric layer 203 need to be etched first to form trenches exposing the source and drain doped layers 202 and vias exposing the gate structure 201. Then, metal material layers are filled in the trenches and vias, and finally, a planarization process is performed to form the first plug 207 and the second plug 208. According to the etching process, when forming the trenches that accommodate the first plug 207 and the vias that accommodate the second plug 208, the cross-sectional shape of the trenches and vias is an inverted trapezoid that is wider at the top and narrower at the bottom. Thus, the cross-sectional shape of the first plug and the second plug formed in the trenches and vias is also an inverted trapezoid that is wider at the top and narrower at the bottom. Along the fin extension direction, the closer to the top of the first plug 207 and the second plug 208, the closer the first plug 207 and the second plug 208 are.

[0071] Therefore, by etching back the first and second initial plugs to a first thickness, the top of the first dielectric layer is made higher than the tops of the first and second plugs. Since the distance between the first and second plugs along the fin extension direction increases as they are closer to the substrate, etching back the first and second initial plugs to a first thickness effectively increases the distance between the first and second plugs. This avoids the connection between the gate structure and the source / drain doped layers after power-on caused by the diffusion of the adhesive layer, further improving the electrical performance of the semiconductor structure.

[0072] like Figure 9As shown, the height difference between the top surface of the first dielectric layer 206 and the top surfaces of the first plug 207 and the second plug 208 is the first thickness H.

[0073] It should be noted that the first thickness H should not be too small or too large. If the first thickness H is too small, the height of the subsequently formed metal interconnect protective layer will also be too small, which is not conducive to the protective effect; if the first thickness H is too large, it will increase the material and deposition time of the subsequent metal interconnect protective layer. Therefore, in this embodiment, the height difference between the top surface of the first dielectric layer and the top surfaces of the first plug and the second plug is within the range of...

[0074] Next, refer to Figure 10 and Figure 11 A metal interconnect protective layer 209 is formed, which covers the sidewall of the first dielectric layer 206.

[0075] The metal interconnect layer 209 is used to protect the first plug 207 and the second plug 208, preventing the subsequent formation of a third plug 213 (shown in the figure) above the first plug 207 and the second plug 208. Figure 16 The gate structure and source / drain doped layers are connected due to alignment deviation.

[0076] In this embodiment, the material of the metal interconnect protective layer 209 is silicon nitride. In other embodiments, the material of the metal interconnect protective layer may also be one or a combination of at least two of silicon nitride, silicon carbide, and silicon oxynitride.

[0077] Specifically, such as Figure 10 As shown, the steps for forming the metal interconnect protective layer 209 include:

[0078] A metal interconnect protective material layer 209a is formed, which conformally covers the top surface and sidewalls of the first dielectric layer 206 and the top surfaces of the first plug 207 and the second plug 208; the metal interconnect protective material layers corresponding to the top surfaces of the first dielectric layer 206, the first plug 207, and the second plug 208 are etched to form a metal interconnect protective layer 209 (shown in...). Figure 11 ).

[0079] Of course, when an adhesive layer is present, the metal interconnect protective material layer also conformally covers the top surface of the adhesive layer.

[0080] In this embodiment, the metal interconnect protective material layer can be formed using Chemical Vapor Deposition (CVD). CVD is a method for generating a thin film by chemically reacting one or more gaseous compounds or elements containing thin film elements. It has good step coverage and allows for precise control of the thickness of the metal interconnect protective material layer. Of course, in other embodiments, the process for forming the metal interconnect protective material layer includes one or more of Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and CVD.

[0081] In this embodiment, as Figure 11 As shown, a dry etching process is used to etch the metal interconnect protective material layer on the top of the first plug 207 and the second plug 208, leaving the remaining metal interconnect protective material layer on the sidewall of the first dielectric layer 206 as the metal interconnect protective layer. During the etching of the metal interconnect protective material layer, the first plug 207 and the second plug 208 serve as etching stop layers.

[0082] like Figures 12-14 As shown, a second dielectric layer 210 is formed on the first dielectric layer 206. Figure 14 As shown), the second dielectric layer 210 has a first through hole 211 exposing the first plug 207 and a second through hole 212 exposing the second plug 208.

[0083] The first through hole 211 and the second through hole 212 provide process space for the subsequent formation of the third plug.

[0084] In this embodiment, the material of the second dielectric layer 210 is an insulating material. Specifically, the material of the second dielectric layer can be one or a combination of at least two of silicon oxide, silicon nitride, or silicon carbide. In one specific embodiment, the material of the second dielectric layer 210 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the difficulty and cost of forming the dielectric layer.

[0085] The steps for forming the second dielectric layer include:

[0086] A second dielectric material layer is formed, which covers the first dielectric layer and fills the space enclosed by the metal interconnect protection layer; the second dielectric material layer above the first plug and the second plug is etched to form the second dielectric layer.

[0087] Specifically, such as Figure 12 and Figure 13As shown, a second dielectric material layer 210a is formed on the substrate. The second dielectric material layer 210a covers the top of the first dielectric layer, the metal interconnect protection layer, the first plug, and the top of the second plug. The top of the second dielectric material layer is planar. A patterned photoresist layer 212 and an anti-reflection layer 214 are formed on the top of the second dielectric material layer. Using the photoresist layer 212 and the anti-reflection layer 214 as an etching mask, the second dielectric material layer 210a above the first plug and the second plug is etched to form a second dielectric layer 210. The second dielectric layer has a first through-hole 211 exposing the first plug 207 and a second through-hole 212 exposing the second plug 208.

[0088] It should be noted that, Figure 13 Four gate structures 201 are shown. Figure 13 The second plug in the section corresponds only to two gate structures 201; the second plugs corresponding to the other two gate structures 201 are in other cross-sections. Figure 13 The first one in Figure 13 The second plug (leftmost) is connected to the first plug, and the gate structure is connected to the source and drain doped layers, belonging to a local interconnect structure (share contact). This embodiment of the invention uses a local interconnect structure as an example for illustration. Of course, in other embodiments, the leftmost first plug and the second plug may not be interconnected, depending on the actual process.

[0089] It is easy to understand that, such as Figure 13 As shown, the process of forming the second dielectric layer includes photolithography and etching. If an overlay occurs during photolithography, for example, the leftmost pattern of the photoresist shifts to the right and the middle pattern shifts to the left, the distance between the two patterns along the fin extension direction will decrease. Then, during the etching of the second dielectric material layer to form the first and second vias, the distance between the first and second vias along the fin extension direction will decrease. Without a metal interconnect protection layer, it is easy to cause the first or second via to expose the first and second plugs simultaneously. Subsequently, a third plug is formed into the first and second vias. After power is applied, it will cause a short circuit between the gate structure and the source / drain doped layer, affecting the electrical performance of the semiconductor structure.

[0090] In this embodiment of the invention, by forming a metal interconnect protective layer on the sidewall of the first dielectric layer, the metal interconnect protective layer can serve as an etching stop layer during the etching process of forming the second dielectric layer. This prevents the first dielectric layer used to isolate the first and second plugs from being etched away. Subsequently, after the third plug is formed in the first and second vias, the metal interconnect protective layer and the first dielectric layer between the metal interconnect protective layers together serve as an isolation structure for the first and second plugs. This prevents the third plug from simultaneously connecting to the first and second plugs, thereby preventing the third plug from simultaneously connecting to the source / drain doped layer and the gate structure, thus improving the electrical performance of the semiconductor structure. Therefore, the semiconductor structure formation method provided by this embodiment of the invention, because the metal interconnect protective layer is disposed on the sidewall of the first dielectric layer, when the first and second vias are formed on the second dielectric layer covering the first dielectric layer, the metal interconnect protective layer can separate the first and second plugs, preventing the first or second via from simultaneously connecting to the gate structure and the source / drain doped layer due to alignment deviations, thereby improving the electrical performance of the device.

[0091] Next, please refer to Figure 15 and Figure 16 After the second dielectric layer is formed, it also includes:

[0092] A third plug 213 is formed, which fills the first through hole and the second through hole.

[0093] It is easy to understand that the first plug 207 connecting the source / drain doped layers 202 is typically an elongated strip structure extending along the extension direction of the gate structure 201, the second plug 208 connecting the gate structure 201 is typically a hole-type structure, and the third plug 213 is used to connect the gate structure 201 and the source / drain doped layers 202 on the same layer. The third plug 213 is typically a hole-type structure to reduce the contact resistance of the semiconductor structure. On the other hand, not all source / drain doped layers 202 and gate structures 201 need to be connected. Therefore, depending on the process requirements, the third plug 213 is used to connect the gate structure 201 that needs to be connected and the source / drain doped layers 202 that need to be connected.

[0094] like Figure 15 As shown, the steps for forming the third plug include:

[0095] A third metal material layer 213a is formed on the substrate, the third metal material layer 213a covers the second dielectric layer 210 and fills the first through hole and the second through hole; the third metal material layer 213a is planarized to form the third plug 213.

[0096] Specifically, the planarization process includes chemical mechanical planarization (CMP), in which the top of the second dielectric layer is used as the planarization stop position during the step of removing the third metal material layer 213a above the second dielectric layer.

[0097] In this embodiment, the material of the third plug includes W. In other embodiments, the material of the third plug includes metallic materials such as Co, Ru, W, Ag, Au, Pt, Ni, Ti, Al, or Cu, or other conductive materials.

[0098] Correspondingly, such as Figure 16 As shown, embodiments of the present invention also provide a semiconductor structure, comprising:

[0099] The substrate includes a substrate 200, a gate structure 201 on the substrate, source / drain doped layers 202 on both sides of the gate structure 201, and an interlayer dielectric layer 203 on both sides of the gate structure 201 and covering the source / drain doped layers 202. A first dielectric layer 206 covers the gate structure 201 and the interlayer dielectric layer 203. A first plug 207 and a second plug 208 penetrate the first dielectric layer 206 and the interlayer dielectric layer 203. The first plug 207 is connected to the source / drain doped layers 202, and the second plug 208 is connected to the gate structure 201. The top of the first dielectric layer 206 is higher than the top of the first plug 207 and the second plug 208.

[0100] A metal interconnect protective layer 209 conformally covers the sidewall of the first dielectric layer 206;

[0101] The second dielectric layer 210 covers the first dielectric layer 206. The second dielectric layer 210 has a first through hole exposing the first plug and a second through hole exposing the second plug.

[0102] The substrate provides a process platform for the subsequent formation of semiconductors.

[0103] This embodiment uses a FinFET (Fin Field-Effect Transistor) semiconductor structure as an example. Accordingly, the substrate includes a substrate 200 and fins 204 located on the substrate 200. In other embodiments, the semiconductor structure can also be a planar transistor (MOSFET).

[0104] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0105] When the subsequently formed semiconductor structure is in operation, the fin 204 at the bottom of the gate structure 201 is used as a channel region.

[0106] In this embodiment, the fin 204 is made of silicon. In other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0107] The gate structure 201 spans the fin 204 and covers part of the top wall and part of the side wall of the fin 204.

[0108] The gate structure 201 is used to turn the channel on or off when the semiconductor structure is in operation.

[0109] Specifically, the material of the gate structure 201 includes metal.

[0110] In this embodiment, the gate structure 201 includes a work function layer (not shown in the figure) and a metal gate layer (not shown in the figure) located on the work function layer.

[0111] When a semiconductor structure is in operation, the work function layer is used to regulate the threshold voltage of the transistor.

[0112] In this embodiment, the material of the metal gate layer includes a magnesium-tungsten alloy. In other embodiments, the material of the metal gate layer includes one or more of Co, Ru, and W.

[0113] When the semiconductor structure is in operation, the source and drain doped layers 202 are used to provide stress to the channel and improve the migration rate of charge carriers in the channel.

[0114] In this embodiment, the semiconductor structure is used to form an NMOS (Negative Channel Metal Oxide Semiconductor), and the source / drain doped layer 202 is silicon carbide or silicon phosphide doped with N-type ions. The N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions.

[0115] In other embodiments, the semiconductor structure can also be used to form a PMOS (Positive Channel Metal Oxide Semiconductor). The source and drain doped layers are silicon germanide doped with P-type ions. The P-type ions include one or more of boron ions, gallium ions, and indium ions.

[0116] Interlayer dielectric layer 203 is used for electrical isolation of adjacent devices.

[0117] In this embodiment, the material of the interlayer dielectric layer 203 is an insulating material. Specifically, the material of the interlayer dielectric layer 203 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 203.

[0118] It should be noted that the substrate also includes a gate cap layer 205, which is disposed on the gate structure 201.

[0119] The gate cap layer 205 is used to protect the top of the gate structure 201 from damage.

[0120] In this embodiment, the gate cap layer 205 is also disposed on the interlayer dielectric layer 203. In other embodiments, the gate cap layer may be disposed only on the top of the gate structure 201.

[0121] In this embodiment, the material of the gate cap layer 205 includes one or more of silicon nitride, silicon oxynitride, silicon carbonitride, and boron nitride silicon carbide.

[0122] The first dielectric layer 206 is used to electrically isolate the first plug 207 of the source / drain doped layer 202 and the second plug 208 of the gate structure 201.

[0123] The first dielectric layer 206 covers the gate structure 201 and the interlayer dielectric layer 203. In this embodiment, the gate cap layer 205 covers the gate structure 201 and the interlayer dielectric layer 203. Therefore, the first dielectric layer 206 covers the gate structure 201 and the interlayer dielectric layer 203 by covering the gate cap layer 205.

[0124] In this embodiment, the first dielectric layer 206 is made of an insulating material. Specifically, the material of the first dielectric layer can be one or a combination of at least two of silicon oxide, silicon nitride, or silicon carbide. In one specific embodiment, the material of the first dielectric layer 206 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the difficulty and cost of forming the dielectric layer.

[0125] The first plug 207 is used to connect the source / drain doped layer 102 to the subsequent metal.

[0126] Specifically, the material of the first plug 207 includes one or more of Co, W, Ta, TaN, Ti, and TiN. In this embodiment, the material of the first plug 207 includes W.

[0127] The second plug 208 is used to connect the gate structure to the back metal.

[0128] Specifically, the material of the second plug 208 includes one or more of Co, W, Ta, TaN, Ti, and TiN. In this embodiment, the material of the second plug 208 includes W.

[0129] The top surface of the first dielectric layer 206 is higher than the top surfaces of the first plug 207 and the second plug 208, providing space for the subsequent formation of a metal interconnect protection layer on the sidewall of the first dielectric layer 206.

[0130] In this embodiment, the top surface of the first dielectric layer 206 is higher than the top surfaces of the first plug 207 and the second plug 208 through a back etching process. Back etching is a dry etching process, which has anisotropic etching characteristics and good control over the etching profile, making it easier to ensure that the final morphology meets the process requirements.

[0131] Of course, in other embodiments, during the process of depositing the first plug and the second plug into the opening of the first dielectric layer, the first plug and the second plug may partially fill the opening of the first dielectric layer, thereby making the top of the first dielectric layer 206 higher than the top of the first plug and the second plug.

[0132] The substrate further includes an adhesive layer 214, which surrounds the bottom and sidewalls of the first plug and the second plug;

[0133] The adhesive layer 214 is used to fix the first plug 207 and the second plug 208, improve the firmness of the first plug 207 and the second plug 208, and prevent the first plug 207 from detaching from the source / drain doped layer 202 and the second plug 208 from detaching from the gate structure 201.

[0134] In this embodiment, the adhesive layer 214 is made of titanium nitride. In other embodiments, the adhesive layer may also be titanium.

[0135] It is easy to understand that before forming the first and second plugs, the first dielectric layer and the interlayer dielectric layer need to be etched to form trenches exposing the source and drain doped layers and vias exposing the gate structure. Then, metal material layers are filled into the trenches and vias, and finally, a planarization process is performed to form the first and second plugs. According to the etching process, when forming the trenches to accommodate the first plugs and the vias to accommodate the second plugs, the cross-sectional shape of the trenches and vias is an inverted trapezoid that is wider at the top and narrower at the bottom. Thus, the cross-sectional shape of the first and second plugs formed in the trenches and vias is also an inverted trapezoid that is wider at the top and narrower at the bottom. Along the fin extension direction, the closer to the top of the first and second plugs, the closer the first and second plugs are.

[0136] Therefore, by etching back the first and second initial plugs to a first thickness, the top of the first dielectric layer is made higher than the tops of the first and second plugs. Since the distance between the first and second plugs along the fin extension direction increases as they are closer to the substrate, etching back the first and second initial plugs to a first thickness effectively increases the distance between the first and second plugs. This avoids the connection between the gate structure and the source / drain doped layers after power-on caused by the diffusion of the adhesive layer, further improving the electrical performance of the semiconductor structure.

[0137] The height difference between the top surface of the first dielectric layer and the top surfaces of the first plug and the second plug is the first thickness H.

[0138] It should be noted that the first thickness H should not be too small or too large. If the first thickness H is too small, the height of the subsequently formed metal interconnect protective layer will also be too small, which is not conducive to the protective effect; if the first thickness H is too large, it will increase the material and deposition time of the subsequent metal interconnect protective layer. Therefore, in this embodiment, the height difference between the top surface of the first dielectric layer and the top surfaces of the first plug and the second plug is within the range of...

[0139] It should be noted that, Figure 16 Four gate structures 201 are shown. Figure 16 The second plug in the section corresponds only to two gate structures 201; the second plugs corresponding to the other two gate structures 201 are in other cross-sections. Figure 16 The first one in Figure 16 The second plug (leftmost) is connected to the first plug, and the gate structure is connected to the source and drain doped layers, belonging to a local interconnect structure (share contact). This embodiment of the invention uses a local interconnect structure as an example for illustration. Of course, in other embodiments, the leftmost first plug and the second plug may not be interconnected, depending on the actual process.

[0140] The metal interconnect layer 209 is used to protect the first plug and the second plug, and to prevent the third plug 213 from being connected to the gate structure and the source / drain doped layer simultaneously due to alignment deviation.

[0141] In this embodiment, the material of the metal interconnect protective layer 209 is silicon nitride. In other embodiments, the material of the metal interconnect protective layer may also be one or a combination of at least two of silicon nitride, silicon carbide, and silicon oxynitride.

[0142] In this embodiment, the process for forming the metal interconnect protective layer is a dry etching process.

[0143] In this embodiment, the material of the second dielectric layer 210 is an insulating material. Specifically, the material of the second dielectric layer can be one or a combination of at least two of silicon oxide, silicon nitride, or silicon carbide. In one specific embodiment, the material of the second dielectric layer 210 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the difficulty and cost of forming the dielectric layer.

[0144] The semiconductor structure provided in this embodiment of the invention further includes a third plug 213, which fills the first through hole and the second through hole.

[0145] In this embodiment, the material of the third plug 213 includes W. In other embodiments, the material of the third plug includes metallic materials such as Co, Ru, W, Ag, Au, Pt, Ni, Ti, Al, or Cu, or other conductive materials.

[0146] It is easy to understand that the process of forming the second dielectric layer includes photolithography and etching. If an alignment misalignment (overlay) occurs during the photolithography process, the distance between the first and second vias along the fin extension direction will become smaller during the etching process to form the first via and the second via. Without a metal interconnect protection layer, it is easy to cause the first or second via to expose the first plug and the second plug at the same time. Then the third plug formed in the first and second vias will connect the gate structure and the source / drain doped layer at the same time. After power is applied, it will cause a short circuit between the gate structure and the source / drain doped layer, affecting the electrical performance of the semiconductor structure.

[0147] In this embodiment of the invention, by forming a metal interconnect protective layer on the sidewall of the first dielectric layer, the metal interconnect protective layer can serve as an etching stop layer during the etching process of forming the second dielectric layer. This prevents the first dielectric layer used to isolate the first and second plugs from being etched away. Subsequently, after the third plug is formed in the first and second vias, the metal interconnect protective layer and the first dielectric layer between the metal interconnect protective layers together serve as an isolation structure for the first and second plugs. This prevents the third plug from simultaneously connecting to both the first and second plugs, thereby preventing the third plug from simultaneously connecting to the source / drain doped layer and the gate structure, thus improving the electrical performance of the semiconductor structure. Therefore, the semiconductor structure provided by this embodiment of the invention, because the metal interconnect protective layer is disposed on the sidewall of the first dielectric layer, can separate the first and second plugs when forming the first and second vias on the second dielectric layer covering the first dielectric layer. This prevents the first or second via from simultaneously connecting to the gate structure and the source / drain doped layer due to alignment deviations, thereby improving the electrical performance of the semiconductor structure.

[0148] The semiconductor structure described in this embodiment can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0149] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate, a gate structure on the substrate, source and drain doped layers on both sides of the gate structure, and an interlayer dielectric layer on both sides of the gate structure and covering the source and drain doped layers, a first dielectric layer covering the gate structure and the interlayer dielectric layer, a first plug and a second plug penetrating the first dielectric layer and the interlayer dielectric layer, the first plug being connected to the source and drain doped layers, the second plug being connected to the gate structure, and the top surface of the first dielectric layer being higher than the top surfaces of the first plug and the second plug; A metal interconnect protective layer is formed, which covers the sidewall of the first dielectric layer located above the top surfaces of the first plug and the second plug; A second dielectric layer is formed on the first dielectric layer, and the second dielectric layer has a first through hole exposing the first plug and a second through hole exposing the second plug.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the metal interconnect protective layer includes: A metal interconnect protective material layer is formed, which conformally covers the top and sidewalls of the first dielectric layer, the top of the first plug, and the top of the second plug; The metal interconnect protective material layer on top of the first dielectric layer, the first plug, and the second plug is etched to form a metal interconnect protective layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The steps for forming the substrate include: An initial substrate is provided, wherein a first initial plug and a second initial plug are formed through the first dielectric layer and the interlayer dielectric layer, the first initial plug is connected to the source / drain doped layer, the second initial plug is connected to the gate structure, and the top of the first dielectric layer is flush with the top of the first initial plug and the top of the second initial plug. The first initial plug and the second initial plug of the first thickness are etched back to form the first plug and the second plug, such that the height of the first dielectric layer is greater than the height of the first plug and the second plug.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The substrate further includes an adhesive layer that surrounds the bottom and sidewalls of the first and second initial plugs; The steps for etching the first initial plug and the second initial plug to the first thickness are as follows: Simultaneously, the first initial plug, the second initial plug, and the adhesive layer of the first thickness are etched.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps for forming the second dielectric layer include: A second dielectric material layer is formed on the substrate, the second dielectric material layer covering the first dielectric layer and filling the space enclosed by the metal interconnect protective layer; The second dielectric material layer above the first plug and the second plug is etched to form a second dielectric layer.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the second dielectric layer is formed, the process also includes: A third plug is formed, which fills the first through hole and the second through hole.

7. The method for forming a semiconductor structure as described in claim 5, characterized in that, The steps to form the third plug include: A third metal material layer is formed on the substrate, the third metal material layer covering the second dielectric layer and filling the first via and the second via; The third metal material layer is planarized to form the third plug.

8. The method for forming a semiconductor structure according to any one of claims 1-7, characterized in that, The range of the height difference between the top surface of the first dielectric layer and the top surfaces of the first plug and the second plug is:

9. The method for forming a semiconductor structure according to any one of claims 1-7, characterized in that, The material of the metal interconnect protective layer is one or a combination of at least two of silicon nitride, silicon carbide, and silicon oxynitride.

10. The method for forming a semiconductor structure according to any one of claims 1-7, characterized in that, The metal interconnect protective layer is formed using a dry etching process.

11. The method for forming a semiconductor structure according to any one of claims 1-7, characterized in that, The first dielectric layer and the second dielectric layer are made of silicon oxide, silicon carbide, or silicon nitride, or a combination of at least two of these materials.

12. A semiconductor structure, characterized in that, include: The substrate includes a substrate, a gate structure on the substrate, source and drain doped layers on both sides of the gate structure, and an interlayer dielectric layer on both sides of the gate structure and covering the source and drain doped layers, a first dielectric layer covering the gate structure and the interlayer dielectric layer, a first plug and a second plug penetrating the first dielectric layer and the interlayer dielectric layer, the first plug being connected to the source and drain doped layers, the second plug being connected to the gate structure, and the height of the first dielectric layer being greater than the height of the first plug and the second plug. A metal interconnect protective layer conformally covers the sidewall of the first dielectric layer located above the top surfaces of the first and second plugs; A second dielectric layer covers the first dielectric layer, and the second dielectric layer has a first through hole exposing the first plug and a second through hole exposing the second plug.

13. The semiconductor structure as described in claim 12, characterized in that, Also includes: A third plug fills the first through hole and the second through hole.

14. The semiconductor structure as claimed in claim 12, characterized in that, The range of the height difference between the first dielectric layer and the heights of the first plug and the second plug is:

15. The semiconductor structure as described in claim 12, characterized in that, The process for forming the metal interconnect protective layer is a dry etching process.

16. The semiconductor structure as claimed in claim 12, characterized in that, Also includes: An adhesive layer surrounds the bottom and sidewalls of the first and second plugs.

17. The semiconductor structure as claimed in claim 16, characterized in that, The adhesive layer is made of titanium nitride or titanium.

18. The semiconductor structure according to any one of claims 12-17, characterized in that, The material of the metal interconnect protective layer is one or a combination of at least two of silicon nitride, silicon carbide, and silicon oxynitride.

19. The semiconductor structure according to any one of claims 12-17, characterized in that, The first dielectric layer and the second dielectric layer are made of silicon oxide, silicon carbide, or silicon nitride, or a combination of at least two of these materials.

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