Transistor and its fabrication method

Abstract

This application provides a transistor and a method for fabricating the same. The method includes: providing a substrate, a solution, an active layer material, and an auxiliary electrode; the substrate includes a base, a gate, and a gate insulating layer sequentially stacked together; the active layer material is dispersed in the solution and is charged; the auxiliary electrode is placed on one side of the substrate facing the gate; the solution is placed between the auxiliary electrode and the gate insulating layer; and an electric field is applied to the gate and the auxiliary electrode to form an electric field between the auxiliary electrode and the gate; the charge of the gate is opposite to that of the active layer material in the solution, and the active layer material is deposited on the gate insulating layer under the action of the electric field to form an active layer. The transistor and fabrication method provided in this application can achieve self-alignment of the bottom gate and the active layer.

Description

Technical Field

[0001] This application relates to the field of transistor technology, specifically to a transistor and a method for manufacturing the same. Background Technology

[0002] A bottom-gate transistor (BGT) is a type of transistor in which the gate is formed on a substrate, while the active layer is formed above the gate and separated from it by a gate insulating layer. In existing technologies, the active layer is typically formed by first depositing an initial active layer using chemical vapor deposition (CVD), followed by patterning the initial active layer using dry etching. Because of the opaque gate insulating layer between the gate and the active layer, this layer can affect the effective self-alignment of the active layer and the gate during dry etching. Summary of the Invention

[0003] Therefore, this application provides a method for fabricating a transistor capable of forming an effective self-aligned transistor with a gate, and a transistor thereof.

[0004] In a first aspect, this application provides a method for manufacturing a transistor, comprising:

[0005] A substrate, a solution, an active layer material, and an auxiliary electrode are provided; wherein, the substrate includes a substrate, at least one gate, and a gate insulating layer sequentially stacked together; the active layer material is dispersed in the solution, and the active layer material dispersed in the solution is charged;

[0006] The auxiliary electrode is placed on one side of the substrate, facing the gate; and the solution is placed between the auxiliary electrode and the gate insulating layer; and

[0007] The gate and the auxiliary electrode are energized to form an electric field between the auxiliary electrode and the gate; the electrical properties of the gate are opposite to those of the active layer material in the solution, and the active layer material is deposited on the gate insulating layer under the action of the electric field to form an active layer.

[0008] In an optional embodiment of this application, the solution is coated or dropped onto the gate insulating layer.

[0009] In an optional embodiment of this application, the electric field is a vertical electric field or a horizontal electric field.

[0010] In an optional embodiment of this application, the auxiliary electrode faces the gate insulating layer; one auxiliary electrode corresponds to one gate.

[0011] In an optional embodiment of this application, a plurality of the auxiliary electrodes are formed on an auxiliary substrate, the auxiliary substrate being located above the substrate.

[0012] In an optional embodiment of this application, the auxiliary electrode is located on the substrate and adjacent to at least one of the gate electrodes.

[0013] In an optional embodiment of this application, the auxiliary electrode is located between two adjacent gate electrodes.

[0014] In an optional embodiment of this application, the auxiliary electrode and the gate are located on the same surface of the substrate.

[0015] In an optional embodiment of this application, the auxiliary electrode and the gate are located on opposite surfaces of the substrate.

[0016] In an optional embodiment of this application, the auxiliary electrode is grounded.

[0017] In an optional embodiment of this application, one of the two adjacent gates serves as the auxiliary electrode.

[0018] In an optional embodiment of this application, the active layer material is at least one of oxide semiconductor, quantum dot, perovskite material, and organic semiconductor material.

[0019] In an optional embodiment of this application, the solvent of the solution is a polar solvent system or a non-polar solvent system.

[0020] In one optional embodiment of this application, the active layer material carries a positive or negative charge in the solution;

[0021] When the active layer material is positively charged in the solution, the electricity in the gate is negatively charged, and the electricity in the auxiliary electrode is positively charged; and

[0022] When the active layer material carries a negative charge in the solution, the electricity in the gate is positive and the electricity in the auxiliary electrode is negative.

[0023] In an optional embodiment of this application, the mass percentage of the active layer material in the solution is defined as W%, the thickness of the deposited active layer is h, the height of the solution is H, and the density of the deposited active layer is ρ. Then W% = ρ*h / H.

[0024] In an optional embodiment of this application, the active layer includes a channel region, and the method for fabricating the transistor further includes:

[0025] A source-drain layer is formed on the active layer, the source-drain layer including a source and a drain, and the channel region is directly opposite the gap between adjacent sources and drains.

[0026] This application also provides a transistor comprising a substrate, at least one gate, a gate insulating layer and an active layer stacked sequentially, wherein the active layer is formed on the gate insulating layer and faces the gate; the active layer is formed on the gate insulating layer by an electrodeposition process, and the orthogonal projections of the active layer and the gate on the substrate completely overlap.

[0027] In an optional embodiment of this application, the transistor further includes an auxiliary electrode located on the substrate, the auxiliary electrode being located between two adjacent gates, and the gates and the auxiliary electrode being located on the same surface of the substrate.

[0028] The transistor fabrication method provided in this application disperses the active layer material in a polar or non-polar solvent system, making the active layer material conductive. By using an auxiliary electrode and applying a voltage to both the auxiliary electrode and the bottom gate (the voltage of the bottom gate is opposite to that of the active layer material), a horizontal or vertical electric field can be formed between the auxiliary electrode and the bottom gate. Under the influence of the electric field, the charged active layer material is deposited on the gate insulating layer to form the active layer of the transistor. Since the electric field lines between the bottom gate and the auxiliary electrode start from the positive electrode and terminate at the negative electrode without outward expansion, the orthogonal projection of the deposited active layer and the bottom gate on the substrate completely overlaps, thereby achieving self-alignment between the bottom gate and the active layer. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A flowchart illustrating a preferred embodiment of the transistor fabrication method provided in this application.

[0031] Figure 2 A cross-sectional view of a substrate, an auxiliary electrode, and a solution in which the active layer material is dispersed, provided in a preferred embodiment of this application.

[0032] Figure 3 This is a schematic diagram of the deposition of an active layer material under the action of an electric field, provided in an embodiment of this application.

[0033] Figure 4 This is a schematic diagram of the deposition of an active layer material under the action of an electric field, provided in another embodiment of this application.

[0034] Figure 5 This is a schematic diagram of the deposition of an active layer material under the action of an electric field, which is provided in another embodiment of this application.

[0035] Figure 6 This is a cross-sectional view of a transistor formed on an active layer, according to a preferred embodiment of this application. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0037] In the description of this application, it should be understood that the terms "upper," "lower," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0038] Reference numerals and / or reference letters may be repeated in different embodiments of this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0039] This application addresses the technical problem of existing technologies where the bottom gate and active layer cannot achieve self-alignment. It provides a transistor and its fabrication method, in which the active layer material is dispersed in a polar or non-polar solvent system, making the active layer material conductive. By using an auxiliary electrode and applying a voltage to both the auxiliary electrode and the bottom gate (the voltage of the bottom gate is opposite to that of the active layer material), a horizontal or vertical electric field can be formed between the auxiliary electrode and the bottom gate. Under the influence of the electric field, the charged active layer material is deposited on the gate insulating layer, forming the active layer of the transistor. Since the electric field lines between the bottom gate and the auxiliary electrode start from the positive terminal and terminate at the negative terminal without outward expansion, the orthogonal projections of the deposited active layer and the bottom gate on the substrate completely overlap, thereby achieving self-alignment between the bottom gate and the active layer.

[0040] Please see Figure 1-5 The preferred embodiment of this application provides a method for manufacturing a transistor 100, including the following steps:

[0041] Step S1, please refer to Figure 1 and Figure 2 The system provides a substrate 10, a solution (not shown), an active layer material (not shown), and an auxiliary electrode 40; wherein the substrate 10 includes a substrate 11, at least one gate 12, and a gate insulating layer 13 stacked together in sequence; the active layer material 30 is dispersed in the solution 20 and is charged.

[0042] The solvent of the solution is either a polar solvent system or a non-polar solvent system.

[0043] The active layer material is at least one of oxide semiconductors, quantum dots, perovskite materials, and organic semiconductor materials. Specifically, the organic semiconductor material can be pentacene, etc.

[0044] In polar solvent systems, organic compounds can lose an OH group. - Or H + The remaining functional groups will be charged. Because nanoparticles can be modified with ligands on their surface, the ligands lose H... + Or OH - Subsequently, the surface of the nanoparticles becomes charged. Therefore, the active layer material carries a positive or negative charge in the solution.

[0045] Wherein, the mass percentage of the active layer material in the solution is defined as W%, the thickness of the deposited active layer is h, the height of the solution is H, and the density of the deposited active layer is ρ, then W% = ρ*h / H.

[0046] For step S2, please refer to [link / reference]. Figure 1 , Figure 2 , Figure 4 and Figure 5 The auxiliary electrode 40 is placed on one side of the substrate 10 and faces the gate 12; and the solution is placed between the auxiliary electrode 40 and the gate insulating layer 13.

[0047] Specifically, the solution is coated or dropped onto the gate insulating layer 13.

[0048] Please see Figure 2 In an optional embodiment of this application, the auxiliary electrode 40 faces the gate insulating layer 13; one auxiliary electrode 40 corresponds to one gate 12.

[0049] Please see Figure 2 In an optional embodiment of this application, a plurality of the auxiliary electrodes 40 are formed on an auxiliary substrate 41, which is located above the substrate 10.

[0050] Please see Figure 4 In an optional embodiment of this application, one of the two adjacent gates 12 serves as the auxiliary electrode 40.

[0051] Please see Figure 5 In an optional embodiment of this application, the auxiliary electrode 40 is located on the substrate 11 and adjacent to at least one of the gates 12. Specifically, the auxiliary electrode 40 is located between two adjacent gates 12.

[0052] In an optional embodiment of this application, the auxiliary electrode 40 and the gate 12 are located on the same surface of the substrate 11.

[0053] In an optional embodiment of this application, the auxiliary electrode 40 and the gate electrode 12 are located on opposite surfaces of the substrate 11.

[0054] In an optional embodiment of this application, the auxiliary electrode 40 is grounded.

[0055] Step S3, please refer to Figure 1 and Figures 3 to 5 The gate 12 and the auxiliary electrode 40 are energized to form an electric field E between the auxiliary electrode 40 and the gate 12. The electrical properties of the gate 12 are opposite to those of the active layer material in the solution. The active layer material is deposited on the gate insulating layer 13 under the action of the electric field E to form an active layer 50.

[0056] The active layer 50 includes a channel region 51.

[0057] In an optional embodiment of this application, the electric field E is a vertical electric field or a horizontal electric field.

[0058] Specifically, when the active layer material is positively charged in the solution, the electricity in the gate 12 is negative and the electricity in the auxiliary electrode 40 is positive; and when the active layer material is negatively charged in the solution, the electricity in the gate 12 is positive and the electricity in the auxiliary electrode 40 is negative.

[0059] Since the electrical properties of the gate 12 are opposite to those of the active layer material in the solution, under the action of the electric field E, the active layer material will move toward the gate 12 and be deposited on the gate insulating layer 13.

[0060] In an optional embodiment of this application, the electric field E is a vertical electric field or a horizontal electric field.

[0061] Specifically, please refer to Figure 3Since the auxiliary electrode 40 is located above the gate insulating layer 13, when electricity with opposite polarities is applied to the auxiliary electrode 40 and the gate 12—for example, the auxiliary electrode 40 is positive, the gate 12 is negative, and the active layer material is positive—an electric field E is formed between the auxiliary electrode 40 and the gate 12. This electric field E is a perpendicular electric field, with electric field lines pointing from the positive electrode 40 to the negative electrode 12. Under the influence of this electric field E, the active layer material is deposited on the gate insulating layer 13 to form the active layer 50. Alternatively, the auxiliary electrode 40 can be negative, the gate 12 can be positive, and the active layer material can be negative.

[0062] Specifically, please refer to Figure 4 In an optional embodiment of this application, the electrical charges passed through two adjacent gates 12 are opposite in nature, thus forming a horizontal electric field between the two adjacent gates 12. This is because the active layer material is deposited on the gate insulating layer 13 at a position corresponding to one of the gates 12 with an electrical charge opposite to that of the active layer material.

[0063] Specifically, please refer to Figure 5 In an optional embodiment of this application, one of the auxiliary electrodes 40 is located between the two gates 12. When the electrical current supplied to one of the gates 12 is opposite to that supplied to the auxiliary electrode 40, a horizontal electric field is formed between the gate 12 and the auxiliary electrode 40.

[0064] In other embodiments, an electric current with the same polarity but opposite polarity to that of the auxiliary electrode 40 can be passed through two adjacent gates 12. In this case, two active layers 50 corresponding to the two gates 12 can be deposited simultaneously.

[0065] For step S4, please refer to [link / reference]. Figure 6 A source-drain layer 60 is formed on the active layer 50. The source-drain layer 60 includes a source 61 and a drain 62. The channel region 51 is directly opposite the gap between adjacent source 61 and drain 62.

[0066] Please see Figure 6 This application also provides a transistor 100, which includes a substrate 11, at least one gate 12, a gate insulating layer 13, and an active layer 50 stacked sequentially together. The active layer 50 is formed on the gate insulating layer 13 and faces the gate 12. The active layer 50 is formed on the gate insulating layer 13 by an electrodeposition process, and the orthogonal projections of the active layer 50 and the gate 12 on the substrate 11 completely overlap. The electrodeposition process can refer to steps S1 to S3 as described above.

[0067] In an optional embodiment of this application, the transistor 100 further includes an auxiliary electrode 40 located on the substrate 11, the auxiliary electrode 40 being located between two adjacent gates 12, and the gates 12 and the auxiliary electrode 40 being located on the same surface of the substrate 11.

[0068] Of course, the transistor 100 also includes a passivation layer (not shown) and a planarization layer (not shown) covering the source and drain layers 60.

[0069] This application also provides an array substrate (not shown), the array substrate including the transistor 100 and an anode (not shown) formed on the planarization layer, a pixel definition layer (not shown) formed on the anode, and a light-emitting unit. The anode penetrates the planarization layer and the passivation layer and is electrically connected to the source-drain layer, the pixel definition layer has a plurality of pixel openings, and the light-emitting unit is located in the pixel openings.

[0070] The transistor fabrication method provided in this application disperses the active layer material in a polar or non-polar solvent system, making the active layer material conductive. By using an auxiliary electrode and applying a voltage to both the auxiliary electrode and the bottom gate (the voltage of the bottom gate is opposite to that of the active layer material), a horizontal or vertical electric field can be formed between the auxiliary electrode and the bottom gate. Under the influence of the electric field, the charged active layer material is deposited on the gate insulating layer to form the active layer of the transistor. Since the electric field lines between the bottom gate and the auxiliary electrode start from the positive electrode and terminate at the negative electrode without outward expansion, the orthogonal projection of the deposited active layer and the bottom gate on the substrate completely overlaps, thereby achieving self-alignment between the bottom gate and the active layer.

[0071] The transistors and their manufacturing methods provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method of fabricating a transistor, comprising: The method comprises: providing a substrate, a solution, an active layer material and an auxiliary electrode; wherein the substrate comprises a substrate, at least one gate electrode and a gate insulating layer stacked together; the active layer material is dispersed in the solution, and the active layer material dispersed in the solution is charged; placing the auxiliary electrode on one side of the substrate; and placing the solution between the auxiliary electrode and the gate insulating layer; and applying electricity to the gate electrode and the auxiliary electrode to form an electric field between the auxiliary electrode and the gate electrode; the electric property of the gate electrode is opposite to the electric property of the active layer material in the solution, and the active layer material is deposited on the gate insulating layer under the action of the electric field to form an active layer.

2. The method of claim 1, wherein the step of forming the gate electrode is performed by forming a gate electrode comprising a first layer of a first material and a second layer of a second material, the first material being different from the second material. The solution is coated or dropped on the gate insulating layer.

3. The method of claim 1, wherein the step of forming the gate electrode is performed by forming a gate electrode comprising a first layer of a first material and a second layer of a second material, the first material being different from the second material. The electric field is a vertical electric field or a horizontal electric field.

4. The method of claim 3, wherein the step of forming the gate electrode is performed by forming a gate electrode comprising a first layer of a first material and a second layer of a second material, the first material being different from the second material. The auxiliary electrode faces the gate insulating layer; one auxiliary electrode corresponds to one gate electrode.

5. The method of claim 4, wherein the step of forming the gate electrode is performed by forming a gate electrode comprising a first layer of a first material and a second layer of a second material, the first material being different from the second material. A plurality of auxiliary electrodes are formed on an auxiliary substrate, and the auxiliary substrate is located above the substrate.

6. The method of claim 3, wherein the step of forming the gate electrode is performed by forming a gate electrode comprising a first layer of a first material and a second layer of a second material, the first material being different from the second material. The auxiliary electrode is located on the substrate and adjacent to at least one gate electrode.

7. The method of claim 6, wherein the step of forming the gate electrode is performed by forming a gate electrode comprising a first layer of a first material and a second layer of a second material, the first material being different from the second material. The auxiliary electrode is located between two adjacent gate electrodes.

8. The method of claim 7, wherein the step of forming the gate electrode is performed by forming a gate electrode comprising a first layer of a first material and a second layer of a second material, the first material being different from the second material. The auxiliary electrode and the gate electrode are located on the same surface of the substrate.

9. The method of claim 7, wherein the step of forming the gate electrode is performed by forming a gate electrode comprising a first layer of a first material and a second layer of a second material, the first material being different from the second material. The auxiliary electrode and the gate electrode are located on opposite surfaces of the substrate.

10. The method of claim 7, wherein the step of forming the gate electrode is performed by forming a gate electrode comprising a first layer of a first material and a second layer of a second material, the first material being different from the second material. The auxiliary electrode is grounded.

11. The method of claim 3, wherein the step of forming the gate electrode is performed by forming a gate electrode comprising a first layer of a first material and a second layer of a second material, the first material being different from the second material. One of the two adjacent gate electrodes serves as the auxiliary electrode.

12. The method of claim 1, wherein The active layer material is at least one of an oxide semiconductor, a quantum dot, a perovskite material and an organic semiconductor material.

13. The method of claim 1, wherein The solvent of the solution is a polar solvent system or a non-polar solvent system.

14. The method of claim 1, wherein The active layer material is positively charged or negatively charged in the solution; When the active layer material is positively charged in the solution, the electricity in the gate electrode is negative, and the electricity in the auxiliary electrode is positive; And When the active layer material is negatively charged in the solution, the electricity in the gate electrode is positive, and the electricity in the auxiliary electrode is negative.

15. The method of claim 1, wherein The mass percentage of the active layer material in the solution is defined as W%, the thickness of the deposited active layer is h, the height of the solution is H, and the density of the deposited active layer is ρ, then W%=ρ*h / H.

16. The method of fabricating a transistor according to any one of claims 1 to 15, wherein The active layer comprises a channel region, and the method for manufacturing the transistor further comprises: forming a source-drain layer on the active layer, the source-drain layer comprising a source electrode and a drain electrode, and the channel region directly facing the gap between the adjacent source electrode and drain electrode.

17. A transistor, comprising: The transistor is formed by the method for manufacturing the transistor according to any one of claims 1-16, and comprises a substrate, at least one gate electrode, a gate insulating layer and an active layer stacked together, the active layer is formed on the gate insulating layer, and the active layer directly faces the gate electrode; characterized in that the active layer is formed on the gate insulating layer by an electrodeposition process, and the active layer and the gate electrode are completely overlapped in the orthographic projection on the substrate.

18. The transistor of claim 17, wherein, The transistor further includes an auxiliary electrode on the substrate, the auxiliary electrode being located between two adjacent ones of the gates, the gates and the auxiliary electrode being on the same surface of the substrate.

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