Stacked chip package and manufacturing method thereof

Abstract

The present invention discloses a stacked chip package and a manufacturing method thereof, which belongs to the field of semiconductor packaging. The package of the present invention includes a base island, pins and a plastic encapsulation material, a bump and a first chip are provided on the base island, the first chip and the bump are respectively connected to the pins through a strip, and a second chip is provided above the strip. The method of the present invention is to half-etch the upper part of the substrate to form the pins, the first base island and the second base island, and the bump is formed on the first base island; then a photosensitive solder resist is coated on the surface of the base island; the first chip is installed on the second base island, and the first chip and the bump are respectively connected to the pins using a strip; then the second chip is installed above the strip; and then the upper part of the substrate is plastic encapsulated with a plastic encapsulation material. The present invention overcomes the shortcomings of the prior art that the chip stacking package occupies a large space and the heat dissipation between the chips is poor. The present invention reduces the space occupied by the chip stack, improves the space utilization rate, and improves the heat dissipation efficiency between the chips.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and more particularly, relates to a stacked chip package and a manufacturing method thereof. Background Art

[0002] Semiconductor packaging refers to the process of processing tested wafers into independent chips according to product model and functional requirements. Three-dimensional packaging technology is a recently developing electronic packaging technology that uses a stacking structure to increase packaging density in three dimensions. It can be applied to packaging at different levels or levels, such as package-on-package (PoP) and package-in-package (PiP), wafer stacking, and chip-on-chip or wafer stacking. Wafer stacking is common in mobile phone products. Its advantage is that standard chips and wire bonding and subsequent packaging can be achieved using existing equipment and processes, but it has limitations on the thickness of the entire package, which cannot be too large.

[0003] In the current chip stacking packaging process, chips are stacked on the silver-plated side of a frame, packaged to form a product, and attached to one side of a PCB board. When the product has many functions, the PCB wiring is complex and the product occupies a large space; in addition, the heat dissipation between the stacked chips is poor, which reduces the chip performance. The above-mentioned problems exist in the stacking packaging processes disclosed in the prior art. For example, the invention is named: Multi-chip Stacking Package (Application Date: April 3, 2009; Application Number: CN200910130575.4), which discloses a multi-chip stacking package, one embodiment of which includes a first chip having a first active surface and a first back surface, a first chip carrier having a first opening and bonded to the first active surface, a plurality of first wires passing through the first opening and for electrically connecting the first active surface and the first carrier, a second chip having a second active surface and a second back surface, an adhesive layer for covering the first wires and bonding the first chip carrier and the second back surface, a second chip carrier having a second opening and bonded to the second active surface and electrically connected, and a plurality of second wires passing through the second opening and for electrically connecting the second active surface and the second chip carrier.

[0004] In addition, there is an invention entitled: Multi-chip stacking packaging structure (application date: May 23, 2018; application number: CN201810499445.7), which discloses a multi-chip stacking packaging structure, which includes: a substrate provided with a base and a boss; a first chip stacking unit and a second chip stacking unit stacked in a stepped manner and in opposite stacking directions; bonding wires, which include a first bonding wire directly connecting the base with each layer of chips in the first chip stacking unit, and a second bonding wire connecting the boss with each layer of chips in the second chip stacking unit. By providing the boss on the substrate, the present invention effectively shortens the length of the bonding wire, reduces its consumption, reduces production costs, shortens welding time, and improves packaging efficiency. In addition, shortening the bonding wire can effectively improve the stability of the chip and avoid excessive swing of the bonding wire during vibration, which may cause short circuits and other situations.

[0005] In summary, how to reduce the space occupied by stacked chips and reduce the heat dissipation between the stacked chips to avoid chip performance degradation is a problem that urgently needs to be solved in the existing technology. Summary of the Invention

[0006] 1. Problem to be solved

[0007] The present invention overcomes the shortcomings of the existing technology of middle-layer chip stacking package, such as large space occupied and poor heat dissipation between chips, and provides a stacked chip package and a manufacturing method thereof, which reduces the space occupied by chip stacking, improves space utilization, and improves the heat dissipation efficiency between chips, effectively avoiding the problem of chip performance degradation, and further improving the practicality and reliability of stacked chips.

[0008] 2. Technical solution

[0009] In order to solve the above problems, the technical solutions adopted by the present invention are as follows:

[0010] A stacked chip package of the present invention includes a base island, which includes a first base island and a second base island, the first base island is provided with a bump, and the second base island is provided with a first chip; pins, which are arranged on both sides of the base island, the first chip and the bumps are respectively connected to the pins through strips, and the second chip is provided above the strips; and a plastic encapsulation material, which is used to cover the base island, the pins, the first chip, the second chip, and the empty area between the base island and the pins.

[0011] Furthermore, a photosensitive solder resist is provided on the surface of the base island, and electrical connection pins are provided below the lead and the base island.

[0012] Furthermore, the height of the second base island is smaller than that of the first base island, and the height of the first chip is the same as that of the bump.

[0013] Furthermore, the second chip is located directly above the base island.

[0014] A method for manufacturing a stacked chip package of the present invention comprises the following steps:

[0015] (1) etching the upper portion of the substrate to form a base island and a lead, wherein the base island includes a first base island and a second base island, and a bump is formed on the first base island;

[0016] (2) coating a layer of photosensitive solder resist on the surface of the base island and developing the photosensitive solder resist;

[0017] (3) mounting the first chip on the second base island, and connecting the first chip and the bumps to the pins respectively using strips;

[0018] (4) Mounting a second chip on top of the strip;

[0019] (5) The upper portion of the substrate is encapsulated with a plastic encapsulating material so that the plastic encapsulating material covers the base island, the pins, the first chip, the second chip, and the empty area between the base island and the pins.

[0020] Furthermore, after step (5), the method further includes: etching the lower portion of the substrate to form electrical connection pins, electroplating the electrical connection pins, and then cutting and separating the substrate to obtain a single stacked chip package.

[0021] Furthermore, the specific process of installing the second chip in step (4) is: firstly place the second chip opposite to the base island, and then install the second chip on the surface of the strip in a face-up or flip-up manner.

[0022] Furthermore, the specific process of connecting the first chip and the bump to the pins respectively using the strip is: attaching one end of the strip to the surface of the first chip or the surface of the bump, and bonding the other end of the strip to the pin.

[0023] Furthermore, the specific process of electroplating the electrical connection pins is: tinning the surfaces of the electrical connection pins.

[0024] 3. Beneficial effects

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] (1) A stacked chip package of the present invention effectively saves the patch space of the substrate by setting the first base island and the second base island; further, the conduction between the bump and the second chip and the conduction and stacking of the first chip and the second chip are achieved through the strip, which not only improves the heat dissipation performance between the chips, thereby ensuring the performance of the first chip and the second chip, but also improves the space utilization of the substrate, reduces the material cost, and further improves the practicality and reliability of the package.

[0027] (2) The present invention provides a method for manufacturing a stacked chip package. By etching to form a first base island and a second base island, space can be saved for mounting the first chip, thereby improving the space utilization of the substrate. Furthermore, by using strips to achieve electrical connection between the bump and the second chip, as well as electrical connection and stacking between the first and second chips, not only does this improve the heat dissipation between the chips, thereby ensuring the performance of the first and second chips, but it also improves the space utilization of the substrate, reduces material costs, and further enhances the practicality and reliability of the package. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic structural diagram of a stacked chip package of the present invention;

[0029] Figure 2 Schematic diagram of the method of the present invention.

[0030] In the figure: 100, substrate; 110, base island; 111, first base island; 112, second base island; 113, bump; 120, pin; 130, electrical connection pin;

[0031] 210, first chip; 220, second chip;

[0032] 300, strips; 400, plastic packaging material. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments; moreover, the various embodiments are not relatively independent and can be combined with each other as needed to achieve better results. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the invention to be protected, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0034] In order to further understand the content of the present invention, the present invention is described in detail with reference to the accompanying drawings and embodiments.

[0035] Example 1

[0036] like Figure 1As shown, a stacked chip package of the present invention includes a base island 110, pins 120, a first chip 210, a second chip 220, and a molding compound 400. The base island 110 includes a first base island 111 and a second base island 112. The first base island 111 is provided with bumps 113. It should be noted that the number of bumps 113 and the distance between bumps 113 are limited by the location of the pressure zone of the second chip 220. In addition, the surface of the first base island 111 is provided with a photosensitive solder resist, thereby preventing short circuit problems in the package. Furthermore, the height of the first base island 111 is greater than the height of the second base island 112, that is, the second base island 112 has space for installing chips, thereby improving the space utilization of the substrate 100. Specifically, the first chip 210 is provided on the second base island 112. The height of the first chip 210 is the same as the height of the bumps 113, thereby facilitating the installation of the second chip 220. The present invention adopts a face-up or flip-up mounting method to mount the first chip 210 on the surface of the second base island 112.

[0037] The pins 120 of the present invention are arranged on both sides of the base island 110, and the first chip 210 and the bumps 113 are electrically connected to the pins 120 respectively. Specifically, the first chip 210 and the bumps 113 are respectively connected to the pins 120 through the strips 300. It should be noted that the strips 300 include a first strip and a second strip, one end of the first strip is connected to the first chip 210, specifically, one end of the first strip is welded to the surface of the first chip 210; the other end of the first strip is bonded to the pins 120 on one side of the base island 110. One end of the second strip is connected to the bumps 113, and the other end of the second strip is bonded to the pins 120 on the other side of the base island 110. It is worth noting that the bonding of the strips 300 can effectively reduce the thickness of the package and can provide better resistance and heat dissipation performance. The material of the strips 300 of the present invention is metal. In this example, the strips 300 are aluminum strips.

[0038] Furthermore, a second chip 220 is mounted on the strip 300 of the present invention. The second chip 220 is located directly above the base island 110, and the second chip 220 is mounted on the surface of the strip 300. The present invention adopts a face-up or flip-up method to mount the second chip 220 on the surface of the strip 300. The second chip 220 is connected and stacked with the first chip 210 through the strip 300, which effectively reduces the space occupied by the chip stacking and greatly improves the space utilization. In addition, the pressure area of ​​the second chip 220 is connected to the bump 113 through the strip 300, thereby realizing the stacking of the first chip 210 and the second chip 220. Furthermore, by providing the strip 300, the reliability of the electrical connection is effectively improved, and the heat dissipation performance between the first chip 210 and the second chip 220 is improved, thereby effectively avoiding the problem of chip performance degradation, thereby ensuring the reliability of the package. It should be further noted that the size of the second chip 220 of the present invention is larger than the size of the first chip 210.

[0039] In addition, the molding compound 400 of the present invention is used to cover the base island 110, the pins 120, the first chip 210, the second chip 220, and the empty area between the base island 110 and the pins 120. That is, the molding compound 400 is used to protect the first chip 210 and the second chip 220, effectively improving the practicality and reliability of the package of the present invention. In this embodiment, the molding compound 400 is an epoxy resin molding compound. Furthermore, an electrical connection pin 130 is provided below the pins 120 and the base island 110 of the present invention, and a tin layer is provided on the surface of the electrical connection pin 130, that is, a layer of tin is plated on the surface of the electrical connection pin 130, thereby ensuring the conduction and connection of the package.

[0040] A stacked chip package of the present invention effectively saves the patch space of the substrate 100 by setting the first base island 111 and the second base island 112, and further realizes the conduction between the bump 113 and the second chip 220 and the conduction and stacking of the first chip 210 and the second chip 220 through the strip 300, which not only improves the heat dissipation performance between the chips, thereby ensuring the performance of the first chip 210 and the second chip 220, but also improves the space utilization of the substrate 100, reduces the material cost, and further improves the practicality and reliability of the package.

[0041] Combine Figure 2 As shown, a method for manufacturing a stacked chip package of the present invention is used to manufacture the above-mentioned stacked chip package. The specific steps of the method of the present invention are as follows:

[0042] (1) The upper portion of the substrate 100 is etched to form a base island 110 and a pin 120, and the base island 110 includes a first base island 111 and a second base island 112. Specifically, the upper portion of the substrate 100 is first half-etched to form a base island to be processed and a pin 120, and then the base island to be processed is half-etched to form the base island 110, which includes a first base island 111 and a second base island 112, and the height of the first base island 111 is greater than the height of the second base island 112, thereby saving space on the substrate 100. It should be noted that when the base island to be processed is half-etched to form the base island 110, bumps 113 are formed on the first base island 111, and the number of bumps 113 and the distance between the bumps 113 are limited according to the position of the pressing area of ​​the second chip 220. In addition, the material of the substrate 100 in this embodiment is copper.

[0043] (2) A layer of photosensitive solder resist is applied to the surface of the base island 110, and the excess portion of the photosensitive solder resist is exposed and developed to remove the excess photosensitive solder resist. It should be noted that the surface of the first base island 111 is entirely coated with photosensitive solder resist, while a portion of the surface of the second base island 112 is coated with photosensitive solder resist, and the remaining portion is used to mount the first chip 210.

[0044] (3) The first chip 210 is mounted on the second base island 112. It should be noted that the first chip 210 is mounted on the surface of the second base island 112 in a face-up or flip-up manner, and the height of the first chip 210 is the same as the height of the bump 113. Furthermore, the first chip 210 and the bump 113 are connected to the pin 120 respectively using a strip 300. Specifically, one end of the strip 300 is attached to the surface of the first chip 210 or the surface of the bump 113, and the other end of the strip 300 is bonded to the pin 120. It should be noted that the strip 300 includes a first strip and a second strip. One end of the first strip is connected to the first chip 210, and the other end of the first strip is bonded to the pin 120 on one side of the base island 110; one end of the second strip is connected to the bump 113, and the other end of the second strip is bonded to the pin 120 on the other side of the base island 110. The connection through the strip 300 can reduce the thickness of the package and improve the heat dissipation performance of the chip.

[0045] (4) Install the second chip 220 above the strip 300. Specifically, first place the second chip 220 opposite the base island 110, and then install the second chip 220 on the surface of the strip 300 in a face-up or flip-up manner, that is, the second chip 220 is electrically connected to the bump 113 and the first chip 210 through the strip 300. It should be noted that the size of the second chip 220 is larger than that of the first chip 210, and the pressing area of ​​the second chip 220 corresponds to the bump 113, that is, electrical connection is achieved at the pressing area position. The first chip 210 and the second chip 220 are electrically connected and stacked through the strip 300, effectively improving space utilization.

[0046] (5) The upper portion of the substrate 100 is molded with a molding compound 400 so that the molding compound 400 covers the base island 110, the pins 120, the first chip 210, the second chip 220, and the empty area between the base island 110 and the pins 120. That is, the first chip 210 and the second chip 220 are protected by the molding compound 400.

[0047] (6) The lower portion of the substrate 100 is etched to form electrical connection pins 130. Specifically, the electrical connection pins 130 are etched below the base island 110 and the pins 120. The electrical connection pins 130 are then electroplated. In this example, the surface of the electrical connection pins 130 is tin-plated. The substrate 100 is then cut and separated to obtain individual stacked chip packages. In this embodiment, the substrate 100 is cut using a laser.

[0048] The present invention provides a method for manufacturing a stacked chip package. By etching to form a first base island 111 and a second base island 112, space is saved for mounting a first chip 210, thereby improving the space utilization of the substrate 100. Furthermore, by using a strip 300, electrical connection is achieved between the bump 113 and the second chip 220, as well as electrical connection and stacking between the first chip 210 and the second chip 220. This not only improves heat dissipation between the chips, thereby ensuring the performance of the first chip 210 and the second chip 220, but also increases the space utilization of the substrate 100, reduces material costs, and further enhances the practicality and reliability of the package.

[0049] The present invention has been described in detail above with reference to specific exemplary embodiments. However, it should be understood that various modifications and variations may be made without departing from the scope of the present invention as defined by the appended claims. The detailed description and accompanying drawings should be considered merely illustrative and not restrictive, and any such modifications and variations, if any, are intended to fall within the scope of the present invention as described herein. In addition, the background art is intended to illustrate the current status and significance of the present technology and is not intended to limit the present invention or the application and fields of application of the present invention.

Claims

1. A stacked chip package, characterized in that: include The base island includes a first base island and a second base island, the first base island is provided with a bump, and the second base island is provided with a first chip; Pins are arranged on both sides of the base island, the first chip and the bumps are connected to the pins through strips, and a second chip is arranged above the strips; A molding compound, which is used to cover the base island, the pins, the first chip, the second chip, and the empty area between the base island and the pins; The strips include a first strip and a second strip, one end of the first strip is welded to the surface of the first chip; the other end of the first strip is bonded to the pin on one side of the base island; one end of the second strip is connected to the bump, and the other end of the second strip is bonded to the pin on the other side of the base island; the height of the second base island is smaller than the height of the first base island, and the height of the first chip is the same as the height of the bump; The second chip is located right above the base island and mounted on the surface of the strip, and the pressing area of ​​the second chip is connected to the bump through the strip.

2. The stacked chip package according to claim 1, wherein: The surface of the base island is provided with a photosensitive solder resist.

3. The stacked chip package according to claim 1, wherein: Electrical connection pins are provided below the pins and the base island.

4. A method for manufacturing the stacked chip package according to any one of claims 1 to 3, characterized in that: The following steps are involved: (1) etching the upper portion of the substrate to form a base island and a pin, wherein the base island includes a first base island and a second base island, and a bump is formed on the first base island; (2) Coating a layer of photosensitive solder resist on the surface of the base island and developing the photosensitive solder resist; (3) Mounting the first chip on the second base island, and connecting the first chip and the bumps to the pins respectively using strips; (4) Installing a second chip on top of the strip; (5) Using a plastic encapsulation material to encapsulate the upper portion of the substrate, so that the plastic encapsulation material covers the base island, the pins, the first chip, the second chip, and the empty area between the base island and the pins.

5. The method for manufacturing a stacked chip package according to claim 4, wherein: After step (5), the method further includes: etching the lower portion of the substrate to form electrical connection pins, electroplating the electrical connection pins, and then cutting and separating the substrate to obtain a single stacked chip package.

6. The method for manufacturing a stacked chip package according to claim 4, wherein: The specific process of installing the second chip in step (4) is: first place the second chip opposite to the base island, and then install the second chip on the surface of the strip by using a face-up or flip-up method.

7. The method for manufacturing a stacked chip package according to claim 4, wherein: The specific process of connecting the first chip and the bump to the pins respectively using the strip is: attaching one end of the strip to the surface of the first chip or the surface of the bump, and bonding the other end of the strip to the pin.

8. The method for manufacturing a stacked chip package according to claim 5, wherein: The specific process of electroplating the electrical connection pins is: tinning the surfaces of the electrical connection pins.

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