Integrated circuit wiring method, device and terminal equipment

Abstract

The present application is applicable to the field of semiconductor technology, and provides an integrated circuit wiring method, device and terminal equipment. The integrated circuit wiring method includes: receiving an integrated circuit wiring instruction, the integrated circuit wiring instruction includes chip PAD position information and bonding finger position information; wherein the chip PAD position information and bonding finger position information meet the following conditions: the coordinates of the chip PAD to be designed are consistent with the coordinates of the center of each of the bonding fingers to be designed; in response to the integrated circuit wiring instruction, based on the chip PAD position information and the bonding finger position information, the chip to be designed and the bonding finger to be designed are set in the first layer to achieve the connection between the chip PAD to be designed and the bonding finger to be designed; wiring is performed based on the connected chip PAD to be designed or each bonding finger to be designed. The present application can greatly reduce the workload of integrated circuit wiring and improve the efficiency of integrated circuit wiring.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to integrated circuit wiring methods, devices and terminal equipment. Background Art

[0002] A traditional integrated circuit may include a chip, multiple bonding fingers and bonding wires. The chip is connected to each bonding finger through bonding wires to realize data transmission between the chip inside the integrated circuit and external devices. Before trial production or mass production of the integrated circuit, it is necessary to design the integrated circuit and simulate its performance to determine it. The traditional integrated circuit design method usually connects the chip PAD and the bonding finger through bonding wires, and then performs wiring. However, the inventors of the present application found in their research that when the number of bonding fingers in the designed integrated circuit is large, the design process of the integrated circuit will take a long time. Summary of the invention

[0003] To overcome the problems existing in the related art, the embodiments of the present application provide an integrated circuit housing wiring method, apparatus and terminal equipment.

[0004] This application is implemented through the following technical solutions:

[0005] In a first aspect, an embodiment of the present application provides an integrated circuit wiring method, comprising:

[0006] Receive an integrated circuit wiring instruction, the integrated circuit wiring instruction includes chip PAD position information and bonding finger position information, the number of bonding fingers to be designed is multiple, and each bonding finger to be designed corresponds to one bonding finger position information; wherein the chip PAD position information and the bonding finger position information meet the following conditions: the coordinates of the chip PAD to be designed are consistent with the coordinates of the center of each bonding finger to be designed;

[0007] In response to the integrated circuit wiring instruction, based on the chip PAD position information and the bonding finger position information, the chip to be designed and the bonding finger to be designed are arranged in the first layer to achieve connectivity between the chip PAD to be designed and the bonding finger to be designed;

[0008] Wiring is performed based on the connected chip PAD to be designed or each bonding finger to be designed.

[0009] The above-mentioned integrated circuit wiring method, after receiving the integrated circuit wiring instruction, sets the chip to be designed and the bonding finger to be designed in the first layer based on the chip PAD position information and the bonding finger position information in the integrated circuit wiring instruction, so that the set chip PAD to be designed and the bonding finger to be designed can be directly connected, and there is no need to set bonding wires between the chip PAD and the bonding finger. For the scenario where there are many chip PADs and bonding fingers and a large number of bonding wires need to be set, the embodiment of the present application can greatly reduce the workload of integrated circuit wiring, improve the efficiency of integrated circuit wiring, and for later simulations (such as LRC, S parameters), it can also eliminate the influence of bonding wires on simulation results, which is closer to the actual test situation of integrated circuit wiring.

[0010] As an implementable method, the step of setting the chip to be designed and the bonding finger to be designed in the first layer based on the chip PAD position information and the bonding finger position information includes:

[0011] Generate a chip to be designed and a bonding finger to be designed based on the chip PAD position information and the bonding finger position information;

[0012] The chip to be designed and the bonding finger to be designed are adjusted into the first layer.

[0013] As another possible implementation method, the step of setting the chip to be designed and the bonding finger to be designed in the same layer based on the chip PAD position information and the bonding finger position information includes:

[0014] Jump to the first layer, and generate a chip to be designed and a bonding finger to be designed based on the chip PAD position information and the bonding finger position information.

[0015] Optionally, the integrated circuit wiring instruction further includes chip parameter information and bonding finger parameter information;

[0016] The generating of the chip to be designed and the bonding finger to be designed comprises:

[0017] A chip to be designed is generated according to the chip parameter information, and a bonding finger to be designed is generated according to the bonding finger parameter information.

[0018] In some embodiments, after receiving the integrated circuit wiring instruction, the method further comprises: responding to the integrated circuit wiring instruction, determining a first position of the chip PAD to be designed in a preset area based on the chip PAD position information;

[0019] The chip to be designed is set based on the chip PAD position information, including: setting the chip to be designed in the first layer based on the chip PAD position information, so that the chip PAD to be designed is located at the first position.

[0020] In some further embodiments, after receiving the integrated circuit routing instruction, the method further comprises: responding to the integrated circuit routing instruction, determining a second position of each of the bonding fingers to be designed in a preset area based on the bonding finger position information;

[0021] Setting each of the bonding fingers to be designed based on the bonding finger position information includes: setting each of the bonding fingers to be designed in the first layer based on the bonding finger position information so that the center of the bonding finger to be designed is located at the second position.

[0022] In some possible implementations, the method further includes:

[0023] If it is detected that the chip to be designed and the bonding to be designed are located in the same layer, and the coordinates of the chip PAD to be designed and the coordinates of the center of each bonding finger to be designed are within a preset range, the chip PAD to be designed and the bonding fingers to be designed are connected.

[0024] In a second aspect, an embodiment of the present application provides an integrated circuit wiring device, including:

[0025] An instruction receiving module is used to receive an integrated circuit wiring instruction, wherein the integrated circuit wiring instruction includes chip PAD position information and bonding finger position information, the number of bonding fingers to be designed is multiple, and each bonding finger to be designed corresponds to one bonding finger position information; wherein the chip PAD position information and bonding finger position information meet the following conditions: the coordinates of the chip PAD to be designed are consistent with the coordinates of the center of each bonding finger to be designed;

[0026] An instruction response module, used for responding to the integrated circuit wiring instruction, and arranging the chip to be designed and the bonding finger to be designed in the first layer based on the chip PAD position information and the bonding finger position information, so as to realize the connection between the chip PAD to be designed and the bonding finger to be designed;

[0027] A wiring module is used to perform wiring based on the connected chip PAD to be designed or each bonding finger to be designed.

[0028] In a third aspect, an embodiment of the present application provides a terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the integrated circuit wiring method as described in any one of the first aspects is implemented.

[0029] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the integrated circuit wiring method as described in any one of the first aspects is implemented.

[0030] In a fifth aspect, an embodiment of the present application provides a computer program product. When the computer program product is run on a terminal device, the terminal device executes the integrated circuit wiring method described in any one of the first aspects above.

[0031] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0033] Figure 1 It is a flowchart of an integrated circuit wiring method provided by an embodiment of the present application;

[0034] Figure 2 It is a schematic diagram of integrated circuit wiring design provided by an embodiment of the present application;

[0035] Figure 3 is a schematic diagram of the structure of an integrated circuit wiring device provided in an embodiment of the present application;

[0036] Figure 4 It is a structural diagram of the terminal device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0038] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0039] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0040] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0041] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0042] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0043] Traditional integrated circuits may include a chip, multiple bonding fingers, and bonding wires. The chip is connected to each bonding finger through bonding wires to achieve data transmission between the chip inside the integrated circuit and external devices. Before trial production or mass production of an integrated circuit, it is necessary to design the integrated circuit and simulate its performance to determine it. The traditional integrated circuit design method usually connects the chip PAD and the bonding finger through bonding wires, and then performs buried layer wiring.

[0044] However, the inventors of the present application discovered during their research that when the number of bonding indices in the designed integrated circuit is large, a large number of bonding wires are required to connect the chip PAD and each bonding finger, which will take up a lot of time in the design process of the integrated circuit wiring and seriously affect work efficiency.

[0045] Based on the above problems, the present application provides an integrated circuit wiring method. Figure 1 FIG. 1 is a schematic flow chart of the integrated circuit wiring method. Figure 1 , the integrated circuit wiring method is described in detail as follows:

[0046] Step 101, receiving an integrated circuit wiring instruction, wherein the integrated circuit wiring instruction includes chip PAD position information and bonding finger position information, there are multiple bonding fingers to be designed, and each bonding finger to be designed corresponds to one bonding finger position information.

[0047] The chip PAD position information and the bonding finger position information satisfy the following condition: the coordinates of the chip PAD to be designed are consistent with the coordinates of the center of each bonding finger to be designed.

[0048] Exemplarily, the coordinates of the chip PAD to be designed are consistent with the coordinates of the center of each bonding finger to be designed, and the coordinates of the chip PAD to be designed are the same as the coordinates of the center of each bonding finger to be designed, or the coordinates of the chip PAD to be designed and the coordinates of the center of each bonding finger to be designed are within a preset range. The above coordinates can be coordinates in an area for displaying the designed integrated circuit in an integrated circuit wiring interface displayed by a terminal device.

[0049] In some embodiments, before step 101, the integrated circuit wiring method may include: detecting a preset operation and generating an integrated circuit wiring instruction. The preset operation may be a specific operation applied by a user in an integrated circuit wiring interface of a terminal device.

[0050] For example, after the terminal device displays the integrated circuit wiring interface, the user enters the chip PAD position information and bonding finger position information, etc. in the interface, and then clicks the control used to start the integrated circuit wiring. At this time, the terminal device detects the click operation and generates basic circuit wiring instructions.

[0051] It should be noted that the chip PAD position information and the bonding finger position information may be specific position coordinates, for example, the two position information are two specific position coordinates in a preset area. Alternatively, the chip PAD position information and the bonding finger position information may be the relationship between the two position information, for example, the two position information represent the distance range between the chip PAD and the bonding finger, etc. Alternatively, the chip PAD position information and the bonding finger position information may be two position areas.

[0052] Step 102, in response to the integrated circuit wiring instruction, based on the chip PAD position information and the bonding finger position information, the chip to be designed and the bonding finger to be designed are set in the first layer to achieve connectivity between the chip PAD to be designed and the bonding finger to be designed.

[0053] In some possible implementations, the above-mentioned setting of the chip to be designed and the bonding fingers to be designed in the first layer based on the chip PAD position information and the bonding finger position information may include: generating the chip to be designed and the bonding fingers to be designed based on the chip PAD position information and the bonding finger position information; adjusting the chip to be designed and the bonding fingers to be designed to the first layer.

[0054] Specifically, the chip to be designed and the bonding fingers to be designed may be generated based on the chip PAD position information and the bonding finger position information; then, the generated chip to be designed and the bonding fingers to be designed are adjusted to be displayed in the first layer.

[0055] In some other possible implementations, the above-mentioned setting of the chip to be designed and the bonding fingers to be designed in the first layer based on the chip PAD position information and the bonding finger position information may include: jumping to the first layer, and generating the chip to be designed and the bonding fingers to be designed based on the chip PAD position information and the bonding finger position information.

[0056] Specifically, the first layer may be jumped to first, and then, based on the chip PAD position information and the bonding finger position information, the chip to be designed and the bonding finger to be designed are directly generated and displayed in the first layer.

[0057] Exemplarily, the above integrated circuit wiring instruction may also include chip parameter information and bonding finger parameter information. Correspondingly, the above generation of the chip to be designed and the bonding finger to be designed may specifically include: generating the chip to be designed according to the chip parameter information, and generating the bonding finger to be designed according to the bonding finger parameter information.

[0058] For example, the chip parameter information may include at least one of the following: chip model, chip performance, number of chips, etc. If the chip parameter information includes the chip model, the chip to be designed is generated according to the chip model, and the generated chip to be designed has the physical structure and function of the chip corresponding to the above chip model. If the chip parameter information includes chip performance, the corresponding chip is determined in the chip database according to the chip performance, and then the chip to be designed is generated. If the chip parameter information includes the number of chips, the commonly used chips can be determined in the chip database, and the chip to be designed is generated according to the commonly used chips and the number of chips. If the chip parameter information includes at least two of the chip model, chip performance and chip number, the chip to be designed is generated according to the information contained.

[0059] For example, the bonding finger parameter information may include at least one of the following: bonding index quantity, bonding finger size, bonding finger shape, etc. If the bonding finger parameter information includes bonding finger size, the corresponding bonding finger is determined in the bonding finger database according to the bonding finger size, and then the bonding finger to be designed is generated. If the bonding finger parameter information includes bonding index quantity, the commonly used bonding fingers are determined in the bonding finger database, and the bonding fingers to be designed are generated according to the commonly used bonding fingers and the bonding index quantity. If the bonding finger parameter information includes bonding finger shape, the corresponding bonding finger can be determined in the bonding finger database according to the bonding finger shape, and then the bonding finger to be designed is generated. If the bonding finger parameter information includes at least two of the bonding index quantity, bonding finger size, and bonding finger shape, the bonding finger to be designed is generated according to the information contained.

[0060] In some embodiments, after step 101, the above integrated circuit wiring method may further include: responding to the integrated circuit wiring instruction, determining the first position of the chip PAD to be designed in the preset area based on the chip PAD position information. Correspondingly, setting the chip to be designed based on the chip PAD position information in step 102 includes: setting the chip to be designed in the first layer based on the chip PAD position information, so that the chip PAD to be designed is located at the first position.

[0061] In some embodiments, after step 101, the integrated circuit wiring method may further include: responding to the integrated circuit wiring instruction, determining the second position of each bonding finger to be designed in the preset area based on the bonding finger position information. Correspondingly, setting each bonding finger to be designed based on the bonding finger position information in step 102 includes: setting each bonding finger to be designed in the first layer based on the bonding finger position information, so that the center of the bonding finger to be designed is located at the second position.

[0062] In an embodiment of the present application, if it is detected that the chip to be designed and the bonding to be designed are located in the same layer, and the coordinates of the chip PAD to be designed are consistent with the coordinates of the center of each bonding finger to be designed, then the chip PAD to be designed and the bonding finger to be designed are connected.

[0063] In one scenario, if it is detected that the chip to be designed and the bonding to be designed are located in the same layer, and the coordinates of the PAD of the chip to be designed are the same as the coordinates of the center of each bonding finger to be designed, such as Figure 2 As shown, the chip PAD to be designed is connected with the bonding finger to be designed.

[0064] In another scenario, if it is detected that the chip to be designed and the bonding to be designed are located in the same layer, and the coordinates of the chip PAD to be designed and the coordinates of the center of each bonding finger to be designed are within a preset range, then the chip PAD to be designed and the bonding fingers to be designed are connected.

[0065] Step 103 : performing wiring based on the connected chip PAD to be designed or each bonding finger to be designed.

[0066] For example, after the connected chip PAD to be designed and the bonding finger to be designed are obtained through steps 101 and 102, wiring can be directly derived from the bonding finger to be designed during buried layer wiring, or wiring can be derived from the chip PAD to be designed. Figure 2 As shown, routing is derived from the bonding finger to be designed.

[0067] The above-mentioned integrated circuit wiring method, after receiving the integrated circuit wiring instruction, sets the chip to be designed and the bonding finger to be designed in the first layer based on the chip PAD position information and the bonding finger position information in the integrated circuit wiring instruction, so that the set chip PAD to be designed and the bonding finger to be designed can be directly connected without setting bonding wires between the chip PAD and the bonding finger. For the scenario where there are many chip PADs and bonding fingers and a large number of bonding wires need to be set, the embodiment of the present application can greatly reduce the workload of integrated circuit wiring, improve the efficiency of integrated circuit wiring, and for later simulations (such as LRC, S parameters), it can also eliminate the influence of bonding wires on simulation results, which is closer to the actual test situation of integrated circuit wiring ceramic shells.

[0068] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0069] Corresponding to the integrated circuit wiring method described in the above embodiment, Figure 3 A structural block diagram of an integrated circuit wiring device provided in an embodiment of the present application is shown. For ease of explanation, only the parts related to the embodiment of the present application are shown.

[0070] See also Figure 3 The integrated circuit wiring device 200 in the embodiment of the present application may include an instruction receiving module 201, an instruction response module 202 and a wiring module 203.

[0071] The instruction receiving module 201 is used to receive integrated circuit wiring instructions, wherein the integrated circuit wiring instructions include chip PAD position information and bonding finger position information, and the number of bonding fingers to be designed is multiple, and each bonding finger to be designed corresponds to one bonding finger position information. The chip PAD position information and bonding finger position information meet the following conditions: the coordinates of the chip PAD to be designed are consistent with the coordinates of the center of each bonding finger to be designed.

[0072] The instruction response module 202 is used to respond to the integrated circuit wiring instruction, and to set the chip to be designed and the bonding finger to be designed in the first layer based on the chip PAD position information and the bonding finger position information to achieve connectivity between the chip PAD to be designed and the bonding finger to be designed.

[0073] The wiring module 203 is used to perform wiring based on the connected chip PAD to be designed or each bonding finger to be designed.

[0074] In one possible implementation, the instruction response module 202 is used to: generate a chip to be designed and a bonding finger to be designed based on the chip PAD position information and the bonding finger position information; and adjust the chip to be designed and the bonding finger to be designed to the first layer.

[0075] In another possible implementation, the instruction response module 202 is used to: jump to the first layer, and generate a chip to be designed and a bonding finger to be designed based on the chip PAD position information and the bonding finger position information.

[0076] Optionally, the integrated circuit wiring instructions also include chip parameter information and bonding finger parameter information; the above-mentioned generating the chip to be designed and the bonding finger to be designed includes: generating the chip to be designed according to the chip parameter information, and generating the bonding finger to be designed according to the bonding finger parameter information.

[0077] In some embodiments, the integrated circuit wiring device 200 may further include: a first position determination module, which is used to respond to the integrated circuit wiring instruction and determine the first position of the chip PAD to be designed in the preset area based on the chip PAD position information. Correspondingly, the instruction response module 200 sets the chip to be designed based on the chip PAD position information, including: setting the chip to be designed to the first layer based on the chip PAD position information, so that the chip PAD to be designed is located at the first position.

[0078] In some embodiments, the integrated circuit wiring device 200 may further include: a second position determination module, which is used to respond to the integrated circuit wiring instruction and determine the second position of each of the bonding fingers to be designed in the preset area based on the bonding finger position information. Correspondingly, the instruction response module 200 sets each of the bonding fingers to be designed based on the bonding finger position information, including: setting each of the bonding fingers to be designed in the first layer based on the bonding finger position information, so that the center of the bonding finger to be designed is located at the second position.

[0079] Optionally, the above-mentioned integrated circuit wiring device 200 may also include: a connection module, which is used to connect the chip PAD to be designed and the bonding finger to be designed when it is detected that the chip to be designed and the bonding to be designed are located on the same layer, and the coordinates of the chip PAD to be designed and the coordinates of the center of each bonding finger to be designed are within a preset range.

[0080] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0081] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0082] The present application also provides a terminal device, see Figure 4 The terminal device 500 may include: at least one processor 510, a memory 520, and a computer program stored in the memory 520 and executable on the at least one processor 510. When the processor 510 executes the computer program, the steps in any of the above-mentioned method embodiments are implemented, for example: Figure 2 Steps 101 to 103 in the illustrated embodiment. Alternatively, when the processor 510 executes the computer program, the functions of each module / unit in the above-mentioned device embodiments are implemented, for example Figure 3 Functions of modules 201 to 203 are shown.

[0083] Exemplarily, the computer program may be divided into one or more modules / units, one or more modules / units are stored in the memory 520, and executed by the processor 510 to complete the present application. The one or more modules / units may be a series of computer program segments capable of completing specific functions, and the program segments are used to describe the execution process of the computer program in the terminal device 500.

[0084] Those skilled in the art will understand that Figure 4 It is only an example of a terminal device and does not constitute a limitation on the terminal device. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components, such as input and output devices, network access devices, buses, etc.

[0085] The processor 510 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0086] The memory 520 may be an internal storage unit of the terminal device, or an external storage device of the terminal device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. The memory 520 is used to store the computer program and other programs and data required by the terminal device. The memory 520 may also be used to temporarily store data that has been output or is to be output.

[0087] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.

[0088] The integrated circuit wiring method provided in the embodiment of the present application can be applied to terminal devices such as computers, tablet computers, laptops, netbooks, personal digital assistants (PDAs), and mobile phones. The embodiment of the present application does not impose any restrictions on the specific type of terminal devices.

[0089] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in each embodiment of the above-mentioned integrated circuit wiring method can be implemented.

[0090] An embodiment of the present application provides a computer program product. When the computer program product is run on a mobile terminal, the mobile terminal can implement the steps in each embodiment of the above-mentioned integrated circuit wiring method when executing the computer program product.

[0091] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the camera / terminal device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), electric carrier signal, telecommunication signal and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0092] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0093] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0094] In the embodiments provided in the present application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0095] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0096] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An integrated circuit wiring method, characterized in that: include: Receive an integrated circuit wiring instruction, the integrated circuit wiring instruction includes chip PAD position information and bonding finger position information, the number of bonding fingers to be designed is multiple, and each bonding finger to be designed corresponds to one bonding finger position information; wherein the chip PAD position information and the bonding finger position information meet the following conditions: the coordinates of the chip PAD to be designed are consistent with the coordinates of the center of each bonding finger to be designed; In response to the integrated circuit wiring instruction, based on the chip PAD position information and the bonding finger position information, the chip to be designed and the bonding finger to be designed are set in the first layer, and when it is detected that the chip to be designed and the bonding finger to be designed are located in the same layer, and the coordinates of the chip PAD to be designed and the coordinates of the center of each bonding finger to be designed are within a preset range, the chip PAD to be designed and the bonding finger to be designed are connected to achieve the connection between the chip PAD to be designed and the bonding finger to be designed; Wiring is performed based on the connected chip PAD to be designed or each bonding finger to be designed.

2. The integrated circuit wiring method according to claim 1, wherein: The step of setting the chip to be designed and the bonding finger to be designed in the first layer based on the chip PAD position information and the bonding finger position information includes: Generate a chip to be designed and a bonding finger to be designed based on the chip PAD position information and the bonding finger position information; The chip to be designed and the bonding finger to be designed are adjusted into the first layer.

3. The integrated circuit wiring method according to claim 1, wherein: The step of setting the chip to be designed and the bonding finger to be designed in the same layer based on the chip PAD position information and the bonding finger position information includes: Jump to the first layer, and generate a chip to be designed and a bonding finger to be designed based on the chip PAD position information and the bonding finger position information.

4. The integrated circuit wiring method according to claim 2 or 3, characterized in that: The integrated circuit wiring instruction also includes chip parameter information and bonding finger parameter information; The generating of the chip to be designed and the bonding finger to be designed comprises: A chip to be designed is generated according to the chip parameter information, and a bonding finger to be designed is generated according to the bonding finger parameter information.

5. The integrated circuit wiring method according to claim 1, wherein: After receiving the integrated circuit wiring instruction, the method further includes: responding to the integrated circuit wiring instruction, determining a first position of the chip PAD to be designed in a preset area based on the chip PAD position information; The chip to be designed is set based on the chip PAD position information, including: setting the chip to be designed in the first layer based on the chip PAD position information, so that the chip PAD to be designed is located at the first position.

6. The integrated circuit wiring method according to claim 1, wherein: After receiving the integrated circuit routing instruction, the method further includes: responding to the integrated circuit routing instruction, determining a second position of each of the bonding fingers to be designed in a preset area based on the bonding finger position information; Setting each of the bonding fingers to be designed based on the bonding finger position information includes: setting each of the bonding fingers to be designed in the first layer based on the bonding finger position information so that the center of the bonding finger to be designed is located at the second position.

7. An integrated circuit wiring device, characterized in that: include: An instruction receiving module is used to receive an integrated circuit wiring instruction, wherein the integrated circuit wiring instruction includes chip PAD position information and bonding finger position information, the number of bonding fingers to be designed is multiple, and each bonding finger to be designed corresponds to one bonding finger position information; wherein the chip PAD position information and bonding finger position information meet the following conditions: the coordinates of the chip PAD to be designed are consistent with the coordinates of the center of each bonding finger to be designed; An instruction response module is used to respond to the integrated circuit wiring instruction, and based on the chip PAD position information and the bonding finger position information, set the chip to be designed and the bonding finger to be designed in the first layer, and detect that the chip to be designed and the bonding to be designed are located in the same layer, and the coordinates of the chip PAD to be designed and the coordinates of the center of each bonding finger to be designed are within a preset range, then connect the chip PAD to be designed and the bonding finger to be designed, so as to achieve the connection between the chip PAD to be designed and the bonding finger to be designed; A wiring module is used to perform wiring based on the connected chip PAD to be designed or each bonding finger to be designed.

8. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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