An integrated structure of an igzo transistor and a gan hemt gate control circuit and a preparation method thereof

Abstract

This invention discloses an integrated structure and fabrication method of an IGZO transistor and a GaN HEMT gate control circuit, relating to the field of semiconductor technology. The integrated structure consists of two parts: a GaN HEMT structure and an IGZO transistor, both grown on a substrate. Based on the growth of GaN HEMT, IGZO transistor, and a diamond substrate, this invention proposes an integrated gate control circuit structure for low-voltage control circuits, where the IGZO transistor controls a high-power GaN HEMT, and both are integrated on a single substrate. GaN HEMT devices are high-power devices, and ensuring their normal operation through heat dissipation is a hot research topic. Diamond, with its excellent thermal conductivity, is used as a substrate to significantly enhance the heat dissipation capabilities of the device and circuit.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to an integrated structure of an IGZO transistor and a GaN HEMT gate control circuit, and a method for fabricating the aforementioned integrated structure. Background Technology

[0002] Third-generation semiconductor materials with wide bandgap (WBGS) are similar to gallium nitride (GaN), diamond, and silicon carbide (SiC). Among them, gallium nitride (GaN) has a wide bandgap, direct bandgap, high breakdown field strength, low dielectric constant, high saturated electron drift velocity, good radiation resistance, and good chemical stability, making it a hot topic in research and application. AlGaN / GaN HEMT devices have many advantages, mainly including high breakdown voltage and low on-resistance, thus they are considered by the industry as excellent power switching devices or power electronic devices. GaN devices have many advantages in high-temperature, high-power, high-frequency, and irradiated applications. Therefore, gallium nitride materials and their circuits are key foundational materials for high-precision technologies such as microelectronics, power electronics, and optoelectronics, and have a certain influence on the defense industry, information technology industry, and other fields.

[0003] In the display industry, IGZO technology has several advantages over α-Si amorphous silicon technology. Firstly, IGZO transistors have high mobility, approximately 10 cm⁻¹. 2 IGZO transistors have a voltage rating of approximately / Vs, at least ten times that of α-Si amorphous silicon, which is fundamental for their use as high-frequency gate-controlled switching devices. IGZO exhibits good stability under illumination, along with advantages such as good uniformity, high transparency, and simple manufacturing processes. Another crucial aspect is the excellent turn-off performance of IGZO transistors, a vital guarantee for reducing power consumption in control circuits. Compared to low-temperature polycrystalline silicon (LTPS), IGZO's leakage current is only one ten-thousandth. If the control circuit's terminal is a small-capacity DC power supply, IGZO transistors will offer significant advantages in terms of low power consumption.

[0004] Typical gallium nitride (GaN) power devices use silicon as the epitaxial substrate, but silicon's thermal conductivity is not ideal, which has hindered the development and application of GaN power devices to some extent. In existing technologies, polycrystalline diamond can be bonded to GaN-based power devices to improve overall heat dissipation. For controlling high-power GaN HEMT devices with low-voltage signals, silicon-based CMOS circuits are generally used. Si-based integrated circuits have performed very well in the semiconductor industry over the years, considering various factors, and are therefore widely used in the integrated circuit field, holding a significant market share. However, Si-based integrated circuits also have limitations, and their performance in some aspects is not as good as compound semiconductors. Currently, dual-channel IGZO transistors are rarely used in low-voltage control circuits. IGZO transistors are mostly used in the display field, but they have advantages such as good turn-off performance and low drive power, making them suitable for driving high-power circuits from low-power circuits. Therefore, how to combine the above two circuit structures and apply them to control high-power GaN HEMTs is a problem that needs to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide an integrated structure of an IGZO transistor and a GaN HEMT gate control circuit and a method for fabricating the same, so as to solve the above-mentioned defects caused by the prior art.

[0006] An integrated structure of an IGZO transistor and a GaN HEMT gate control circuit is provided. The integrated structure is divided into two parts, one of which is a GaN HEMT structure and the other of which is an IGZO transistor. Both parts are grown on a substrate (101).

[0007] The GaN HEMT structure consists of, from bottom to top, a substrate, an AlGaN buffer layer, a GaN layer, an AlN layer, and an Al layer. 0.2 Ga 0.8 N-layer, AlGaN layer, first SiN layer, source / drain electrodes, Al2O3 dielectric layer, GaN HEMT gate;

[0008] The IGZO transistor consists of, from bottom to top, a substrate, a SiO2 layer, an ITO layer (serving as the source, drain, and gate), an Al2O3 buffer layer, an IGZO base layer, an IGZO Boost layer, an HfO2 dielectric layer, and the IGZO transistor gate.

[0009] After the above two parts are fabricated, a second SiN layer 118, lead-out electrodes connected to the source and drain electrodes, an external metal line 120 connected to the source and drain lead-out electrodes of the GaN HEMT, a first lead-out metal line connected to the gate of the GaN HEMT, a second lead-out metal line connected to the ITO layer, a third metal lead-out line, a first metal wire connected to the gate lead-out metal line of the GaN HEMT, and a second metal wire connected to the source and drain lead-out metal lines of the IGZO transistor, respectively.

[0010] Furthermore, the substrate is made of diamond material with epitaxial GaN thin film and has a size range of 2-8 inches.

[0011] Furthermore, a SiN layer is grown on the substrate, and then etching is performed in the corresponding GaN HEMT device location area to form a recessed hole, in which the GaN HEMT device is fabricated.

[0012] Furthermore, the AlGaN buffer layer is grown using a metal-organic source chemical vapor deposition method.

[0013] Furthermore, the Al 0.2 Ga 0.8 The thickness of the N layer is 6 nm, and the thickness of the AlGaN layer is 20 nm.

[0014] The above-mentioned devices can be fabricated using the following methods:

[0015] (1) A relatively thick SiN layer is grown on the substrate, and then etching is performed in the corresponding GaN HEMT device location area to form a concave hole;

[0016] (2) Based on the above structure, an AlGaN buffer layer is grown by metal-organic chemical vapor deposition.

[0017] (3) A GaN buffer layer is formed by unintentional doping on the above structure using metal-organic chemical vapor deposition or other methods, with a thickness of 100 nm-10 μm;

[0018] (4) An AlN layer was formed by unintentional doping on the above structure using a metal-organic source chemical vapor deposition method;

[0019] (5) Al was formed by unintentionally doping and growing the above structure using metal-organic chemical vapor deposition. 0.2 Ga 0.8 N layers;

[0020] (6) An AlGaN layer was formed by unintentional doping growth on the basis of the above structure using a metal-organic source chemical vapor deposition method;

[0021] (7) Etch on the AlGaN layer to leave a recess, and grow it in the recess using PECVD to preserve the position of the gate dielectric and gate electrode;

[0022] (8) The first SiN layer 107 with a thickness of 100 nm was grown on the basis of the above structure using the PECVD method;

[0023] (9) Electrodes with ohmic contacts are fabricated by magnetron sputtering to serve as source and drain electrodes. At the same time, the first SiN layer is etched at the original AlGaN layer recess position to leave several recesses larger than the original recess size. SiO2 is grown in the larger recesses using PECVD to preserve the position of the gate dielectric and gate electrode.

[0024] (10) Etch SiO2, grow gate Al2O3 dielectric layer using ALD, and fabricate GaN HEMT gate on this basis;

[0025] (11) A second SiN layer with a thickness of 300 nm was grown on the basis of the above structure using the PECVD method;

[0026] (12) The Al2O3 dielectric layer, the first SiN layer and the second SiN layer are etched to form through holes, and metals such as Ti / Al / Ni / Au are deposited to bring out the source and drain electrodes. Pad points are left above the SiN layer. In the corresponding areas of the gate electrode and the source and drain electrodes, the SiN layer is etched to deposit metals such as Ti / Al / Ni / Au to bring out the gate electrode metal and the source and drain electrode metal. Then, the second SiN layer is grown above using the PECVD method.

[0027] (13) Etch at the position corresponding to the IGZO transistor to etch a recess in the originally grown second SiN layer, and fabricate the IGZO transistor in this recess area;

[0028] (14) Then, etching is performed in the channel region to form a concave hole, leaving space for the IGZO base layer: In 0.52 Ga 0.29 Zn 0.19 O and IGZO Boost layers: In 0.82 Ga 0.08 Zn 0.10 The fabrication of O; and the growth of a SiO2 masking layer in the surrounding area to ensure that the IGZO base layer and IGZO Boost layer are fabricated in the area near the channel;

[0029] (15) Remove the excess SiO2 masking layer around it, and then grow the Al2O3 buffer layer using ALD growth, in order to improve the interface problem.

[0030] (16) Based on the above structure, the HfO2 dielectric layer is grown by ALD with a thickness of 50 nm;

[0031] (17) A certain degree of etching is performed in the corresponding channel area to leave a pit. The gate of the IGZO transistor is an ITO dielectric and is grown using ALD. Due to the reserved pit, a T-shaped gate is made here.

[0032] (18) Etch the HfO2 dielectric layer and Al2O3 buffer layer to form a through hole, fabricate a Ti / Al / Ni / Au multilayer metal, and fabricate a second lead metal line. At this time, it should be ensured that the second SiN layers of the two devices are at the same height. At this time, fabricate a metal wire with a width that can meet the maximum current drive and connect the source terminal of the IGZO transistor and the drain terminal of the GaN HEMT.

[0033] (19) On this basis, the second SiN layer is grown as a passivation layer and isolation layer to protect the device;

[0034] (20) Etching is performed at the source and drain ends of the GaN HEMT and in the corresponding region of the drain end of the IGZO transistor to form recessed holes. Metal electrodes are then fabricated within these recessed holes to create the external metal line connecting the source and drain of the GaN HEMT and the second metal wire leading out from the drain end of the IGZO transistor. It is worth mentioning that the external metal line connecting the source and drain of the GaN HEMT and the second metal wire do not overlap in three-dimensional space.

[0035] Furthermore, the SiO2 layer is grown using a thermal oxidation method.

[0036] Furthermore, the ITO layer is grown using ALD and serves as the gate and drain terminals of the IGZO transistor, with a thickness of approximately 10 nm.

[0037] Furthermore, the actual component allocation ratio of the IGZO base layer is In. 0.52 Ga 0.29 Zn 0.19 O was grown using ALD with a thickness of 10 nm.

[0038] Furthermore, the actual component allocation ratio of the IGZO Boost layer 115 is In. 0.82 Ga 0.08 Zn 0.10 O was grown using ALD and has a thickness of 3 nm.

[0039] The advantages of this invention are:

[0040] (1) Based on the growth of GaN HEMT, IGZO transistors and diamond substrates, this invention proposes an integrated gate control circuit structure in which IGZO transistors are used to control high-power GaN HEMT in a low-voltage control circuit, and these are integrated on a single substrate. GaN HEMT devices are high-power devices, and how to dissipate heat to ensure their normal operation is a hot research topic. Diamond material has good thermal conductivity, and its introduction as a substrate can effectively enhance the heat dissipation capacity of the device and circuit.

[0041] (2) IGZO transistors are widely used in mobile display screens and are representative devices of low-power circuits. Introducing them as devices used in control circuits can effectively reduce the power consumption of the control circuits. In the field of display screen applications, the excellent turn-off performance of IGZO transistors has been proven, and their application in control circuits can ensure good turn-off performance.

[0042] (3) The mobility of IGZO transistors is at least ten times that of α-Si amorphous silicon. As a control circuit device, it can guarantee the operating frequency of the circuit to a certain extent.

[0043] (4) When the power supply of the control circuit comes from a small-capacity DC battery, the IGZO transistor can be used as a control circuit device in this case, which can save control power consumption to a great extent and provide a solution for controlling high-power devices with a small mobile power supply. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the structure of the present invention.

[0045] Among them: 101 substrate, 102 AlGaN buffer layer, 103 GaN layer, 104 AlN layer, 105 Al 0.2 Ga 0.8 N-layer, 106 AlGaN layer, 107 First SiN layer, 108 Source / drain electrodes, 109 Al2O3 dielectric layer, 110 GaN HEMT gate, 111 SiO2 layer, 112 ITO layer, 113 Al2O3 buffer layer, 114 IGZO base layer, 115 IGZO Boost layer, 116 HfO2 dielectric layer, 117 IGZO transistor gate, 118 Second SiN layer, 119 Lead electrode, 120 External metal line, 121 First lead metal line, 122 Second lead metal line, 123 Third metal lead line, 124 First metal wire, 125 Second metal wire Detailed Implementation

[0046] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0047] Example 1

[0048] (1) A relatively thick SiN layer 118 is grown on the substrate 101, and then etching is performed in the corresponding GaN HEMT device location area to form a concave hole;

[0049] (2) Based on the above structure, an AlGaN buffer layer 102 was grown by metal-organic chemical vapor deposition.

[0050] (3) GaN layer 103 with a thickness of 1 μm is grown unintentionally on the above structure by metal-organic chemical vapor deposition or other methods;

[0051] (4) An AlN layer 104 was formed by unintentional doping growth on the basis of the above structure using a metal-organic source chemical vapor deposition method;

[0052] (5) Al was formed by unintentionally doping and growing the above structure using metal-organic chemical vapor deposition. 0.2 Ga 0.8 Nth floor 105;

[0053] (6) An AlGaN layer 106 was formed by unintentional doping growth on the basis of the above structure using a metal-organic source chemical vapor deposition method;

[0054] (7) Etch on AlGaN layer 106 to leave a recess, and grow SiO2 in the recess using PECVD to preserve the position of the gate dielectric and gate electrode;

[0055] (8) The first SiN layer 107 with a thickness of 100 nm was grown on the basis of the above structure using the PECVD method;

[0056] (9) Electrodes with ohmic contacts are fabricated by magnetron sputtering to serve as source and drain electrodes. At the same time, the first SiN layer 107 is etched based on the original recessed hole position of the AlGaN layer 106 to leave several recessed holes with a larger size than the original recessed hole. SiO2 is grown in the larger recessed holes using PECVD to preserve the position of the gate dielectric and gate electrode.

[0057] (10) Etch SiO2, grow gate Al2O3 dielectric layer 109 using ALD, and fabricate GaN HEMT gate terminal 110 on this basis;

[0058] (11) A second SiN layer 118 with a thickness of 300 nm was grown on the basis of the above structure using the PECVD method;

[0059] (12) The Al2O3 dielectric layer 109, the first SiN layer 107 and the second SiN layer 118 are etched to form a via, and metals such as Ti / Al / Ni / Au are deposited. The source and drain electrodes 108 are led out. Pad points are left above the SiN layer 111. In the area corresponding to the GaN HEMT gate terminal 110 and the source and drain electrodes 108, the SiN layer 111 is etched to deposit metals such as Ti / Al / Ni / Au, the first lead metal line 121 and the lead electrode 119 are deposited. Then, the SiN layer 118 is grown above using the PECVD method.

[0060] (13) Etch at the position corresponding to the IGZO transistor to etch a recess in the originally grown SiN layer 118, and fabricate the IGZO transistor in this recess area;

[0061] (14) Then, etching is performed in the channel region to form a concave hole, leaving a space for the IGZO base layer 114: In 0.52 Ga 0.29 Zn 0.19 O and IGZO Boost layer 115: In 0.82 Ga 0.08 Zn 0.10 The fabrication of O; and the growth of a SiO2 masking layer in the surrounding area to ensure that the IGZO base layer 114 and IGZO Boost layer 115 are fabricated in the area near the channel;

[0062] (15) Remove the excess SiO2 masking layer around it, and then grow the Al2O3 buffer layer 113 using ALD growth, in order to improve the interface problem.

[0063] (16) Based on the above structure, the HfO2 dielectric layer 116 is grown by ALD with a thickness of 50 nm;

[0064] (17) A certain degree of etching is performed in the corresponding channel area to leave a pit. The gate terminal 117 of the IGZO transistor is an ITO dielectric and is grown using ALD. Due to the reserved pit, a T-shaped gate is made here.

[0065] (18) Etch the HfO2 dielectric layer 116 and Al2O3 buffer layer 113 to form a through hole, fabricate a Ti / Al / Ni / Au multilayer metal, and fabricate a second lead metal line 122. At this time, it should be ensured that the second SiN layer 118 of the two devices are at the same height. At this time, fabricate a metal wire 124 with a width that can meet the maximum current drive, and connect the source terminal of the IGZO transistor and the drain terminal of the GaN HEMT.

[0066] (19) On this basis, the second SiN layer 118 is grown as a passivation layer and isolation layer to protect the device;

[0067] (20) Etching is performed at the source and drain ends of the GaN HEMT and in the corresponding region of the drain end of the IGZO transistor to form recessed holes. Metal electrodes are then fabricated within these recessed holes to create the external metal line 120 connecting the source and drain of the GaN HEMT and the second metal wire 125 leading out from the drain end of the IGZO transistor. It is worth mentioning that the external metal line 120 connecting the source and drain of the GaN HEMT and the connecting metal wire 124 do not overlap in three-dimensional space.

[0068] Example 2

[0069] The rest is the same as in Example 1, except that the thickness of GaN layer 103 in step (3) is 100 nm.

[0070] Example 3

[0071] The rest is the same as in Example 1, except that the thickness of GaN layer 103 in step (3) is 10 μm.

[0072] As is known from common technical knowledge, this invention can be implemented through other embodiments that do not depart from its spirit or essential characteristics. Therefore, the disclosed embodiments described above are merely illustrative in all respects and are not the only ones. All modifications within the scope of this invention or its equivalents are included in this invention.

Claims

1. An integrated structure of an IGZO transistor and a GaN HEMT gate control circuit, characterized in that, The above integrated structure is specifically divided into two parts, one of which is a GaN HEMT structure and the other is an IGZO transistor. Both of these parts are grown on a substrate (101). The GaN HEMT structure consists of, from bottom to top, a substrate (101), an AlGaN buffer layer (102), a GaN layer (103), an AlN layer (104), and an Al... 0.2 Ga 0.8 N layer (105), AlGaN layer (106), first SiN layer (107), source / drain electrodes (108), Al2O3 dielectric layer (109), GaN HEMT gate (110); The IGZO transistor is provided with the following layers from bottom to top: substrate (101), SiO2 layer (111), ITO layer (112) (serving as source, drain and gate), Al2O3 buffer layer (113), IGZO base layer (114), IGZO Boost layer (115), HfO2 dielectric layer (116), and IGZO transistor gate (117); After the above two parts are fabricated, a second SiN layer (118), a lead-out electrode (119) connected to the source / drain electrode (107), an external metal line (120) connected to the GaN HEMT source / drain lead-out electrode (119), a first lead-out metal line (121) connected to the GaN HEMT gate terminal (110), a second lead-out metal line (122) connected to the ITO layer (112), a third metal lead-out line (123), a first metal wire (124) connected to the GaN HEMT gate terminal lead-out metal line (121), and a second metal wire (125) connected to the IGZO transistor source / drain lead-out metal line (122) respectively.

2. The integrated structure of an IGZO transistor and a GaN HEMT gate control circuit according to claim 1, characterized in that, The substrate (101) is made of diamond material with epitaxial GaN thin film and has a size range of 2-8 inches.

3. The integrated structure of an IGZO transistor and a GaN HEMT gate control circuit according to claim 1, characterized in that, A SiN layer is grown on the substrate (101), and then etching is performed in the corresponding GaN HEMT device location area to form a recessed hole, and a GaN HEMT device is fabricated in this area.

4. The method for fabricating an integrated structure of an IGZO transistor and a GaN HEMT gate control circuit according to claim 1, characterized in that, Includes the following steps: (1) A relatively thick SiN layer (118) is grown on the substrate (101), and then etched in the corresponding GaN HEMT device location area to form a concave hole; (2) Based on the above structure, an AlGaN buffer layer (102) was grown using a metal-organic source chemical vapor deposition method; (3) A GaN buffer layer (103) is formed by unintentional doping on the above structure using metal-organic chemical vapor deposition or other methods, with a thickness of 100 nm-10 μm; (4) An AlN layer (104) was formed by unintentional doping on the above structure using metal-organic chemical vapor deposition. (5) Al was formed by unintentionally doping and growing the above structure using metal-organic chemical vapor deposition. 0.2 Ga 0.8 N layers (105); (6) An AlGaN layer (106) was formed by unintentional doping on the above structure using a metal-organic source chemical vapor deposition method; (7) Etch on the AlGaN layer (106) to leave a recess, and grow SiO2 in the recess using PECVD to preserve the position of the gate dielectric and gate electrode; (8) A first SiN layer (107) with a thickness of 100 nm was grown on the basis of the above structure using the PECVD method; (9) Electrodes with ohmic contacts are fabricated by magnetron sputtering as electrodes for the source and drain ends. At the same time, the first SiN layer (107) is etched based on the original recessed hole position of the AlGaN layer (106) to leave several recessed holes with a larger size than the original recessed hole. SiO2 is grown in the larger recessed holes using PECVD method to preserve the position of the gate dielectric and gate electrode. (10) Etch SiO2, grow gate Al2O3 dielectric layer (109) using ALD, and fabricate GaN HEMT gate terminal (110) on this basis; (11) A second SiN layer (118) with a thickness of 300 nm was grown on the basis of the above structure using the PECVD method; (12) The Al2O3 dielectric layer (109), the first SiN layer (107) and the second SiN layer (118) are etched to form through holes, and metals such as Ti / Al / Ni / Au are deposited to bring out the source and drain electrodes. Pad points are left above the first SiN layer (107). In the corresponding areas of the gate electrode (110) and the source and drain electrodes (108), the first SiN layer (107) is etched to deposit metals such as Ti / Al / Ni / Au to bring out the gate electrode metal (121) and the source and drain electrode metal (119). Then, the second SiN layer (118) is grown above using the PECVD method. (13) Etch at the position corresponding to the IGZO transistor to etch a recess in the originally grown second SiN layer (118), and fabricate the IGZO transistor in this recess area; (14) Then, etching is performed in the channel region to form a concave hole, leaving space for the IGZO base layer (114): In 0.52 Ga 0.29 Zn 0.19 O and IGZO Boost layers (115): In 0.82 Ga 0.08 Zn 0.10 O fabrication; and grow a SiO2 masking layer in the surrounding area to ensure that the IGZO base layer (114) and IGZO Boost layer (115) are fabricated in the area near the channel; (15) Remove the excess SiO2 masking layer around it, and then grow the Al2O3 buffer layer (113); (16) Based on the above structure, the HfO2 dielectric layer (116) is grown by ALD with a thickness of 50 nm; (17) A certain degree of etching is performed in the corresponding channel area to leave a pit. The gate end (117) of the IGZO transistor is an ITO dielectric and is grown using ALD. Due to the reserved pit, a T-shaped gate is made here. (18) Etch the HfO2 dielectric layer (116) and Al2O3 buffer layer (113) to form a via, fabricate a Ti / Al / Ni / Au multilayer metal, fabricate a second lead metal line (122), ensure that the second SiN layer (118) of the two devices are near the same height, at this time fabricate a metal wire (124) with a width that can meet the maximum current drive, and connect the source terminal of the IGZO transistor and the drain terminal of the GaN HEMT; (19) On this basis, the second SiN layer (118) is grown as a passivation layer and isolation layer to protect the device; (20) Etching is performed at the source and drain ends of the GaN HEMT and the corresponding area of ​​the drain end of the IGZO transistor to form a recessed hole. Metal electrodes are fabricated in the recessed hole to create an external metal line (120) connecting the source and drain of the GaN HEMT and a second metal wire (125) leading out from the drain end of the IGZO transistor. The external metal line (120) connected to the source and drain electrodes of the GaN HEMT and the first metal wire (124) do not overlap in three-dimensional space.

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