Semiconductor structure and manufacturing method
By employing axisymmetric design and N-type dopant to cut off leakage paths in the semiconductor structure, the problems of leakage and data refresh characteristic degradation caused by interference between memory cells are solved, thereby improving the reliability of highly integrated semiconductor products.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2020-09-03
- Publication Date
- 2026-05-26
AI Technical Summary
As semiconductor manufacturing processes become miniaturized, leakage current and data refresh characteristics deteriorate due to interference between memory cells. Existing technologies occupy a large area and cause current overhead, resulting in reduced reliability.
It adopts an axisymmetric structure design, which includes an active region, drain, data line contacts, gate layer and word lines. By forming an axisymmetric trench structure, interference errors between memory cells are reduced. N-type dopants are used to cut off the leakage path and deep data line contacts are formed to block electronic signal interference.
It effectively reduces interference errors between memory cells caused by miniaturization of manufacturing processes, prevents changes in inter-row coupling characteristics, and improves the reliability of highly integrated semiconductor products.
Smart Images
Figure CN114141771B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor structure and its manufacturing method. Background Technology
[0002] To manufacture highly integrated ULSI (Ultra-Limited Series) DRAMs that have evolved with increasing capacity, component sizes have shrunk to below the nanometer level, and the physical distance between components has also become closer. This has led to interference problems between adjacent components, especially in DRAMs, which rely on capacitors for data storage and require data refresh within a certain time interval. Specific word lines are repeatedly activated within the cell refresh interval, causing leakage due to interference between adjacent cells. Data retention time is shorter than the refresh cycle (e.g., 32 or 64 ms), meaning data is read before the refresh is even complete. One method to control this is by using a dedicated counter in the DRAM controller to track the number of row activations and shortening the refresh interval when repeated accesses of specific word lines occur. Another method is to use a dedicated counter in the DRAM controller to track the number of row activations and refresh only adjacent rows when repeated accesses of specific word lines occur. Figure 1 The diagram shows a buried gate transistor structure from the prior art. These two methods are used in existing DDR4 and later memory systems. To track the number of active rows, a dedicated counter is required, resulting in space occupation and current overhead in the memory system. Repeatedly receiving a specific row address can lead to changes in adjacent row data or inability to read the data, reducing reliability. This is because miniaturization in manufacturing processes causes interference errors between memory cells, a phenomenon that will become more severe with further miniaturization. If a specific word line is repeatedly activated (i.e., the word line voltage switches repeatedly), the high potential level generated during activation and deactivation may cause electrons to flow to the damaged row, resulting in some cells in the adjacent damaged row leaking charge faster than expected. Summary of the Invention
[0003] The purpose of this application is to provide a semiconductor structure and a method for manufacturing the same. To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general description, nor is it intended to identify key / important components or to describe the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.
[0004] According to one aspect of the embodiments of this application, a semiconductor structure is provided, which is an axisymmetric structure, comprising:
[0005] An active region; a recessed portion is formed in the middle of the active region, and a protrusion is formed on each side of the recessed portion;
[0006] A drain electrode is located at the bottom of the recess;
[0007] A data line contact is located on the drain electrode; the axis of symmetry of the semiconductor structure passes through the active region, the drain electrode, and the data line contact.
[0008] Two gate layers are located on the side of the gate sidewall layer on the same side away from the axis of symmetry;
[0009] Two word lines are located above the gate layer on the same side;
[0010] Two source electrodes are located on the protrusion on the same side.
[0011] According to another aspect of the embodiments of this application, a method for manufacturing a semiconductor structure is provided, comprising:
[0012] An axisymmetric structure is provided; the axisymmetric structure includes an active region;
[0013] A first groove is formed in the middle of the active region, and protrusions are formed on both sides of the first groove in the active region.
[0014] A gate oxide layer is formed at the bottom of the first trench;
[0015] A gate layer is formed on the gate oxide layer;
[0016] A second trench is formed that penetrates the gate layer and the gate oxide layer;
[0017] An N-type dopant is implanted into the active region, a drain is formed at the location of the active region directly below the second trench, and a source is formed on the protrusion.
[0018] A data line contact is formed within the second trench, directly above the drain electrode;
[0019] Word lines are formed on the gate oxide layer and the gate layer.
[0020] According to another aspect of the embodiments of this application, an electronic device is provided, including the semiconductor structure described above.
[0021] One aspect of the technical solution provided in this application embodiment may include the following beneficial effects:
[0022] The semiconductor structure provided in this application can reduce interference errors caused by the miniaturization of the manufacturing process between memory cells, prevent characteristic changes (deterioration) caused by inter-row coupling, and effectively improve the reliability of highly integrated semiconductor products.
[0023] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description, or some features and advantages may be inferred from the description or determined without question, or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This illustrates a prior art buried gate transistor structure;
[0026] Figure 2 The structure provided in the embodiments of this application is shown;
[0027] Figure 3 It shows in Figure 2 The structure after etching the first trench based on the structure shown;
[0028] Figure 4 It shows in Figure 3 The structure shown is based on which the gate oxide layer and the structure after the gate layer are formed;
[0029] Figure 5 It shows in Figure 4 The structure shown is formed by coating a first SiN layer and a second mask layer on top of the existing structure.
[0030] Figure 6 It shows in Figure 5 The structure after etching the second trench based on the structure shown;
[0031] Figure 7 It shows in Figure 6 The structure shown is obtained by implanting an N-type dopant into the original structure.
[0032] Figure 8 It shows in Figure 7 The structure is formed by adding data line contacts, word lines, and storage junction contacts based on the structure shown. Detailed Implementation
[0033] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0034] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0035] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0036] like Figures 2-8 As shown, one embodiment of this application provides a method for manufacturing a semiconductor structure, including:
[0037] S10. A structure is provided, the structure including an active region 5, isolation structures 6 located on both sides of the active region 5, and a first mask layer 2 covering the top surface of the active region 5 and the isolation structures 6, such as... Figure 2 As shown.
[0038] The top surface of the isolation structure 6 can be flush with the top surface of the active region 5, or slightly lower than the top surface of the active region 5, depending on actual needs. In this embodiment, the technical solution adopted is that the top surface of the isolation structure 6 is flush with the top surface of the active region 5. A first mask layer 2 is covered on the active region 5 and the isolation structure 6, and this mask layer is used to etch the active region 5.
[0039] Specifically, an active region 5 is first formed, then an isolation structure 6 is formed on both sides of the active region 5, and finally a first mask layer 2 is formed on the active region 5 and the isolation structure 6, completely covering the top surface of the active region 5 and the top surface of the isolation structure 6.
[0040] In some embodiments, the step of forming the active region 5 includes: providing a semiconductor substrate; forming a silicon oxide pad layer on the semiconductor substrate using thermal oxidation; forming a silicon nitride etch barrier layer on the pad oxide layer using chemical vapor deposition; forming a photoresist layer on the etch barrier layer using spin coating; defining the active region pattern through exposure and development processes; using the photoresist layer as a mask, etching the etch barrier layer, pad oxide layer, and semiconductor substrate using dry etching to form trenches; removing the remaining pad oxide layer and the remaining etch barrier layer; the region between two adjacent trenches is the active region 5. The first mask layer 2 can be an oxide layer, such as a silicon oxide layer.
[0041] S20. The first trench 1 is etched on the active region 5.
[0042] The first mask layer 2 and the active region 5 are etched sequentially. A first trench 1 is etched on the active region 5, and a protrusion 17 is formed on each side of the first trench 1 on the active region 5. Figure 3 As shown.
[0043] S30, A gate oxide layer 3 and a gate layer 4 are formed in the first trench 1.
[0044] First, an oxide layer is deposited in the first trench 1 to form an oxide layer. The top surface of this oxide layer is lower than the top surface of the protrusion 17 of the active region 5. Then, a groove is etched on the oxide layer, and a gate layer 4 is deposited in this groove. The top surface of the gate layer 4 is flush with the top surface of the oxide layer. Figure 4 As shown.
[0045] S40, coating the first SiN layer 7 and the second mask layer 8.
[0046] The first SiN layer 7 covers the top surface of the gate oxide layer 3 and the gate layer 4, and the top surface of the first SiN layer 7 is flush with the top surface of the active region 5. The second mask layer 8 covers the top surface of the active region 5, the top surface of the isolation structure 6, and the top surface of the first SiN layer 7, as shown below. Figure 5 As shown.
[0047] S50, the second mask layer 8, the first SiN layer 7, the gate layer 4 and the gate oxide layer 3 are etched sequentially from top to bottom to obtain the second trench 9.
[0048] The central axis of the second trench 9 coincides with the central axis of the active region 5. The second mask layer 8, the first SiN layer 7, the gate layer 4, and the gate oxide layer 3 are each divided by the second trench 9 into two symmetrical parts about the central axis of the active region 5, as shown below. Figure 6 As shown.
[0049] S60. Remove the second mask layer 8, then implant N-type dopant into the active region 5. A drain (N-type) 11 is formed at the bottom of the first trench 1 in the active region 5, and a source (N-type) 10 is formed on the protrusion 17 of the active region 5. Gate sidewall layers 12 are formed on both sides of the second trench 9. The upper part of the protrusion 17 is implanted with N-type dopant to form the source (N-type) 10. The drain (N-type) 11 is located directly below the second trench 9. The source (N-type) 10 is located between the first SiN layer 7 and the isolation structure 6, above the active region 5. The two gate sidewall layers 12 are located on both sides of the second trench 9, and the gate sidewall layers 12 are in contact with the gate oxide layer 3, the gate layer 4, and the first SiN layer 7. Figure 7 As shown.
[0050] S70, forming data line contact 14, word line 16 and storage junction contact 13.
[0051] Data line contacts 14 are formed within the second trench 9. A word line 16 is formed by extending the first SiN layer 7 upwards. A storage junction contact 13 is formed on one side of the word line 16, above the source (N-type) 10. A second silicon nitride layer 15 is formed on one side of the storage contact 13, above the isolation structure 6, as shown below. Figure 8 As shown.
[0052] The semiconductor structure has an axisymmetric cross-section. It includes an active region 5, a drain (N-type) 11, a data line contact 14, and two gate sidewall layers 12, two gate layers 4, two gate oxide layers 3, two word lines 16, two source (N-type) 10, two isolation structures 6, two second silicon nitride layers 15, and two memory contacts 13, all symmetrically arranged about the central axis of the active region 5. The central axes of the active region 5, the drain (N-type) 11, and the data line contact 14 coincide.
[0053] A recessed portion (i.e., the first groove 1) is formed in the middle of the active region 5, and a protrusion (i.e., the protrusion 17) is formed on each side of the recessed portion.
[0054] The drain (N-type) 11 is located at the bottom of the recess in the active region 5. The data line contact 14 is located on the drain (N-type) 11. Two gate sidewall layers 12 are located on both sides of the data line contact 14 and are in contact with both sides of the data line contact 14.
[0055] The structures on both sides of the central axis are symmetrical, referred to as the first side and the second side, respectively. On the first side of the central axis (e.g., the right side), the gate layer 4 and the gate oxide layer 3 are located on the side of the gate sidewall layer 12 away from the central axis. The bottom surface and the side away from the central axis of the gate layer 4 are in contact with the gate oxide layer 3. The top surfaces of the gate layer 4 and the gate oxide layer 3 are flush. The gate layer 4 and the gate oxide layer 3 are located within the recessed portion of the active region 5. The outer surface of the gate oxide layer 3 is in contact with the active region 5. The word line 16 is located directly above the gate layer 4 and the gate oxide layer 3. The upper portion of the word line 16 on the side near the central axis is in contact with the data line contact 14, and the lower portion of the word line 16 on the side near the central axis is in contact with the gate sidewall layer 12. The source (N-type) 10 is located on the upper part of the protrusion on the side of the active region 5 away from the central axis. The word line 16 is located on the side of the source (N-type) 10 near the central axis, and the isolation structure 6 is located on the side of the source (N-type) 10 away from the central axis. The storage contact 13 is located on the top surface of the source (N-type) 10. The second silicon nitride layer 15 is located on the top surface of the isolation structure 6 on the side of the storage contact 13 away from the central axis. The structure on the second side of the central axis is symmetrical about the central axis to the structure on the first side.
[0056] like Figure 8 As shown, this embodiment also provides a semiconductor structure, which is an axisymmetric structure, including:
[0057] An active region 5; a recessed portion is formed in the middle of the active region 5, and a protrusion 17 is formed on each side of the recessed portion;
[0058] A drain electrode 11 is located at the bottom of the recess;
[0059] A data line contact 14 is located on the drain 11; the symmetry axis L of the semiconductor structure passes through the active region 5, the drain 11 and the data line contact 14.
[0060] The gate sidewall layer 12 is located on one side of the data line contact 14;
[0061] Two isolation structures 6 are located on either side of the active region 5;
[0062] Two gate layers 4 are located on the side of the gate sidewall layer 12 away from the axis of symmetry L, respectively.
[0063] Two word lines 16 are located above the gate layer 4 on the same side;
[0064] Two source electrodes 10 are located on the same side protrusion 17.
[0065] The semiconductor structure also includes two gate oxide layers 3, located on the outside of the gate layer 4 on the same side and between the active region 5.
[0066] The semiconductor structure also includes:
[0067] Two storage contacts 13 are located on the top surface of the source electrode 10 on the same side.
[0068] The semiconductor structure further includes:
[0069] Two nitride layers are located on the top surface of the isolation structure 6 on the same side, and the nitride layer can be a second silicon nitride layer 15.
[0070] The isolation structure 6 is a field oxide layer or a shallow trench isolation.
[0071] The gate layer 4 can be a polysilicon gate layer or a metal gate layer.
[0072] The silicon nitride layer in this embodiment can also be replaced with other nitride layers.
[0073] The semiconductor structure provided in this application can reduce interference errors caused by the miniaturization of the manufacturing process between memory cells, prevent characteristic changes (deterioration) caused by inter-row coupling, and effectively improve the reliability of highly integrated semiconductor products.
[0074] This embodiment uses a mask that only exposes the drain region for P-type ion implantation, creating a deep N-type region between adjacent word lines to cut off the leakage path. A deep data line contact 14 is formed between the two word lines 16 sharing the active region 5. After forming the N-type region of the transistor drain portion, interference between adjacent word lines can be blocked. This method can reduce interference errors between memory cells caused by miniaturization of the manufacturing process, prevent characteristic changes (degradation) caused by inter-row coupling, and effectively improve the low reliability of highly integrated products.
[0075] In the method of this application embodiment, when forming buried channel array transistors, two word lines 16 sharing the same active region 5 are integrated and fabricated using the same pattern. The depth of the recess (i.e., the first trench 1) on the active region 5 is set according to the gate channel length. Gate sidewalls are formed on the separate sidewalls of the two word lines, and self-aligned data line contacts are fabricated based on these sidewalls.
[0076] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0077] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A semiconductor structure, characterized in that, It is an axisymmetric structure, including: An active region; a recessed portion is formed in the middle of the active region, and a protrusion is formed on each side of the recessed portion; A drain electrode is located at the bottom of the recess; A data line contact is located on the drain electrode; the axis of symmetry of the semiconductor structure passes through the active region, the drain electrode, and the data line contact. Two gate layers are located on the side of the gate sidewall layer away from the axis of symmetry, respectively. Two word lines are located above the gate layer on the same side; Two source electrodes are located on the protrusion on the same side.
2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes two gate oxide layers, located on the outer side of the gate layer on the same side and between the active region.
3. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: Two storage contacts are located on the top surface of the source electrode on the same side.
4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes two isolation structures, located on either side of the active region.
5. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure also includes: Two nitride layers are located on the top surface of the isolation structure on the same side.
6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a gate sidewall layer located on one side of the data line contact.
7. A method for manufacturing a semiconductor structure, characterized in that, include: An axisymmetric structure is provided; the axisymmetric structure includes an active region; A first groove is formed in the middle of the active region, and protrusions are formed on both sides of the first groove in the active region. A gate oxide layer is formed at the bottom of the first trench; A gate layer is formed on the gate oxide layer; A second trench is formed that penetrates the gate layer and the gate oxide layer; An N-type dopant is implanted into the active region, a drain is formed at the location of the active region directly below the second trench, and a source is formed on the protrusion. Forming a data line contact within the second trench, directly above the drain, includes: forming gate sidewall layers on both sides of the second trench by implanting an N-type dopant into the active region; forming the data line contact within the second trench, directly above the drain, includes forming the data line contact within the second trench, between the two gate sidewall layers, and directly above the drain. Word lines are formed on the gate oxide layer and the gate layer.
8. The method according to claim 7, characterized in that, The method further includes: A storage contact is formed on the top surface of each of the two source electrodes.
9. The method according to claim 7, characterized in that, The axisymmetric structure further includes isolation structures located on both sides of the active region; the method further includes forming a nitride layer on the top surface of each of the two isolation structures.
10. An electronic device comprising a semiconductor structure as claimed in any one of claims 1 to 6.
11. The electronic device according to claim 10, including a smartphone, computer, tablet computer, wearable smart device, artificial intelligence device, and power bank.