Dynamic Random Access Memory Structure

Abstract

The present invention discloses a dynamic random access memory structure, comprising a substrate, a plurality of contact structures located on the substrate, a first set of patterns located above the contact structures, wherein the first set of patterns includes a plurality of first curved patterns, and a second set of patterns located in the same plane as the first set of patterns, wherein the second set of patterns includes a plurality of second curved patterns, and wherein, when viewed from a top view, the plurality of first curved patterns and the plurality of second curved patterns intersect each other.

Description

[0001] This application is a divisional application of the application with the application number 202010469714.2, the application date of May 28, 2020, and the invention title of "Dynamic Random Access Memory Structure". Technical Field

[0002] The present invention relates to a semiconductor structure, in particular to a dynamic random access memory structure having a kite-shaped storage point contact pad. Background Art

[0003] Due to the development of semiconductor components towards high density, the component sizes within the unit area are continuously decreasing. Semiconductor components are widely used in the electronics industry due to their small size, multiple functions, and / or low manufacturing cost. Semiconductor components are divided into semiconductor components for storing logical data, semiconductor logic components for operating and processing logical data operations, or hybrid semiconductor components having both the functions of semiconductor storage components and semiconductor logic components and / or other semiconductor component functions.

[0004] Semiconductor components typically may include vertically stacked patterns and contact plugs for electrically connecting the stacked patterns to each other. As semiconductor components become highly dense, the space between the patterns and / or the space between the patterns and the contact plugs gradually decreases, thus increasing the parasitic capacitance between the patterns and / or between the patterns and the contact plugs. Parasitic capacitance may cause deterioration of the performance of semiconductor components (e.g., reducing the operating speed). Summary of the Invention

[0005] The present invention provides a semiconductor structure, in particular a dynamic random access memory structure having a kite-shaped storage point contact pad. By designing the kite-shaped storage point contact pad, it is easier to connect other components (such as storage point contacts or capacitors), improving the efficiency and manufacturing yield of the semiconductor structure.

[0006] According to an embodiment, the present invention provides a semiconductor structure, comprising a substrate, a plurality of contact structures located on the substrate, a first set of patterns located above the contact structures, wherein the first set of patterns includes a plurality of first curved patterns, and a second set of patterns located in the same plane as the first set of patterns, wherein the second set of patterns includes a plurality of second curved patterns, and wherein, from a top view, the plurality of first curved patterns and the plurality of second curved patterns intersect each other.

[0007] Optionally, from a top view, it includes a plurality of storage point contact pads, and each storage point contact pad is a kite-shaped pattern.

[0008] Optionally, any one of the kite-shaped pattern storage point contact pads is formed by being surrounded by any two adjacent first curved patterns and any two adjacent second curved patterns.

[0009] Optionally, the kite-shaped pattern includes two long sides and two short sides, where the two long sides have the same length and are adjacent to each other, and the two short sides also have the same length and are adjacent to each other.

[0010] Optionally, among the storage point contact pads of the plurality of kite-shaped patterns, the storage point contact pads of some of the kite-shaped patterns are arranged in a forward direction, and the storage point contact pads of the remaining kite-shaped patterns are arranged in a reverse direction.

[0011] Optionally, the storage point contact pads of the kite-shaped patterns arranged in the forward direction and the storage point contact pads of the kite-shaped patterns arranged in the reverse direction are rotated 180 degrees with respect to each other on the plan view.

[0012] Optionally, each first curve pattern is a broken line pattern, and each second curve pattern is also a broken line pattern.

[0013] Optionally, the broken line pattern is composed of a plurality of short line patterns connected in series, and the angle between any two adjacent short line patterns is greater than 90 degrees.

[0014] Optionally, it further includes an active region located in the substrate, and the contact structure is electrically connected to the active region.

[0015] Optionally, it further includes at least one bit line located on the substrate, and the bit line is located between two adjacent contact structures.

[0016] In this embodiment, the storage point contact pad is designed as a kite shape, so the overlapping area between the storage point contact pad and the contact structure is larger. In addition, since both the first curve pattern and the second curve pattern are designed as curves or broken lines, the length at the junction of the first curve pattern and the second curve pattern is also longer, which means that the subsequently filled insulating layer can more effectively electrically isolate adjacent storage point contact pads and avoid short circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the provided drawings.

[0018] Figure 1 A cross-sectional view of a semiconductor structure showing a preferred embodiment of the present invention.

[0019] Figure 2It is a top view schematic diagram when the patterning step of the semiconductor structure of the present invention is carried out.

[0020] Figure 3 An enlarged schematic diagram of the kite-shaped storage point contact pad SNPAD is drawn.

[0021] Figure 4 A schematic diagram of the junction of the first curve pattern and the second curve pattern according to another preferred embodiment of the present invention is drawn.

[0022] Figure 5 A schematic diagram of the shape and position of the arc-shaped storage point contact pad according to another embodiment of the present invention is drawn.

[0023] Among them, the reference numerals are explained as follows:

[0024] 10 - Substrate;

[0025] 11 - Active region;

[0026] 12 - Insulating layer;

[0027] 13 - Insulating layer;

[0028] 14 - Bit line;

[0029] 16 - Sidewall;

[0030] 20 - Capacitor structure;

[0031] 22 - Insulating layer;

[0032] 25 - Conductive layer;

[0033] 30 - First pattern;

[0034] 31 - First curve pattern;

[0035] 32 - Short line pattern;

[0036] 33 - Short line pattern;

[0037] 40 - Second pattern;

[0038] 41 - Second curve pattern;

[0039] 42 - Short line pattern;

[0040] 43 - Short line pattern;

[0041] A - Short side;

[0042] B - Long side;

[0043] C - Included angle;

[0044] D - Included angle;

[0045] BC - Bit - line contact structure;

[0046] INT - Junction;

[0047] INT2 - Junction;

[0048] SC - Storage - point contact structure;

[0049] SNPAD - Storage - point contact pad;

[0050] SNPAD’ - Storage - point contact pad;

[0051] SNPAD1’ - Storage - point contact pad;

[0052] SNPAD2’ - Storage - point contact pad;

[0053] D1 - First direction;

[0054] D2 - Second direction;

[0055] L1 - Overlap dimension;

[0056] L2 - Overlap dimension;

[0057] L3 - Length;

[0058] L4 - Length. Detailed implementation

[0059] Sufficient details have been disclosed below to enable those skilled in the art to implement it. Furthermore, the object structures and operation processes well - known to some of those skilled in the art will not be described in detail. Of course, other embodiments can also be applied in the present invention, or any structural, logical, and electrical changes can be made without departing from the embodiments described in the text.

[0060] Similarly, the embodiments in the drawings are only schematic and some details are not drawn to scale for clear description. In addition, for simplicity and clarity, when multiple embodiments have some similar features, these similar features will be represented by the same substantive marks.

[0061] Please refer to Figure 1 , in which Figure 1 represents a cross - sectional view of a semiconductor structure of a preferred embodiment of the present invention. As Figure 1 shown, the semiconductor structure of the present invention is, for example, a dynamic random - access memory (DRAM), which includes a substrate 10. On the substrate 10, there are a plurality of active regions 11 and a plurality of insulating layers 12 beside the active regions 11. The substrate 10 and the active regions 11 include, for example, semiconductor materials such as silicon or other suitable materials, and the insulating layer 12 can include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., but is not limited thereto.

[0062] On the base 10, there is at least also an insulating layer 13, a plurality of bit lines 14, a plurality of storage node contact structures SC, and at least one bit line contact structure BC. The insulating layer 13 is located between the bit lines 14 and the base 10. The bit lines 14 may include a plurality of structures arranged parallel to each other, spanning above the base 10. The storage node contact structure SC is between two adjacent bit lines 14. Here, the storage node contact structure SC is partially located in the active region 11, electrically connecting the active region 11 and the subsequent formed capacitor structure 20. The bit line contact structure BC is located on the base 10, used to electrically connect the active region 11 and part of the bit lines 14. Additionally, there are a plurality of sidewalls 16 for electrically isolating the bit lines 14, the storage node contact structure SC, or the bit line contact structure BC. The sidewalls 16 are, for example, silicon nitride or a composite layer of silicon nitride and silicon oxide, but are not limited thereto.

[0063] In addition, between the storage node contact structure SC and the capacitor structure 20, there may also be a storage node pad SNPAD. Here, the storage node pad SNPAD is used to electrically connect the storage node contact structure SC and the capacitor structure 20. Additionally, between adjacent storage node pads SNPAD, there is also an insulating layer 22, used to electrically isolate adjacent storage node pads SNPAD to avoid short circuits.

[0064] The above components are the main components of a dynamic random access memory (DRAM). Since the related technologies of DRAM are known in the art, they will not be elaborated here.

[0065] From Figure 1 it can be seen that if the width of the storage node pad SNPAD is enlarged, it can be more easily overlapped and contacted with the storage node contact structure SC, that is, it can help the alignment and electrical connection between the storage node contact structure SC and the capacitor structure 20. In other words, if the width of the storage node pad SNPAD is increased, it helps to improve the quality and yield of the DRAM structure. However, if the size of the storage node pad SNPAD is simply increased, it may cause adjacent storage node pads SNPAD to contact each other and cause a short circuit. Therefore, how to balance the size of the storage node pad SNPAD and the size of the surrounding insulating layer 22, and at the same time, as much as possible, expand the overlapping area between the storage node pad SNPAD and the contact structure SC, is one of the main purposes of the present invention.

[0066] In an actual manufacturing process, after components such as bit line 14, storage point contact structure SC, and bit line contact structure BC are completed, a conductive layer (not shown in the figure) is first comprehensively covered on the above components. Next, an etching step is used to form grooves in the conductive layer to isolate the conductive layer into different regions, and then an insulating layer is filled in the grooves. The remaining conductive layer here is the above-mentioned storage point contact pad SNPAD, and the insulating layer formed after filling the grooves is the above-mentioned insulating layer 22. Finally, a capacitor structure 20 is formed above the storage point contact pad SNPAD.

[0067] In the above embodiment, a conductive layer is first formed, then grooves are formed in the conductive layer, and an insulating layer is filled in the grooves. In other embodiments of the present invention, after components such as bit line 14, storage point contact structure SC, and bit line contact structure BC are completed, an insulating layer (not shown in the figure) can also be first comprehensively covered, then a patterned mask is formed on the insulating layer, and by etching, part of the insulating layer is removed to form grooves, and then a conductive layer is refilled in the grooves. At this time, the conductive layer filled in the grooves is defined as the above-mentioned storage point contact pad SNPAD. This method also falls within the scope of the present invention.

[0068] The feature of the present invention is that in the above etching compensation step, special patterned grooves and a storage point contact pad SNPAD with a special pattern are formed through a special patterning step to satisfy that the storage point contact pad SNPAD and the contact structure SC have a larger overlapping area. In addition, it is also possible to avoid as much as possible that the size of the storage point contact pad SNPAD is too large and contacts the adjacent storage point contact pad SNPAD to cause a short circuit.

[0069] Please refer to Figure 2 , Figure 2 is a top view schematic diagram when the semiconductor structure of the present invention is undergoing a patterning step. To simplify the drawing, only some components are marked in Figure 2 , including the storage point contact structure SC and the groove pattern required for the patterning step. The remaining components such as the active region 11, insulating layer 12, insulating layer 13, bit line 14, bit line contact structure BC, etc. are not marked in Figure 2 .

[0070] As Figure 2 shown, after components such as bit line 14, storage point contact structure SC, and bit line contact structure BC are completed (to simplify the drawing, Figure 2(Only the position of the storage point contact structure SC is drawn), forming a conductive layer 25 to cover the above components. Then, a first patterning step is performed to form a set of first patterns 30 in the conductive layer 25. Next, a second patterning step is performed to form a set of second patterns 40 in the conductive layer 25. The first patterns 30 include a plurality of first curve (or broken line) patterns 31, and the second patterns 40 include a plurality of second curve (or broken line) patterns 41. The first curve pattern 31 and the second curve pattern 41 may be grooves. Or in other embodiments, if the insulating layer is formed first and then the conductive layer (SNPAD) is formed, the first curve pattern 31 and the second curve pattern 41 here may also be mask patterns. From a top view, the first patterns 30 and the second patterns 40 are located on the same plane and intersect with each other. That is to say, the plurality of first curve patterns 31 and the plurality of second curve patterns 41 intersect with each other. And after the first patterns 30 and the second patterns 40 intersect, the remaining conductive layer 25 presents a kite shape. Here, the conductive layer 25 surrounded by two first curve patterns 31 and two second curve patterns 41 is the above-mentioned Figure 1 storage point contact pad SNPAD mentioned in

[0071] In this embodiment, as Figure 2 shown, the first patterns 30 include a plurality of first curve patterns 31, and each first curve pattern 31 is arranged substantially along a first direction (such as D1). In detail, the first curve pattern 31 is a broken line pattern, including short line patterns 32 and short line patterns 33 that are alternately connected in series. On both sides of any short line pattern 32 are short line patterns 33. And for the same first curve pattern 31, the short line patterns 32 are arranged parallel to each other, and the short line patterns 33 are also arranged parallel to each other.

[0072] In this embodiment, as Figure 2 shown, the second patterns 40 include a plurality of second curve patterns 41, and each second curve pattern 41 is arranged substantially along a second direction (such as D2). In detail, the second curve pattern 41 is a broken line pattern, including short line patterns 42 and short line patterns 43 that are alternately connected in series. On both sides of any short line pattern 42 are short line patterns 43. And for the same second curve pattern 41, the short line patterns 42 are arranged parallel to each other, and the short line patterns 43 are also arranged parallel to each other.

[0073] Although the first curve pattern 31 and the second curve pattern 41 are both designed as broken line patterns in this embodiment, in other preferred embodiments of the present invention, the first curve pattern 31 and the second curve pattern 41 can be designed as other curve patterns, such as wavy patterns, which also fall within the scope of the present invention.

[0074] After the first curve pattern 31 and the second curve pattern 41 of the present invention are formed in the conductive layer 25, from a top view, the conductive layer 25 is divided into many intervals. Each interval is formed by being surrounded by two adjacent first curve patterns 31 and any two adjacent second curve patterns 41. Each of these intervals can be regarded as a storage point contact pad SNPAD, and the storage point contact pad SNPAD presents a kite shape. To more clearly illustrate the kite-shaped storage point contact pad SNPAD, Figure 3 An enlarged schematic diagram of the kite-shaped storage point contact pad SNPAD is drawn.

[0075] As Figure 3 shown, the kite-shaped storage point contact pad SNPAD in this embodiment includes four sides, two short sides A and two long sides B. The lengths of the two short sides A are equal, and the lengths of the two long sides B are also equal. The two short sides A are in direct contact, forming an angle C between the two short sides, and the angle C is an obtuse angle (that is, the angle is greater than 90 degrees). There is an angle D between the two long sides B, and the angle D is an acute angle (that is, the angle is less than 90 degrees).

[0076] In addition, as Figure 2 and Figure 3 shown, for the kite-shaped storage point contact pad SNPAD in this embodiment, some of the storage point contact pads SNPAD are arranged in a forward direction, while the remaining storage point contact pads SNPAD are arranged in a reverse direction. For example, Figure 3 the storage point contact pad SNPAD on the left in can be defined as being arranged in a forward direction, and the storage point contact pad SNPAD on the right can be defined as being arranged in a reverse direction, but it is not limited to this. The definitions of the forward arrangement and the reverse arrangement are patterns that are flipped 180 degrees with respect to each other on the same plane (such as the XY plane). In this embodiment, along the X-axis direction, the kite-shaped storage point contact pads SNPAD arranged in a forward direction and the kite-shaped storage point contact pads SNPAD arranged in a reverse direction are arranged alternately. Therefore, all the kite-shaped storage point contact pads SNPAD will be more evenly distributed, and it is less likely to have short circuits due to mutual contact.

[0077] As Figure 2 shown, in this embodiment, the storage point contact pad SNPAD is designed in a kite shape, so the overlapping area between the storage point contact pad SNPAD and the contact structure SC is larger (such as the overlapping dimension L1 shown in Figure 2 ). In addition, since both the first curve pattern 31 and the second curve pattern 41 are designed as curves or broken lines, the length of the junction INT between the first curve pattern 31 and the second curve pattern 41 is also longer (such as Figure 2The overlapping dimension L2) of the junction INT shown represents the subsequently filled insulating layer 22, which can more effectively electrically isolate adjacent storage point contact pads SNPAD and avoid short circuits. In addition, in this preferred embodiment, the junction INT is hexagonal, but it is not limited thereto.

[0078] In another preferred embodiment of the present invention, please refer to Figure 4 , which shows the junction of the first curve pattern and the second curve pattern. To clearly show the diagram, except for the junction INT2, the other components are not shown in Figure 4 . In this preferred embodiment, during the manufacturing process, the junction INT2 may be rounded due to etching. As Figure 4 shown, the junction INT2 has a pattern similar to the junction INT in the above embodiment, but the angle of the junction INT2 is more rounded due to etching. This embodiment also falls within the scope of the present invention.

[0079] In addition, in another preferred embodiment of the present invention, please refer to Figure 5 , which shows a schematic diagram of the shape and position of the storage point contact pad SNPAD' according to another embodiment of the present invention. To clearly show the diagram, except for the storage point contact pad SNPAD', the other components are not shown in Figure 5 . In this preferred embodiment, the storage point contact pads SNPAD are arranged in a checkerboard pattern, and each storage point contact pad SNPAD' has an arc-shaped zither pattern. The arc-shaped zither pattern is similar to the zither pattern described in the previous embodiment, but due to the influence of the etching process during the manufacturing process, the corners of the zither pattern are rounded to form the storage point contact pad SNPAD' with an arc-shaped zither pattern. In this preferred embodiment, as Figure 5As shown, the storage point contact pad SNPAD' of the arc-shaped zheng-shaped pattern includes two long arc sides and two short arc sides, where the two long arc sides have the same length and are adjacent to each other, and the two short arc sides also have the same length and are adjacent to each other. Among the storage point contact pads SNPAD' of the plurality of arc-shaped zheng-shaped patterns, some of the storage point contact pads SNPAD' are arranged in the forward direction, and the remaining storage point contact pads SNPAD' are arranged in the reverse direction. The storage point contact pads SNPAD' arranged in the forward direction and the storage point contact pads SNPAD' arranged in the reverse direction are rotated 180 degrees with respect to each other on the plan view. In addition, along the first direction, the shortest distance between any storage point contact pad SNPAD' and an adjacent another storage point contact pad (such as SNPAD1') is defined as the length L3, and along the second direction, the shortest distance between any storage point contact pad SNPAD' and an adjacent another storage point contact pad (such as SNPAD2') is defined as the length L4, where the length L3 and the length L4 are not equal, and the above-mentioned first direction and the above-mentioned second direction are not parallel to each other. This embodiment also falls within the scope of the present invention.

[0080] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A dynamic random access memory structure, comprising: A substrate; and A plurality of conductive patterns arranged on the substrate, wherein the conductive patterns are arranged in a checkerboard staggered pattern, and each conductive pattern presents an arc-shaped kite pattern, wherein some of the conductive patterns in the arc-shaped kite pattern are arranged in a forward direction, and the remaining conductive patterns are arranged in a reverse direction, wherein the forward arrangement and the reverse arrangement are 180-degree rotations of each other in a plan view; the conductive patterns in odd-numbered columns are arranged in a forward direction, and the conductive patterns in even-numbered columns are arranged in a reverse direction, and the conductive patterns arranged in a forward direction are different from the conductive patterns arranged in a reverse direction.

2. The dynamic random access memory structure according to claim 1, wherein In a first direction, the shortest distance between the conductive pattern and another adjacent conductive pattern is a length L3, and in a second direction, the shortest distance between the conductive pattern and another adjacent conductive pattern is a length L4, wherein the length L3 is different from the length L4.

3. The dynamic random access memory structure according to claim 2, wherein Wherein the first direction and the second direction are not parallel to each other.

4. The dynamic random access memory structure according to claim 1, wherein The corners of the arc-shaped kite pattern are rounded.

5. The dynamic random access memory structure according to claim 1, characterized in that, The arc-shaped kite pattern is formed by being surrounded by any two adjacent first curve patterns and any two adjacent second curve patterns.

6. The dynamic random access memory structure according to claim 1, wherein The arc-shaped kite pattern includes two long sides and two short sides, wherein the two long sides have the same length and are adjacent to each other, and the two short sides also have the same length and are adjacent to each other.

7. A dynamic random access memory structure, comprising: A substrate; and A plurality of conductive patterns arranged on the substrate, wherein the conductive patterns are arranged in a checkerboard staggered pattern, the conductive patterns include four sides, namely two short sides and two long sides, and the two short sides are in direct contact with each other, forming an included angle therebetween, and the included angle is an obtuse angle, an included angle is formed between the two long sides, and the included angle is an acute angle, and the two included angles are rounded; The two short sides have the same length, and the two long sides also have the same length.

8. The dynamic random access memory structure according to claim 7, wherein Each conductive pattern presents an arc-shaped kite pattern, wherein some of the conductive patterns in the arc-shaped kite pattern are arranged in a forward direction, and the remaining conductive patterns are arranged in a reverse direction, and the forward arrangement and the reverse arrangement are 180-degree rotations of each other in a plan view.

9. The dynamic random access memory structure according to claim 7, wherein In a first direction, the shortest distance between the conductive pattern and another adjacent conductive pattern is a length L3, and in a second direction, the shortest distance between the conductive pattern and another adjacent conductive pattern is a length L4, wherein the length L3 is different from the length L4.

10. The dynamic random access memory structure according to claim 9, wherein Wherein the first direction and the second direction are not parallel to each other.

11. The dynamic random access memory structure according to claim 8, wherein The arc-shaped kite pattern is formed by being surrounded by any two adjacent first curve patterns and any two adjacent second curve patterns.

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