Shielded gate trench field effect transistor and preparation method thereof

Abstract

The present application relates to a shielded-gate trench field-effect transistor, comprising: a substrate region, a drift region, a body region, a source region, a trench region, a drain, and a source; the drift region is connected to the substrate region, with the direction of the substrate region pointing toward the drift region being considered upward, and the body region and the source region are sequentially arranged above the drift region; the trench region is arranged lateral to the body region and is respectively connected to the drift region, the body region, and the source region; the trench region includes a shield gate, a control gate, an insulating layer, and a metal gate; the source region is composed of a P-type source region and an N-type source region, the P-type source region and the N-type source region being arranged in parallel and respectively connected to the trench region; and the shield gate is connected to the drift region. When avalanche breakdown occurs, hole current can be directly injected into the P-type source region along the side of the trench region, shortening the path of hole current movement, thereby suppressing the turn-on of the parasitic transistor and improving avalanche resistance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a shielded gate trench field effect transistor and a method for preparing the same. Background Art

[0002] Shielded-gate trench field-effect transistors (SGTs) have been widely used in important low-voltage applications such as power management. SGTs offer high channel density and excellent charge compensation. Furthermore, their shielded gate structure effectively isolates the coupling between the control gate and the drain, significantly reducing transfer capacitance.

[0003] Therefore, SGT has lower specific on-resistance, smaller conduction loss and switching loss, and higher operating frequency.

[0004] However, when a traditional SGT is blocked or turned on by a forward high voltage, the SGT is prone to generate hole current due to the avalanche effect. This hole current flowing through the substrate channel will cause the parasitic transistor to turn on, and the turning on of the parasitic transistor will cause the transistor to fail avalanche.

[0005] Therefore, in order to suppress the turn-on of the parasitic transistor in the SGT before the SGT avalanche failure occurs, it is urgent to design a new shielded gate trench field effect transistor. Summary of the Invention

[0006] To overcome the problems existing in the related art, the present application provides a shielded gate trench field effect transistor, characterized in that it includes:

[0007] Substrate region 1, drift region 2, body region 3, source region 4, trench region 5, source 7 and drain 6;

[0008] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 being considered upward.

[0009] The base region 3 and the source region 4 are sequentially arranged above the drift region 2;

[0010] The trench region 5 is arranged on the side of the base region 3 and is connected to the drift region 2, the base region 3 and the source region 4 respectively;

[0011] The source region 4 is composed of a P-type source region 41 and an N-type source region 42 . The P-type source region 41 and the N-type source region 42 are arranged in parallel along the top surface of the base region 3 and are respectively connected to the trench region 5 .

[0012] The trench region 5 includes a shield gate 51, a control gate 52, an insulating layer 53, and a metal gate. The control gate 52 and the shield gate 51 are sequentially arranged in the trench region 5 from top to bottom and separated by the insulating layer 53. The control gate 52 is connected to the base region 3 and the source region 4 respectively through the insulating layer 53, and the shield gate 51 is connected to the drift region 2 through the insulating layer 53.

[0013] The source electrode 7 is disposed above the source region 4 ; the drain electrode 6 is disposed below the substrate region 1 ; and the metal gate is disposed above the control gate 52 .

[0014] In one embodiment, on the longitudinal section of the source region 4, at least two P-type source regions 41 and at least two N-type source regions 42 are alternately arranged, and the P-type source region 41 is connected to the trench region 5, so that the distance between the P-type source region 41 and the trench region 5 is reduced.

[0015] In one embodiment, the shielded gate trench field effect transistor further includes a barrier buffer zone 8:

[0016] The potential barrier buffer area 8 is disposed between the drift region 2 and the base region 3 .

[0017] In one embodiment, a metal layer is provided between the drift region 2 and the base region 3 , and the interface between the metal layer and the drift region 2 forms the potential barrier buffer region 8 .

[0018] In one embodiment, the potential barrier buffer region 8 is a Schottky junction between the base region 3 and the drift region 2 .

[0019] In one embodiment, the doping concentrations of the P-type source region 41 and the N-type source region 42 are both heavily doped.

[0020] In one embodiment, the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is a heavy doping concentration;

[0021] The doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is a light doping concentration;

[0022] The doping type of the base region 3 is P-type doping, and the doping concentration of the base region 3 is medium doping concentration;

[0023] The doping concentration of the source region 4 is a heavy doping concentration; the doping concentration of the control gate 52 is a heavy doping concentration, and the doping type of the control gate 52 is P-type doping.

[0024] A second aspect of the present application provides a method for preparing a shielded gate trench field effect transistor, which is used to prepare the shielded gate trench field effect transistor described in the first aspect of the present application, comprising:

[0025] preparing a substrate region with semiconductor material;

[0026] epitaxially forming a drift region on the substrate region;

[0027] forming a matrix region on the drift region by ion implantation or diffusion;

[0028] etching a trench on one side of the drift region;

[0029] Depositing P-type doped semiconductor material, polysilicon, oxide and polysilicon in sequence in the trench to form a shield gate, an insulating layer and a control gate;

[0030] On the base region, forming the P-type source region and the N-type source region with a P-type doped semiconductor material and an N-type doped semiconductor material respectively;

[0031] forming a source electrode above the source region;

[0032] forming a metal gate over the trench;

[0033] A drain is formed below the substrate region.

[0034] In one embodiment, before forming a base region on the drift region by ion implantation or diffusion, the method includes:

[0035] Metal is deposited on the drift region to form a potential barrier buffer zone.

[0036] In one embodiment, the step of doping the substrate region to form a source region includes:

[0037] On the base region, a P-type source region and an N-type source region are formed using a P-type doped semiconductor material and an N-type doped semiconductor material respectively, so that the P-type source region and the N-type source region are connected.

[0038] The technical solution provided by this application may have the following beneficial effects:

[0039] When in the avalanche state, the drift region is in a forward blocking state, and the drift region acts as a reverse-biased voltage-withstand region. The hole current generated by impact ionization in the reverse-biased voltage-withstand region can be diverted to the P-type source region. Since the hole current is generated at the junction of the trench region and the drift region, the hole current passes through the substrate region along the interface and then flows into the P-type source region.

[0040] The present application provides a shielded-gate trench field-effect transistor (FET) having a source region composed of a P-type source region and an N-type source region, the P-type source regions and the N-type source regions being arranged alternately, with the P-type source region being disposed adjacent to the trench region. Therefore, when avalanche breakdown occurs, hole current can be directly injected into the P-type source region along the sides of the trench region, shortening the path for hole migration, corresponding to a lower forward bias voltage, suppressing the turn-on of the parasitic transistor, and improving the avalanche withstand capability of the FET.

[0041] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and other objects, features and advantages of the present application will become more apparent through a more detailed description of exemplary embodiments of the present application in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the present application.

[0043] Figure 1 1 is a schematic structural diagram of a shielded-gate trench field-effect transistor shown in an embodiment of the present application;

[0044] Figure 2 yes Figure 1 A cross-sectional view of the shielded gate trench field effect transistor AA' shown;

[0045] Figure 3 It is a schematic structural diagram of a shielded gate trench field effect transistor in the prior art;

[0046] Figure 4 1 is a schematic flow chart of a method for preparing a shielded gate trench field effect transistor shown in an embodiment of the present application;

[0047] Figure 5 This is another flow chart of a method for preparing a shielded gate trench field effect transistor shown in an embodiment of the present application. DETAILED DESCRIPTION

[0048] The preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. Instead, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0049] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0050] It should be understood that although the terms "first", "second", "third", etc. may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0051] Example 1

[0052] When a conventional SGT is blocked or turned on by a forward high voltage, it is prone to generating hole current due to the avalanche effect. This hole current flows through the substrate channel, causing the parasitic transistor to turn on. The turning on of the parasitic transistor will cause the transistor to fail avalanche.

[0053] In response to the above problems, an embodiment of the present application provides a shielded gate trench field effect transistor, which can suppress the turn-on of a parasitic transistor in an SGT before the SGT undergoes avalanche failure.

[0054] The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0055] Figure 1 1 is a schematic structural diagram of a shielded-gate trench field-effect transistor shown in an embodiment of the present application;

[0056] Figure 2 yes Figure 1 A cross-sectional view of the shielded gate trench field effect transistor AA' shown;

[0057] See also Figure 1 and Figure 2 The shielded gate trench field effect transistor comprises: a substrate region 1, a drift region 2, a body region 3, a source region 4, a trench region 5, a source electrode 7 and a drain electrode 6;

[0058] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 being considered upward.

[0059] The base region 3 and the source region 4 are sequentially arranged above the drift region 2;

[0060] The trench region 5 is arranged on the side of the base region 3 and is connected to the drift region 2, the base region 3 and the source region 4 respectively;

[0061] The source region 4 is composed of a P-type source region 41 and an N-type source region 42 . The P-type source region 41 and the N-type source region 42 are arranged in parallel along the top surface of the base region 3 and are respectively connected to the trench region 5 .

[0062] The trench region 5 includes a shield gate 51, a control gate 52, an insulating layer 53, and a metal gate. The control gate 52 and the shield gate 51 are sequentially arranged in the trench region 5 from top to bottom and separated by the insulating layer 53. The control gate 52 is connected to the base region 3 and the source region 4 respectively through the insulating layer 53, and the shield gate 51 is connected to the drift region 2 through the insulating layer 53.

[0063] The source electrode 7 is disposed above the source region 4 ; the drain electrode 6 is disposed below the substrate region 1 ; and the metal gate is disposed above the control gate 52 .

[0064] In an embodiment of the present application, the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is a heavy doping concentration; the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is a light doping concentration; the doping type of the base region 3 is P-type doping, and the doping concentration of the base region 3 is a medium doping concentration; the doping concentration of the source region 4 is a heavy doping concentration; the doping concentration of the control gate 52 is a heavy doping concentration, and the doping type of the control gate 52 is P-type doping.

[0065] In the embodiment of the present application, the light doping concentration range is 1×10 15 cm -3 to 5×10 16 cm -3 The doping concentration range is 1×10 17 cm -3 to 5×10 18 cm -3 The range of heavy doping concentration is 1×10 19 cm -3 to 5×10 20 cm -3 .

[0066] In the embodiment of the present application, the doping type of the shielding gate 51 is P-type doping, the doping type of the P-type source region 41 is P-type doping, and the doping concentration of the P-type source region 41 is medium doping concentration or heavy doping concentration.

[0067] Furthermore, the doping type and doping concentration of the shielding gate 51 may be a heavy doping concentration or a medium doping concentration.

[0068] Preferably, the P-type source region 41 and the N-type source region 42 are both set to the same doping concentration, for example, both are medium doping concentration or both are heavy doping concentration, so that the P-type source region 41 can more easily receive hole current and achieve better shunting effect.

[0069] When in the avalanche state, the drift region 2 is in a forward blocking state, and the drift region 2 acts as a reverse-biased voltage-withstanding region. The hole current generated by impact ionization in the reverse-biased voltage-withstanding region can be diverted to the P-type source region 41. Since the hole current is generated at the interface between the trench region 5 and the drift region 2, the hole current passes through the base region 3 along the interface and then flows into the P-type source region 41.

[0070] Figure 3 It is a structural schematic diagram of a shielded gate trench field effect transistor in the prior art;

[0071] like Figure 3 As shown, when a hole current caused by the avalanche effect occurs, the hole current needs to bypass the N-type source region 42 to reach the P-type source region 41 , so the hole current has a longer movement path.

[0072] like Figure 2 As shown, when a hole current appears in the shielded gate trench field effect transistor in the embodiment of the present application, the hole current is directly injected into the P-type source region 41 , so the movement path of the hole current is shorter.

[0073] The present application provides a shielded-gate trench field-effect transistor, whose source region 4 is composed of a P-type source region 41 and an N-type source region 42. The P-type source regions 41 and the N-type source regions 42 are arranged alternately, and the P-type source regions 41 are connected to both the trench region 5 and the body region 3. Therefore, when avalanche breakdown occurs, hole current can be directly injected into the P-type source region 41 along the side of the trench region 5. The path of hole current movement becomes shorter, corresponding to a lower forward bias voltage, suppressing the turn-on of the parasitic transistor, and improving the avalanche withstand capability of the shielded-gate trench field-effect transistor.

[0074] Preferably, M P-type source regions 41 and M N-type source regions 42 are arranged alternately, where M is an integer greater than 1. The projected areas of the P-type source regions 41 and the N-type source regions 42 on the placement plane are equal, so that hole current can flow into one of the closest P-type source regions 41, thereby achieving a better diversion effect.

[0075] Example 2

[0076] Based on the above-mentioned embodiment 1, the embodiment of the present application provides another shielded gate trench field effect transistor, which can effectively guide the hole current to enter the base region and flow into the P-type source region 41 more evenly when an avalanche occurs.

[0077] The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0078] See also Figure 1 and Figure 2 , the shielded gate trench field effect transistor comprises:

[0079] Substrate region 1, drift region 2, body region 3, source region 4, trench region 5, source 7 and drain 6;

[0080] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 being considered upward.

[0081] The base region 3 and the source region 4 are sequentially arranged above the drift region 2;

[0082] The trench region 5 is arranged on the side of the base region 3 and is connected to the drift region 2, the base region 3 and the source region 4 respectively;

[0083] The source region 4 is composed of a P-type source region 41 and an N-type source region 42. The P-type source region 41 and the N-type source region 42 are arranged side by side along the top surface of the base region 3 and are respectively connected to the trench region 5.

[0084] The trench region 5 includes a shield gate 51, a control gate 52, an insulating layer 53, and a metal gate. The control gate 52 and the shield gate 51 are sequentially arranged in the trench region 5 from top to bottom and separated by the insulating layer 53. The control gate 52 is connected to the base region 3 and the source region 4 respectively through the insulating layer 53, and the shield gate 51 is connected to the drift region 2 through the insulating layer 53.

[0085] The source electrode 7 is disposed above the source region 4 ; the drain electrode 6 is disposed below the substrate region 1 ; and the metal gate is disposed above the control gate 52 .

[0086] Furthermore, the potential barrier buffer region 8 is provided between the drift region 2 and the base region 3 .

[0087] In the embodiment of the present application, a metal layer is provided between the drift region 2 and the base region 3, and the interface between the metal layer and the drift region 2 forms the barrier buffer region 8. The barrier buffer region 8 is a Schottky junction between the base region 3 and the drift region 2.

[0088] The Schottky junction, similar to the PN junction, has nonlinear impedance characteristics, also known as rectification characteristics. However, in a Schottky junction, the drift of majority carriers plays a major role, with virtually no stored carriers. Therefore, when the transistor is reverse-conducting, the Schottky junction's reverse recovery time is very short, effectively reducing the transistor's reverse recovery time and increasing its switching speed.

[0089] At the same time, in the embodiment of the present application, compared with the PN junction formed between the base region 3 and the drift region 2, when an avalanche hole current occurs, the Schottky junction set between the base region 3 and the drift region 2 can effectively guide the hole current to enter the base region 3 more evenly after entering the metal layer, so that the hole current is evenly diverted to each P-type source region 41, thereby improving the diversion ability of the P-type source region 41 to the hole current.

[0090] In the embodiment of the present application, the doping concentrations of the P-type source region 41 and the N-type source region 42 are both heavily doped.

[0091] Since the doping concentrations of the P-type source region 41 and the N-type source region 42 are both heavily doped, an ohmic contact is formed, so that the resistance value of the contact surface between the two is much smaller than the resistance of the semiconductor itself. As a result, most of the voltage drop occurs in the active area rather than the contact surface. That is, the ohmic contact does not generate obvious additional impedance in the device, nor does it cause a significant change in the equilibrium carrier concentration inside the device, which is beneficial to maintaining the performance of the device.

[0092] Example 3

[0093] Corresponding to the aforementioned shielded gate trench field effect transistor and its embodiments, the present application also provides a method for preparing a shielded gate trench field effect transistor and corresponding embodiments.

[0094] Figure 4 It is a schematic flow chart of a method for preparing a shielded gate trench field effect transistor shown in an embodiment of the present application.

[0095] See also Figure 4 , the method for preparing the shielded gate trench field effect transistor comprises:

[0096] 401. Prepare a substrate region using semiconductor material;

[0097] In the embodiment of the present application, the substrate region is prepared using an N-type heavily doped semiconductor material, that is, the doping type of the substrate region is N-type doping, and the doping concentration of the substrate region is a heavily doped concentration.

[0098] In an embodiment of the present application, the semiconductor material is silicon material or silicon carbide material.

[0099] 402. Forming a drift region by epitaxial growth on the substrate region;

[0100] In the embodiments of the present application, different epitaxial processes may be used according to actual needs, including but not limited to vapor phase epitaxy (VPE) or chemical vapor deposition (CVD).

[0101] 403. Forming a matrix region on the drift region by ion implantation or diffusion;

[0102] Ion implantation is the process of doping silicon materials. In practice, a power device is placed at one end of an ion implanter, with a doping ion source located at the other. At the doping ion source, the dopant atoms are ionized, becoming charged. The electric field propels them at high speeds, forcing them through the surface of the device. The momentum of the atoms propagates through the power device, forming a doped region.

[0103] The diffusion process is the process of doping pure impurity atoms into the surface of silicon materials. In actual applications, diborane or phosphine is usually used as an ion source, and intermittent diffusion or substitutional diffusion is used to dope pure impurity atoms into the surface of silicon materials.

[0104] It should be noted that the embodiments of the present application do not have strict restrictions on the preparation method used for the substrate region. In actual practice, the above-mentioned different processes can be selected according to actual needs to complete the preparation of the substrate region.

[0105] 404. Etching a trench on one side of the drift region;

[0106] In an embodiment of the present application, a groove is etched on one side of the drift region by a photolithography process, and the residual photoresist is removed by wet etching or dry etching.

[0107] 405. Depositing a P-type doped semiconductor material, polysilicon, oxide, and polysilicon in sequence in the trench to form a shield gate, an insulating layer, and a control gate;

[0108] Preferably, in an embodiment of the present application, P-type medium-doped semiconductor material, P-type medium-doped polysilicon, oxide and heavily-doped polysilicon are sequentially deposited in the trench to form the shielding gate, insulating layer and control gate.

[0109] 406. Form the P-type source region and the N-type source region on the base region using a P-type doped semiconductor material and an N-type doped semiconductor material, respectively;

[0110] Furthermore, the P-type source region and the N-type source region are connected.

[0111] In an embodiment of the present application, P-type doped semiconductor material and N-type doped semiconductor material are doped on the base region to form a P-type source region and an N-type source region. The base region and the N-type source region connected to the trench region are short-circuited through the P-type source region, thereby suppressing the substrate floating effect of the power semiconductor device and ensuring the stability of the device performance.

[0112] In the embodiment of the present application, preferably, the doping concentrations of the above-mentioned P-type doped semiconductor material and N-type doped semiconductor material are both heavily doped to form an ohmic contact, thereby ensuring that no significant additional impedance is generated in the device.

[0113] 407. forming a source electrode above the source region;

[0114] 408. Form a metal gate above the trench;

[0115] 409. Fabricate a drain below the substrate region.

[0116] An embodiment of the present application provides a method for preparing a shielded gate trench field-effect transistor, wherein a P-type source region and an N-type source region are formed above a base region using a P-type doped semiconductor material and an N-type doped semiconductor material, respectively. The P-type source region and the N-type source region are arranged in parallel and are respectively connected to the trench region, so that the interface between the trench region and the base region is short-circuited with both the P-type source region and the N-type source region.

[0117] When hole current occurs, it is generated in the drift region and flows along the interface between the trench region and the body region to the source region. The hole current can be directly injected into the nearest P-type source region without bypassing the N-type source region and then injecting into the P-type source region.

[0118] Compared with the traditional SGT, the arrangement structure of the P-type source region and the N-type source region is changed when the source region is formed; above the substrate region, the P-type source region and the N-type source region are parallel and connected to the trench region at the same time, so that the P-type source region is directly short-circuited with the trench region, reducing the path length of the hole current, corresponding to a lower forward bias voltage, which can effectively suppress the turn-on of the parasitic transistor and improve the avalanche withstand capability of the shielded gate trench field effect transistor.

[0119] Example 4

[0120] Based on the method for preparing the shielded gate trench field effect transistor shown in the third embodiment above, an embodiment of the present application provides a method for preparing a shielded gate trench field effect transistor provided with a Schottky junction.

[0121] The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0122] Figure 5 This is another schematic flow chart of a method for preparing a shielded gate trench field effect transistor shown in an embodiment of the present application.

[0123] See also Figure 5 , the method for preparing the shielded gate trench field effect transistor comprises:

[0124] 501. Prepare a substrate region using semiconductor material;

[0125] 502. Forming a drift region by epitaxial growth on the substrate region;

[0126] 503. Forming the potential barrier buffer zone on the drift region by depositing metal;

[0127] 504. Forming a matrix region above the barrier buffer region by ion implantation or diffusion;

[0128] In an embodiment of the present application, a metal layer is provided between the drift region and the base region, and the interface between the metal layer and the drift region forms the barrier buffer region, which is a Schottky junction between the base region and the drift region.

[0129] The Schottky junction, similar to the PN junction, has nonlinear impedance characteristics, also known as rectification characteristics. However, in a Schottky junction, the drift of majority carriers plays a major role, with virtually no stored carriers. Therefore, when the transistor is reverse-conducting, the Schottky junction's reverse recovery time is very short, effectively reducing the transistor's reverse recovery time and increasing its switching speed.

[0130] 505. Etching a groove on one side of the drift region;

[0131] 506. Depositing a P-type doped semiconductor material, polysilicon, oxide, and polysilicon in sequence in the trench to form a shield gate, an insulating layer, and a control gate;

[0132] 507. Form the P-type source region and the N-type source region on the base region using a P-type doped semiconductor material and an N-type doped semiconductor material, respectively;

[0133] 508. forming a source electrode above the source region;

[0134] 509. Form a metal gate above the trench;

[0135] 510. Fabricate a drain below the substrate region.

[0136] In the embodiment of the present application, the above steps 501 to 510 are steps 401 to 409 in embodiment three with step 503 added thereto. Therefore, except for step 503, the remaining steps of the two are the same and will not be repeated here.

[0137] An embodiment of the present application provides a method for preparing a shielded gate trench field effect transistor. Compared with the prior art method of forming a PN junction between the base region and the drift region, forming a Schottky junction between the base region and the drift region can effectively improve the uniformity of the hole current.

[0138] When avalanche hole current appears, the Schottky junction set between the substrate region and the drift region can effectively guide the hole current to enter the substrate region more evenly after entering the metal layer, so that the hole current is evenly diverted to each P-type source region, thereby improving the P-type source region's ability to divert hole current.

[0139] The embodiments of the present application have been described above. The above description is illustrative and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to the technology in the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A shielded gate trench field effect transistor, characterized in that: include: A substrate region (1), a drift region (2), a base region (3), a source region (4), a trench region (5), a drain (6), and a source (7); The drift region (2) is connected to the substrate region (1), with the direction from the substrate region (1) to the drift region (2) being considered upward. The base region (3) and the source region (4) are sequentially arranged above the drift region (2); The trench region (5) is arranged on the side of the base region (3) and is respectively connected to the drift region (2), the base region (3) and the source region (4); The source region (4) is composed of a P-type source region (41) and an N-type source region (42), wherein the P-type source region (41) and the N-type source region (42) are arranged in parallel along the top surface of the base region (3) and are respectively connected to the trench region (5); The trench region (5) comprises a shielding gate (51), a control gate (52), an insulating layer (53) and a metal gate; the control gate (52) and the shielding gate (51) are sequentially arranged in the trench region (5) from top to bottom and separated by the insulating layer (53); the control gate (52) is connected to the base region (3) and the source region (4) respectively through the insulating layer (53), and the shielding gate (51) is connected to the drift region (2) through the insulating layer (53); The source electrode (7) is arranged above the source region (4); the drain electrode (6) is arranged below the substrate region (1); and the metal gate is arranged above the control gate (52); Also included is the barrier buffer (8): The potential barrier buffer zone (8) is arranged between the drift zone (2) and the base zone (3); the potential barrier buffer zone (8) is a Schottky junction between the base zone (3) and the drift zone (2).

2. The shielded gate trench field effect transistor according to claim 1, wherein: On a longitudinal section of the source region (4), at least two P-type source regions (41) and at least two N-type source regions (42) are alternately arranged, and the P-type source region (41) is connected to the trench region (5), so that the distance between the P-type source region (41) and the trench region (5) is reduced.

3. The shielded gate trench field effect transistor according to claim 1, wherein: A metal layer is provided between the drift region (2) and the base region (3), and the interface between the metal layer and the drift region (2) forms the potential barrier buffer region (8).

4. The shielded gate trench field effect transistor according to claim 1, wherein: The doping concentrations of the P-type source region (41) and the N-type source region (42) are both heavily doped.

5. The shielded gate trench field effect transistor according to claim 1, wherein: The doping type of the substrate region (1) is N-type doping, and the doping concentration of the substrate region (1) is a heavy doping concentration; The doping type of the drift region (2) is N-type doping, and the doping concentration of the drift region (2) is a light doping concentration; The doping type of the matrix region (3) is P-type doping, and the doping concentration of the matrix region (3) is a medium doping concentration; The doping concentration of the source region (4) is a heavy doping concentration; the doping concentration of the control gate (52) is a heavy doping concentration, and the doping type of the control gate (52) is P-type doping.

6. A method for preparing a shielded gate trench field effect transistor, characterized in that: For preparing the shielded gate trench field effect transistor according to any one of claims 1 to 5, comprising: preparing a substrate region with semiconductor material; epitaxially forming a drift region on the substrate region; forming a matrix region on the drift region by ion implantation or diffusion; etching a trench on one side of the drift region; Depositing P-type doped semiconductor material, polysilicon, oxide and polysilicon in sequence in the trench to form a shield gate, an insulating layer and a control gate; On the base region, forming the P-type source region and the N-type source region with a P-type doped semiconductor material and an N-type doped semiconductor material respectively; forming a source electrode above the source region; forming a metal gate over the trench; A drain is formed below the substrate region.

7. The method for preparing a shielded gate trench field effect transistor according to claim 6, wherein: Before forming a matrix region on the drift region by ion implantation or diffusion, the method includes: Metal is deposited on the drift region to form a potential barrier buffer zone.

8. The method for preparing a shielded gate trench field effect transistor according to claim 7, wherein: The doping to form the source region on the base region includes: forming a P-type source region and an N-type source region on the base region using a P-type doped semiconductor material and an N-type doped semiconductor material respectively, so that the P-type source region and the N-type source region are connected.

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